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util: remove util_is_pot in favor of util_is_power_of_two
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "util/u_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33 #include "nv50_transfer.h"
34
35 #define NV50_SU_MAX_TEMP 127
36 #define NV50_SU_MAX_ADDR 4
37 //#define NV50_PROGRAM_DUMP
38
39 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
40
41 /* ARL - gallium craps itself on progs/vp/arl.txt
42 *
43 * MSB - Like MAD, but MUL+SUB
44 * - Fuck it off, introduce a way to negate args for ops that
45 * support it.
46 *
47 * Look into inlining IMMD for ops other than MOV (make it general?)
48 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
49 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
50 *
51 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
52 * case, if the emit_src() causes the inst to suddenly become long.
53 *
54 * Verify half-insns work where expected - and force disable them where they
55 * don't work - MUL has it forcibly disabled atm as it fixes POW..
56 *
57 * FUCK! watch dst==src vectors, can overwrite components that are needed.
58 * ie. SUB R0, R0.yzxw, R0
59 *
60 * Things to check with renouveau:
61 * FP attr/result assignment - how?
62 * attrib
63 * - 0x16bc maps vp output onto fp hpos
64 * - 0x16c0 maps vp output onto fp col0
65 * result
66 * - colr always 0-3
67 * - depr always 4
68 * 0x16bc->0x16e8 --> some binding between vp/fp regs
69 * 0x16b8 --> VP output count
70 *
71 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
72 * "MOV rcol.x, fcol.y" = 0x00000004
73 * 0x19a8 --> as above but 0x00000100 and 0x00000000
74 * - 0x00100000 used when KIL used
75 * 0x196c --> as above but 0x00000011 and 0x00000000
76 *
77 * 0x1988 --> 0xXXNNNNNN
78 * - XX == FP high something
79 */
80 struct nv50_reg {
81 enum {
82 P_TEMP,
83 P_ATTR,
84 P_RESULT,
85 P_CONST,
86 P_IMMD,
87 P_ADDR
88 } type;
89 int index;
90
91 int hw;
92 int mod;
93
94 int rhw; /* result hw for FP outputs, or interpolant index */
95 int acc; /* instruction where this reg is last read (first insn == 1) */
96
97 int vtx; /* vertex index, for GP inputs (TGSI Dimension.Index) */
98 int indirect[2]; /* index into pc->addr, or -1 */
99
100 ubyte buf_index; /* c{0 .. 15}[] or g{0 .. 15}[] */
101 };
102
103 #define NV50_MOD_NEG 1
104 #define NV50_MOD_ABS 2
105 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
106 #define NV50_MOD_SAT 4
107 #define NV50_MOD_I32 8
108
109 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
110
111 /* STACK: Conditionals and loops have to use the (per warp) stack.
112 * Stack entries consist of an entry type (divergent path, join at),
113 * a mask indicating the active threads of the warp, and an address.
114 * MPs can store 12 stack entries internally, if we need more (and
115 * we probably do), we have to create a stack buffer in VRAM.
116 */
117 /* impose low limits for now */
118 #define NV50_MAX_COND_NESTING 4
119 #define NV50_MAX_LOOP_NESTING 3
120
121 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
122
123 struct nv50_pc {
124 struct nv50_program *p;
125
126 /* hw resources */
127 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
128 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
129
130 /* tgsi resources */
131 struct nv50_reg *temp;
132 int temp_nr;
133 struct nv50_reg *attr;
134 int attr_nr;
135 struct nv50_reg *result;
136 int result_nr;
137 struct nv50_reg *param;
138 int param_nr;
139 struct nv50_reg *immd;
140 uint32_t *immd_buf;
141 int immd_nr;
142 struct nv50_reg **addr;
143 int addr_nr;
144 struct nv50_reg *sysval;
145 int sysval_nr;
146
147 struct nv50_reg *temp_temp[16];
148 struct nv50_program_exec *temp_temp_exec[16];
149 unsigned temp_temp_nr;
150
151 /* broadcast and destination replacement regs */
152 struct nv50_reg *r_brdc;
153 struct nv50_reg *r_dst[4];
154
155 struct nv50_reg reg_instances[16];
156 unsigned reg_instance_nr;
157
158 unsigned interp_mode[32];
159 /* perspective interpolation registers */
160 struct nv50_reg *iv_p;
161 struct nv50_reg *iv_c;
162
163 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
164 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
165 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
166 int if_lvl, loop_lvl;
167 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
168
169 unsigned *insn_pos; /* actual program offset of each TGSI insn */
170 boolean in_subroutine;
171
172 /* current instruction and total number of insns */
173 unsigned insn_cur;
174 unsigned insn_nr;
175
176 boolean allow32;
177
178 uint8_t edgeflag_out;
179 };
180
181 static struct nv50_reg *get_address_reg(struct nv50_pc *, struct nv50_reg *);
182
183 static INLINE void
184 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
185 {
186 reg->type = type;
187 reg->index = index;
188 reg->hw = hw;
189 reg->mod = 0;
190 reg->rhw = -1;
191 reg->vtx = -1;
192 reg->acc = 0;
193 reg->indirect[0] = reg->indirect[1] = -1;
194 reg->buf_index = (type == P_CONST) ? 1 : 0;
195 }
196
197 static INLINE unsigned
198 popcnt4(uint32_t val)
199 {
200 static const unsigned cnt[16]
201 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
202 return cnt[val & 0xf];
203 }
204
205 static void
206 terminate_mbb(struct nv50_pc *pc)
207 {
208 int i;
209
210 /* remove records of temporary address register values */
211 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
212 if (pc->r_addr[i].index < 0)
213 pc->r_addr[i].acc = 0;
214 }
215
216 static void
217 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
218 {
219 int i = 0;
220
221 if (reg->type == P_RESULT) {
222 if (pc->p->cfg.high_result < (reg->hw + 1))
223 pc->p->cfg.high_result = reg->hw + 1;
224 }
225
226 if (reg->type != P_TEMP)
227 return;
228
229 if (reg->hw >= 0) {
230 /*XXX: do this here too to catch FP temp-as-attr usage..
231 * not clean, but works */
232 if (pc->p->cfg.high_temp < (reg->hw + 1))
233 pc->p->cfg.high_temp = reg->hw + 1;
234 return;
235 }
236
237 if (reg->rhw != -1) {
238 /* try to allocate temporary with index rhw first */
239 if (!(pc->r_temp[reg->rhw])) {
240 pc->r_temp[reg->rhw] = reg;
241 reg->hw = reg->rhw;
242 if (pc->p->cfg.high_temp < (reg->rhw + 1))
243 pc->p->cfg.high_temp = reg->rhw + 1;
244 return;
245 }
246 /* make sure we don't get things like $r0 needs to go
247 * in $r1 and $r1 in $r0
248 */
249 i = pc->result_nr * 4;
250 }
251
252 for (; i < NV50_SU_MAX_TEMP; i++) {
253 if (!(pc->r_temp[i])) {
254 pc->r_temp[i] = reg;
255 reg->hw = i;
256 if (pc->p->cfg.high_temp < (i + 1))
257 pc->p->cfg.high_temp = i + 1;
258 return;
259 }
260 }
261
262 NOUVEAU_ERR("out of registers\n");
263 abort();
264 }
265
266 static INLINE struct nv50_reg *
267 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
268 {
269 struct nv50_reg *ri;
270
271 assert(pc->reg_instance_nr < 16);
272 ri = &pc->reg_instances[pc->reg_instance_nr++];
273 if (reg) {
274 alloc_reg(pc, reg);
275 *ri = *reg;
276 reg->indirect[0] = reg->indirect[1] = -1;
277 reg->mod = 0;
278 }
279 return ri;
280 }
281
282 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
283 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
284 * lest we risk temp_temps overwriting regs alloc'd "later".
285 */
286 static struct nv50_reg *
287 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
288 {
289 struct nv50_reg *r;
290 int i;
291
292 if (dst && dst->type == P_TEMP && dst->hw == -1)
293 return dst;
294
295 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
296 if (!pc->r_temp[i]) {
297 r = MALLOC_STRUCT(nv50_reg);
298 ctor_reg(r, P_TEMP, -1, i);
299 pc->r_temp[i] = r;
300 return r;
301 }
302 }
303
304 NOUVEAU_ERR("out of registers\n");
305 abort();
306 return NULL;
307 }
308
309 #if 0
310 /* release the hardware resource held by r */
311 static void
312 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
313 {
314 assert(r->type == P_TEMP);
315 if (r->hw == -1)
316 return;
317
318 assert(pc->r_temp[r->hw] == r);
319 pc->r_temp[r->hw] = NULL;
320
321 r->acc = 0;
322 if (r->index == -1)
323 FREE(r);
324 }
325 #endif
326
327 static void
328 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
329 {
330 if (r->index == -1) {
331 unsigned hw = r->hw;
332
333 FREE(pc->r_temp[hw]);
334 pc->r_temp[hw] = NULL;
335 }
336 }
337
338 static int
339 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
340 {
341 int i;
342
343 if ((idx + 4) >= NV50_SU_MAX_TEMP)
344 return 1;
345
346 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
347 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
348 return alloc_temp4(pc, dst, idx + 4);
349
350 for (i = 0; i < 4; i++) {
351 dst[i] = MALLOC_STRUCT(nv50_reg);
352 ctor_reg(dst[i], P_TEMP, -1, idx + i);
353 pc->r_temp[idx + i] = dst[i];
354 }
355
356 return 0;
357 }
358
359 static void
360 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
361 {
362 int i;
363
364 for (i = 0; i < 4; i++)
365 free_temp(pc, reg[i]);
366 }
367
368 static struct nv50_reg *
369 temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
370 {
371 if (pc->temp_temp_nr >= 16)
372 assert(0);
373
374 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
375 pc->temp_temp_exec[pc->temp_temp_nr] = e;
376 return pc->temp_temp[pc->temp_temp_nr++];
377 }
378
379 /* This *must* be called for all nv50_program_exec that have been
380 * given as argument to temp_temp, or the temps will be leaked !
381 */
382 static void
383 kill_temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
384 {
385 int i;
386
387 for (i = 0; i < pc->temp_temp_nr; i++)
388 if (pc->temp_temp_exec[i] == e)
389 free_temp(pc, pc->temp_temp[i]);
390 if (!e)
391 pc->temp_temp_nr = 0;
392 }
393
394 static int
395 ctor_immd_4u32(struct nv50_pc *pc,
396 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
397 {
398 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
399
400 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
401
402 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
403 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
404 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
405 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
406
407 return pc->immd_nr++;
408 }
409
410 static INLINE int
411 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
412 {
413 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
414 }
415
416 static struct nv50_reg *
417 alloc_immd(struct nv50_pc *pc, float f)
418 {
419 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
420 unsigned hw;
421
422 for (hw = 0; hw < pc->immd_nr * 4; hw++)
423 if (pc->immd_buf[hw] == fui(f))
424 break;
425
426 if (hw == pc->immd_nr * 4)
427 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
428
429 ctor_reg(r, P_IMMD, -1, hw);
430 return r;
431 }
432
433 static struct nv50_program_exec *
434 exec(struct nv50_pc *pc)
435 {
436 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
437
438 e->param.index = -1;
439 return e;
440 }
441
442 static void
443 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
444 {
445 struct nv50_program *p = pc->p;
446
447 if (p->exec_tail)
448 p->exec_tail->next = e;
449 if (!p->exec_head)
450 p->exec_head = e;
451 p->exec_tail = e;
452 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
453
454 kill_temp_temp(pc, e);
455 }
456
457 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
458
459 static boolean
460 is_long(struct nv50_program_exec *e)
461 {
462 if (e->inst[0] & 1)
463 return TRUE;
464 return FALSE;
465 }
466
467 static boolean
468 is_immd(struct nv50_program_exec *e)
469 {
470 if (is_long(e) && (e->inst[1] & 3) == 3)
471 return TRUE;
472 return FALSE;
473 }
474
475 static boolean
476 is_join(struct nv50_program_exec *e)
477 {
478 if (is_long(e) && (e->inst[1] & 3) == 2)
479 return TRUE;
480 return FALSE;
481 }
482
483 static INLINE boolean
484 is_control_flow(struct nv50_program_exec *e)
485 {
486 return (e->inst[0] & 2);
487 }
488
489 static INLINE void
490 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
491 struct nv50_program_exec *e)
492 {
493 assert(!is_immd(e));
494 set_long(pc, e);
495 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
496 e->inst[1] |= (pred << 7) | (idx << 12);
497 }
498
499 static INLINE void
500 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
501 struct nv50_program_exec *e)
502 {
503 set_long(pc, e);
504 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
505 e->inst[1] |= (idx << 4) | (on << 6);
506 }
507
508 static INLINE void
509 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
510 {
511 if (is_long(e))
512 return;
513
514 e->inst[0] |= 1;
515 set_pred(pc, 0xf, 0, e);
516 set_pred_wr(pc, 0, 0, e);
517 }
518
519 static INLINE void
520 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
521 {
522 if (dst->type == P_RESULT) {
523 set_long(pc, e);
524 e->inst[1] |= 0x00000008;
525 }
526
527 alloc_reg(pc, dst);
528 if (dst->hw > 63)
529 set_long(pc, e);
530 e->inst[0] |= (dst->hw << 2);
531 }
532
533 static INLINE void
534 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
535 {
536 set_long(pc, e);
537 /* XXX: can't be predicated - bits overlap; cases where both
538 * are required should be avoided by using pc->allow32 */
539 set_pred(pc, 0, 0, e);
540 set_pred_wr(pc, 0, 0, e);
541
542 e->inst[1] |= 0x00000002 | 0x00000001;
543 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
544 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
545 }
546
547 static INLINE void
548 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
549 {
550 assert(a->type == P_ADDR);
551
552 assert(!(e->inst[0] & 0x0c000000));
553 assert(!(e->inst[1] & 0x00000004));
554
555 e->inst[0] |= (a->hw & 3) << 26;
556 e->inst[1] |= a->hw & 4;
557 }
558
559 static void
560 emit_arl(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, uint8_t);
561
562 static void
563 emit_shl_imm(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, int);
564
565 static void
566 emit_mov_from_addr(struct nv50_pc *pc, struct nv50_reg *dst,
567 struct nv50_reg *src)
568 {
569 struct nv50_program_exec *e = exec(pc);
570
571 e->inst[1] = 0x40000000;
572 set_long(pc, e);
573 set_dst(pc, dst, e);
574 set_addr(e, src);
575
576 emit(pc, e);
577 }
578
579 static void
580 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
581 struct nv50_reg *src0, uint16_t src1_val)
582 {
583 struct nv50_program_exec *e = exec(pc);
584
585 e->inst[0] = 0xd0000000 | (src1_val << 9);
586 e->inst[1] = 0x20000000;
587 set_long(pc, e);
588 e->inst[0] |= dst->hw << 2;
589 if (src0) /* otherwise will add to $a0, which is always 0 */
590 set_addr(e, src0);
591
592 emit(pc, e);
593 }
594
595 #define INTERP_LINEAR 0
596 #define INTERP_FLAT 1
597 #define INTERP_PERSPECTIVE 2
598 #define INTERP_CENTROID 4
599
600 /* interpolant index has been stored in dst->rhw */
601 static void
602 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
603 unsigned mode)
604 {
605 struct nv50_program_exec *e = exec(pc);
606 assert(dst->rhw != -1);
607
608 e->inst[0] |= 0x80000000;
609 set_dst(pc, dst, e);
610 e->inst[0] |= (dst->rhw << 16);
611
612 if (mode & INTERP_FLAT) {
613 e->inst[0] |= (1 << 8);
614 } else {
615 if (mode & INTERP_PERSPECTIVE) {
616 e->inst[0] |= (1 << 25);
617 alloc_reg(pc, iv);
618 e->inst[0] |= (iv->hw << 9);
619 }
620
621 if (mode & INTERP_CENTROID)
622 e->inst[0] |= (1 << 24);
623 }
624
625 emit(pc, e);
626 }
627
628 static void
629 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
630 struct nv50_program_exec *e)
631 {
632 set_long(pc, e);
633
634 e->param.index = src->hw & 127;
635 e->param.shift = s;
636 e->param.mask = m << (s % 32);
637
638 if (src->hw < 0 || src->hw > 127) /* need (additional) address reg */
639 set_addr(e, get_address_reg(pc, src));
640 else
641 if (src->acc < 0) {
642 assert(src->type == P_CONST);
643 set_addr(e, pc->addr[src->indirect[0]]);
644 }
645
646 e->inst[1] |= (src->buf_index << 22);
647 }
648
649 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
650 static void
651 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
652 {
653 struct nv50_program_exec *e = exec(pc);
654
655 e->inst[0] = 0x10000000;
656 if (!pc->allow32)
657 set_long(pc, e);
658
659 set_dst(pc, dst, e);
660
661 if (!is_long(e) && src->type == P_IMMD) {
662 set_immd(pc, src, e);
663 /*XXX: 32-bit, but steals part of "half" reg space - need to
664 * catch and handle this case if/when we do half-regs
665 */
666 } else
667 if (src->type == P_IMMD || src->type == P_CONST) {
668 set_long(pc, e);
669 set_data(pc, src, 0x7f, 9, e);
670 e->inst[1] |= 0x20000000; /* mov from c[] */
671 } else {
672 if (src->type == P_ATTR) {
673 set_long(pc, e);
674 e->inst[1] |= 0x00200000;
675
676 if (src->vtx >= 0) {
677 /* indirect (vertex base + c) load from p[] */
678 e->inst[0] |= 0x01800000;
679 set_addr(e, get_address_reg(pc, src));
680 }
681 }
682
683 alloc_reg(pc, src);
684 if (src->hw > 63)
685 set_long(pc, e);
686 e->inst[0] |= (src->hw << 9);
687 }
688
689 if (is_long(e) && !is_immd(e)) {
690 e->inst[1] |= 0x04000000; /* 32-bit */
691 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
692 if (!(e->inst[1] & 0x20000000))
693 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
694 } else
695 e->inst[0] |= 0x00008000;
696
697 emit(pc, e);
698 }
699
700 static INLINE void
701 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
702 {
703 struct nv50_reg *imm = alloc_immd(pc, f);
704 emit_mov(pc, dst, imm);
705 FREE(imm);
706 }
707
708 /* Assign the hw of the discarded temporary register src
709 * to the tgsi register dst and free src.
710 */
711 static void
712 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
713 {
714 assert(src->index == -1 && src->hw != -1);
715
716 if (pc->if_lvl || pc->loop_lvl ||
717 (dst->type != P_TEMP) ||
718 (src->hw < pc->result_nr * 4 &&
719 pc->p->type == PIPE_SHADER_FRAGMENT) ||
720 pc->p->info.opcode_count[TGSI_OPCODE_CAL] ||
721 pc->p->info.opcode_count[TGSI_OPCODE_BRA]) {
722
723 emit_mov(pc, dst, src);
724 free_temp(pc, src);
725 return;
726 }
727
728 if (dst->hw != -1)
729 pc->r_temp[dst->hw] = NULL;
730 pc->r_temp[src->hw] = dst;
731 dst->hw = src->hw;
732
733 FREE(src);
734 }
735
736 static void
737 emit_nop(struct nv50_pc *pc)
738 {
739 struct nv50_program_exec *e = exec(pc);
740
741 e->inst[0] = 0xf0000000;
742 set_long(pc, e);
743 e->inst[1] = 0xe0000000;
744 emit(pc, e);
745 }
746
747 static boolean
748 check_swap_src_0_1(struct nv50_pc *pc,
749 struct nv50_reg **s0, struct nv50_reg **s1)
750 {
751 struct nv50_reg *src0 = *s0, *src1 = *s1;
752
753 if (src0->type == P_CONST) {
754 if (src1->type != P_CONST) {
755 *s0 = src1;
756 *s1 = src0;
757 return TRUE;
758 }
759 } else
760 if (src1->type == P_ATTR) {
761 if (src0->type != P_ATTR) {
762 *s0 = src1;
763 *s1 = src0;
764 return TRUE;
765 }
766 }
767
768 return FALSE;
769 }
770
771 static void
772 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
773 struct nv50_program_exec *e)
774 {
775 struct nv50_reg *temp;
776
777 if (src->type != P_TEMP) {
778 temp = temp_temp(pc, e);
779 emit_mov(pc, temp, src);
780 src = temp;
781 }
782
783 alloc_reg(pc, src);
784 if (src->hw > 63)
785 set_long(pc, e);
786 e->inst[0] |= (src->hw << 9);
787 }
788
789 static void
790 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
791 {
792 if (src->type == P_ATTR) {
793 set_long(pc, e);
794 e->inst[1] |= 0x00200000;
795
796 if (src->vtx >= 0) {
797 e->inst[0] |= 0x01800000; /* src from p[] */
798 set_addr(e, get_address_reg(pc, src));
799 }
800 } else
801 if (src->type == P_CONST || src->type == P_IMMD) {
802 struct nv50_reg *temp = temp_temp(pc, e);
803
804 emit_mov(pc, temp, src);
805 src = temp;
806 }
807
808 alloc_reg(pc, src);
809 if (src->hw > 63)
810 set_long(pc, e);
811 e->inst[0] |= (src->hw << 9);
812 }
813
814 static void
815 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
816 {
817 if (src->type == P_ATTR) {
818 struct nv50_reg *temp = temp_temp(pc, e);
819
820 emit_mov(pc, temp, src);
821 src = temp;
822 } else
823 if (src->type == P_CONST || src->type == P_IMMD) {
824 if (e->inst[0] & 0x01800000) {
825 struct nv50_reg *temp = temp_temp(pc, e);
826
827 emit_mov(pc, temp, src);
828 src = temp;
829 } else {
830 assert(!(e->inst[0] & 0x00800000));
831 set_data(pc, src, 0x7f, 16, e);
832 e->inst[0] |= 0x00800000;
833 }
834 }
835
836 alloc_reg(pc, src);
837 if (src->hw > 63)
838 set_long(pc, e);
839 e->inst[0] |= ((src->hw & 127) << 16);
840 }
841
842 static void
843 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
844 {
845 set_long(pc, e);
846
847 if (src->type == P_ATTR) {
848 struct nv50_reg *temp = temp_temp(pc, e);
849
850 emit_mov(pc, temp, src);
851 src = temp;
852 } else
853 if (src->type == P_CONST || src->type == P_IMMD) {
854 if (e->inst[0] & 0x01800000) {
855 struct nv50_reg *temp = temp_temp(pc, e);
856
857 emit_mov(pc, temp, src);
858 src = temp;
859 } else {
860 assert(!(e->inst[0] & 0x01000000));
861 set_data(pc, src, 0x7f, 32+14, e);
862 e->inst[0] |= 0x01000000;
863 }
864 }
865
866 alloc_reg(pc, src);
867 e->inst[1] |= ((src->hw & 127) << 14);
868 }
869
870 static void
871 set_half_src(struct nv50_pc *pc, struct nv50_reg *src, int lh,
872 struct nv50_program_exec *e, int pos)
873 {
874 struct nv50_reg *r = src;
875
876 alloc_reg(pc, r);
877 if (r->type != P_TEMP) {
878 r = temp_temp(pc, e);
879 emit_mov(pc, r, src);
880 }
881
882 if (r->hw > (NV50_SU_MAX_TEMP / 2)) {
883 NOUVEAU_ERR("out of low GPRs\n");
884 abort();
885 }
886
887 e->inst[pos / 32] |= ((src->hw * 2) + lh) << (pos % 32);
888 }
889
890 #if 0
891 static void
892 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
893 {
894 struct nv50_program_exec *e = exec(pc);
895
896 assert(dst->type == P_TEMP);
897 e->inst[1] = 0x20000000 | (pred << 12);
898 set_long(pc, e);
899 set_dst(pc, dst, e);
900
901 emit(pc, e);
902 }
903 #endif
904
905 static void
906 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
907 {
908 struct nv50_program_exec *e = exec(pc);
909
910 e->inst[0] = 0x000001fc;
911 e->inst[1] = 0xa0000008;
912 set_long(pc, e);
913 set_pred_wr(pc, 1, pred, e);
914 set_src_0_restricted(pc, src, e);
915
916 emit(pc, e);
917 }
918
919 static void
920 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
921 struct nv50_reg *src1)
922 {
923 struct nv50_program_exec *e = exec(pc);
924
925 e->inst[0] |= 0xc0000000;
926
927 if (!pc->allow32)
928 set_long(pc, e);
929
930 check_swap_src_0_1(pc, &src0, &src1);
931 set_dst(pc, dst, e);
932 set_src_0(pc, src0, e);
933 if (src1->type == P_IMMD && !is_long(e)) {
934 if (src0->mod ^ src1->mod)
935 e->inst[0] |= 0x00008000;
936 set_immd(pc, src1, e);
937 } else {
938 set_src_1(pc, src1, e);
939 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
940 if (is_long(e))
941 e->inst[1] |= 0x08000000;
942 else
943 e->inst[0] |= 0x00008000;
944 }
945 }
946
947 emit(pc, e);
948 }
949
950 static void
951 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
952 struct nv50_reg *src0, struct nv50_reg *src1)
953 {
954 struct nv50_program_exec *e = exec(pc);
955
956 e->inst[0] = 0xb0000000;
957
958 alloc_reg(pc, src1);
959 check_swap_src_0_1(pc, &src0, &src1);
960
961 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
962 set_long(pc, e);
963 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
964 ((src1->mod & NV50_MOD_NEG) << 27);
965 }
966
967 set_dst(pc, dst, e);
968 set_src_0(pc, src0, e);
969 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
970 set_src_2(pc, src1, e);
971 else
972 if (src1->type == P_IMMD)
973 set_immd(pc, src1, e);
974 else
975 set_src_1(pc, src1, e);
976
977 emit(pc, e);
978 }
979
980 static void
981 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
982 uint8_t s)
983 {
984 struct nv50_program_exec *e = exec(pc);
985
986 set_long(pc, e);
987 e->inst[1] |= 0xc0000000;
988
989 e->inst[0] |= dst->hw << 2;
990 e->inst[0] |= s << 16; /* shift left */
991 set_src_0(pc, src, e);
992
993 emit(pc, e);
994 }
995
996 static boolean
997 address_reg_suitable(struct nv50_reg *a, struct nv50_reg *r)
998 {
999 if (!r)
1000 return FALSE;
1001
1002 if (r->vtx != a->vtx)
1003 return FALSE;
1004 if (r->vtx >= 0)
1005 return (r->indirect[1] == a->indirect[1]);
1006
1007 if (r->hw < a->rhw || (r->hw - a->rhw) >= 128)
1008 return FALSE;
1009
1010 if (a->index >= 0)
1011 return (a->index == r->indirect[0]);
1012 return (a->indirect[0] == r->indirect[0]);
1013 }
1014
1015 static void
1016 load_vertex_base(struct nv50_pc *pc, struct nv50_reg *dst,
1017 struct nv50_reg *a, int shift)
1018 {
1019 struct nv50_reg mem, *temp;
1020
1021 ctor_reg(&mem, P_ATTR, -1, dst->vtx);
1022
1023 assert(dst->type == P_ADDR);
1024 if (!a) {
1025 emit_arl(pc, dst, &mem, 0);
1026 return;
1027 }
1028 temp = alloc_temp(pc, NULL);
1029
1030 if (shift) {
1031 emit_mov_from_addr(pc, temp, a);
1032 if (shift < 0)
1033 emit_shl_imm(pc, temp, temp, shift);
1034 emit_arl(pc, dst, temp, MAX2(shift, 0));
1035 }
1036 emit_mov(pc, temp, &mem);
1037 set_addr(pc->p->exec_tail, dst);
1038
1039 emit_arl(pc, dst, temp, 0);
1040 free_temp(pc, temp);
1041 }
1042
1043 /* case (ref == NULL): allocate address register for TGSI_FILE_ADDRESS
1044 * case (vtx >= 0, acc >= 0): load vertex base from a[vtx * 4] to $aX
1045 * case (vtx >= 0, acc < 0): load vertex base from s[$aY + vtx * 4] to $aX
1046 * case (vtx < 0, acc >= 0): memory address too high to encode
1047 * case (vtx < 0, acc < 0): get source register for TGSI_FILE_ADDRESS
1048 */
1049 static struct nv50_reg *
1050 get_address_reg(struct nv50_pc *pc, struct nv50_reg *ref)
1051 {
1052 int i;
1053 struct nv50_reg *a_ref, *a = NULL;
1054
1055 for (i = 0; i < NV50_SU_MAX_ADDR; ++i) {
1056 if (pc->r_addr[i].acc == 0)
1057 a = &pc->r_addr[i]; /* an unused address reg */
1058 else
1059 if (address_reg_suitable(&pc->r_addr[i], ref)) {
1060 pc->r_addr[i].acc = pc->insn_cur;
1061 return &pc->r_addr[i];
1062 } else
1063 if (!a && pc->r_addr[i].index < 0 &&
1064 pc->r_addr[i].acc < pc->insn_cur)
1065 a = &pc->r_addr[i];
1066 }
1067 if (!a) {
1068 /* We'll be able to spill address regs when this
1069 * mess is replaced with a proper compiler ...
1070 */
1071 NOUVEAU_ERR("out of address regs\n");
1072 abort();
1073 return NULL;
1074 }
1075
1076 /* initialize and reserve for this TGSI instruction */
1077 a->rhw = 0;
1078 a->index = a->indirect[0] = a->indirect[1] = -1;
1079 a->acc = pc->insn_cur;
1080
1081 if (!ref) {
1082 a->vtx = -1;
1083 return a;
1084 }
1085 a->vtx = ref->vtx;
1086
1087 /* now put in the correct value ... */
1088
1089 if (ref->vtx >= 0) {
1090 a->indirect[1] = ref->indirect[1];
1091
1092 /* For an indirect vertex index, we need to shift address right
1093 * by 2, the address register will contain vtx * 16, we need to
1094 * load from a[vtx * 4].
1095 */
1096 load_vertex_base(pc, a, (ref->acc < 0) ?
1097 pc->addr[ref->indirect[1]] : NULL, -2);
1098 } else {
1099 assert(ref->acc < 0 || ref->indirect[0] < 0);
1100
1101 a->rhw = ref->hw & ~0x7f;
1102 a->indirect[0] = ref->indirect[0];
1103 a_ref = (ref->acc < 0) ? pc->addr[ref->indirect[0]] : NULL;
1104
1105 emit_add_addr_imm(pc, a, a_ref, a->rhw * 4);
1106 }
1107 return a;
1108 }
1109
1110 #define NV50_MAX_F32 0x880
1111 #define NV50_MAX_S32 0x08c
1112 #define NV50_MAX_U32 0x084
1113 #define NV50_MIN_F32 0x8a0
1114 #define NV50_MIN_S32 0x0ac
1115 #define NV50_MIN_U32 0x0a4
1116
1117 static void
1118 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
1119 struct nv50_reg *src0, struct nv50_reg *src1)
1120 {
1121 struct nv50_program_exec *e = exec(pc);
1122
1123 set_long(pc, e);
1124 e->inst[0] |= 0x30000000 | ((sub & 0x800) << 20);
1125 e->inst[1] |= (sub << 24);
1126
1127 check_swap_src_0_1(pc, &src0, &src1);
1128 set_dst(pc, dst, e);
1129 set_src_0(pc, src0, e);
1130 set_src_1(pc, src1, e);
1131
1132 if (src0->mod & NV50_MOD_ABS)
1133 e->inst[1] |= 0x00100000;
1134 if (src1->mod & NV50_MOD_ABS)
1135 e->inst[1] |= 0x00080000;
1136
1137 emit(pc, e);
1138 }
1139
1140 static INLINE void
1141 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1142 struct nv50_reg *src1)
1143 {
1144 src1->mod ^= NV50_MOD_NEG;
1145 emit_add(pc, dst, src0, src1);
1146 src1->mod ^= NV50_MOD_NEG;
1147 }
1148
1149 static void
1150 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1151 struct nv50_reg *src1, unsigned op)
1152 {
1153 struct nv50_program_exec *e = exec(pc);
1154
1155 e->inst[0] = 0xd0000000;
1156 set_long(pc, e);
1157
1158 check_swap_src_0_1(pc, &src0, &src1);
1159 set_dst(pc, dst, e);
1160 set_src_0(pc, src0, e);
1161
1162 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1163 op != TGSI_OPCODE_XOR)
1164 assert(!"invalid bit op");
1165
1166 assert(!(src0->mod | src1->mod));
1167
1168 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1169 set_immd(pc, src1, e);
1170 if (op == TGSI_OPCODE_OR)
1171 e->inst[0] |= 0x0100;
1172 else
1173 if (op == TGSI_OPCODE_XOR)
1174 e->inst[0] |= 0x8000;
1175 } else {
1176 set_src_1(pc, src1, e);
1177 e->inst[1] |= 0x04000000; /* 32 bit */
1178 if (op == TGSI_OPCODE_OR)
1179 e->inst[1] |= 0x4000;
1180 else
1181 if (op == TGSI_OPCODE_XOR)
1182 e->inst[1] |= 0x8000;
1183 }
1184
1185 emit(pc, e);
1186 }
1187
1188 static void
1189 emit_not(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1190 {
1191 struct nv50_program_exec *e = exec(pc);
1192
1193 e->inst[0] = 0xd0000000;
1194 e->inst[1] = 0x0402c000;
1195 set_long(pc, e);
1196 set_dst(pc, dst, e);
1197 set_src_1(pc, src, e);
1198
1199 emit(pc, e);
1200 }
1201
1202 static void
1203 emit_shift(struct nv50_pc *pc, struct nv50_reg *dst,
1204 struct nv50_reg *src0, struct nv50_reg *src1, unsigned dir)
1205 {
1206 struct nv50_program_exec *e = exec(pc);
1207
1208 e->inst[0] = 0x30000000;
1209 e->inst[1] = 0xc4000000;
1210
1211 set_long(pc, e);
1212 set_dst(pc, dst, e);
1213 set_src_0(pc, src0, e);
1214
1215 if (src1->type == P_IMMD) {
1216 e->inst[1] |= (1 << 20);
1217 e->inst[0] |= (pc->immd_buf[src1->hw] & 0x7f) << 16;
1218 } else
1219 set_src_1(pc, src1, e);
1220
1221 if (dir != TGSI_OPCODE_SHL)
1222 e->inst[1] |= (1 << 29);
1223
1224 if (dir == TGSI_OPCODE_ISHR)
1225 e->inst[1] |= (1 << 27);
1226
1227 emit(pc, e);
1228 }
1229
1230 static void
1231 emit_shl_imm(struct nv50_pc *pc, struct nv50_reg *dst,
1232 struct nv50_reg *src, int s)
1233 {
1234 struct nv50_program_exec *e = exec(pc);
1235
1236 e->inst[0] = 0x30000000;
1237 e->inst[1] = 0xc4100000;
1238 if (s < 0) {
1239 e->inst[1] |= 1 << 29;
1240 s = -s;
1241 }
1242 e->inst[1] |= ((s & 0x7f) << 16);
1243
1244 set_long(pc, e);
1245 set_dst(pc, dst, e);
1246 set_src_0(pc, src, e);
1247
1248 emit(pc, e);
1249 }
1250
1251 static void
1252 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1253 struct nv50_reg *src1, struct nv50_reg *src2)
1254 {
1255 struct nv50_program_exec *e = exec(pc);
1256
1257 e->inst[0] |= 0xe0000000;
1258
1259 check_swap_src_0_1(pc, &src0, &src1);
1260 set_dst(pc, dst, e);
1261 set_src_0(pc, src0, e);
1262 set_src_1(pc, src1, e);
1263 set_src_2(pc, src2, e);
1264
1265 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1266 e->inst[1] |= 0x04000000;
1267 if (src2->mod & NV50_MOD_NEG)
1268 e->inst[1] |= 0x08000000;
1269
1270 emit(pc, e);
1271 }
1272
1273 static INLINE void
1274 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1275 struct nv50_reg *src1, struct nv50_reg *src2)
1276 {
1277 src2->mod ^= NV50_MOD_NEG;
1278 emit_mad(pc, dst, src0, src1, src2);
1279 src2->mod ^= NV50_MOD_NEG;
1280 }
1281
1282 #define NV50_FLOP_RCP 0
1283 #define NV50_FLOP_RSQ 2
1284 #define NV50_FLOP_LG2 3
1285 #define NV50_FLOP_SIN 4
1286 #define NV50_FLOP_COS 5
1287 #define NV50_FLOP_EX2 6
1288
1289 /* rcp, rsqrt, lg2 support neg and abs */
1290 static void
1291 emit_flop(struct nv50_pc *pc, unsigned sub,
1292 struct nv50_reg *dst, struct nv50_reg *src)
1293 {
1294 struct nv50_program_exec *e = exec(pc);
1295
1296 e->inst[0] |= 0x90000000;
1297 if (sub || src->mod) {
1298 set_long(pc, e);
1299 e->inst[1] |= (sub << 29);
1300 }
1301
1302 set_dst(pc, dst, e);
1303 set_src_0_restricted(pc, src, e);
1304
1305 assert(!src->mod || sub < 4);
1306
1307 if (src->mod & NV50_MOD_NEG)
1308 e->inst[1] |= 0x04000000;
1309 if (src->mod & NV50_MOD_ABS)
1310 e->inst[1] |= 0x00100000;
1311
1312 emit(pc, e);
1313 }
1314
1315 static void
1316 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1317 {
1318 struct nv50_program_exec *e = exec(pc);
1319
1320 e->inst[0] |= 0xb0000000;
1321
1322 set_dst(pc, dst, e);
1323 set_src_0(pc, src, e);
1324 set_long(pc, e);
1325 e->inst[1] |= (6 << 29) | 0x00004000;
1326
1327 if (src->mod & NV50_MOD_NEG)
1328 e->inst[1] |= 0x04000000;
1329 if (src->mod & NV50_MOD_ABS)
1330 e->inst[1] |= 0x00100000;
1331
1332 emit(pc, e);
1333 }
1334
1335 static void
1336 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1337 {
1338 struct nv50_program_exec *e = exec(pc);
1339
1340 e->inst[0] |= 0xb0000000;
1341
1342 set_dst(pc, dst, e);
1343 set_src_0(pc, src, e);
1344 set_long(pc, e);
1345 e->inst[1] |= (6 << 29);
1346
1347 if (src->mod & NV50_MOD_NEG)
1348 e->inst[1] |= 0x04000000;
1349 if (src->mod & NV50_MOD_ABS)
1350 e->inst[1] |= 0x00100000;
1351
1352 emit(pc, e);
1353 }
1354
1355 #define CVT_RN (0x00 << 16)
1356 #define CVT_FLOOR (0x02 << 16)
1357 #define CVT_CEIL (0x04 << 16)
1358 #define CVT_TRUNC (0x06 << 16)
1359 #define CVT_SAT (0x08 << 16)
1360 #define CVT_ABS (0x10 << 16)
1361
1362 #define CVT_X32_X32 0x04004000
1363 #define CVT_X32_S32 0x04014000
1364 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1365 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1366 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1367 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1368 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1369 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1370 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1371 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1372
1373 #define CVT_NEG 0x20000000
1374 #define CVT_RI 0x08000000
1375
1376 static void
1377 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1378 int wp, uint32_t cvn)
1379 {
1380 struct nv50_program_exec *e;
1381
1382 e = exec(pc);
1383
1384 if (src->mod & NV50_MOD_NEG) cvn |= CVT_NEG;
1385 if (src->mod & NV50_MOD_ABS) cvn |= CVT_ABS;
1386
1387 e->inst[0] = 0xa0000000;
1388 e->inst[1] = cvn;
1389 set_long(pc, e);
1390 set_src_0(pc, src, e);
1391
1392 if (wp >= 0)
1393 set_pred_wr(pc, 1, wp, e);
1394
1395 if (dst)
1396 set_dst(pc, dst, e);
1397 else {
1398 e->inst[0] |= 0x000001fc;
1399 e->inst[1] |= 0x00000008;
1400 }
1401
1402 emit(pc, e);
1403 }
1404
1405 /* nv50 Condition codes:
1406 * 0x1 = LT
1407 * 0x2 = EQ
1408 * 0x3 = LE
1409 * 0x4 = GT
1410 * 0x5 = NE
1411 * 0x6 = GE
1412 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1413 * 0x8 = unordered bit (allows NaN)
1414 *
1415 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1416 */
1417 static void
1418 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1419 struct nv50_reg *src0, struct nv50_reg *src1, uint8_t mode)
1420 {
1421 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1422
1423 struct nv50_program_exec *e = exec(pc);
1424 struct nv50_reg *rdst;
1425
1426 assert(ccode < 16);
1427 if (check_swap_src_0_1(pc, &src0, &src1))
1428 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1429
1430 rdst = dst;
1431 if (dst && dst->type != P_TEMP)
1432 dst = alloc_temp(pc, NULL);
1433
1434 set_long(pc, e);
1435 e->inst[0] |= 0x30000000 | (mode << 24);
1436 e->inst[1] |= 0x60000000 | (ccode << 14);
1437
1438 if (wp >= 0)
1439 set_pred_wr(pc, 1, wp, e);
1440 if (dst)
1441 set_dst(pc, dst, e);
1442 else {
1443 e->inst[0] |= 0x000001fc;
1444 e->inst[1] |= 0x00000008;
1445 }
1446
1447 set_src_0(pc, src0, e);
1448 set_src_1(pc, src1, e);
1449
1450 emit(pc, e);
1451
1452 if (rdst && mode == 0x80) /* convert to float ? */
1453 emit_cvt(pc, rdst, dst, -1, CVT_ABS | CVT_F32_S32);
1454 if (rdst && rdst != dst)
1455 free_temp(pc, dst);
1456 }
1457
1458 static INLINE void
1459 map_tgsi_setop_hw(unsigned op, uint8_t *cc, uint8_t *ty)
1460 {
1461 switch (op) {
1462 case TGSI_OPCODE_SLT: *cc = 0x1; *ty = 0x80; break;
1463 case TGSI_OPCODE_SGE: *cc = 0x6; *ty = 0x80; break;
1464 case TGSI_OPCODE_SEQ: *cc = 0x2; *ty = 0x80; break;
1465 case TGSI_OPCODE_SGT: *cc = 0x4; *ty = 0x80; break;
1466 case TGSI_OPCODE_SLE: *cc = 0x3; *ty = 0x80; break;
1467 case TGSI_OPCODE_SNE: *cc = 0xd; *ty = 0x80; break;
1468
1469 case TGSI_OPCODE_ISLT: *cc = 0x1; *ty = 0x0c; break;
1470 case TGSI_OPCODE_ISGE: *cc = 0x6; *ty = 0x0c; break;
1471 case TGSI_OPCODE_USEQ: *cc = 0x2; *ty = 0x04; break;
1472 case TGSI_OPCODE_USGE: *cc = 0x6; *ty = 0x04; break;
1473 case TGSI_OPCODE_USLT: *cc = 0x1; *ty = 0x04; break;
1474 case TGSI_OPCODE_USNE: *cc = 0x5; *ty = 0x04; break;
1475 default:
1476 assert(0);
1477 return;
1478 }
1479 }
1480
1481 static void
1482 emit_add_b32(struct nv50_pc *pc, struct nv50_reg *dst,
1483 struct nv50_reg *src0, struct nv50_reg *rsrc1)
1484 {
1485 struct nv50_program_exec *e = exec(pc);
1486 struct nv50_reg *src1;
1487
1488 e->inst[0] = 0x20000000;
1489
1490 alloc_reg(pc, rsrc1);
1491 check_swap_src_0_1(pc, &src0, &rsrc1);
1492
1493 src1 = rsrc1;
1494 if (src0->mod & rsrc1->mod & NV50_MOD_NEG) {
1495 src1 = temp_temp(pc, e);
1496 emit_cvt(pc, src1, rsrc1, -1, CVT_S32_S32);
1497 }
1498
1499 if (!pc->allow32 || src1->hw > 63 ||
1500 (src1->type != P_TEMP && src1->type != P_IMMD))
1501 set_long(pc, e);
1502
1503 set_dst(pc, dst, e);
1504 set_src_0(pc, src0, e);
1505
1506 if (is_long(e)) {
1507 e->inst[1] |= 1 << 26;
1508 set_src_2(pc, src1, e);
1509 } else {
1510 e->inst[0] |= 0x8000;
1511 if (src1->type == P_IMMD)
1512 set_immd(pc, src1, e);
1513 else
1514 set_src_1(pc, src1, e);
1515 }
1516
1517 if (src0->mod & NV50_MOD_NEG)
1518 e->inst[0] |= 1 << 28;
1519 else
1520 if (src1->mod & NV50_MOD_NEG)
1521 e->inst[0] |= 1 << 22;
1522
1523 emit(pc, e);
1524 }
1525
1526 static void
1527 emit_mad_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1528 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1,
1529 struct nv50_reg *src2)
1530 {
1531 struct nv50_program_exec *e = exec(pc);
1532
1533 e->inst[0] = 0x60000000;
1534 if (!pc->allow32)
1535 set_long(pc, e);
1536 set_dst(pc, dst, e);
1537
1538 set_half_src(pc, src0, lh_0, e, 9);
1539 set_half_src(pc, src1, lh_1, e, 16);
1540 alloc_reg(pc, src2);
1541 if (is_long(e) || (src2->type != P_TEMP) || (src2->hw != dst->hw))
1542 set_src_2(pc, src2, e);
1543
1544 emit(pc, e);
1545 }
1546
1547 static void
1548 emit_mul_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1549 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1)
1550 {
1551 struct nv50_program_exec *e = exec(pc);
1552
1553 e->inst[0] = 0x40000000;
1554 set_long(pc, e);
1555 set_dst(pc, dst, e);
1556
1557 set_half_src(pc, src0, lh_0, e, 9);
1558 set_half_src(pc, src1, lh_1, e, 16);
1559
1560 emit(pc, e);
1561 }
1562
1563 static void
1564 emit_sad(struct nv50_pc *pc, struct nv50_reg *dst,
1565 struct nv50_reg *src0, struct nv50_reg *src1, struct nv50_reg *src2)
1566 {
1567 struct nv50_program_exec *e = exec(pc);
1568
1569 e->inst[0] = 0x50000000;
1570 if (!pc->allow32)
1571 set_long(pc, e);
1572 check_swap_src_0_1(pc, &src0, &src1);
1573 set_dst(pc, dst, e);
1574 set_src_0(pc, src0, e);
1575 set_src_1(pc, src1, e);
1576 alloc_reg(pc, src2);
1577 if (is_long(e) || (src2->type != dst->type) || (src2->hw != dst->hw))
1578 set_src_2(pc, src2, e);
1579
1580 if (is_long(e))
1581 e->inst[1] |= 0x0c << 24;
1582 else
1583 e->inst[0] |= 0x81 << 8;
1584
1585 emit(pc, e);
1586 }
1587
1588 static INLINE void
1589 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1590 {
1591 emit_cvt(pc, dst, src, -1, CVT_FLOOR | CVT_F32_F32 | CVT_RI);
1592 }
1593
1594 static void
1595 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1596 struct nv50_reg *v, struct nv50_reg *e)
1597 {
1598 struct nv50_reg *temp = alloc_temp(pc, NULL);
1599
1600 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1601 emit_mul(pc, temp, temp, e);
1602 emit_preex2(pc, temp, temp);
1603 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1604
1605 free_temp(pc, temp);
1606 }
1607
1608 static INLINE void
1609 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1610 {
1611 emit_cvt(pc, dst, src, -1, CVT_SAT | CVT_F32_F32);
1612 }
1613
1614 static void
1615 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1616 struct nv50_reg **src)
1617 {
1618 struct nv50_reg *one = alloc_immd(pc, 1.0);
1619 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1620 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1621 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1622 struct nv50_reg *tmp[4] = { 0 };
1623 boolean allow32 = pc->allow32;
1624
1625 pc->allow32 = FALSE;
1626
1627 if (mask & (3 << 1)) {
1628 tmp[0] = alloc_temp(pc, NULL);
1629 emit_minmax(pc, NV50_MAX_F32, tmp[0], src[0], zero);
1630 }
1631
1632 if (mask & (1 << 2)) {
1633 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1634
1635 tmp[1] = temp_temp(pc, NULL);
1636 emit_minmax(pc, NV50_MAX_F32, tmp[1], src[1], zero);
1637
1638 tmp[3] = temp_temp(pc, NULL);
1639 emit_minmax(pc, NV50_MAX_F32, tmp[3], src[3], neg128);
1640 emit_minmax(pc, NV50_MIN_F32, tmp[3], tmp[3], pos128);
1641
1642 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1643 emit_mov(pc, dst[2], zero);
1644 set_pred(pc, 3, 0, pc->p->exec_tail);
1645 }
1646
1647 if (mask & (1 << 1))
1648 assimilate_temp(pc, dst[1], tmp[0]);
1649 else
1650 if (mask & (1 << 2))
1651 free_temp(pc, tmp[0]);
1652
1653 pc->allow32 = allow32;
1654
1655 /* do this last, in case src[i,j] == dst[0,3] */
1656 if (mask & (1 << 0))
1657 emit_mov(pc, dst[0], one);
1658
1659 if (mask & (1 << 3))
1660 emit_mov(pc, dst[3], one);
1661
1662 FREE(pos128);
1663 FREE(neg128);
1664 FREE(zero);
1665 FREE(one);
1666 }
1667
1668 static void
1669 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1670 {
1671 struct nv50_program_exec *e;
1672 const int r_pred = 1;
1673
1674 e = exec(pc);
1675 e->inst[0] = 0x00000002; /* discard */
1676 set_long(pc, e); /* sets cond code to ALWAYS */
1677
1678 if (src) {
1679 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1680 /* write to predicate reg */
1681 emit_cvt(pc, NULL, src, r_pred, CVT_F32_F32);
1682 }
1683
1684 emit(pc, e);
1685 }
1686
1687 static struct nv50_program_exec *
1688 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1689 {
1690 struct nv50_program_exec *e = exec(pc);
1691
1692 e->inst[0] = (op << 28) | 2;
1693 set_long(pc, e);
1694 if (pred >= 0)
1695 set_pred(pc, cc, pred, e);
1696
1697 emit(pc, e);
1698 return e;
1699 }
1700
1701 static INLINE struct nv50_program_exec *
1702 emit_breakaddr(struct nv50_pc *pc)
1703 {
1704 return emit_control_flow(pc, 0x4, -1, 0);
1705 }
1706
1707 static INLINE void
1708 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1709 {
1710 emit_control_flow(pc, 0x5, pred, cc);
1711 }
1712
1713 static INLINE struct nv50_program_exec *
1714 emit_joinat(struct nv50_pc *pc)
1715 {
1716 return emit_control_flow(pc, 0xa, -1, 0);
1717 }
1718
1719 static INLINE struct nv50_program_exec *
1720 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1721 {
1722 return emit_control_flow(pc, 0x1, pred, cc);
1723 }
1724
1725 static INLINE struct nv50_program_exec *
1726 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1727 {
1728 return emit_control_flow(pc, 0x2, pred, cc);
1729 }
1730
1731 static INLINE void
1732 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1733 {
1734 emit_control_flow(pc, 0x3, pred, cc);
1735 }
1736
1737 static void
1738 emit_prim_cmd(struct nv50_pc *pc, unsigned cmd)
1739 {
1740 struct nv50_program_exec *e = exec(pc);
1741
1742 e->inst[0] = 0xf0000000 | (cmd << 9);
1743 e->inst[1] = 0xc0000000;
1744 set_long(pc, e);
1745
1746 emit(pc, e);
1747 }
1748
1749 #define QOP_ADD 0
1750 #define QOP_SUBR 1
1751 #define QOP_SUB 2
1752 #define QOP_MOV_SRC1 3
1753
1754 /* For a quad of threads / top left, top right, bottom left, bottom right
1755 * pixels, do a different operation, and take src0 from a specific thread.
1756 */
1757 static void
1758 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1759 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1760 {
1761 struct nv50_program_exec *e = exec(pc);
1762
1763 e->inst[0] = 0xc0000000;
1764 e->inst[1] = 0x80000000;
1765 set_long(pc, e);
1766 e->inst[0] |= lane_src0 << 16;
1767 set_src_0(pc, src0, e);
1768 set_src_2(pc, src1, e);
1769
1770 if (wp >= 0)
1771 set_pred_wr(pc, 1, wp, e);
1772
1773 if (dst)
1774 set_dst(pc, dst, e);
1775 else {
1776 e->inst[0] |= 0x000001fc;
1777 e->inst[1] |= 0x00000008;
1778 }
1779
1780 e->inst[0] |= (qop & 3) << 20;
1781 e->inst[1] |= (qop >> 2) << 22;
1782
1783 emit(pc, e);
1784 }
1785
1786 static void
1787 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1788 struct nv50_reg **src, unsigned arg, boolean proj)
1789 {
1790 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1791
1792 src[0]->mod |= NV50_MOD_ABS;
1793 src[1]->mod |= NV50_MOD_ABS;
1794 src[2]->mod |= NV50_MOD_ABS;
1795
1796 emit_minmax(pc, NV50_MAX_F32, t[2], src[0], src[1]);
1797 emit_minmax(pc, NV50_MAX_F32, t[2], src[2], t[2]);
1798
1799 src[0]->mod = mod[0];
1800 src[1]->mod = mod[1];
1801 src[2]->mod = mod[2];
1802
1803 if (proj && 0 /* looks more correct without this */)
1804 emit_mul(pc, t[2], t[2], src[3]);
1805 else
1806 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1807 emit_mov(pc, t[3], src[3]);
1808
1809 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1810
1811 emit_mul(pc, t[0], src[0], t[2]);
1812 emit_mul(pc, t[1], src[1], t[2]);
1813 emit_mul(pc, t[2], src[2], t[2]);
1814 }
1815
1816 static void
1817 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1818 struct nv50_reg **src, unsigned dim, unsigned arg)
1819 {
1820 unsigned c, mode;
1821
1822 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1823 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1824
1825 t[3]->rhw = src[3]->rhw;
1826 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1827 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1828
1829 for (c = 0; c < dim; ++c) {
1830 t[c]->rhw = src[c]->rhw;
1831 emit_interp(pc, t[c], t[3], mode);
1832 }
1833 if (arg != dim) { /* depth reference value */
1834 t[dim]->rhw = src[2]->rhw;
1835 emit_interp(pc, t[dim], t[3], mode);
1836 }
1837 } else {
1838 /* XXX: for some reason the blob sometimes uses MAD
1839 * (mad f32 $rX $rY $rZ neg $r63)
1840 */
1841 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1842 for (c = 0; c < dim; ++c)
1843 emit_mul(pc, t[c], src[c], t[3]);
1844 if (arg != dim) /* depth reference value */
1845 emit_mul(pc, t[dim], src[2], t[3]);
1846 }
1847 }
1848
1849 static INLINE void
1850 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1851 {
1852 switch (type) {
1853 case TGSI_TEXTURE_1D:
1854 *arg = *dim = 1;
1855 break;
1856 case TGSI_TEXTURE_SHADOW1D:
1857 *dim = 1;
1858 *arg = 2;
1859 break;
1860 case TGSI_TEXTURE_UNKNOWN:
1861 case TGSI_TEXTURE_2D:
1862 case TGSI_TEXTURE_RECT:
1863 *arg = *dim = 2;
1864 break;
1865 case TGSI_TEXTURE_SHADOW2D:
1866 case TGSI_TEXTURE_SHADOWRECT:
1867 *dim = 2;
1868 *arg = 3;
1869 break;
1870 case TGSI_TEXTURE_3D:
1871 case TGSI_TEXTURE_CUBE:
1872 *dim = *arg = 3;
1873 break;
1874 default:
1875 assert(0);
1876 break;
1877 }
1878 }
1879
1880 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1881 * different LOD values, so branch off groups of equal LOD.
1882 */
1883 static void
1884 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1885 struct nv50_reg *src, struct nv50_program_exec *tex)
1886 {
1887 struct nv50_program_exec *join_at;
1888 unsigned i, target = pc->p->exec_size + 9 * 2;
1889
1890 if (pc->p->type != PIPE_SHADER_FRAGMENT) {
1891 emit(pc, tex);
1892 return;
1893 }
1894 pc->allow32 = FALSE;
1895
1896 /* Subtract lod of each pixel from lod of top left pixel, jump
1897 * texlod insn if result is 0, then repeat for 2 other pixels.
1898 */
1899 join_at = emit_joinat(pc);
1900 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1901 emit_branch(pc, 0, 2)->param.index = target;
1902
1903 for (i = 1; i < 4; ++i) {
1904 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1905 emit_branch(pc, 0, 2)->param.index = target;
1906 }
1907
1908 emit_mov(pc, tlod, src); /* target */
1909 emit(pc, tex); /* texlod */
1910
1911 join_at->param.index = target + 2 * 2;
1912 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1913 }
1914
1915 static void
1916 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1917 struct nv50_program_exec *tex)
1918 {
1919 struct nv50_program_exec *e;
1920 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1921 int r_pred = 0;
1922 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1923
1924 pc->allow32 = FALSE;
1925 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1926
1927 /* Subtract bias value of thread i from bias values of each thread,
1928 * store result in r_pred, and set bit i in r_bits if result was 0.
1929 */
1930 assert(arg < 4);
1931 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1932 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1933 emit_mov(pc, r_bits, &imm_1248);
1934 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1935 }
1936 emit_mov_to_pred(pc, r_pred, r_bits);
1937
1938 /* The lanes of a quad are now grouped by the bit in r_pred they have
1939 * set. Put the input values for TEX into a new register set for each
1940 * group and execute TEX only for a specific group.
1941 * We cannot use the same register set for each group because we need
1942 * the derivatives, which are implicitly calculated, to be correct.
1943 */
1944 for (i = 1; i < 4; ++i) {
1945 alloc_temp4(pc, t123[i], 0);
1946
1947 for (c = 0; c <= arg; ++c)
1948 emit_mov(pc, t123[i][c], t[c]);
1949
1950 *(e = exec(pc)) = *(tex);
1951 e->inst[0] &= ~0x01fc;
1952 set_dst(pc, t123[i][0], e);
1953 set_pred(pc, cc[i], r_pred, e);
1954 emit(pc, e);
1955 }
1956 /* finally TEX on the original regs (where we kept the input) */
1957 set_pred(pc, cc[0], r_pred, tex);
1958 emit(pc, tex);
1959
1960 /* put the 3 * n other results into regs for lane 0 */
1961 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1962 for (i = 1; i < 4; ++i) {
1963 for (c = 0; c < n; ++c) {
1964 emit_mov(pc, t[c], t123[i][c]);
1965 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1966 }
1967 free_temp4(pc, t123[i]);
1968 }
1969
1970 emit_nop(pc);
1971 free_temp(pc, r_bits);
1972 }
1973
1974 static void
1975 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1976 struct nv50_reg **src, unsigned unit, unsigned type,
1977 boolean proj, int bias_lod)
1978 {
1979 struct nv50_reg *t[4];
1980 struct nv50_program_exec *e;
1981 unsigned c, dim, arg;
1982
1983 /* t[i] must be within a single 128 bit super-reg */
1984 alloc_temp4(pc, t, 0);
1985
1986 e = exec(pc);
1987 e->inst[0] = 0xf0000000;
1988 set_long(pc, e);
1989 set_dst(pc, t[0], e);
1990
1991 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1992 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1993
1994 /* live flag (don't set if TEX results affect input to another TEX): */
1995 /* e->inst[0] |= 0x00000004; */
1996
1997 get_tex_dim(type, &dim, &arg);
1998
1999 if (type == TGSI_TEXTURE_CUBE) {
2000 e->inst[0] |= 0x08000000;
2001 load_cube_tex_coords(pc, t, src, arg, proj);
2002 } else
2003 if (proj)
2004 load_proj_tex_coords(pc, t, src, dim, arg);
2005 else {
2006 for (c = 0; c < dim; c++)
2007 emit_mov(pc, t[c], src[c]);
2008 if (arg != dim) /* depth reference value (always src.z here) */
2009 emit_mov(pc, t[dim], src[2]);
2010 }
2011
2012 e->inst[0] |= (mask & 0x3) << 25;
2013 e->inst[1] |= (mask & 0xc) << 12;
2014
2015 if (!bias_lod) {
2016 e->inst[0] |= (arg - 1) << 22;
2017 emit(pc, e);
2018 } else
2019 if (bias_lod < 0) {
2020 assert(pc->p->type == PIPE_SHADER_FRAGMENT);
2021 e->inst[0] |= arg << 22;
2022 e->inst[1] |= 0x20000000; /* texbias */
2023 emit_mov(pc, t[arg], src[3]);
2024 emit_texbias_sequence(pc, t, arg, e);
2025 } else {
2026 e->inst[0] |= arg << 22;
2027 e->inst[1] |= 0x40000000; /* texlod */
2028 emit_mov(pc, t[arg], src[3]);
2029 emit_texlod_sequence(pc, t[arg], src[3], e);
2030 }
2031
2032 #if 1
2033 c = 0;
2034 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
2035 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
2036 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
2037 if (mask & 8) emit_mov(pc, dst[3], t[c]);
2038
2039 free_temp4(pc, t);
2040 #else
2041 /* XXX: if p.e. MUL is used directly after TEX, it would still use
2042 * the texture coordinates, not the fetched values: latency ? */
2043
2044 for (c = 0; c < 4; c++) {
2045 if (mask & (1 << c))
2046 assimilate_temp(pc, dst[c], t[c]);
2047 else
2048 free_temp(pc, t[c]);
2049 }
2050 #endif
2051 }
2052
2053 static void
2054 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2055 {
2056 struct nv50_program_exec *e = exec(pc);
2057
2058 assert(src->type == P_TEMP);
2059
2060 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
2061 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
2062 set_long(pc, e);
2063 set_dst(pc, dst, e);
2064 set_src_0(pc, src, e);
2065 set_src_2(pc, src, e);
2066
2067 emit(pc, e);
2068 }
2069
2070 static void
2071 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2072 {
2073 struct nv50_program_exec *e = exec(pc);
2074
2075 assert(src->type == P_TEMP);
2076
2077 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
2078 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
2079 set_long(pc, e);
2080 set_dst(pc, dst, e);
2081 set_src_0(pc, src, e);
2082 set_src_2(pc, src, e);
2083
2084 emit(pc, e);
2085 }
2086
2087 static void
2088 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
2089 {
2090 unsigned q = 0, m = ~0;
2091
2092 assert(!is_long(e));
2093
2094 switch (e->inst[0] >> 28) {
2095 case 0x1:
2096 /* MOV */
2097 q = 0x0403c000;
2098 m = 0xffff7fff;
2099 break;
2100 case 0x2:
2101 case 0x3:
2102 /* ADD, SUB, SUBR b32 */
2103 m = ~(0x8000 | (127 << 16));
2104 q = ((e->inst[0] & (~m)) >> 2) | (1 << 26);
2105 break;
2106 case 0x5:
2107 /* SAD */
2108 m = ~(0x81 << 8);
2109 q = (0x0c << 24) | ((e->inst[0] & (0x7f << 2)) << 12);
2110 break;
2111 case 0x6:
2112 /* MAD u16 */
2113 q = (e->inst[0] & (0x7f << 2)) << 12;
2114 break;
2115 case 0x8:
2116 /* INTERP (move centroid, perspective and flat bits) */
2117 m = ~0x03000100;
2118 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
2119 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
2120 break;
2121 case 0x9:
2122 /* RCP */
2123 break;
2124 case 0xB:
2125 /* ADD */
2126 m = ~(127 << 16);
2127 q = ((e->inst[0] & (~m)) >> 2);
2128 break;
2129 case 0xC:
2130 /* MUL */
2131 m = ~0x00008000;
2132 q = ((e->inst[0] & (~m)) << 12);
2133 break;
2134 case 0xE:
2135 /* MAD (if src2 == dst) */
2136 q = ((e->inst[0] & 0x1fc) << 12);
2137 break;
2138 default:
2139 assert(0);
2140 break;
2141 }
2142
2143 set_long(pc, e);
2144 pc->p->exec_size++;
2145
2146 e->inst[0] &= m;
2147 e->inst[1] |= q;
2148 }
2149
2150 /* Some operations support an optional negation flag. */
2151 static int
2152 get_supported_mods(const struct tgsi_full_instruction *insn, int i)
2153 {
2154 switch (insn->Instruction.Opcode) {
2155 case TGSI_OPCODE_ADD:
2156 case TGSI_OPCODE_COS:
2157 case TGSI_OPCODE_DDX:
2158 case TGSI_OPCODE_DDY:
2159 case TGSI_OPCODE_DP3:
2160 case TGSI_OPCODE_DP4:
2161 case TGSI_OPCODE_EX2:
2162 case TGSI_OPCODE_KIL:
2163 case TGSI_OPCODE_LG2:
2164 case TGSI_OPCODE_MAD:
2165 case TGSI_OPCODE_MUL:
2166 case TGSI_OPCODE_POW:
2167 case TGSI_OPCODE_RCP:
2168 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
2169 case TGSI_OPCODE_SCS:
2170 case TGSI_OPCODE_SIN:
2171 case TGSI_OPCODE_SUB:
2172 return NV50_MOD_NEG;
2173 case TGSI_OPCODE_MAX:
2174 case TGSI_OPCODE_MIN:
2175 case TGSI_OPCODE_INEG: /* tgsi src sign toggle/set would be stupid */
2176 return NV50_MOD_ABS;
2177 case TGSI_OPCODE_CEIL:
2178 case TGSI_OPCODE_FLR:
2179 case TGSI_OPCODE_TRUNC:
2180 return NV50_MOD_NEG | NV50_MOD_ABS;
2181 case TGSI_OPCODE_F2I:
2182 case TGSI_OPCODE_F2U:
2183 case TGSI_OPCODE_I2F:
2184 case TGSI_OPCODE_U2F:
2185 return NV50_MOD_NEG | NV50_MOD_ABS | NV50_MOD_I32;
2186 case TGSI_OPCODE_UADD:
2187 return NV50_MOD_NEG | NV50_MOD_I32;
2188 case TGSI_OPCODE_SAD:
2189 case TGSI_OPCODE_SHL:
2190 case TGSI_OPCODE_IMAX:
2191 case TGSI_OPCODE_IMIN:
2192 case TGSI_OPCODE_ISHR:
2193 case TGSI_OPCODE_NOT:
2194 case TGSI_OPCODE_UMAD:
2195 case TGSI_OPCODE_UMAX:
2196 case TGSI_OPCODE_UMIN:
2197 case TGSI_OPCODE_UMUL:
2198 case TGSI_OPCODE_USHR:
2199 return NV50_MOD_I32;
2200 default:
2201 return 0;
2202 }
2203 }
2204
2205 /* Return a read mask for source registers deduced from opcode & write mask. */
2206 static unsigned
2207 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
2208 {
2209 unsigned x, mask = insn->Dst[0].Register.WriteMask;
2210
2211 switch (insn->Instruction.Opcode) {
2212 case TGSI_OPCODE_COS:
2213 case TGSI_OPCODE_SIN:
2214 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
2215 case TGSI_OPCODE_DP3:
2216 return 0x7;
2217 case TGSI_OPCODE_DP4:
2218 case TGSI_OPCODE_DPH:
2219 case TGSI_OPCODE_KIL: /* WriteMask ignored */
2220 return 0xf;
2221 case TGSI_OPCODE_DST:
2222 return mask & (c ? 0xa : 0x6);
2223 case TGSI_OPCODE_EX2:
2224 case TGSI_OPCODE_EXP:
2225 case TGSI_OPCODE_LG2:
2226 case TGSI_OPCODE_LOG:
2227 case TGSI_OPCODE_POW:
2228 case TGSI_OPCODE_RCP:
2229 case TGSI_OPCODE_RSQ:
2230 case TGSI_OPCODE_SCS:
2231 return 0x1;
2232 case TGSI_OPCODE_IF:
2233 return 0x1;
2234 case TGSI_OPCODE_LIT:
2235 return 0xb;
2236 case TGSI_OPCODE_TEX:
2237 case TGSI_OPCODE_TXB:
2238 case TGSI_OPCODE_TXL:
2239 case TGSI_OPCODE_TXP:
2240 {
2241 const struct tgsi_instruction_texture *tex;
2242
2243 assert(insn->Instruction.Texture);
2244 tex = &insn->Texture;
2245
2246 mask = 0x7;
2247 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
2248 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
2249 mask |= 0x8; /* bias, lod or proj */
2250
2251 switch (tex->Texture) {
2252 case TGSI_TEXTURE_1D:
2253 mask &= 0x9;
2254 break;
2255 case TGSI_TEXTURE_SHADOW1D:
2256 mask &= 0x5;
2257 break;
2258 case TGSI_TEXTURE_2D:
2259 mask &= 0xb;
2260 break;
2261 default:
2262 break;
2263 }
2264 }
2265 return mask;
2266 case TGSI_OPCODE_XPD:
2267 x = 0;
2268 if (mask & 1) x |= 0x6;
2269 if (mask & 2) x |= 0x5;
2270 if (mask & 4) x |= 0x3;
2271 return x;
2272 default:
2273 break;
2274 }
2275
2276 return mask;
2277 }
2278
2279 static struct nv50_reg *
2280 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
2281 {
2282 switch (dst->Register.File) {
2283 case TGSI_FILE_TEMPORARY:
2284 return &pc->temp[dst->Register.Index * 4 + c];
2285 case TGSI_FILE_OUTPUT:
2286 return &pc->result[dst->Register.Index * 4 + c];
2287 case TGSI_FILE_ADDRESS:
2288 {
2289 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
2290 if (!r) {
2291 r = get_address_reg(pc, NULL);
2292 r->index = dst->Register.Index * 4 + c;
2293 pc->addr[r->index] = r;
2294 }
2295 assert(r);
2296 return r;
2297 }
2298 case TGSI_FILE_NULL:
2299 return NULL;
2300 case TGSI_FILE_SYSTEM_VALUE:
2301 assert(pc->sysval[dst->Register.Index].type == P_RESULT);
2302 assert(c == 0);
2303 return &pc->sysval[dst->Register.Index];
2304 default:
2305 break;
2306 }
2307
2308 return NULL;
2309 }
2310
2311 static struct nv50_reg *
2312 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
2313 int mod)
2314 {
2315 struct nv50_reg *r = NULL;
2316 struct nv50_reg *temp = NULL;
2317 unsigned sgn, c, swz, cvn;
2318
2319 if (src->Register.File != TGSI_FILE_CONSTANT)
2320 assert(!src->Register.Indirect);
2321
2322 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
2323
2324 c = tgsi_util_get_full_src_register_swizzle(src, chan);
2325 switch (c) {
2326 case TGSI_SWIZZLE_X:
2327 case TGSI_SWIZZLE_Y:
2328 case TGSI_SWIZZLE_Z:
2329 case TGSI_SWIZZLE_W:
2330 switch (src->Register.File) {
2331 case TGSI_FILE_INPUT:
2332 r = &pc->attr[src->Register.Index * 4 + c];
2333
2334 if (!src->Dimension.Dimension)
2335 break;
2336 r = reg_instance(pc, r);
2337 r->vtx = src->Dimension.Index;
2338
2339 if (!src->Dimension.Indirect)
2340 break;
2341 swz = tgsi_util_get_src_register_swizzle(
2342 &src->DimIndirect, 0);
2343 r->acc = -1;
2344 r->indirect[1] = src->DimIndirect.Index * 4 + swz;
2345 break;
2346 case TGSI_FILE_TEMPORARY:
2347 r = &pc->temp[src->Register.Index * 4 + c];
2348 break;
2349 case TGSI_FILE_CONSTANT:
2350 if (!src->Register.Indirect) {
2351 r = &pc->param[src->Register.Index * 4 + c];
2352 break;
2353 }
2354 /* Indicate indirection by setting r->acc < 0 and
2355 * use the index field to select the address reg.
2356 */
2357 r = reg_instance(pc, NULL);
2358 ctor_reg(r, P_CONST, -1, src->Register.Index * 4 + c);
2359
2360 swz = tgsi_util_get_src_register_swizzle(
2361 &src->Indirect, 0);
2362 r->acc = -1;
2363 r->indirect[0] = src->Indirect.Index * 4 + swz;
2364 break;
2365 case TGSI_FILE_IMMEDIATE:
2366 r = &pc->immd[src->Register.Index * 4 + c];
2367 break;
2368 case TGSI_FILE_SAMPLER:
2369 return NULL;
2370 case TGSI_FILE_ADDRESS:
2371 r = pc->addr[src->Register.Index * 4 + c];
2372 assert(r);
2373 break;
2374 case TGSI_FILE_SYSTEM_VALUE:
2375 assert(c == 0);
2376 r = &pc->sysval[src->Register.Index];
2377 break;
2378 default:
2379 assert(0);
2380 break;
2381 }
2382 break;
2383 default:
2384 assert(0);
2385 break;
2386 }
2387
2388 cvn = (mod & NV50_MOD_I32) ? CVT_S32_S32 : CVT_F32_F32;
2389
2390 switch (sgn) {
2391 case TGSI_UTIL_SIGN_CLEAR:
2392 r->mod = NV50_MOD_ABS;
2393 break;
2394 case TGSI_UTIL_SIGN_SET:
2395 r->mod = NV50_MOD_NEG_ABS;
2396 break;
2397 case TGSI_UTIL_SIGN_TOGGLE:
2398 r->mod = NV50_MOD_NEG;
2399 break;
2400 default:
2401 assert(!r->mod && sgn == TGSI_UTIL_SIGN_KEEP);
2402 break;
2403 }
2404
2405 if ((r->mod & mod) != r->mod) {
2406 temp = temp_temp(pc, NULL);
2407 emit_cvt(pc, temp, r, -1, cvn);
2408 r->mod = 0;
2409 r = temp;
2410 } else
2411 r->mod |= mod & NV50_MOD_I32;
2412
2413 assert(r);
2414 if (r->acc >= 0 && r->vtx < 0 && r != temp)
2415 return reg_instance(pc, r); /* will clear r->mod */
2416 return r;
2417 }
2418
2419 /* return TRUE for ops that produce only a single result */
2420 static boolean
2421 is_scalar_op(unsigned op)
2422 {
2423 switch (op) {
2424 case TGSI_OPCODE_COS:
2425 case TGSI_OPCODE_DP2:
2426 case TGSI_OPCODE_DP3:
2427 case TGSI_OPCODE_DP4:
2428 case TGSI_OPCODE_DPH:
2429 case TGSI_OPCODE_EX2:
2430 case TGSI_OPCODE_LG2:
2431 case TGSI_OPCODE_POW:
2432 case TGSI_OPCODE_RCP:
2433 case TGSI_OPCODE_RSQ:
2434 case TGSI_OPCODE_SIN:
2435 /*
2436 case TGSI_OPCODE_KIL:
2437 case TGSI_OPCODE_LIT:
2438 case TGSI_OPCODE_SCS:
2439 */
2440 return TRUE;
2441 default:
2442 return FALSE;
2443 }
2444 }
2445
2446 /* Returns a bitmask indicating which dst components depend
2447 * on source s, component c (reverse of nv50_tgsi_src_mask).
2448 */
2449 static unsigned
2450 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2451 {
2452 if (is_scalar_op(op))
2453 return 0x1;
2454
2455 switch (op) {
2456 case TGSI_OPCODE_DST:
2457 return (1 << c) & (s ? 0xa : 0x6);
2458 case TGSI_OPCODE_XPD:
2459 switch (c) {
2460 case 0: return 0x6;
2461 case 1: return 0x5;
2462 case 2: return 0x3;
2463 case 3: return 0x0;
2464 default:
2465 assert(0);
2466 return 0x0;
2467 }
2468 case TGSI_OPCODE_EXP:
2469 case TGSI_OPCODE_LOG:
2470 case TGSI_OPCODE_LIT:
2471 case TGSI_OPCODE_SCS:
2472 case TGSI_OPCODE_TEX:
2473 case TGSI_OPCODE_TXB:
2474 case TGSI_OPCODE_TXL:
2475 case TGSI_OPCODE_TXP:
2476 /* these take care of dangerous swizzles themselves */
2477 return 0x0;
2478 case TGSI_OPCODE_IF:
2479 case TGSI_OPCODE_KIL:
2480 /* don't call this function for these ops */
2481 assert(0);
2482 return 0;
2483 default:
2484 /* linear vector instruction */
2485 return (1 << c);
2486 }
2487 }
2488
2489 static INLINE boolean
2490 has_pred(struct nv50_program_exec *e, unsigned cc)
2491 {
2492 if (!is_long(e) || is_immd(e))
2493 return FALSE;
2494 return ((e->inst[1] & 0x780) == (cc << 7));
2495 }
2496
2497 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2498 * join_at ENDIF
2499 * @p0.eq bra ENDIF
2500 * single_op
2501 * ENDIF: nop.join
2502 */
2503 static boolean
2504 nv50_kill_branch(struct nv50_pc *pc)
2505 {
2506 int lvl = pc->if_lvl;
2507
2508 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2509 return FALSE;
2510 if (is_immd(pc->p->exec_tail))
2511 return FALSE;
2512
2513 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2514 * reg may no longer be valid, since we currently always use $p0
2515 */
2516 if (has_pred(pc->if_insn[lvl], 0xf))
2517 return FALSE;
2518 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2519
2520 /* We'll use the exec allocated for JOIN_AT (we can't easily
2521 * access nv50_program_exec's prev).
2522 */
2523 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2524
2525 *pc->if_join[lvl] = *pc->p->exec_tail;
2526
2527 FREE(pc->if_insn[lvl]);
2528 FREE(pc->p->exec_tail);
2529
2530 pc->p->exec_tail = pc->if_join[lvl];
2531 pc->p->exec_tail->next = NULL;
2532 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2533
2534 return TRUE;
2535 }
2536
2537 static void
2538 nv50_fp_move_results(struct nv50_pc *pc)
2539 {
2540 struct nv50_reg reg;
2541 unsigned i;
2542
2543 ctor_reg(&reg, P_TEMP, -1, -1);
2544
2545 for (i = 0; i < pc->result_nr * 4; ++i) {
2546 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2547 continue;
2548 if (pc->result[i].rhw != pc->result[i].hw) {
2549 reg.hw = pc->result[i].rhw;
2550 emit_mov(pc, &reg, &pc->result[i]);
2551 }
2552 }
2553 }
2554
2555 static boolean
2556 nv50_program_tx_insn(struct nv50_pc *pc,
2557 const struct tgsi_full_instruction *inst)
2558 {
2559 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2560 unsigned mask, sat, unit = 0;
2561 int i, c;
2562
2563 mask = inst->Dst[0].Register.WriteMask;
2564 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2565
2566 memset(src, 0, sizeof(src));
2567
2568 for (c = 0; c < 4; c++) {
2569 if ((mask & (1 << c)) && !pc->r_dst[c])
2570 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2571 else
2572 dst[c] = pc->r_dst[c];
2573 rdst[c] = dst[c];
2574 }
2575
2576 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2577 const struct tgsi_full_src_register *fs = &inst->Src[i];
2578 unsigned src_mask;
2579 int mod_supp;
2580
2581 src_mask = nv50_tgsi_src_mask(inst, i);
2582 mod_supp = get_supported_mods(inst, i);
2583
2584 if (fs->Register.File == TGSI_FILE_SAMPLER)
2585 unit = fs->Register.Index;
2586
2587 for (c = 0; c < 4; c++)
2588 if (src_mask & (1 << c))
2589 src[i][c] = tgsi_src(pc, c, fs, mod_supp);
2590 }
2591
2592 brdc = temp = pc->r_brdc;
2593 if (brdc && brdc->type != P_TEMP) {
2594 temp = temp_temp(pc, NULL);
2595 if (sat)
2596 brdc = temp;
2597 } else
2598 if (sat) {
2599 for (c = 0; c < 4; c++) {
2600 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2601 continue;
2602 /* rdst[c] = dst[c]; */ /* done above */
2603 dst[c] = temp_temp(pc, NULL);
2604 }
2605 }
2606
2607 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2608
2609 switch (inst->Instruction.Opcode) {
2610 case TGSI_OPCODE_ABS:
2611 for (c = 0; c < 4; c++) {
2612 if (!(mask & (1 << c)))
2613 continue;
2614 emit_cvt(pc, dst[c], src[0][c], -1,
2615 CVT_ABS | CVT_F32_F32);
2616 }
2617 break;
2618 case TGSI_OPCODE_ADD:
2619 for (c = 0; c < 4; c++) {
2620 if (!(mask & (1 << c)))
2621 continue;
2622 emit_add(pc, dst[c], src[0][c], src[1][c]);
2623 }
2624 break;
2625 case TGSI_OPCODE_AND:
2626 case TGSI_OPCODE_XOR:
2627 case TGSI_OPCODE_OR:
2628 for (c = 0; c < 4; c++) {
2629 if (!(mask & (1 << c)))
2630 continue;
2631 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2632 inst->Instruction.Opcode);
2633 }
2634 break;
2635 case TGSI_OPCODE_ARL:
2636 temp = temp_temp(pc, NULL);
2637 for (c = 0; c < 4; c++) {
2638 if (!(mask & (1 << c)))
2639 continue;
2640 emit_cvt(pc, temp, src[0][c], -1,
2641 CVT_FLOOR | CVT_S32_F32);
2642 emit_arl(pc, dst[c], temp, 4);
2643 }
2644 break;
2645 case TGSI_OPCODE_BGNLOOP:
2646 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2647 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2648 terminate_mbb(pc);
2649 break;
2650 case TGSI_OPCODE_BGNSUB:
2651 assert(!pc->in_subroutine);
2652 pc->in_subroutine = TRUE;
2653 /* probably not necessary, but align to 8 byte boundary */
2654 if (!is_long(pc->p->exec_tail))
2655 convert_to_long(pc, pc->p->exec_tail);
2656 break;
2657 case TGSI_OPCODE_BRK:
2658 assert(pc->loop_lvl > 0);
2659 emit_break(pc, -1, 0);
2660 break;
2661 case TGSI_OPCODE_CAL:
2662 assert(inst->Label.Label < pc->insn_nr);
2663 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2664 /* replaced by actual offset in nv50_program_fixup_insns */
2665 break;
2666 case TGSI_OPCODE_CEIL:
2667 for (c = 0; c < 4; c++) {
2668 if (!(mask & (1 << c)))
2669 continue;
2670 emit_cvt(pc, dst[c], src[0][c], -1,
2671 CVT_CEIL | CVT_F32_F32 | CVT_RI);
2672 }
2673 break;
2674 case TGSI_OPCODE_CMP:
2675 pc->allow32 = FALSE;
2676 for (c = 0; c < 4; c++) {
2677 if (!(mask & (1 << c)))
2678 continue;
2679 emit_cvt(pc, NULL, src[0][c], 1, CVT_F32_F32);
2680 emit_mov(pc, dst[c], src[1][c]);
2681 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2682 emit_mov(pc, dst[c], src[2][c]);
2683 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2684 }
2685 break;
2686 case TGSI_OPCODE_CONT:
2687 assert(pc->loop_lvl > 0);
2688 emit_branch(pc, -1, 0)->param.index =
2689 pc->loop_pos[pc->loop_lvl - 1];
2690 break;
2691 case TGSI_OPCODE_COS:
2692 if (mask & 8) {
2693 emit_precossin(pc, temp, src[0][3]);
2694 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2695 if (!(mask &= 7))
2696 break;
2697 if (temp == dst[3])
2698 temp = brdc = temp_temp(pc, NULL);
2699 }
2700 emit_precossin(pc, temp, src[0][0]);
2701 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2702 break;
2703 case TGSI_OPCODE_DDX:
2704 for (c = 0; c < 4; c++) {
2705 if (!(mask & (1 << c)))
2706 continue;
2707 emit_ddx(pc, dst[c], src[0][c]);
2708 }
2709 break;
2710 case TGSI_OPCODE_DDY:
2711 for (c = 0; c < 4; c++) {
2712 if (!(mask & (1 << c)))
2713 continue;
2714 emit_ddy(pc, dst[c], src[0][c]);
2715 }
2716 break;
2717 case TGSI_OPCODE_DP3:
2718 emit_mul(pc, temp, src[0][0], src[1][0]);
2719 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2720 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2721 break;
2722 case TGSI_OPCODE_DP4:
2723 emit_mul(pc, temp, src[0][0], src[1][0]);
2724 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2725 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2726 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2727 break;
2728 case TGSI_OPCODE_DPH:
2729 emit_mul(pc, temp, src[0][0], src[1][0]);
2730 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2731 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2732 emit_add(pc, brdc, src[1][3], temp);
2733 break;
2734 case TGSI_OPCODE_DST:
2735 if (mask & (1 << 1))
2736 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2737 if (mask & (1 << 2))
2738 emit_mov(pc, dst[2], src[0][2]);
2739 if (mask & (1 << 3))
2740 emit_mov(pc, dst[3], src[1][3]);
2741 if (mask & (1 << 0))
2742 emit_mov_immdval(pc, dst[0], 1.0f);
2743 break;
2744 case TGSI_OPCODE_ELSE:
2745 emit_branch(pc, -1, 0);
2746 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2747 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2748 terminate_mbb(pc);
2749 break;
2750 case TGSI_OPCODE_EMIT:
2751 emit_prim_cmd(pc, 1);
2752 break;
2753 case TGSI_OPCODE_ENDIF:
2754 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2755
2756 /* try to replace branch over 1 insn with a predicated insn */
2757 if (nv50_kill_branch(pc) == TRUE)
2758 break;
2759
2760 if (pc->if_join[pc->if_lvl]) {
2761 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2762 pc->if_join[pc->if_lvl] = NULL;
2763 }
2764 terminate_mbb(pc);
2765 /* emit a NOP as join point, we could set it on the next
2766 * one, but would have to make sure it is long and !immd
2767 */
2768 JOIN_ON(emit_nop(pc));
2769 break;
2770 case TGSI_OPCODE_ENDLOOP:
2771 emit_branch(pc, -1, 0)->param.index =
2772 pc->loop_pos[--pc->loop_lvl];
2773 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2774 terminate_mbb(pc);
2775 break;
2776 case TGSI_OPCODE_ENDPRIM:
2777 emit_prim_cmd(pc, 2);
2778 break;
2779 case TGSI_OPCODE_ENDSUB:
2780 assert(pc->in_subroutine);
2781 terminate_mbb(pc);
2782 pc->in_subroutine = FALSE;
2783 break;
2784 case TGSI_OPCODE_EX2:
2785 emit_preex2(pc, temp, src[0][0]);
2786 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2787 break;
2788 case TGSI_OPCODE_EXP:
2789 {
2790 struct nv50_reg *t[2];
2791
2792 assert(!temp);
2793 t[0] = temp_temp(pc, NULL);
2794 t[1] = temp_temp(pc, NULL);
2795
2796 if (mask & 0x6)
2797 emit_mov(pc, t[0], src[0][0]);
2798 if (mask & 0x3)
2799 emit_flr(pc, t[1], src[0][0]);
2800
2801 if (mask & (1 << 1))
2802 emit_sub(pc, dst[1], t[0], t[1]);
2803 if (mask & (1 << 0)) {
2804 emit_preex2(pc, t[1], t[1]);
2805 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2806 }
2807 if (mask & (1 << 2)) {
2808 emit_preex2(pc, t[0], t[0]);
2809 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2810 }
2811 if (mask & (1 << 3))
2812 emit_mov_immdval(pc, dst[3], 1.0f);
2813 }
2814 break;
2815 case TGSI_OPCODE_F2I:
2816 for (c = 0; c < 4; c++) {
2817 if (!(mask & (1 << c)))
2818 continue;
2819 emit_cvt(pc, dst[c], src[0][c], -1,
2820 CVT_TRUNC | CVT_S32_F32);
2821 }
2822 break;
2823 case TGSI_OPCODE_F2U:
2824 for (c = 0; c < 4; c++) {
2825 if (!(mask & (1 << c)))
2826 continue;
2827 emit_cvt(pc, dst[c], src[0][c], -1,
2828 CVT_TRUNC | CVT_U32_F32);
2829 }
2830 break;
2831 case TGSI_OPCODE_FLR:
2832 for (c = 0; c < 4; c++) {
2833 if (!(mask & (1 << c)))
2834 continue;
2835 emit_flr(pc, dst[c], src[0][c]);
2836 }
2837 break;
2838 case TGSI_OPCODE_FRC:
2839 temp = temp_temp(pc, NULL);
2840 for (c = 0; c < 4; c++) {
2841 if (!(mask & (1 << c)))
2842 continue;
2843 emit_flr(pc, temp, src[0][c]);
2844 emit_sub(pc, dst[c], src[0][c], temp);
2845 }
2846 break;
2847 case TGSI_OPCODE_I2F:
2848 for (c = 0; c < 4; c++) {
2849 if (!(mask & (1 << c)))
2850 continue;
2851 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_S32);
2852 }
2853 break;
2854 case TGSI_OPCODE_IF:
2855 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2856 emit_cvt(pc, NULL, src[0][0], 0, CVT_ABS | CVT_F32_F32);
2857 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2858 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2859 terminate_mbb(pc);
2860 break;
2861 case TGSI_OPCODE_IMAX:
2862 for (c = 0; c < 4; c++) {
2863 if (!(mask & (1 << c)))
2864 continue;
2865 emit_minmax(pc, 0x08c, dst[c], src[0][c], src[1][c]);
2866 }
2867 break;
2868 case TGSI_OPCODE_IMIN:
2869 for (c = 0; c < 4; c++) {
2870 if (!(mask & (1 << c)))
2871 continue;
2872 emit_minmax(pc, 0x0ac, dst[c], src[0][c], src[1][c]);
2873 }
2874 break;
2875 case TGSI_OPCODE_INEG:
2876 for (c = 0; c < 4; c++) {
2877 if (!(mask & (1 << c)))
2878 continue;
2879 emit_cvt(pc, dst[c], src[0][c], -1,
2880 CVT_S32_S32 | CVT_NEG);
2881 }
2882 break;
2883 case TGSI_OPCODE_KIL:
2884 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2885 emit_kil(pc, src[0][0]);
2886 emit_kil(pc, src[0][1]);
2887 emit_kil(pc, src[0][2]);
2888 emit_kil(pc, src[0][3]);
2889 break;
2890 case TGSI_OPCODE_KILP:
2891 emit_kil(pc, NULL);
2892 break;
2893 case TGSI_OPCODE_LIT:
2894 emit_lit(pc, &dst[0], mask, &src[0][0]);
2895 break;
2896 case TGSI_OPCODE_LG2:
2897 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2898 break;
2899 case TGSI_OPCODE_LOG:
2900 {
2901 struct nv50_reg *t[2];
2902
2903 t[0] = temp_temp(pc, NULL);
2904 if (mask & (1 << 1))
2905 t[1] = temp_temp(pc, NULL);
2906 else
2907 t[1] = t[0];
2908
2909 emit_cvt(pc, t[0], src[0][0], -1, CVT_ABS | CVT_F32_F32);
2910 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2911 if (mask & (1 << 2))
2912 emit_mov(pc, dst[2], t[1]);
2913 emit_flr(pc, t[1], t[1]);
2914 if (mask & (1 << 0))
2915 emit_mov(pc, dst[0], t[1]);
2916 if (mask & (1 << 1)) {
2917 t[1]->mod = NV50_MOD_NEG;
2918 emit_preex2(pc, t[1], t[1]);
2919 t[1]->mod = 0;
2920 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2921 emit_mul(pc, dst[1], t[0], t[1]);
2922 }
2923 if (mask & (1 << 3))
2924 emit_mov_immdval(pc, dst[3], 1.0f);
2925 }
2926 break;
2927 case TGSI_OPCODE_LRP:
2928 temp = temp_temp(pc, NULL);
2929 for (c = 0; c < 4; c++) {
2930 if (!(mask & (1 << c)))
2931 continue;
2932 emit_sub(pc, temp, src[1][c], src[2][c]);
2933 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2934 }
2935 break;
2936 case TGSI_OPCODE_MAD:
2937 for (c = 0; c < 4; c++) {
2938 if (!(mask & (1 << c)))
2939 continue;
2940 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2941 }
2942 break;
2943 case TGSI_OPCODE_MAX:
2944 for (c = 0; c < 4; c++) {
2945 if (!(mask & (1 << c)))
2946 continue;
2947 emit_minmax(pc, 0x880, dst[c], src[0][c], src[1][c]);
2948 }
2949 break;
2950 case TGSI_OPCODE_MIN:
2951 for (c = 0; c < 4; c++) {
2952 if (!(mask & (1 << c)))
2953 continue;
2954 emit_minmax(pc, 0x8a0, dst[c], src[0][c], src[1][c]);
2955 }
2956 break;
2957 case TGSI_OPCODE_MOV:
2958 for (c = 0; c < 4; c++) {
2959 if (!(mask & (1 << c)))
2960 continue;
2961 emit_mov(pc, dst[c], src[0][c]);
2962 }
2963 break;
2964 case TGSI_OPCODE_MUL:
2965 for (c = 0; c < 4; c++) {
2966 if (!(mask & (1 << c)))
2967 continue;
2968 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2969 }
2970 break;
2971 case TGSI_OPCODE_NOT:
2972 for (c = 0; c < 4; c++) {
2973 if (!(mask & (1 << c)))
2974 continue;
2975 emit_not(pc, dst[c], src[0][c]);
2976 }
2977 break;
2978 case TGSI_OPCODE_POW:
2979 emit_pow(pc, brdc, src[0][0], src[1][0]);
2980 break;
2981 case TGSI_OPCODE_RCP:
2982 if (!sat && popcnt4(mask) == 1)
2983 brdc = dst[ffs(mask) - 1];
2984 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2985 break;
2986 case TGSI_OPCODE_RET:
2987 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2988 nv50_fp_move_results(pc);
2989 emit_ret(pc, -1, 0);
2990 break;
2991 case TGSI_OPCODE_RSQ:
2992 if (!sat && popcnt4(mask) == 1)
2993 brdc = dst[ffs(mask) - 1];
2994 src[0][0]->mod |= NV50_MOD_ABS;
2995 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2996 break;
2997 case TGSI_OPCODE_SAD:
2998 for (c = 0; c < 4; c++) {
2999 if (!(mask & (1 << c)))
3000 continue;
3001 emit_sad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
3002 }
3003 break;
3004 case TGSI_OPCODE_SCS:
3005 temp = temp_temp(pc, NULL);
3006 if (mask & 3)
3007 emit_precossin(pc, temp, src[0][0]);
3008 if (mask & (1 << 0))
3009 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
3010 if (mask & (1 << 1))
3011 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
3012 if (mask & (1 << 2))
3013 emit_mov_immdval(pc, dst[2], 0.0);
3014 if (mask & (1 << 3))
3015 emit_mov_immdval(pc, dst[3], 1.0);
3016 break;
3017 case TGSI_OPCODE_SHL:
3018 case TGSI_OPCODE_ISHR:
3019 case TGSI_OPCODE_USHR:
3020 for (c = 0; c < 4; c++) {
3021 if (!(mask & (1 << c)))
3022 continue;
3023 emit_shift(pc, dst[c], src[0][c], src[1][c],
3024 inst->Instruction.Opcode);
3025 }
3026 break;
3027 case TGSI_OPCODE_SIN:
3028 if (mask & 8) {
3029 emit_precossin(pc, temp, src[0][3]);
3030 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
3031 if (!(mask &= 7))
3032 break;
3033 if (temp == dst[3])
3034 temp = brdc = temp_temp(pc, NULL);
3035 }
3036 emit_precossin(pc, temp, src[0][0]);
3037 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
3038 break;
3039 case TGSI_OPCODE_SLT:
3040 case TGSI_OPCODE_SGE:
3041 case TGSI_OPCODE_SEQ:
3042 case TGSI_OPCODE_SGT:
3043 case TGSI_OPCODE_SLE:
3044 case TGSI_OPCODE_SNE:
3045 case TGSI_OPCODE_ISLT:
3046 case TGSI_OPCODE_ISGE:
3047 case TGSI_OPCODE_USEQ:
3048 case TGSI_OPCODE_USGE:
3049 case TGSI_OPCODE_USLT:
3050 case TGSI_OPCODE_USNE:
3051 {
3052 uint8_t cc, ty;
3053
3054 map_tgsi_setop_hw(inst->Instruction.Opcode, &cc, &ty);
3055
3056 for (c = 0; c < 4; c++) {
3057 if (!(mask & (1 << c)))
3058 continue;
3059 emit_set(pc, cc, dst[c], -1, src[0][c], src[1][c], ty);
3060 }
3061 }
3062 break;
3063 case TGSI_OPCODE_SUB:
3064 for (c = 0; c < 4; c++) {
3065 if (!(mask & (1 << c)))
3066 continue;
3067 emit_sub(pc, dst[c], src[0][c], src[1][c]);
3068 }
3069 break;
3070 case TGSI_OPCODE_TEX:
3071 emit_tex(pc, dst, mask, src[0], unit,
3072 inst->Texture.Texture, FALSE, 0);
3073 break;
3074 case TGSI_OPCODE_TXB:
3075 emit_tex(pc, dst, mask, src[0], unit,
3076 inst->Texture.Texture, FALSE, -1);
3077 break;
3078 case TGSI_OPCODE_TXL:
3079 emit_tex(pc, dst, mask, src[0], unit,
3080 inst->Texture.Texture, FALSE, 1);
3081 break;
3082 case TGSI_OPCODE_TXP:
3083 emit_tex(pc, dst, mask, src[0], unit,
3084 inst->Texture.Texture, TRUE, 0);
3085 break;
3086 case TGSI_OPCODE_TRUNC:
3087 for (c = 0; c < 4; c++) {
3088 if (!(mask & (1 << c)))
3089 continue;
3090 emit_cvt(pc, dst[c], src[0][c], -1,
3091 CVT_TRUNC | CVT_F32_F32 | CVT_RI);
3092 }
3093 break;
3094 case TGSI_OPCODE_U2F:
3095 for (c = 0; c < 4; c++) {
3096 if (!(mask & (1 << c)))
3097 continue;
3098 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_U32);
3099 }
3100 break;
3101 case TGSI_OPCODE_UADD:
3102 for (c = 0; c < 4; c++) {
3103 if (!(mask & (1 << c)))
3104 continue;
3105 emit_add_b32(pc, dst[c], src[0][c], src[1][c]);
3106 }
3107 break;
3108 case TGSI_OPCODE_UMAX:
3109 for (c = 0; c < 4; c++) {
3110 if (!(mask & (1 << c)))
3111 continue;
3112 emit_minmax(pc, 0x084, dst[c], src[0][c], src[1][c]);
3113 }
3114 break;
3115 case TGSI_OPCODE_UMIN:
3116 for (c = 0; c < 4; c++) {
3117 if (!(mask & (1 << c)))
3118 continue;
3119 emit_minmax(pc, 0x0a4, dst[c], src[0][c], src[1][c]);
3120 }
3121 break;
3122 case TGSI_OPCODE_UMAD:
3123 {
3124 assert(!temp);
3125 temp = temp_temp(pc, NULL);
3126 for (c = 0; c < 4; c++) {
3127 if (!(mask & (1 << c)))
3128 continue;
3129 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3130 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3131 temp);
3132 emit_shl_imm(pc, temp, temp, 16);
3133 emit_mad_u16(pc, temp, src[0][c], 0, src[1][c], 0,
3134 temp);
3135 emit_add_b32(pc, dst[c], temp, src[2][c]);
3136 }
3137 }
3138 break;
3139 case TGSI_OPCODE_UMUL:
3140 {
3141 assert(!temp);
3142 temp = temp_temp(pc, NULL);
3143 for (c = 0; c < 4; c++) {
3144 if (!(mask & (1 << c)))
3145 continue;
3146 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3147 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3148 temp);
3149 emit_shl_imm(pc, temp, temp, 16);
3150 emit_mad_u16(pc, dst[c], src[0][c], 0, src[1][c], 0,
3151 temp);
3152 }
3153 }
3154 break;
3155 case TGSI_OPCODE_XPD:
3156 temp = temp_temp(pc, NULL);
3157 if (mask & (1 << 0)) {
3158 emit_mul(pc, temp, src[0][2], src[1][1]);
3159 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
3160 }
3161 if (mask & (1 << 1)) {
3162 emit_mul(pc, temp, src[0][0], src[1][2]);
3163 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
3164 }
3165 if (mask & (1 << 2)) {
3166 emit_mul(pc, temp, src[0][1], src[1][0]);
3167 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
3168 }
3169 if (mask & (1 << 3))
3170 emit_mov_immdval(pc, dst[3], 1.0);
3171 break;
3172 case TGSI_OPCODE_END:
3173 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3174 nv50_fp_move_results(pc);
3175
3176 if (!pc->p->exec_tail ||
3177 is_immd(pc->p->exec_tail) ||
3178 is_join(pc->p->exec_tail) ||
3179 is_control_flow(pc->p->exec_tail))
3180 emit_nop(pc);
3181
3182 /* last insn must be long so it can have the exit bit set */
3183 if (!is_long(pc->p->exec_tail))
3184 convert_to_long(pc, pc->p->exec_tail);
3185
3186 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
3187
3188 terminate_mbb(pc);
3189 break;
3190 default:
3191 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
3192 return FALSE;
3193 }
3194
3195 if (brdc) {
3196 if (sat)
3197 emit_sat(pc, brdc, brdc);
3198 for (c = 0; c < 4; c++)
3199 if ((mask & (1 << c)) && dst[c] != brdc)
3200 emit_mov(pc, dst[c], brdc);
3201 } else
3202 if (sat) {
3203 for (c = 0; c < 4; c++) {
3204 if (!(mask & (1 << c)))
3205 continue;
3206 /* In this case we saturate later, and dst[c] won't
3207 * be another temp_temp (and thus lost), since rdst
3208 * already is TEMP (see above). */
3209 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
3210 continue;
3211 emit_sat(pc, rdst[c], dst[c]);
3212 }
3213 }
3214
3215 kill_temp_temp(pc, NULL);
3216 pc->reg_instance_nr = 0;
3217
3218 return TRUE;
3219 }
3220
3221 static void
3222 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
3223 {
3224 struct nv50_reg *r, *reg = NULL;
3225 const struct tgsi_full_src_register *src;
3226 const struct tgsi_dst_register *dst;
3227 unsigned i, c, k, mask;
3228
3229 dst = &insn->Dst[0].Register;
3230 mask = dst->WriteMask;
3231
3232 if (dst->File == TGSI_FILE_TEMPORARY)
3233 reg = pc->temp;
3234 else
3235 if (dst->File == TGSI_FILE_OUTPUT) {
3236 reg = pc->result;
3237
3238 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
3239 dst->Index == pc->edgeflag_out &&
3240 insn->Src[0].Register.File == TGSI_FILE_INPUT)
3241 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
3242 }
3243
3244 if (reg) {
3245 for (c = 0; c < 4; c++) {
3246 if (!(mask & (1 << c)))
3247 continue;
3248 reg[dst->Index * 4 + c].acc = pc->insn_nr;
3249 }
3250 }
3251
3252 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3253 src = &insn->Src[i];
3254
3255 if (src->Register.File == TGSI_FILE_TEMPORARY)
3256 reg = pc->temp;
3257 else
3258 if (src->Register.File == TGSI_FILE_INPUT)
3259 reg = pc->attr;
3260 else
3261 continue;
3262
3263 mask = nv50_tgsi_src_mask(insn, i);
3264
3265 for (c = 0; c < 4; c++) {
3266 if (!(mask & (1 << c)))
3267 continue;
3268 k = tgsi_util_get_full_src_register_swizzle(src, c);
3269
3270 r = &reg[src->Register.Index * 4 + k];
3271
3272 /* If used before written, pre-allocate the reg,
3273 * lest we overwrite results from a subroutine.
3274 */
3275 if (!r->acc && r->type == P_TEMP)
3276 alloc_reg(pc, r);
3277
3278 r->acc = pc->insn_nr;
3279 }
3280 }
3281 }
3282
3283 /* Returns a bitmask indicating which dst components need to be
3284 * written to temporaries first to avoid 'corrupting' sources.
3285 *
3286 * m[i] (out) indicate component to write in the i-th position
3287 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
3288 */
3289 static unsigned
3290 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
3291 {
3292 unsigned i, c, x, unsafe = 0;
3293
3294 for (c = 0; c < 4; c++)
3295 m[c] = c;
3296
3297 /* Swap as long as a dst component written earlier is depended on
3298 * by one written later, but the next one isn't depended on by it.
3299 */
3300 for (c = 0; c < 3; c++) {
3301 if (rdep[m[c + 1]] & (1 << m[c]))
3302 continue; /* if next one is depended on by us */
3303 for (i = c + 1; i < 4; i++)
3304 /* if we are depended on by a later one */
3305 if (rdep[m[c]] & (1 << m[i]))
3306 break;
3307 if (i == 4)
3308 continue;
3309 /* now, swap */
3310 x = m[c];
3311 m[c] = m[c + 1];
3312 m[c + 1] = x;
3313
3314 /* restart */
3315 c = 0;
3316 }
3317
3318 /* mark dependencies that could not be resolved by reordering */
3319 for (i = 0; i < 3; ++i)
3320 for (c = i + 1; c < 4; ++c)
3321 if (rdep[m[i]] & (1 << m[c]))
3322 unsafe |= (1 << i);
3323
3324 /* NOTE: $unsafe is with respect to order, not component */
3325 return unsafe;
3326 }
3327
3328 /* Select a suitable dst register for broadcasting scalar results,
3329 * or return NULL if we have to allocate an extra TEMP.
3330 *
3331 * If e.g. only 1 component is written, we may also emit the final
3332 * result to a write-only register.
3333 */
3334 static struct nv50_reg *
3335 tgsi_broadcast_dst(struct nv50_pc *pc,
3336 const struct tgsi_full_dst_register *fd, unsigned mask)
3337 {
3338 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
3339 int c = ffs(~mask & fd->Register.WriteMask);
3340 if (c)
3341 return tgsi_dst(pc, c - 1, fd);
3342 } else {
3343 int c = ffs(fd->Register.WriteMask) - 1;
3344 if ((1 << c) == fd->Register.WriteMask)
3345 return tgsi_dst(pc, c, fd);
3346 }
3347
3348 return NULL;
3349 }
3350
3351 /* Scan source swizzles and return a bitmask indicating dst regs that
3352 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
3353 */
3354 static unsigned
3355 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
3356 unsigned rdep[4])
3357 {
3358 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
3359 const struct tgsi_full_src_register *fs;
3360 unsigned i, deqs = 0;
3361
3362 for (i = 0; i < 4; ++i)
3363 rdep[i] = 0;
3364
3365 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3366 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
3367 int ms = get_supported_mods(insn, i);
3368
3369 fs = &insn->Src[i];
3370 if (fs->Register.File != fd->Register.File ||
3371 fs->Register.Index != fd->Register.Index)
3372 continue;
3373
3374 for (chn = 0; chn < 4; ++chn) {
3375 unsigned s, c;
3376
3377 if (!(mask & (1 << chn))) /* src is not read */
3378 continue;
3379 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
3380 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
3381
3382 if (!(fd->Register.WriteMask & (1 << c)))
3383 continue;
3384
3385 if (s == TGSI_UTIL_SIGN_TOGGLE && !(ms & NV50_MOD_NEG))
3386 continue;
3387 if (s == TGSI_UTIL_SIGN_CLEAR && !(ms & NV50_MOD_ABS))
3388 continue;
3389 if ((s == TGSI_UTIL_SIGN_SET) && ((ms & 3) != 3))
3390 continue;
3391
3392 rdep[c] |= nv50_tgsi_dst_revdep(
3393 insn->Instruction.Opcode, i, chn);
3394 deqs |= (1 << c);
3395 }
3396 }
3397
3398 return deqs;
3399 }
3400
3401 static boolean
3402 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
3403 {
3404 struct tgsi_full_instruction insn = tok->FullInstruction;
3405 const struct tgsi_full_dst_register *fd;
3406 unsigned i, deqs, rdep[4], m[4];
3407
3408 fd = &tok->FullInstruction.Dst[0];
3409 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
3410
3411 if (is_scalar_op(insn.Instruction.Opcode)) {
3412 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
3413 if (!pc->r_brdc)
3414 pc->r_brdc = temp_temp(pc, NULL);
3415 return nv50_program_tx_insn(pc, &insn);
3416 }
3417 pc->r_brdc = NULL;
3418
3419 if (!deqs || (!rdep[0] && !rdep[1] && !rdep[2] && !rdep[3]))
3420 return nv50_program_tx_insn(pc, &insn);
3421
3422 deqs = nv50_revdep_reorder(m, rdep);
3423
3424 for (i = 0; i < 4; ++i) {
3425 assert(pc->r_dst[m[i]] == NULL);
3426
3427 insn.Dst[0].Register.WriteMask =
3428 fd->Register.WriteMask & (1 << m[i]);
3429
3430 if (!insn.Dst[0].Register.WriteMask)
3431 continue;
3432
3433 if (deqs & (1 << i))
3434 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
3435
3436 if (!nv50_program_tx_insn(pc, &insn))
3437 return FALSE;
3438 }
3439
3440 for (i = 0; i < 4; i++) {
3441 struct nv50_reg *reg = pc->r_dst[i];
3442 if (!reg)
3443 continue;
3444 pc->r_dst[i] = NULL;
3445
3446 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
3447 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
3448 else
3449 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
3450 free_temp(pc, reg);
3451 }
3452
3453 return TRUE;
3454 }
3455
3456 static void
3457 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
3458 {
3459 struct nv50_reg *iv, **ppiv;
3460 unsigned mode = pc->interp_mode[reg->index];
3461
3462 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
3463 iv = *ppiv;
3464
3465 if ((mode & INTERP_PERSPECTIVE) && !iv) {
3466 iv = *ppiv = alloc_temp(pc, NULL);
3467 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
3468
3469 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
3470 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
3471
3472 /* XXX: when loading interpolants dynamically, move these
3473 * to the program head, or make sure it can't be skipped.
3474 */
3475 }
3476
3477 emit_interp(pc, reg, iv, mode);
3478 }
3479
3480 /* The face input is always at v[255] (varying space), with a
3481 * value of 0 for back-facing, and 0xffffffff for front-facing.
3482 */
3483 static void
3484 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *sv)
3485 {
3486 struct nv50_reg *temp = alloc_temp(pc, NULL);
3487 int r_pred = 0;
3488
3489 temp->rhw = 255;
3490 emit_interp(pc, temp, NULL, INTERP_FLAT);
3491
3492 emit_cvt(pc, sv, temp, r_pred, CVT_ABS | CVT_F32_S32);
3493
3494 emit_not(pc, temp, temp);
3495 set_pred(pc, 0x2, r_pred, pc->p->exec_tail);
3496 emit_cvt(pc, sv, temp, -1, CVT_F32_S32);
3497 set_pred(pc, 0x2, r_pred, pc->p->exec_tail);
3498
3499 free_temp(pc, temp);
3500 }
3501
3502 static void
3503 load_instance_id(struct nv50_pc *pc, unsigned index)
3504 {
3505 struct nv50_reg reg, mem;
3506
3507 ctor_reg(&reg, P_TEMP, -1, -1);
3508 ctor_reg(&mem, P_CONST, -1, 24); /* startInstance */
3509 mem.buf_index = 2;
3510
3511 emit_add_b32(pc, &reg, &pc->sysval[index], &mem);
3512 pc->sysval[index] = reg;
3513 }
3514
3515 static void
3516 copy_semantic_info(struct nv50_program *p)
3517 {
3518 unsigned i, id;
3519
3520 for (i = 0; i < p->cfg.in_nr; ++i) {
3521 id = p->cfg.in[i].id;
3522 p->cfg.in[i].sn = p->info.input_semantic_name[id];
3523 p->cfg.in[i].si = p->info.input_semantic_index[id];
3524 }
3525
3526 for (i = 0; i < p->cfg.out_nr; ++i) {
3527 id = p->cfg.out[i].id;
3528 p->cfg.out[i].sn = p->info.output_semantic_name[id];
3529 p->cfg.out[i].si = p->info.output_semantic_index[id];
3530 }
3531 }
3532
3533 static boolean
3534 nv50_program_tx_prep(struct nv50_pc *pc)
3535 {
3536 struct tgsi_parse_context tp;
3537 struct nv50_program *p = pc->p;
3538 boolean ret = FALSE;
3539 unsigned i, c, instance_id = 0, vertex_id = 0, flat_nr = 0;
3540
3541 tgsi_parse_init(&tp, pc->p->pipe.tokens);
3542 while (!tgsi_parse_end_of_tokens(&tp)) {
3543 const union tgsi_full_token *tok = &tp.FullToken;
3544
3545 tgsi_parse_token(&tp);
3546 switch (tok->Token.Type) {
3547 case TGSI_TOKEN_TYPE_IMMEDIATE:
3548 {
3549 const struct tgsi_full_immediate *imm =
3550 &tp.FullToken.FullImmediate;
3551
3552 ctor_immd_4f32(pc, imm->u[0].Float,
3553 imm->u[1].Float,
3554 imm->u[2].Float,
3555 imm->u[3].Float);
3556 }
3557 break;
3558 case TGSI_TOKEN_TYPE_DECLARATION:
3559 {
3560 const struct tgsi_full_declaration *d;
3561 unsigned si, last, first, mode;
3562
3563 d = &tp.FullToken.FullDeclaration;
3564 first = d->Range.First;
3565 last = d->Range.Last;
3566
3567 switch (d->Declaration.File) {
3568 case TGSI_FILE_TEMPORARY:
3569 break;
3570 case TGSI_FILE_OUTPUT:
3571 if (!d->Declaration.Semantic ||
3572 p->type == PIPE_SHADER_FRAGMENT)
3573 break;
3574
3575 si = d->Semantic.Index;
3576 switch (d->Semantic.Name) {
3577 case TGSI_SEMANTIC_BCOLOR:
3578 p->cfg.two_side[si].hw = first;
3579 if (p->cfg.out_nr > first)
3580 p->cfg.out_nr = first;
3581 break;
3582 case TGSI_SEMANTIC_PSIZE:
3583 p->cfg.psiz = first;
3584 if (p->cfg.out_nr > first)
3585 p->cfg.out_nr = first;
3586 break;
3587 case TGSI_SEMANTIC_EDGEFLAG:
3588 pc->edgeflag_out = first;
3589 break;
3590 /*
3591 case TGSI_SEMANTIC_CLIP_DISTANCE:
3592 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3593 break;
3594 */
3595 default:
3596 break;
3597 }
3598 break;
3599 case TGSI_FILE_INPUT:
3600 {
3601 if (p->type != PIPE_SHADER_FRAGMENT)
3602 break;
3603
3604 switch (d->Declaration.Interpolate) {
3605 case TGSI_INTERPOLATE_CONSTANT:
3606 mode = INTERP_FLAT;
3607 flat_nr++;
3608 break;
3609 case TGSI_INTERPOLATE_PERSPECTIVE:
3610 mode = INTERP_PERSPECTIVE;
3611 p->cfg.regs[1] |= 0x08 << 24;
3612 break;
3613 default:
3614 mode = INTERP_LINEAR;
3615 break;
3616 }
3617 if (d->Declaration.Centroid)
3618 mode |= INTERP_CENTROID;
3619
3620 assert(last < 32);
3621 for (i = first; i <= last; i++)
3622 pc->interp_mode[i] = mode;
3623 }
3624 break;
3625 case TGSI_FILE_SYSTEM_VALUE:
3626 assert(d->Declaration.Semantic);
3627 switch (d->Semantic.Name) {
3628 case TGSI_SEMANTIC_FACE:
3629 assert(p->type == PIPE_SHADER_FRAGMENT);
3630 load_frontfacing(pc,
3631 &pc->sysval[first]);
3632 break;
3633 case TGSI_SEMANTIC_INSTANCEID:
3634 assert(p->type == PIPE_SHADER_VERTEX);
3635 instance_id = first;
3636 p->cfg.regs[0] |= (1 << 4);
3637 break;
3638 case TGSI_SEMANTIC_PRIMID:
3639 assert(p->type != PIPE_SHADER_VERTEX);
3640 p->cfg.prim_id = first;
3641 break;
3642 /*
3643 case TGSI_SEMANTIC_PRIMIDIN:
3644 assert(p->type == PIPE_SHADER_GEOMETRY);
3645 pc->sysval[first].hw = 6;
3646 p->cfg.regs[0] |= (1 << 8);
3647 break;
3648 case TGSI_SEMANTIC_VERTEXID:
3649 assert(p->type == PIPE_SHADER_VERTEX);
3650 vertex_id = first;
3651 p->cfg.regs[0] |= (1 << 12) | (1 << 0);
3652 break;
3653 */
3654 }
3655 break;
3656 case TGSI_FILE_ADDRESS:
3657 case TGSI_FILE_CONSTANT:
3658 case TGSI_FILE_SAMPLER:
3659 break;
3660 default:
3661 NOUVEAU_ERR("bad decl file %d\n",
3662 d->Declaration.File);
3663 goto out_err;
3664 }
3665 }
3666 break;
3667 case TGSI_TOKEN_TYPE_INSTRUCTION:
3668 pc->insn_nr++;
3669 prep_inspect_insn(pc, &tok->FullInstruction);
3670 break;
3671 default:
3672 break;
3673 }
3674 }
3675
3676 if (p->type == PIPE_SHADER_VERTEX || p->type == PIPE_SHADER_GEOMETRY) {
3677 int rid = 0;
3678
3679 if (p->type == PIPE_SHADER_GEOMETRY) {
3680 for (i = 0; i < pc->attr_nr; ++i) {
3681 p->cfg.in[i].hw = rid;
3682 p->cfg.in[i].id = i;
3683
3684 for (c = 0; c < 4; ++c) {
3685 int n = i * 4 + c;
3686 if (!pc->attr[n].acc)
3687 continue;
3688 pc->attr[n].hw = rid++;
3689 p->cfg.in[i].mask |= 1 << c;
3690 }
3691 }
3692 } else {
3693 for (i = 0; i < pc->attr_nr * 4; ++i) {
3694 if (pc->attr[i].acc) {
3695 pc->attr[i].hw = rid++;
3696 p->cfg.attr[i / 32] |= 1 << (i % 32);
3697 }
3698 }
3699 if (p->cfg.regs[0] & (1 << 0))
3700 pc->sysval[vertex_id].hw = rid++;
3701 if (p->cfg.regs[0] & (1 << 4)) {
3702 pc->sysval[instance_id].hw = rid++;
3703 load_instance_id(pc, instance_id);
3704 }
3705 }
3706
3707 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3708 p->cfg.out[i].hw = rid;
3709 p->cfg.out[i].id = i;
3710
3711 for (c = 0; c < 4; ++c) {
3712 int n = i * 4 + c;
3713 if (!pc->result[n].acc)
3714 continue;
3715 pc->result[n].hw = rid++;
3716 p->cfg.out[i].mask |= 1 << c;
3717 }
3718 }
3719 if (p->cfg.prim_id < 0x40) {
3720 /* GP has to write to PrimitiveID */
3721 ctor_reg(&pc->sysval[p->cfg.prim_id],
3722 P_RESULT, p->cfg.prim_id, rid);
3723 p->cfg.prim_id = rid++;
3724 }
3725
3726 for (c = 0; c < 2; ++c)
3727 if (p->cfg.two_side[c].hw < 0x40)
3728 p->cfg.two_side[c] = p->cfg.out[
3729 p->cfg.two_side[c].hw];
3730
3731 if (p->cfg.psiz < 0x40)
3732 p->cfg.psiz = p->cfg.out[p->cfg.psiz].hw;
3733
3734 copy_semantic_info(p);
3735 } else
3736 if (p->type == PIPE_SHADER_FRAGMENT) {
3737 int rid = 0, aid;
3738 unsigned n = 0, m = pc->attr_nr - flat_nr;
3739
3740 pc->allow32 = TRUE;
3741
3742 /* do we read FragCoord ? */
3743 if (pc->attr_nr &&
3744 p->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) {
3745 /* select FCRD components we want accessible */
3746 for (c = 0; c < 4; ++c)
3747 if (pc->attr[c].acc)
3748 p->cfg.regs[1] |= 1 << (24 + c);
3749 aid = 0;
3750 } else /* offset by 1 if FCRD.w is needed for pinterp */
3751 aid = popcnt4(p->cfg.regs[1] >> 24);
3752
3753 /* non-flat interpolants have to be mapped to
3754 * the lower hardware IDs, so sort them:
3755 */
3756 for (i = 0; i < pc->attr_nr; i++) {
3757 if (pc->interp_mode[i] == INTERP_FLAT)
3758 p->cfg.in[m++].id = i;
3759 else {
3760 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3761 p->cfg.in[n].linear = TRUE;
3762 p->cfg.in[n++].id = i;
3763 }
3764 }
3765 copy_semantic_info(p);
3766
3767 for (n = 0; n < pc->attr_nr; ++n) {
3768 p->cfg.in[n].hw = rid = aid;
3769 i = p->cfg.in[n].id;
3770
3771 if (p->info.input_semantic_name[i] ==
3772 TGSI_SEMANTIC_FACE) {
3773 load_frontfacing(pc, &pc->attr[i * 4]);
3774 continue;
3775 }
3776
3777 for (c = 0; c < 4; ++c) {
3778 if (!pc->attr[i * 4 + c].acc)
3779 continue;
3780 pc->attr[i * 4 + c].rhw = rid++;
3781 p->cfg.in[n].mask |= 1 << c;
3782
3783 load_interpolant(pc, &pc->attr[i * 4 + c]);
3784 }
3785 aid += popcnt4(p->cfg.in[n].mask);
3786 }
3787
3788 m = popcnt4(p->cfg.regs[1] >> 24);
3789
3790 /* set count of non-position inputs and of non-flat
3791 * non-position inputs for FP_INTERPOLANT_CTRL
3792 */
3793 p->cfg.regs[1] |= aid - m;
3794
3795 if (flat_nr) {
3796 i = p->cfg.in[pc->attr_nr - flat_nr].hw;
3797 p->cfg.regs[1] |= (i - m) << 16;
3798 } else
3799 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3800
3801 /* mark color semantic for light-twoside */
3802 n = 0x80;
3803 for (i = 0; i < p->cfg.in_nr; i++) {
3804 if (p->cfg.in[i].sn == TGSI_SEMANTIC_COLOR) {
3805 n = MIN2(n, p->cfg.in[i].hw - m);
3806 p->cfg.two_side[p->cfg.in[i].si] = p->cfg.in[i];
3807
3808 p->cfg.regs[0] += /* increase colour count */
3809 popcnt4(p->cfg.in[i].mask) << 16;
3810 }
3811 }
3812 if (n < 0x80)
3813 p->cfg.regs[0] += n;
3814
3815 if (p->cfg.prim_id < 0x40) {
3816 pc->sysval[p->cfg.prim_id].rhw = rid++;
3817 emit_interp(pc, &pc->sysval[p->cfg.prim_id], NULL,
3818 INTERP_FLAT);
3819 /* increase FP_INTERPOLANT_CTRL_COUNT */
3820 p->cfg.regs[1] += 1;
3821 }
3822
3823 /* Initialize FP results:
3824 * FragDepth is always first TGSI and last hw output
3825 */
3826 i = p->info.writes_z ? 4 : 0;
3827 for (rid = 0; i < pc->result_nr * 4; i++)
3828 pc->result[i].rhw = rid++;
3829 if (p->info.writes_z)
3830 pc->result[2].rhw = rid++;
3831
3832 p->cfg.high_result = rid;
3833
3834 /* separate/different colour results for MRTs ? */
3835 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3836 p->cfg.regs[2] |= 1;
3837 }
3838
3839 if (pc->immd_nr) {
3840 int rid = 0;
3841
3842 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3843 if (!pc->immd)
3844 goto out_err;
3845
3846 for (i = 0; i < pc->immd_nr; i++) {
3847 for (c = 0; c < 4; c++, rid++)
3848 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3849 }
3850 }
3851
3852 ret = TRUE;
3853 out_err:
3854 if (pc->iv_p)
3855 free_temp(pc, pc->iv_p);
3856 if (pc->iv_c)
3857 free_temp(pc, pc->iv_c);
3858
3859 tgsi_parse_free(&tp);
3860 return ret;
3861 }
3862
3863 static void
3864 free_nv50_pc(struct nv50_pc *pc)
3865 {
3866 if (pc->immd)
3867 FREE(pc->immd);
3868 if (pc->param)
3869 FREE(pc->param);
3870 if (pc->result)
3871 FREE(pc->result);
3872 if (pc->attr)
3873 FREE(pc->attr);
3874 if (pc->temp)
3875 FREE(pc->temp);
3876 if (pc->sysval)
3877 FREE(pc->sysval);
3878 if (pc->insn_pos)
3879 FREE(pc->insn_pos);
3880
3881 FREE(pc);
3882 }
3883
3884 static INLINE uint32_t
3885 nv50_map_gs_output_prim(unsigned pprim)
3886 {
3887 switch (pprim) {
3888 case PIPE_PRIM_POINTS:
3889 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_POINTS;
3890 case PIPE_PRIM_LINE_STRIP:
3891 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP;
3892 case PIPE_PRIM_TRIANGLE_STRIP:
3893 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP;
3894 default:
3895 NOUVEAU_ERR("invalid GS_OUTPUT_PRIMITIVE: %u\n", pprim);
3896 abort();
3897 return 0;
3898 }
3899 }
3900
3901 static boolean
3902 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3903 {
3904 int i, c;
3905 unsigned rtype[2] = { P_ATTR, P_RESULT };
3906
3907 pc->p = p;
3908 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3909 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3910 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3911 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3912 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3913 assert(pc->addr_nr <= 2);
3914 pc->sysval_nr = p->info.file_max[TGSI_FILE_SYSTEM_VALUE] + 1;
3915
3916 p->cfg.high_temp = 4;
3917
3918 p->cfg.two_side[0].hw = 0x40;
3919 p->cfg.two_side[1].hw = 0x40;
3920 p->cfg.prim_id = 0x40;
3921
3922 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3923
3924 for (i = 0; i < p->info.num_properties; ++i) {
3925 unsigned *data = &p->info.properties[i].data[0];
3926
3927 switch (p->info.properties[i].name) {
3928 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
3929 p->cfg.prim_type = nv50_map_gs_output_prim(data[0]);
3930 break;
3931 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
3932 p->cfg.vert_count = data[0];
3933 break;
3934 default:
3935 break;
3936 }
3937 }
3938
3939 switch (p->type) {
3940 case PIPE_SHADER_VERTEX:
3941 p->cfg.psiz = 0x40;
3942 p->cfg.clpd = 0x40;
3943 p->cfg.out_nr = pc->result_nr;
3944 break;
3945 case PIPE_SHADER_GEOMETRY:
3946 assert(p->cfg.prim_type);
3947 assert(p->cfg.vert_count);
3948
3949 p->cfg.psiz = 0x80;
3950 p->cfg.clpd = 0x80;
3951 p->cfg.prim_id = 0x80;
3952 p->cfg.out_nr = pc->result_nr;
3953 p->cfg.in_nr = pc->attr_nr;
3954
3955 p->cfg.two_side[0].hw = 0x80;
3956 p->cfg.two_side[1].hw = 0x80;
3957 break;
3958 case PIPE_SHADER_FRAGMENT:
3959 rtype[0] = rtype[1] = P_TEMP;
3960
3961 p->cfg.regs[0] = 0x01000004;
3962 p->cfg.in_nr = pc->attr_nr;
3963
3964 if (p->info.writes_z) {
3965 p->cfg.regs[2] |= 0x00000100;
3966 p->cfg.regs[3] |= 0x00000011;
3967 }
3968 if (p->info.uses_kill)
3969 p->cfg.regs[2] |= 0x00100000;
3970 break;
3971 }
3972
3973 if (pc->temp_nr) {
3974 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3975 if (!pc->temp)
3976 return FALSE;
3977
3978 for (i = 0; i < pc->temp_nr * 4; ++i)
3979 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3980 }
3981
3982 if (pc->attr_nr) {
3983 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3984 if (!pc->attr)
3985 return FALSE;
3986
3987 for (i = 0; i < pc->attr_nr * 4; ++i)
3988 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3989 }
3990
3991 if (pc->result_nr) {
3992 unsigned nr = pc->result_nr * 4;
3993
3994 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3995 if (!pc->result)
3996 return FALSE;
3997
3998 for (i = 0; i < nr; ++i)
3999 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
4000 }
4001
4002 if (pc->param_nr) {
4003 int rid = 0;
4004
4005 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
4006 if (!pc->param)
4007 return FALSE;
4008
4009 for (i = 0; i < pc->param_nr; ++i)
4010 for (c = 0; c < 4; ++c, ++rid)
4011 ctor_reg(&pc->param[rid], P_CONST, i, rid);
4012 }
4013
4014 if (pc->addr_nr) {
4015 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
4016 if (!pc->addr)
4017 return FALSE;
4018 }
4019 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
4020 ctor_reg(&pc->r_addr[i], P_ADDR, -1, i + 1);
4021
4022 if (pc->sysval_nr) {
4023 pc->sysval = CALLOC(pc->sysval_nr, sizeof(struct nv50_reg *));
4024 if (!pc->sysval)
4025 return FALSE;
4026 /* will only ever use SYSTEM_VALUE[i].x (hopefully) */
4027 for (i = 0; i < pc->sysval_nr; ++i)
4028 ctor_reg(&pc->sysval[i], rtype[0], i, -1);
4029 }
4030
4031 return TRUE;
4032 }
4033
4034 static void
4035 nv50_program_fixup_insns(struct nv50_pc *pc)
4036 {
4037 struct nv50_program_exec *e, **bra_list;
4038 unsigned i, n, pos;
4039
4040 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
4041
4042 /* Collect branch instructions, we need to adjust their offsets
4043 * when converting 32 bit instructions to 64 bit ones
4044 */
4045 for (n = 0, e = pc->p->exec_head; e; e = e->next)
4046 if (e->param.index >= 0 && !e->param.mask)
4047 bra_list[n++] = e;
4048
4049 /* Make sure we don't have any single 32 bit instructions. */
4050 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
4051 pos += is_long(e) ? 2 : 1;
4052
4053 if ((pos & 1) && (!e->next || is_long(e->next))) {
4054 for (i = 0; i < n; ++i)
4055 if (bra_list[i]->param.index >= pos)
4056 bra_list[i]->param.index += 1;
4057 for (i = 0; i < pc->insn_nr; ++i)
4058 if (pc->insn_pos[i] >= pos)
4059 pc->insn_pos[i] += 1;
4060 convert_to_long(pc, e);
4061 ++pos;
4062 }
4063 }
4064
4065 FREE(bra_list);
4066
4067 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
4068 return;
4069
4070 /* fill in CALL offsets */
4071 for (e = pc->p->exec_head; e; e = e->next) {
4072 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
4073 e->param.index = pc->insn_pos[e->param.index];
4074 }
4075 }
4076
4077 static boolean
4078 nv50_program_tx(struct nv50_program *p)
4079 {
4080 struct tgsi_parse_context parse;
4081 struct nv50_pc *pc;
4082 boolean ret;
4083
4084 pc = CALLOC_STRUCT(nv50_pc);
4085 if (!pc)
4086 return FALSE;
4087
4088 ret = ctor_nv50_pc(pc, p);
4089 if (ret == FALSE)
4090 goto out_cleanup;
4091
4092 ret = nv50_program_tx_prep(pc);
4093 if (ret == FALSE)
4094 goto out_cleanup;
4095
4096 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
4097
4098 tgsi_parse_init(&parse, pc->p->pipe.tokens);
4099 while (!tgsi_parse_end_of_tokens(&parse)) {
4100 const union tgsi_full_token *tok = &parse.FullToken;
4101
4102 /* previously allow32 was FALSE for first & last instruction */
4103 pc->allow32 = TRUE;
4104
4105 tgsi_parse_token(&parse);
4106
4107 switch (tok->Token.Type) {
4108 case TGSI_TOKEN_TYPE_INSTRUCTION:
4109 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
4110 ++pc->insn_cur;
4111 ret = nv50_tgsi_insn(pc, tok);
4112 if (ret == FALSE)
4113 goto out_err;
4114 break;
4115 default:
4116 break;
4117 }
4118 }
4119
4120 nv50_program_fixup_insns(pc);
4121
4122 p->param_nr = pc->param_nr * 4;
4123 p->immd_nr = pc->immd_nr * 4;
4124 p->immd = pc->immd_buf;
4125
4126 out_err:
4127 tgsi_parse_free(&parse);
4128
4129 out_cleanup:
4130 free_nv50_pc(pc);
4131 return ret;
4132 }
4133
4134 static void
4135 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
4136 {
4137 if (nv50_program_tx(p) == FALSE)
4138 assert(0);
4139 p->translated = TRUE;
4140 }
4141
4142 static void
4143 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
4144 unsigned start, unsigned count, unsigned cbuf)
4145 {
4146 struct nouveau_channel *chan = nv50->screen->base.channel;
4147 struct nouveau_grobj *tesla = nv50->screen->tesla;
4148
4149 while (count) {
4150 unsigned nr = count > 2047 ? 2047 : count;
4151
4152 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
4153 OUT_RING (chan, (cbuf << 0) | (start << 8));
4154 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
4155 OUT_RINGp (chan, map, nr);
4156
4157 map += nr;
4158 start += nr;
4159 count -= nr;
4160 }
4161 }
4162
4163 static void
4164 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
4165 {
4166 struct pipe_context *pipe = &nv50->pipe;
4167 struct pipe_transfer *transfer;
4168
4169 if (!p->data[0] && p->immd_nr) {
4170 struct nouveau_resource *heap = nv50->screen->immd_heap;
4171
4172 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
4173 while (heap->next && heap->size < p->immd_nr) {
4174 struct nv50_program *evict = heap->next->priv;
4175 nouveau_resource_free(&evict->data[0]);
4176 }
4177
4178 if (nouveau_resource_alloc(heap, p->immd_nr, p,
4179 &p->data[0]))
4180 assert(0);
4181 }
4182
4183 /* immediates only need to be uploaded again when freed */
4184 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
4185 p->immd_nr, NV50_CB_PMISC);
4186 }
4187
4188 assert(p->param_nr <= 16384);
4189
4190 if (p->param_nr) {
4191 unsigned cb;
4192 uint32_t *map = pipe_buffer_map(pipe,
4193 nv50->constbuf[p->type],
4194 PIPE_TRANSFER_READ,
4195 &transfer);
4196 switch (p->type) {
4197 case PIPE_SHADER_GEOMETRY: cb = NV50_CB_PGP; break;
4198 case PIPE_SHADER_FRAGMENT: cb = NV50_CB_PFP; break;
4199 default:
4200 cb = NV50_CB_PVP;
4201 assert(p->type == PIPE_SHADER_VERTEX);
4202 break;
4203 }
4204
4205 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
4206 pipe_buffer_unmap(pipe, nv50->constbuf[p->type],
4207 transfer);
4208 }
4209 }
4210
4211 static void
4212 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
4213 {
4214 struct nouveau_channel *chan = nv50->screen->base.channel;
4215 struct nouveau_grobj *tesla = nv50->screen->tesla;
4216 struct nv50_program_exec *e;
4217 uint32_t *up, i;
4218 boolean upload = FALSE;
4219 unsigned offset;
4220 int width;
4221
4222 if (!p->bo) {
4223 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
4224 p->exec_size * 4, &p->bo);
4225 upload = TRUE;
4226 }
4227
4228 if (p->data[0] && p->data[0]->start != p->data_start[0])
4229 upload = TRUE;
4230
4231 if (!upload)
4232 return;
4233
4234 up = MALLOC(p->exec_size * 4);
4235
4236 for (i = 0, e = p->exec_head; e; e = e->next) {
4237 unsigned ei, ci, bs;
4238
4239 if (e->param.index >= 0 && e->param.mask) {
4240 bs = (e->inst[1] >> 22) & 0x07;
4241 assert(bs < 2);
4242 ei = e->param.shift >> 5;
4243 ci = e->param.index;
4244 if (bs == 0)
4245 ci += p->data[bs]->start;
4246
4247 e->inst[ei] &= ~e->param.mask;
4248 e->inst[ei] |= (ci << e->param.shift);
4249 } else
4250 if (e->param.index >= 0) {
4251 /* zero mask means param is a jump/branch offset */
4252 assert(!(e->param.index & 1));
4253 /* seem to be 8 byte steps */
4254 ei = (e->param.index >> 1) + 0 /* START_ID */;
4255
4256 e->inst[0] &= 0xf0000fff;
4257 e->inst[0] |= ei << 12;
4258 }
4259
4260 up[i++] = e->inst[0];
4261 if (is_long(e))
4262 up[i++] = e->inst[1];
4263 }
4264 assert(i == p->exec_size);
4265
4266 if (p->data[0])
4267 p->data_start[0] = p->data[0]->start;
4268
4269 #ifdef NV50_PROGRAM_DUMP
4270 NOUVEAU_ERR("-------\n");
4271 for (e = p->exec_head; e; e = e->next) {
4272 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
4273 if (is_long(e))
4274 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
4275 }
4276 #endif
4277
4278 /* SIFC_HEIGHT/SIFC_WIDTH of 65536 do not work, and are not reported
4279 * as data error either. hw bug ? */
4280 #define SIFC_MAX_WIDTH (65536 - 256)
4281 offset = 0;
4282 width = p->exec_size * 4;
4283 while (width > 0) {
4284 nv50_upload_sifc(nv50, p->bo, offset, NOUVEAU_BO_VRAM,
4285 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
4286 &up[offset / 4], NV50_2D_SIFC_FORMAT_R8_UNORM,
4287 0, 0, 0, MIN2(SIFC_MAX_WIDTH, width), 1, 1);
4288 width -= SIFC_MAX_WIDTH;
4289 offset += SIFC_MAX_WIDTH;
4290 }
4291 BEGIN_RING(chan, tesla, NV50TCL_CODE_CB_FLUSH, 1);
4292 OUT_RING (chan, 0);
4293
4294 FREE(up);
4295 }
4296
4297 struct nouveau_stateobj *
4298 nv50_vertprog_validate(struct nv50_context *nv50)
4299 {
4300 struct nouveau_grobj *tesla = nv50->screen->tesla;
4301 struct nv50_program *p = nv50->vertprog;
4302 struct nouveau_stateobj *so;
4303
4304 if (!p->translated) {
4305 nv50_program_validate(nv50, p);
4306 if (!p->translated)
4307 assert(0);
4308 }
4309
4310 nv50_program_validate_data(nv50, p);
4311 nv50_program_validate_code(nv50, p);
4312
4313 if (!(nv50->dirty & NV50_NEW_VERTPROG))
4314 return NULL;
4315
4316 so = so_new(5, 7, 2);
4317 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
4318 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4319 NOUVEAU_BO_HIGH, 0, 0);
4320 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4321 NOUVEAU_BO_LOW, 0, 0);
4322 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
4323 so_data (so, p->cfg.attr[0]);
4324 so_data (so, p->cfg.attr[1]);
4325 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
4326 so_data (so, p->cfg.high_result);
4327 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_TEMP, 1);
4328 so_data (so, p->cfg.high_temp);
4329 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
4330 so_data (so, 0); /* program start offset */
4331 return so;
4332 }
4333
4334 struct nouveau_stateobj *
4335 nv50_fragprog_validate(struct nv50_context *nv50)
4336 {
4337 struct nouveau_grobj *tesla = nv50->screen->tesla;
4338 struct nv50_program *p = nv50->fragprog;
4339 struct nouveau_stateobj *so;
4340
4341 if (!p->translated) {
4342 nv50_program_validate(nv50, p);
4343 if (!p->translated)
4344 assert(0);
4345 }
4346
4347 nv50_program_validate_data(nv50, p);
4348 nv50_program_validate_code(nv50, p);
4349
4350 if (!(nv50->dirty & NV50_NEW_FRAGPROG))
4351 return NULL;
4352
4353 so = so_new(6, 7, 2);
4354 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
4355 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4356 NOUVEAU_BO_HIGH, 0, 0);
4357 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4358 NOUVEAU_BO_LOW, 0, 0);
4359 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
4360 so_data (so, p->cfg.high_temp);
4361 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
4362 so_data (so, p->cfg.high_result);
4363 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
4364 so_data (so, p->cfg.regs[2]);
4365 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
4366 so_data (so, p->cfg.regs[3]);
4367 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
4368 so_data (so, 0); /* program start offset */
4369 return so;
4370 }
4371
4372 struct nouveau_stateobj *
4373 nv50_geomprog_validate(struct nv50_context *nv50)
4374 {
4375 struct nouveau_grobj *tesla = nv50->screen->tesla;
4376 struct nv50_program *p = nv50->geomprog;
4377 struct nouveau_stateobj *so;
4378
4379 if (!p->translated) {
4380 nv50_program_validate(nv50, p);
4381 if (!p->translated)
4382 assert(0);
4383 }
4384
4385 nv50_program_validate_data(nv50, p);
4386 nv50_program_validate_code(nv50, p);
4387
4388 if (!(nv50->dirty & NV50_NEW_GEOMPROG))
4389 return NULL;
4390
4391 so = so_new(6, 7, 2);
4392 so_method(so, tesla, NV50TCL_GP_ADDRESS_HIGH, 2);
4393 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4394 NOUVEAU_BO_HIGH, 0, 0);
4395 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4396 NOUVEAU_BO_LOW, 0, 0);
4397 so_method(so, tesla, NV50TCL_GP_REG_ALLOC_TEMP, 1);
4398 so_data (so, p->cfg.high_temp);
4399 so_method(so, tesla, NV50TCL_GP_REG_ALLOC_RESULT, 1);
4400 so_data (so, p->cfg.high_result);
4401 so_method(so, tesla, NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE, 1);
4402 so_data (so, p->cfg.prim_type);
4403 so_method(so, tesla, NV50TCL_GP_VERTEX_OUTPUT_COUNT, 1);
4404 so_data (so, p->cfg.vert_count);
4405 so_method(so, tesla, NV50TCL_GP_START_ID, 1);
4406 so_data (so, 0);
4407 return so;
4408 }
4409
4410 static uint32_t
4411 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
4412 {
4413 struct nv50_program *vp;
4414 struct nv50_program *fp = nv50->fragprog;
4415 unsigned i, c, m = base;
4416 uint32_t origin = 0x00000010;
4417
4418 vp = nv50->geomprog ? nv50->geomprog : nv50->vertprog;
4419
4420 /* XXX: this might not work correctly in all cases yet - we'll
4421 * just assume that an FP generic input that is not written in
4422 * the VP is PointCoord.
4423 */
4424 memset(pntc, 0, 8 * sizeof(uint32_t));
4425
4426 for (i = 0; i < fp->cfg.in_nr; i++) {
4427 unsigned j, n = popcnt4(fp->cfg.in[i].mask);
4428
4429 if (fp->cfg.in[i].sn != TGSI_SEMANTIC_GENERIC) {
4430 m += n;
4431 continue;
4432 }
4433
4434 for (j = 0; j < vp->cfg.out_nr; ++j)
4435 if (vp->cfg.out[j].sn == fp->cfg.in[i].sn &&
4436 vp->cfg.out[j].si == fp->cfg.in[i].si)
4437 break;
4438
4439 if (j < vp->info.num_outputs) {
4440 ubyte enable =
4441 (nv50->rasterizer->pipe.sprite_coord_enable >> vp->cfg.out[j].si) & 1;
4442
4443 if (enable == 0) {
4444 m += n;
4445 continue;
4446 }
4447 }
4448
4449 /* this is either PointCoord or replaced by sprite coords */
4450 for (c = 0; c < 4; c++) {
4451 if (!(fp->cfg.in[i].mask & (1 << c)))
4452 continue;
4453 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
4454 ++m;
4455 }
4456 }
4457 return (nv50->rasterizer->pipe.sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT ? 0 : origin);
4458 }
4459
4460 static int
4461 nv50_vec4_map(uint32_t *map32, int mid, uint8_t zval, uint32_t lin[4],
4462 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
4463 {
4464 int c;
4465 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
4466 uint8_t *map = (uint8_t *)map32;
4467
4468 for (c = 0; c < 4; ++c) {
4469 if (mf & 1) {
4470 if (fpi->linear == TRUE)
4471 lin[mid / 32] |= 1 << (mid % 32);
4472 if (mv & 1)
4473 map[mid] = oid;
4474 else
4475 map[mid] = (c == 3) ? (zval + 1) : zval;
4476 ++mid;
4477 }
4478
4479 oid += mv & 1;
4480 mf >>= 1;
4481 mv >>= 1;
4482 }
4483
4484 return mid;
4485 }
4486
4487 struct nouveau_stateobj *
4488 nv50_fp_linkage_validate(struct nv50_context *nv50)
4489 {
4490 struct nouveau_grobj *tesla = nv50->screen->tesla;
4491 struct nv50_program *vp = nv50->vertprog;
4492 struct nv50_program *fp = nv50->fragprog;
4493 struct nouveau_stateobj *so;
4494 struct nv50_sreg4 dummy;
4495 int i, n, c, m = 0;
4496 uint32_t map[16], lin[4], reg[6], pcrd[8];
4497 uint8_t zval = 0x40;
4498
4499 if (nv50->geomprog) {
4500 vp = nv50->geomprog;
4501 zval = 0x80;
4502 }
4503 memset(map, 0, sizeof(map));
4504 memset(lin, 0, sizeof(lin));
4505
4506 reg[1] = 0x00000004; /* low and high clip distance map ids */
4507 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
4508 reg[3] = 0x00000000; /* point size map id & enable */
4509 reg[5] = 0x00000000; /* primitive ID map slot */
4510 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
4511 reg[4] = fp->cfg.regs[1]; /* interpolant info */
4512
4513 dummy.linear = FALSE;
4514 dummy.mask = 0xf; /* map all components of HPOS */
4515 m = nv50_vec4_map(map, m, zval, lin, &dummy, &vp->cfg.out[0]);
4516
4517 dummy.mask = 0x0;
4518
4519 if (vp->cfg.clpd < 0x40) {
4520 for (c = 0; c < vp->cfg.clpd_nr; ++c) {
4521 map[m / 4] |= (vp->cfg.clpd + c) << ((m % 4) * 8);
4522 ++m;
4523 }
4524 reg[1] = (m << 8);
4525 }
4526
4527 reg[0] |= m << 8; /* adjust BFC0 id */
4528
4529 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
4530 if (nv50->rasterizer->pipe.light_twoside) {
4531 struct nv50_sreg4 *vpo = &vp->cfg.two_side[0];
4532 struct nv50_sreg4 *fpi = &fp->cfg.two_side[0];
4533
4534 m = nv50_vec4_map(map, m, zval, lin, &fpi[0], &vpo[0]);
4535 m = nv50_vec4_map(map, m, zval, lin, &fpi[1], &vpo[1]);
4536 }
4537
4538 reg[0] += m - 4; /* adjust FFC0 id */
4539 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
4540
4541 for (i = 0; i < fp->cfg.in_nr; i++) {
4542 /* maybe even remove these from cfg.io */
4543 if (fp->cfg.in[i].sn == TGSI_SEMANTIC_POSITION ||
4544 fp->cfg.in[i].sn == TGSI_SEMANTIC_FACE)
4545 continue;
4546
4547 for (n = 0; n < vp->cfg.out_nr; ++n)
4548 if (vp->cfg.out[n].sn == fp->cfg.in[i].sn &&
4549 vp->cfg.out[n].si == fp->cfg.in[i].si)
4550 break;
4551
4552 m = nv50_vec4_map(map, m, zval, lin, &fp->cfg.in[i],
4553 (n < vp->cfg.out_nr) ?
4554 &vp->cfg.out[n] : &dummy);
4555 }
4556 /* PrimitiveID either is replaced by the system value, or
4557 * written by the geometry shader into an output register
4558 */
4559 if (fp->cfg.prim_id < 0x40) {
4560 map[m / 4] |= vp->cfg.prim_id << ((m % 4) * 8);
4561 reg[5] = m++;
4562 }
4563
4564 if (nv50->rasterizer->pipe.point_size_per_vertex) {
4565 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
4566 reg[3] = (m++ << 4) | 1;
4567 }
4568
4569 /* now fill the stateobj (at most 28 so_data) */
4570 so = so_new(10, 54, 0);
4571
4572 n = (m + 3) / 4;
4573 assert(m <= 64);
4574 if (vp->type == PIPE_SHADER_GEOMETRY) {
4575 so_method(so, tesla, NV50TCL_GP_RESULT_MAP_SIZE, 1);
4576 so_data (so, m);
4577 so_method(so, tesla, NV50TCL_GP_RESULT_MAP(0), n);
4578 so_datap (so, map, n);
4579 } else {
4580 so_method(so, tesla, NV50TCL_VP_GP_BUILTIN_ATTR_EN, 1);
4581 so_data (so, vp->cfg.regs[0]);
4582
4583 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_4, 1);
4584 so_data (so, reg[5]);
4585
4586 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4587 so_data (so, m);
4588 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
4589 so_datap (so, map, n);
4590 }
4591
4592 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
4593 so_datap (so, reg, 4);
4594
4595 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
4596 so_data (so, reg[4]);
4597
4598 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
4599 so_datap (so, lin, 4);
4600
4601 if (nv50->rasterizer->pipe.sprite_coord_enable) {
4602 so_method(so, tesla, NV50TCL_POINT_SPRITE_CTRL, 1);
4603 so_data (so,
4604 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff));
4605
4606 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
4607 so_datap (so, pcrd, 8);
4608 }
4609
4610 so_method(so, tesla, NV50TCL_GP_ENABLE, 1);
4611 so_data (so, (vp->type == PIPE_SHADER_GEOMETRY) ? 1 : 0);
4612
4613 return so;
4614 }
4615
4616 static int
4617 construct_vp_gp_mapping(uint32_t *map32, int m,
4618 struct nv50_program *vp, struct nv50_program *gp)
4619 {
4620 uint8_t *map = (uint8_t *)map32;
4621 int i, j, c;
4622
4623 for (i = 0; i < gp->cfg.in_nr; ++i) {
4624 uint8_t oid = 0, mv = 0, mg = gp->cfg.in[i].mask;
4625
4626 for (j = 0; j < vp->cfg.out_nr; ++j) {
4627 if (vp->cfg.out[j].sn == gp->cfg.in[i].sn &&
4628 vp->cfg.out[j].si == gp->cfg.in[i].si) {
4629 mv = vp->cfg.out[j].mask;
4630 oid = vp->cfg.out[j].hw;
4631 break;
4632 }
4633 }
4634
4635 for (c = 0; c < 4; ++c, mv >>= 1, mg >>= 1) {
4636 if (mg & mv & 1)
4637 map[m++] = oid;
4638 else
4639 if (mg & 1)
4640 map[m++] = (c == 3) ? 0x41 : 0x40;
4641 oid += mv & 1;
4642 }
4643 }
4644 return m;
4645 }
4646
4647 struct nouveau_stateobj *
4648 nv50_gp_linkage_validate(struct nv50_context *nv50)
4649 {
4650 struct nouveau_grobj *tesla = nv50->screen->tesla;
4651 struct nouveau_stateobj *so;
4652 struct nv50_program *vp = nv50->vertprog;
4653 struct nv50_program *gp = nv50->geomprog;
4654 uint32_t map[16];
4655 int m = 0;
4656
4657 if (!gp)
4658 return NULL;
4659 memset(map, 0, sizeof(map));
4660
4661 m = construct_vp_gp_mapping(map, m, vp, gp);
4662
4663 so = so_new(3, 24 - 3, 0);
4664
4665 so_method(so, tesla, NV50TCL_VP_GP_BUILTIN_ATTR_EN, 1);
4666 so_data (so, vp->cfg.regs[0] | gp->cfg.regs[0]);
4667
4668 assert(m <= 32);
4669 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4670 so_data (so, m);
4671
4672 m = (m + 3) / 4;
4673 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), m);
4674 so_datap (so, map, m);
4675
4676 return so;
4677 }
4678
4679 void
4680 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
4681 {
4682 while (p->exec_head) {
4683 struct nv50_program_exec *e = p->exec_head;
4684
4685 p->exec_head = e->next;
4686 FREE(e);
4687 }
4688 p->exec_tail = NULL;
4689 p->exec_size = 0;
4690
4691 nouveau_bo_ref(NULL, &p->bo);
4692
4693 FREE(p->immd);
4694 nouveau_resource_free(&p->data[0]);
4695
4696 p->translated = 0;
4697 }