2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "util/u_inlines.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
32 #include "nv50_context.h"
33 #include "nv50_transfer.h"
35 #define NV50_SU_MAX_TEMP 127
36 #define NV50_SU_MAX_ADDR 4
37 //#define NV50_PROGRAM_DUMP
39 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
41 /* ARL - gallium craps itself on progs/vp/arl.txt
43 * MSB - Like MAD, but MUL+SUB
44 * - Fuck it off, introduce a way to negate args for ops that
47 * Look into inlining IMMD for ops other than MOV (make it general?)
48 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
49 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
51 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
52 * case, if the emit_src() causes the inst to suddenly become long.
54 * Verify half-insns work where expected - and force disable them where they
55 * don't work - MUL has it forcibly disabled atm as it fixes POW..
57 * FUCK! watch dst==src vectors, can overwrite components that are needed.
58 * ie. SUB R0, R0.yzxw, R0
60 * Things to check with renouveau:
61 * FP attr/result assignment - how?
63 * - 0x16bc maps vp output onto fp hpos
64 * - 0x16c0 maps vp output onto fp col0
68 * 0x16bc->0x16e8 --> some binding between vp/fp regs
69 * 0x16b8 --> VP output count
71 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
72 * "MOV rcol.x, fcol.y" = 0x00000004
73 * 0x19a8 --> as above but 0x00000100 and 0x00000000
74 * - 0x00100000 used when KIL used
75 * 0x196c --> as above but 0x00000011 and 0x00000000
77 * 0x1988 --> 0xXXNNNNNN
78 * - XX == FP high something
94 int rhw
; /* result hw for FP outputs, or interpolant index */
95 int acc
; /* instruction where this reg is last read (first insn == 1) */
97 int vtx
; /* vertex index, for GP inputs (TGSI Dimension.Index) */
98 int indirect
[2]; /* index into pc->addr, or -1 */
100 ubyte buf_index
; /* c{0 .. 15}[] or g{0 .. 15}[] */
103 #define NV50_MOD_NEG 1
104 #define NV50_MOD_ABS 2
105 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
106 #define NV50_MOD_SAT 4
107 #define NV50_MOD_I32 8
109 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
111 /* STACK: Conditionals and loops have to use the (per warp) stack.
112 * Stack entries consist of an entry type (divergent path, join at),
113 * a mask indicating the active threads of the warp, and an address.
114 * MPs can store 12 stack entries internally, if we need more (and
115 * we probably do), we have to create a stack buffer in VRAM.
117 /* impose low limits for now */
118 #define NV50_MAX_COND_NESTING 4
119 #define NV50_MAX_LOOP_NESTING 3
121 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
124 struct nv50_program
*p
;
127 struct nv50_reg
*r_temp
[NV50_SU_MAX_TEMP
];
128 struct nv50_reg r_addr
[NV50_SU_MAX_ADDR
];
131 struct nv50_reg
*temp
;
133 struct nv50_reg
*attr
;
135 struct nv50_reg
*result
;
137 struct nv50_reg
*param
;
139 struct nv50_reg
*immd
;
142 struct nv50_reg
**addr
;
144 struct nv50_reg
*sysval
;
147 struct nv50_reg
*temp_temp
[16];
148 struct nv50_program_exec
*temp_temp_exec
[16];
149 unsigned temp_temp_nr
;
151 /* broadcast and destination replacement regs */
152 struct nv50_reg
*r_brdc
;
153 struct nv50_reg
*r_dst
[4];
155 struct nv50_reg reg_instances
[16];
156 unsigned reg_instance_nr
;
158 unsigned interp_mode
[32];
159 /* perspective interpolation registers */
160 struct nv50_reg
*iv_p
;
161 struct nv50_reg
*iv_c
;
163 struct nv50_program_exec
*if_insn
[NV50_MAX_COND_NESTING
];
164 struct nv50_program_exec
*if_join
[NV50_MAX_COND_NESTING
];
165 struct nv50_program_exec
*loop_brka
[NV50_MAX_LOOP_NESTING
];
166 int if_lvl
, loop_lvl
;
167 unsigned loop_pos
[NV50_MAX_LOOP_NESTING
];
169 unsigned *insn_pos
; /* actual program offset of each TGSI insn */
170 boolean in_subroutine
;
172 /* current instruction and total number of insns */
178 uint8_t edgeflag_out
;
181 static struct nv50_reg
*get_address_reg(struct nv50_pc
*, struct nv50_reg
*);
184 ctor_reg(struct nv50_reg
*reg
, unsigned type
, int index
, int hw
)
193 reg
->indirect
[0] = reg
->indirect
[1] = -1;
194 reg
->buf_index
= (type
== P_CONST
) ? 1 : 0;
197 static INLINE
unsigned
198 popcnt4(uint32_t val
)
200 static const unsigned cnt
[16]
201 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
202 return cnt
[val
& 0xf];
206 terminate_mbb(struct nv50_pc
*pc
)
210 /* remove records of temporary address register values */
211 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
212 if (pc
->r_addr
[i
].index
< 0)
213 pc
->r_addr
[i
].acc
= 0;
217 alloc_reg(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
221 if (reg
->type
== P_RESULT
) {
222 if (pc
->p
->cfg
.high_result
< (reg
->hw
+ 1))
223 pc
->p
->cfg
.high_result
= reg
->hw
+ 1;
226 if (reg
->type
!= P_TEMP
)
230 /*XXX: do this here too to catch FP temp-as-attr usage..
231 * not clean, but works */
232 if (pc
->p
->cfg
.high_temp
< (reg
->hw
+ 1))
233 pc
->p
->cfg
.high_temp
= reg
->hw
+ 1;
237 if (reg
->rhw
!= -1) {
238 /* try to allocate temporary with index rhw first */
239 if (!(pc
->r_temp
[reg
->rhw
])) {
240 pc
->r_temp
[reg
->rhw
] = reg
;
242 if (pc
->p
->cfg
.high_temp
< (reg
->rhw
+ 1))
243 pc
->p
->cfg
.high_temp
= reg
->rhw
+ 1;
246 /* make sure we don't get things like $r0 needs to go
247 * in $r1 and $r1 in $r0
249 i
= pc
->result_nr
* 4;
252 for (; i
< NV50_SU_MAX_TEMP
; i
++) {
253 if (!(pc
->r_temp
[i
])) {
256 if (pc
->p
->cfg
.high_temp
< (i
+ 1))
257 pc
->p
->cfg
.high_temp
= i
+ 1;
262 NOUVEAU_ERR("out of registers\n");
266 static INLINE
struct nv50_reg
*
267 reg_instance(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
271 assert(pc
->reg_instance_nr
< 16);
272 ri
= &pc
->reg_instances
[pc
->reg_instance_nr
++];
276 reg
->indirect
[0] = reg
->indirect
[1] = -1;
282 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
283 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
284 * lest we risk temp_temps overwriting regs alloc'd "later".
286 static struct nv50_reg
*
287 alloc_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
)
292 if (dst
&& dst
->type
== P_TEMP
&& dst
->hw
== -1)
295 for (i
= 0; i
< NV50_SU_MAX_TEMP
; i
++) {
296 if (!pc
->r_temp
[i
]) {
297 r
= MALLOC_STRUCT(nv50_reg
);
298 ctor_reg(r
, P_TEMP
, -1, i
);
304 NOUVEAU_ERR("out of registers\n");
310 /* release the hardware resource held by r */
312 release_hw(struct nv50_pc
*pc
, struct nv50_reg
*r
)
314 assert(r
->type
== P_TEMP
);
318 assert(pc
->r_temp
[r
->hw
] == r
);
319 pc
->r_temp
[r
->hw
] = NULL
;
328 free_temp(struct nv50_pc
*pc
, struct nv50_reg
*r
)
330 if (r
->index
== -1) {
333 FREE(pc
->r_temp
[hw
]);
334 pc
->r_temp
[hw
] = NULL
;
339 alloc_temp4(struct nv50_pc
*pc
, struct nv50_reg
*dst
[4], int idx
)
343 if ((idx
+ 4) >= NV50_SU_MAX_TEMP
)
346 if (pc
->r_temp
[idx
] || pc
->r_temp
[idx
+ 1] ||
347 pc
->r_temp
[idx
+ 2] || pc
->r_temp
[idx
+ 3])
348 return alloc_temp4(pc
, dst
, idx
+ 4);
350 for (i
= 0; i
< 4; i
++) {
351 dst
[i
] = MALLOC_STRUCT(nv50_reg
);
352 ctor_reg(dst
[i
], P_TEMP
, -1, idx
+ i
);
353 pc
->r_temp
[idx
+ i
] = dst
[i
];
360 free_temp4(struct nv50_pc
*pc
, struct nv50_reg
*reg
[4])
364 for (i
= 0; i
< 4; i
++)
365 free_temp(pc
, reg
[i
]);
368 static struct nv50_reg
*
369 temp_temp(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
371 if (pc
->temp_temp_nr
>= 16)
374 pc
->temp_temp
[pc
->temp_temp_nr
] = alloc_temp(pc
, NULL
);
375 pc
->temp_temp_exec
[pc
->temp_temp_nr
] = e
;
376 return pc
->temp_temp
[pc
->temp_temp_nr
++];
379 /* This *must* be called for all nv50_program_exec that have been
380 * given as argument to temp_temp, or the temps will be leaked !
383 kill_temp_temp(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
387 for (i
= 0; i
< pc
->temp_temp_nr
; i
++)
388 if (pc
->temp_temp_exec
[i
] == e
)
389 free_temp(pc
, pc
->temp_temp
[i
]);
391 pc
->temp_temp_nr
= 0;
395 ctor_immd_4u32(struct nv50_pc
*pc
,
396 uint32_t x
, uint32_t y
, uint32_t z
, uint32_t w
)
398 unsigned size
= pc
->immd_nr
* 4 * sizeof(uint32_t);
400 pc
->immd_buf
= REALLOC(pc
->immd_buf
, size
, size
+ 4 * sizeof(uint32_t));
402 pc
->immd_buf
[(pc
->immd_nr
* 4) + 0] = x
;
403 pc
->immd_buf
[(pc
->immd_nr
* 4) + 1] = y
;
404 pc
->immd_buf
[(pc
->immd_nr
* 4) + 2] = z
;
405 pc
->immd_buf
[(pc
->immd_nr
* 4) + 3] = w
;
407 return pc
->immd_nr
++;
411 ctor_immd_4f32(struct nv50_pc
*pc
, float x
, float y
, float z
, float w
)
413 return ctor_immd_4u32(pc
, fui(x
), fui(y
), fui(z
), fui(w
));
416 static struct nv50_reg
*
417 alloc_immd(struct nv50_pc
*pc
, float f
)
419 struct nv50_reg
*r
= MALLOC_STRUCT(nv50_reg
);
422 for (hw
= 0; hw
< pc
->immd_nr
* 4; hw
++)
423 if (pc
->immd_buf
[hw
] == fui(f
))
426 if (hw
== pc
->immd_nr
* 4)
427 hw
= ctor_immd_4f32(pc
, f
, -f
, 0.5 * f
, 0) * 4;
429 ctor_reg(r
, P_IMMD
, -1, hw
);
433 static struct nv50_program_exec
*
434 exec(struct nv50_pc
*pc
)
436 struct nv50_program_exec
*e
= CALLOC_STRUCT(nv50_program_exec
);
443 emit(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
445 struct nv50_program
*p
= pc
->p
;
448 p
->exec_tail
->next
= e
;
452 p
->exec_size
+= (e
->inst
[0] & 1) ? 2 : 1;
454 kill_temp_temp(pc
, e
);
457 static INLINE
void set_long(struct nv50_pc
*, struct nv50_program_exec
*);
460 is_long(struct nv50_program_exec
*e
)
468 is_immd(struct nv50_program_exec
*e
)
470 if (is_long(e
) && (e
->inst
[1] & 3) == 3)
476 is_join(struct nv50_program_exec
*e
)
478 if (is_long(e
) && (e
->inst
[1] & 3) == 2)
483 static INLINE boolean
484 is_control_flow(struct nv50_program_exec
*e
)
486 return (e
->inst
[0] & 2);
490 set_pred(struct nv50_pc
*pc
, unsigned pred
, unsigned idx
,
491 struct nv50_program_exec
*e
)
495 e
->inst
[1] &= ~((0x1f << 7) | (0x3 << 12));
496 e
->inst
[1] |= (pred
<< 7) | (idx
<< 12);
500 set_pred_wr(struct nv50_pc
*pc
, unsigned on
, unsigned idx
,
501 struct nv50_program_exec
*e
)
504 e
->inst
[1] &= ~((0x3 << 4) | (1 << 6));
505 e
->inst
[1] |= (idx
<< 4) | (on
<< 6);
509 set_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
515 set_pred(pc
, 0xf, 0, e
);
516 set_pred_wr(pc
, 0, 0, e
);
520 set_dst(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_program_exec
*e
)
522 if (dst
->type
== P_RESULT
) {
524 e
->inst
[1] |= 0x00000008;
530 e
->inst
[0] |= (dst
->hw
<< 2);
534 set_immd(struct nv50_pc
*pc
, struct nv50_reg
*imm
, struct nv50_program_exec
*e
)
537 /* XXX: can't be predicated - bits overlap; cases where both
538 * are required should be avoided by using pc->allow32 */
539 set_pred(pc
, 0, 0, e
);
540 set_pred_wr(pc
, 0, 0, e
);
542 e
->inst
[1] |= 0x00000002 | 0x00000001;
543 e
->inst
[0] |= (pc
->immd_buf
[imm
->hw
] & 0x3f) << 16;
544 e
->inst
[1] |= (pc
->immd_buf
[imm
->hw
] >> 6) << 2;
548 set_addr(struct nv50_program_exec
*e
, struct nv50_reg
*a
)
550 assert(a
->type
== P_ADDR
);
552 assert(!(e
->inst
[0] & 0x0c000000));
553 assert(!(e
->inst
[1] & 0x00000004));
555 e
->inst
[0] |= (a
->hw
& 3) << 26;
556 e
->inst
[1] |= a
->hw
& 4;
560 emit_arl(struct nv50_pc
*, struct nv50_reg
*, struct nv50_reg
*, uint8_t);
563 emit_shl_imm(struct nv50_pc
*, struct nv50_reg
*, struct nv50_reg
*, int);
566 emit_mov_from_addr(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
567 struct nv50_reg
*src
)
569 struct nv50_program_exec
*e
= exec(pc
);
571 e
->inst
[1] = 0x40000000;
580 emit_add_addr_imm(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
581 struct nv50_reg
*src0
, uint16_t src1_val
)
583 struct nv50_program_exec
*e
= exec(pc
);
585 e
->inst
[0] = 0xd0000000 | (src1_val
<< 9);
586 e
->inst
[1] = 0x20000000;
588 e
->inst
[0] |= dst
->hw
<< 2;
589 if (src0
) /* otherwise will add to $a0, which is always 0 */
595 #define INTERP_LINEAR 0
596 #define INTERP_FLAT 1
597 #define INTERP_PERSPECTIVE 2
598 #define INTERP_CENTROID 4
600 /* interpolant index has been stored in dst->rhw */
602 emit_interp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*iv
,
605 struct nv50_program_exec
*e
= exec(pc
);
606 assert(dst
->rhw
!= -1);
608 e
->inst
[0] |= 0x80000000;
610 e
->inst
[0] |= (dst
->rhw
<< 16);
612 if (mode
& INTERP_FLAT
) {
613 e
->inst
[0] |= (1 << 8);
615 if (mode
& INTERP_PERSPECTIVE
) {
616 e
->inst
[0] |= (1 << 25);
618 e
->inst
[0] |= (iv
->hw
<< 9);
621 if (mode
& INTERP_CENTROID
)
622 e
->inst
[0] |= (1 << 24);
629 set_data(struct nv50_pc
*pc
, struct nv50_reg
*src
, unsigned m
, unsigned s
,
630 struct nv50_program_exec
*e
)
634 e
->param
.index
= src
->hw
& 127;
636 e
->param
.mask
= m
<< (s
% 32);
638 if (src
->hw
< 0 || src
->hw
> 127) /* need (additional) address reg */
639 set_addr(e
, get_address_reg(pc
, src
));
642 assert(src
->type
== P_CONST
);
643 set_addr(e
, pc
->addr
[src
->indirect
[0]]);
646 e
->inst
[1] |= (src
->buf_index
<< 22);
649 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
651 emit_mov(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
653 struct nv50_program_exec
*e
= exec(pc
);
655 e
->inst
[0] = 0x10000000;
661 if (!is_long(e
) && src
->type
== P_IMMD
) {
662 set_immd(pc
, src
, e
);
663 /*XXX: 32-bit, but steals part of "half" reg space - need to
664 * catch and handle this case if/when we do half-regs
667 if (src
->type
== P_IMMD
|| src
->type
== P_CONST
) {
669 set_data(pc
, src
, 0x7f, 9, e
);
670 e
->inst
[1] |= 0x20000000; /* mov from c[] */
672 if (src
->type
== P_ATTR
) {
674 e
->inst
[1] |= 0x00200000;
677 /* indirect (vertex base + c) load from p[] */
678 e
->inst
[0] |= 0x01800000;
679 set_addr(e
, get_address_reg(pc
, src
));
686 e
->inst
[0] |= (src
->hw
<< 9);
689 if (is_long(e
) && !is_immd(e
)) {
690 e
->inst
[1] |= 0x04000000; /* 32-bit */
691 e
->inst
[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
692 if (!(e
->inst
[1] & 0x20000000))
693 e
->inst
[1] |= 0x00030000; /* lane mask 2:3 */
695 e
->inst
[0] |= 0x00008000;
701 emit_mov_immdval(struct nv50_pc
*pc
, struct nv50_reg
*dst
, float f
)
703 struct nv50_reg
*imm
= alloc_immd(pc
, f
);
704 emit_mov(pc
, dst
, imm
);
708 /* Assign the hw of the discarded temporary register src
709 * to the tgsi register dst and free src.
712 assimilate_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
714 assert(src
->index
== -1 && src
->hw
!= -1);
716 if (pc
->if_lvl
|| pc
->loop_lvl
||
717 (dst
->type
!= P_TEMP
) ||
718 (src
->hw
< pc
->result_nr
* 4 &&
719 pc
->p
->type
== PIPE_SHADER_FRAGMENT
) ||
720 pc
->p
->info
.opcode_count
[TGSI_OPCODE_CAL
] ||
721 pc
->p
->info
.opcode_count
[TGSI_OPCODE_BRA
]) {
723 emit_mov(pc
, dst
, src
);
729 pc
->r_temp
[dst
->hw
] = NULL
;
730 pc
->r_temp
[src
->hw
] = dst
;
737 emit_nop(struct nv50_pc
*pc
)
739 struct nv50_program_exec
*e
= exec(pc
);
741 e
->inst
[0] = 0xf0000000;
743 e
->inst
[1] = 0xe0000000;
748 check_swap_src_0_1(struct nv50_pc
*pc
,
749 struct nv50_reg
**s0
, struct nv50_reg
**s1
)
751 struct nv50_reg
*src0
= *s0
, *src1
= *s1
;
753 if (src0
->type
== P_CONST
) {
754 if (src1
->type
!= P_CONST
) {
760 if (src1
->type
== P_ATTR
) {
761 if (src0
->type
!= P_ATTR
) {
772 set_src_0_restricted(struct nv50_pc
*pc
, struct nv50_reg
*src
,
773 struct nv50_program_exec
*e
)
775 struct nv50_reg
*temp
;
777 if (src
->type
!= P_TEMP
) {
778 temp
= temp_temp(pc
, e
);
779 emit_mov(pc
, temp
, src
);
786 e
->inst
[0] |= (src
->hw
<< 9);
790 set_src_0(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
792 if (src
->type
== P_ATTR
) {
794 e
->inst
[1] |= 0x00200000;
797 e
->inst
[0] |= 0x01800000; /* src from p[] */
798 set_addr(e
, get_address_reg(pc
, src
));
801 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
802 struct nv50_reg
*temp
= temp_temp(pc
, e
);
804 emit_mov(pc
, temp
, src
);
811 e
->inst
[0] |= (src
->hw
<< 9);
815 set_src_1(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
817 if (src
->type
== P_ATTR
) {
818 struct nv50_reg
*temp
= temp_temp(pc
, e
);
820 emit_mov(pc
, temp
, src
);
823 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
824 if (e
->inst
[0] & 0x01800000) {
825 struct nv50_reg
*temp
= temp_temp(pc
, e
);
827 emit_mov(pc
, temp
, src
);
830 assert(!(e
->inst
[0] & 0x00800000));
831 set_data(pc
, src
, 0x7f, 16, e
);
832 e
->inst
[0] |= 0x00800000;
839 e
->inst
[0] |= ((src
->hw
& 127) << 16);
843 set_src_2(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
847 if (src
->type
== P_ATTR
) {
848 struct nv50_reg
*temp
= temp_temp(pc
, e
);
850 emit_mov(pc
, temp
, src
);
853 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
854 if (e
->inst
[0] & 0x01800000) {
855 struct nv50_reg
*temp
= temp_temp(pc
, e
);
857 emit_mov(pc
, temp
, src
);
860 assert(!(e
->inst
[0] & 0x01000000));
861 set_data(pc
, src
, 0x7f, 32+14, e
);
862 e
->inst
[0] |= 0x01000000;
867 e
->inst
[1] |= ((src
->hw
& 127) << 14);
871 set_half_src(struct nv50_pc
*pc
, struct nv50_reg
*src
, int lh
,
872 struct nv50_program_exec
*e
, int pos
)
874 struct nv50_reg
*r
= src
;
877 if (r
->type
!= P_TEMP
) {
878 r
= temp_temp(pc
, e
);
879 emit_mov(pc
, r
, src
);
882 if (r
->hw
> (NV50_SU_MAX_TEMP
/ 2)) {
883 NOUVEAU_ERR("out of low GPRs\n");
887 e
->inst
[pos
/ 32] |= ((src
->hw
* 2) + lh
) << (pos
% 32);
892 emit_mov_from_pred(struct nv50_pc
*pc
, struct nv50_reg
*dst
, int pred
)
894 struct nv50_program_exec
*e
= exec(pc
);
896 assert(dst
->type
== P_TEMP
);
897 e
->inst
[1] = 0x20000000 | (pred
<< 12);
906 emit_mov_to_pred(struct nv50_pc
*pc
, int pred
, struct nv50_reg
*src
)
908 struct nv50_program_exec
*e
= exec(pc
);
910 e
->inst
[0] = 0x000001fc;
911 e
->inst
[1] = 0xa0000008;
913 set_pred_wr(pc
, 1, pred
, e
);
914 set_src_0_restricted(pc
, src
, e
);
920 emit_mul(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
921 struct nv50_reg
*src1
)
923 struct nv50_program_exec
*e
= exec(pc
);
925 e
->inst
[0] |= 0xc0000000;
930 check_swap_src_0_1(pc
, &src0
, &src1
);
932 set_src_0(pc
, src0
, e
);
933 if (src1
->type
== P_IMMD
&& !is_long(e
)) {
934 if (src0
->mod
^ src1
->mod
)
935 e
->inst
[0] |= 0x00008000;
936 set_immd(pc
, src1
, e
);
938 set_src_1(pc
, src1
, e
);
939 if ((src0
->mod
^ src1
->mod
) & NV50_MOD_NEG
) {
941 e
->inst
[1] |= 0x08000000;
943 e
->inst
[0] |= 0x00008000;
951 emit_add(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
952 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
954 struct nv50_program_exec
*e
= exec(pc
);
956 e
->inst
[0] = 0xb0000000;
959 check_swap_src_0_1(pc
, &src0
, &src1
);
961 if (!pc
->allow32
|| (src0
->mod
| src1
->mod
) || src1
->hw
> 63) {
963 e
->inst
[1] |= ((src0
->mod
& NV50_MOD_NEG
) << 26) |
964 ((src1
->mod
& NV50_MOD_NEG
) << 27);
968 set_src_0(pc
, src0
, e
);
969 if (src1
->type
== P_CONST
|| src1
->type
== P_ATTR
|| is_long(e
))
970 set_src_2(pc
, src1
, e
);
972 if (src1
->type
== P_IMMD
)
973 set_immd(pc
, src1
, e
);
975 set_src_1(pc
, src1
, e
);
981 emit_arl(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
984 struct nv50_program_exec
*e
= exec(pc
);
987 e
->inst
[1] |= 0xc0000000;
989 e
->inst
[0] |= dst
->hw
<< 2;
990 e
->inst
[0] |= s
<< 16; /* shift left */
991 set_src_0(pc
, src
, e
);
997 address_reg_suitable(struct nv50_reg
*a
, struct nv50_reg
*r
)
1002 if (r
->vtx
!= a
->vtx
)
1005 return (r
->indirect
[1] == a
->indirect
[1]);
1007 if (r
->hw
< a
->rhw
|| (r
->hw
- a
->rhw
) >= 128)
1011 return (a
->index
== r
->indirect
[0]);
1012 return (a
->indirect
[0] == r
->indirect
[0]);
1016 load_vertex_base(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1017 struct nv50_reg
*a
, int shift
)
1019 struct nv50_reg mem
, *temp
;
1021 ctor_reg(&mem
, P_ATTR
, -1, dst
->vtx
);
1023 assert(dst
->type
== P_ADDR
);
1025 emit_arl(pc
, dst
, &mem
, 0);
1028 temp
= alloc_temp(pc
, NULL
);
1031 emit_mov_from_addr(pc
, temp
, a
);
1033 emit_shl_imm(pc
, temp
, temp
, shift
);
1034 emit_arl(pc
, dst
, temp
, MAX2(shift
, 0));
1036 emit_mov(pc
, temp
, &mem
);
1037 set_addr(pc
->p
->exec_tail
, dst
);
1039 emit_arl(pc
, dst
, temp
, 0);
1040 free_temp(pc
, temp
);
1043 /* case (ref == NULL): allocate address register for TGSI_FILE_ADDRESS
1044 * case (vtx >= 0, acc >= 0): load vertex base from a[vtx * 4] to $aX
1045 * case (vtx >= 0, acc < 0): load vertex base from s[$aY + vtx * 4] to $aX
1046 * case (vtx < 0, acc >= 0): memory address too high to encode
1047 * case (vtx < 0, acc < 0): get source register for TGSI_FILE_ADDRESS
1049 static struct nv50_reg
*
1050 get_address_reg(struct nv50_pc
*pc
, struct nv50_reg
*ref
)
1053 struct nv50_reg
*a_ref
, *a
= NULL
;
1055 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
) {
1056 if (pc
->r_addr
[i
].acc
== 0)
1057 a
= &pc
->r_addr
[i
]; /* an unused address reg */
1059 if (address_reg_suitable(&pc
->r_addr
[i
], ref
)) {
1060 pc
->r_addr
[i
].acc
= pc
->insn_cur
;
1061 return &pc
->r_addr
[i
];
1063 if (!a
&& pc
->r_addr
[i
].index
< 0 &&
1064 pc
->r_addr
[i
].acc
< pc
->insn_cur
)
1068 /* We'll be able to spill address regs when this
1069 * mess is replaced with a proper compiler ...
1071 NOUVEAU_ERR("out of address regs\n");
1076 /* initialize and reserve for this TGSI instruction */
1078 a
->index
= a
->indirect
[0] = a
->indirect
[1] = -1;
1079 a
->acc
= pc
->insn_cur
;
1087 /* now put in the correct value ... */
1089 if (ref
->vtx
>= 0) {
1090 a
->indirect
[1] = ref
->indirect
[1];
1092 /* For an indirect vertex index, we need to shift address right
1093 * by 2, the address register will contain vtx * 16, we need to
1094 * load from a[vtx * 4].
1096 load_vertex_base(pc
, a
, (ref
->acc
< 0) ?
1097 pc
->addr
[ref
->indirect
[1]] : NULL
, -2);
1099 assert(ref
->acc
< 0 || ref
->indirect
[0] < 0);
1101 a
->rhw
= ref
->hw
& ~0x7f;
1102 a
->indirect
[0] = ref
->indirect
[0];
1103 a_ref
= (ref
->acc
< 0) ? pc
->addr
[ref
->indirect
[0]] : NULL
;
1105 emit_add_addr_imm(pc
, a
, a_ref
, a
->rhw
* 4);
1110 #define NV50_MAX_F32 0x880
1111 #define NV50_MAX_S32 0x08c
1112 #define NV50_MAX_U32 0x084
1113 #define NV50_MIN_F32 0x8a0
1114 #define NV50_MIN_S32 0x0ac
1115 #define NV50_MIN_U32 0x0a4
1118 emit_minmax(struct nv50_pc
*pc
, unsigned sub
, struct nv50_reg
*dst
,
1119 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
1121 struct nv50_program_exec
*e
= exec(pc
);
1124 e
->inst
[0] |= 0x30000000 | ((sub
& 0x800) << 20);
1125 e
->inst
[1] |= (sub
<< 24);
1127 check_swap_src_0_1(pc
, &src0
, &src1
);
1128 set_dst(pc
, dst
, e
);
1129 set_src_0(pc
, src0
, e
);
1130 set_src_1(pc
, src1
, e
);
1132 if (src0
->mod
& NV50_MOD_ABS
)
1133 e
->inst
[1] |= 0x00100000;
1134 if (src1
->mod
& NV50_MOD_ABS
)
1135 e
->inst
[1] |= 0x00080000;
1141 emit_sub(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
1142 struct nv50_reg
*src1
)
1144 src1
->mod
^= NV50_MOD_NEG
;
1145 emit_add(pc
, dst
, src0
, src1
);
1146 src1
->mod
^= NV50_MOD_NEG
;
1150 emit_bitop2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
1151 struct nv50_reg
*src1
, unsigned op
)
1153 struct nv50_program_exec
*e
= exec(pc
);
1155 e
->inst
[0] = 0xd0000000;
1158 check_swap_src_0_1(pc
, &src0
, &src1
);
1159 set_dst(pc
, dst
, e
);
1160 set_src_0(pc
, src0
, e
);
1162 if (op
!= TGSI_OPCODE_AND
&& op
!= TGSI_OPCODE_OR
&&
1163 op
!= TGSI_OPCODE_XOR
)
1164 assert(!"invalid bit op");
1166 assert(!(src0
->mod
| src1
->mod
));
1168 if (src1
->type
== P_IMMD
&& src0
->type
== P_TEMP
&& pc
->allow32
) {
1169 set_immd(pc
, src1
, e
);
1170 if (op
== TGSI_OPCODE_OR
)
1171 e
->inst
[0] |= 0x0100;
1173 if (op
== TGSI_OPCODE_XOR
)
1174 e
->inst
[0] |= 0x8000;
1176 set_src_1(pc
, src1
, e
);
1177 e
->inst
[1] |= 0x04000000; /* 32 bit */
1178 if (op
== TGSI_OPCODE_OR
)
1179 e
->inst
[1] |= 0x4000;
1181 if (op
== TGSI_OPCODE_XOR
)
1182 e
->inst
[1] |= 0x8000;
1189 emit_not(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1191 struct nv50_program_exec
*e
= exec(pc
);
1193 e
->inst
[0] = 0xd0000000;
1194 e
->inst
[1] = 0x0402c000;
1196 set_dst(pc
, dst
, e
);
1197 set_src_1(pc
, src
, e
);
1203 emit_shift(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1204 struct nv50_reg
*src0
, struct nv50_reg
*src1
, unsigned dir
)
1206 struct nv50_program_exec
*e
= exec(pc
);
1208 e
->inst
[0] = 0x30000000;
1209 e
->inst
[1] = 0xc4000000;
1212 set_dst(pc
, dst
, e
);
1213 set_src_0(pc
, src0
, e
);
1215 if (src1
->type
== P_IMMD
) {
1216 e
->inst
[1] |= (1 << 20);
1217 e
->inst
[0] |= (pc
->immd_buf
[src1
->hw
] & 0x7f) << 16;
1219 set_src_1(pc
, src1
, e
);
1221 if (dir
!= TGSI_OPCODE_SHL
)
1222 e
->inst
[1] |= (1 << 29);
1224 if (dir
== TGSI_OPCODE_ISHR
)
1225 e
->inst
[1] |= (1 << 27);
1231 emit_shl_imm(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1232 struct nv50_reg
*src
, int s
)
1234 struct nv50_program_exec
*e
= exec(pc
);
1236 e
->inst
[0] = 0x30000000;
1237 e
->inst
[1] = 0xc4100000;
1239 e
->inst
[1] |= 1 << 29;
1242 e
->inst
[1] |= ((s
& 0x7f) << 16);
1245 set_dst(pc
, dst
, e
);
1246 set_src_0(pc
, src
, e
);
1252 emit_mad(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
1253 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
1255 struct nv50_program_exec
*e
= exec(pc
);
1257 e
->inst
[0] |= 0xe0000000;
1259 check_swap_src_0_1(pc
, &src0
, &src1
);
1260 set_dst(pc
, dst
, e
);
1261 set_src_0(pc
, src0
, e
);
1262 set_src_1(pc
, src1
, e
);
1263 set_src_2(pc
, src2
, e
);
1265 if ((src0
->mod
^ src1
->mod
) & NV50_MOD_NEG
)
1266 e
->inst
[1] |= 0x04000000;
1267 if (src2
->mod
& NV50_MOD_NEG
)
1268 e
->inst
[1] |= 0x08000000;
1274 emit_msb(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
1275 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
1277 src2
->mod
^= NV50_MOD_NEG
;
1278 emit_mad(pc
, dst
, src0
, src1
, src2
);
1279 src2
->mod
^= NV50_MOD_NEG
;
1282 #define NV50_FLOP_RCP 0
1283 #define NV50_FLOP_RSQ 2
1284 #define NV50_FLOP_LG2 3
1285 #define NV50_FLOP_SIN 4
1286 #define NV50_FLOP_COS 5
1287 #define NV50_FLOP_EX2 6
1289 /* rcp, rsqrt, lg2 support neg and abs */
1291 emit_flop(struct nv50_pc
*pc
, unsigned sub
,
1292 struct nv50_reg
*dst
, struct nv50_reg
*src
)
1294 struct nv50_program_exec
*e
= exec(pc
);
1296 e
->inst
[0] |= 0x90000000;
1297 if (sub
|| src
->mod
) {
1299 e
->inst
[1] |= (sub
<< 29);
1302 set_dst(pc
, dst
, e
);
1303 set_src_0_restricted(pc
, src
, e
);
1305 assert(!src
->mod
|| sub
< 4);
1307 if (src
->mod
& NV50_MOD_NEG
)
1308 e
->inst
[1] |= 0x04000000;
1309 if (src
->mod
& NV50_MOD_ABS
)
1310 e
->inst
[1] |= 0x00100000;
1316 emit_preex2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1318 struct nv50_program_exec
*e
= exec(pc
);
1320 e
->inst
[0] |= 0xb0000000;
1322 set_dst(pc
, dst
, e
);
1323 set_src_0(pc
, src
, e
);
1325 e
->inst
[1] |= (6 << 29) | 0x00004000;
1327 if (src
->mod
& NV50_MOD_NEG
)
1328 e
->inst
[1] |= 0x04000000;
1329 if (src
->mod
& NV50_MOD_ABS
)
1330 e
->inst
[1] |= 0x00100000;
1336 emit_precossin(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1338 struct nv50_program_exec
*e
= exec(pc
);
1340 e
->inst
[0] |= 0xb0000000;
1342 set_dst(pc
, dst
, e
);
1343 set_src_0(pc
, src
, e
);
1345 e
->inst
[1] |= (6 << 29);
1347 if (src
->mod
& NV50_MOD_NEG
)
1348 e
->inst
[1] |= 0x04000000;
1349 if (src
->mod
& NV50_MOD_ABS
)
1350 e
->inst
[1] |= 0x00100000;
1355 #define CVT_RN (0x00 << 16)
1356 #define CVT_FLOOR (0x02 << 16)
1357 #define CVT_CEIL (0x04 << 16)
1358 #define CVT_TRUNC (0x06 << 16)
1359 #define CVT_SAT (0x08 << 16)
1360 #define CVT_ABS (0x10 << 16)
1362 #define CVT_X32_X32 0x04004000
1363 #define CVT_X32_S32 0x04014000
1364 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1365 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1366 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1367 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1368 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1369 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1370 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1371 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1373 #define CVT_NEG 0x20000000
1374 #define CVT_RI 0x08000000
1377 emit_cvt(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
1378 int wp
, uint32_t cvn
)
1380 struct nv50_program_exec
*e
;
1384 if (src
->mod
& NV50_MOD_NEG
) cvn
|= CVT_NEG
;
1385 if (src
->mod
& NV50_MOD_ABS
) cvn
|= CVT_ABS
;
1387 e
->inst
[0] = 0xa0000000;
1390 set_src_0(pc
, src
, e
);
1393 set_pred_wr(pc
, 1, wp
, e
);
1396 set_dst(pc
, dst
, e
);
1398 e
->inst
[0] |= 0x000001fc;
1399 e
->inst
[1] |= 0x00000008;
1405 /* nv50 Condition codes:
1412 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1413 * 0x8 = unordered bit (allows NaN)
1415 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1418 emit_set(struct nv50_pc
*pc
, unsigned ccode
, struct nv50_reg
*dst
, int wp
,
1419 struct nv50_reg
*src0
, struct nv50_reg
*src1
, uint8_t mode
)
1421 static const unsigned cc_swapped
[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1423 struct nv50_program_exec
*e
= exec(pc
);
1424 struct nv50_reg
*rdst
;
1427 if (check_swap_src_0_1(pc
, &src0
, &src1
))
1428 ccode
= cc_swapped
[ccode
& 7] | (ccode
& 8);
1431 if (dst
&& dst
->type
!= P_TEMP
)
1432 dst
= alloc_temp(pc
, NULL
);
1435 e
->inst
[0] |= 0x30000000 | (mode
<< 24);
1436 e
->inst
[1] |= 0x60000000 | (ccode
<< 14);
1439 set_pred_wr(pc
, 1, wp
, e
);
1441 set_dst(pc
, dst
, e
);
1443 e
->inst
[0] |= 0x000001fc;
1444 e
->inst
[1] |= 0x00000008;
1447 set_src_0(pc
, src0
, e
);
1448 set_src_1(pc
, src1
, e
);
1452 if (rdst
&& mode
== 0x80) /* convert to float ? */
1453 emit_cvt(pc
, rdst
, dst
, -1, CVT_ABS
| CVT_F32_S32
);
1454 if (rdst
&& rdst
!= dst
)
1459 map_tgsi_setop_hw(unsigned op
, uint8_t *cc
, uint8_t *ty
)
1462 case TGSI_OPCODE_SLT
: *cc
= 0x1; *ty
= 0x80; break;
1463 case TGSI_OPCODE_SGE
: *cc
= 0x6; *ty
= 0x80; break;
1464 case TGSI_OPCODE_SEQ
: *cc
= 0x2; *ty
= 0x80; break;
1465 case TGSI_OPCODE_SGT
: *cc
= 0x4; *ty
= 0x80; break;
1466 case TGSI_OPCODE_SLE
: *cc
= 0x3; *ty
= 0x80; break;
1467 case TGSI_OPCODE_SNE
: *cc
= 0xd; *ty
= 0x80; break;
1469 case TGSI_OPCODE_ISLT
: *cc
= 0x1; *ty
= 0x0c; break;
1470 case TGSI_OPCODE_ISGE
: *cc
= 0x6; *ty
= 0x0c; break;
1471 case TGSI_OPCODE_USEQ
: *cc
= 0x2; *ty
= 0x04; break;
1472 case TGSI_OPCODE_USGE
: *cc
= 0x6; *ty
= 0x04; break;
1473 case TGSI_OPCODE_USLT
: *cc
= 0x1; *ty
= 0x04; break;
1474 case TGSI_OPCODE_USNE
: *cc
= 0x5; *ty
= 0x04; break;
1482 emit_add_b32(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1483 struct nv50_reg
*src0
, struct nv50_reg
*rsrc1
)
1485 struct nv50_program_exec
*e
= exec(pc
);
1486 struct nv50_reg
*src1
;
1488 e
->inst
[0] = 0x20000000;
1490 alloc_reg(pc
, rsrc1
);
1491 check_swap_src_0_1(pc
, &src0
, &rsrc1
);
1494 if (src0
->mod
& rsrc1
->mod
& NV50_MOD_NEG
) {
1495 src1
= temp_temp(pc
, e
);
1496 emit_cvt(pc
, src1
, rsrc1
, -1, CVT_S32_S32
);
1499 if (!pc
->allow32
|| src1
->hw
> 63 ||
1500 (src1
->type
!= P_TEMP
&& src1
->type
!= P_IMMD
))
1503 set_dst(pc
, dst
, e
);
1504 set_src_0(pc
, src0
, e
);
1507 e
->inst
[1] |= 1 << 26;
1508 set_src_2(pc
, src1
, e
);
1510 e
->inst
[0] |= 0x8000;
1511 if (src1
->type
== P_IMMD
)
1512 set_immd(pc
, src1
, e
);
1514 set_src_1(pc
, src1
, e
);
1517 if (src0
->mod
& NV50_MOD_NEG
)
1518 e
->inst
[0] |= 1 << 28;
1520 if (src1
->mod
& NV50_MOD_NEG
)
1521 e
->inst
[0] |= 1 << 22;
1527 emit_mad_u16(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1528 struct nv50_reg
*src0
, int lh_0
, struct nv50_reg
*src1
, int lh_1
,
1529 struct nv50_reg
*src2
)
1531 struct nv50_program_exec
*e
= exec(pc
);
1533 e
->inst
[0] = 0x60000000;
1536 set_dst(pc
, dst
, e
);
1538 set_half_src(pc
, src0
, lh_0
, e
, 9);
1539 set_half_src(pc
, src1
, lh_1
, e
, 16);
1540 alloc_reg(pc
, src2
);
1541 if (is_long(e
) || (src2
->type
!= P_TEMP
) || (src2
->hw
!= dst
->hw
))
1542 set_src_2(pc
, src2
, e
);
1548 emit_mul_u16(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1549 struct nv50_reg
*src0
, int lh_0
, struct nv50_reg
*src1
, int lh_1
)
1551 struct nv50_program_exec
*e
= exec(pc
);
1553 e
->inst
[0] = 0x40000000;
1555 set_dst(pc
, dst
, e
);
1557 set_half_src(pc
, src0
, lh_0
, e
, 9);
1558 set_half_src(pc
, src1
, lh_1
, e
, 16);
1564 emit_sad(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1565 struct nv50_reg
*src0
, struct nv50_reg
*src1
, struct nv50_reg
*src2
)
1567 struct nv50_program_exec
*e
= exec(pc
);
1569 e
->inst
[0] = 0x50000000;
1572 check_swap_src_0_1(pc
, &src0
, &src1
);
1573 set_dst(pc
, dst
, e
);
1574 set_src_0(pc
, src0
, e
);
1575 set_src_1(pc
, src1
, e
);
1576 alloc_reg(pc
, src2
);
1577 if (is_long(e
) || (src2
->type
!= dst
->type
) || (src2
->hw
!= dst
->hw
))
1578 set_src_2(pc
, src2
, e
);
1581 e
->inst
[1] |= 0x0c << 24;
1583 e
->inst
[0] |= 0x81 << 8;
1589 emit_flr(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1591 emit_cvt(pc
, dst
, src
, -1, CVT_FLOOR
| CVT_F32_F32
| CVT_RI
);
1595 emit_pow(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1596 struct nv50_reg
*v
, struct nv50_reg
*e
)
1598 struct nv50_reg
*temp
= alloc_temp(pc
, NULL
);
1600 emit_flop(pc
, NV50_FLOP_LG2
, temp
, v
);
1601 emit_mul(pc
, temp
, temp
, e
);
1602 emit_preex2(pc
, temp
, temp
);
1603 emit_flop(pc
, NV50_FLOP_EX2
, dst
, temp
);
1605 free_temp(pc
, temp
);
1609 emit_sat(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1611 emit_cvt(pc
, dst
, src
, -1, CVT_SAT
| CVT_F32_F32
);
1615 emit_lit(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1616 struct nv50_reg
**src
)
1618 struct nv50_reg
*one
= alloc_immd(pc
, 1.0);
1619 struct nv50_reg
*zero
= alloc_immd(pc
, 0.0);
1620 struct nv50_reg
*neg128
= alloc_immd(pc
, -127.999999);
1621 struct nv50_reg
*pos128
= alloc_immd(pc
, 127.999999);
1622 struct nv50_reg
*tmp
[4] = { 0 };
1623 boolean allow32
= pc
->allow32
;
1625 pc
->allow32
= FALSE
;
1627 if (mask
& (3 << 1)) {
1628 tmp
[0] = alloc_temp(pc
, NULL
);
1629 emit_minmax(pc
, NV50_MAX_F32
, tmp
[0], src
[0], zero
);
1632 if (mask
& (1 << 2)) {
1633 set_pred_wr(pc
, 1, 0, pc
->p
->exec_tail
);
1635 tmp
[1] = temp_temp(pc
, NULL
);
1636 emit_minmax(pc
, NV50_MAX_F32
, tmp
[1], src
[1], zero
);
1638 tmp
[3] = temp_temp(pc
, NULL
);
1639 emit_minmax(pc
, NV50_MAX_F32
, tmp
[3], src
[3], neg128
);
1640 emit_minmax(pc
, NV50_MIN_F32
, tmp
[3], tmp
[3], pos128
);
1642 emit_pow(pc
, dst
[2], tmp
[1], tmp
[3]);
1643 emit_mov(pc
, dst
[2], zero
);
1644 set_pred(pc
, 3, 0, pc
->p
->exec_tail
);
1647 if (mask
& (1 << 1))
1648 assimilate_temp(pc
, dst
[1], tmp
[0]);
1650 if (mask
& (1 << 2))
1651 free_temp(pc
, tmp
[0]);
1653 pc
->allow32
= allow32
;
1655 /* do this last, in case src[i,j] == dst[0,3] */
1656 if (mask
& (1 << 0))
1657 emit_mov(pc
, dst
[0], one
);
1659 if (mask
& (1 << 3))
1660 emit_mov(pc
, dst
[3], one
);
1669 emit_kil(struct nv50_pc
*pc
, struct nv50_reg
*src
)
1671 struct nv50_program_exec
*e
;
1672 const int r_pred
= 1;
1675 e
->inst
[0] = 0x00000002; /* discard */
1676 set_long(pc
, e
); /* sets cond code to ALWAYS */
1679 set_pred(pc
, 0x1 /* cc = LT */, r_pred
, e
);
1680 /* write to predicate reg */
1681 emit_cvt(pc
, NULL
, src
, r_pred
, CVT_F32_F32
);
1687 static struct nv50_program_exec
*
1688 emit_control_flow(struct nv50_pc
*pc
, unsigned op
, int pred
, unsigned cc
)
1690 struct nv50_program_exec
*e
= exec(pc
);
1692 e
->inst
[0] = (op
<< 28) | 2;
1695 set_pred(pc
, cc
, pred
, e
);
1701 static INLINE
struct nv50_program_exec
*
1702 emit_breakaddr(struct nv50_pc
*pc
)
1704 return emit_control_flow(pc
, 0x4, -1, 0);
1708 emit_break(struct nv50_pc
*pc
, int pred
, unsigned cc
)
1710 emit_control_flow(pc
, 0x5, pred
, cc
);
1713 static INLINE
struct nv50_program_exec
*
1714 emit_joinat(struct nv50_pc
*pc
)
1716 return emit_control_flow(pc
, 0xa, -1, 0);
1719 static INLINE
struct nv50_program_exec
*
1720 emit_branch(struct nv50_pc
*pc
, int pred
, unsigned cc
)
1722 return emit_control_flow(pc
, 0x1, pred
, cc
);
1725 static INLINE
struct nv50_program_exec
*
1726 emit_call(struct nv50_pc
*pc
, int pred
, unsigned cc
)
1728 return emit_control_flow(pc
, 0x2, pred
, cc
);
1732 emit_ret(struct nv50_pc
*pc
, int pred
, unsigned cc
)
1734 emit_control_flow(pc
, 0x3, pred
, cc
);
1738 emit_prim_cmd(struct nv50_pc
*pc
, unsigned cmd
)
1740 struct nv50_program_exec
*e
= exec(pc
);
1742 e
->inst
[0] = 0xf0000000 | (cmd
<< 9);
1743 e
->inst
[1] = 0xc0000000;
1752 #define QOP_MOV_SRC1 3
1754 /* For a quad of threads / top left, top right, bottom left, bottom right
1755 * pixels, do a different operation, and take src0 from a specific thread.
1758 emit_quadop(struct nv50_pc
*pc
, struct nv50_reg
*dst
, int wp
, int lane_src0
,
1759 struct nv50_reg
*src0
, struct nv50_reg
*src1
, ubyte qop
)
1761 struct nv50_program_exec
*e
= exec(pc
);
1763 e
->inst
[0] = 0xc0000000;
1764 e
->inst
[1] = 0x80000000;
1766 e
->inst
[0] |= lane_src0
<< 16;
1767 set_src_0(pc
, src0
, e
);
1768 set_src_2(pc
, src1
, e
);
1771 set_pred_wr(pc
, 1, wp
, e
);
1774 set_dst(pc
, dst
, e
);
1776 e
->inst
[0] |= 0x000001fc;
1777 e
->inst
[1] |= 0x00000008;
1780 e
->inst
[0] |= (qop
& 3) << 20;
1781 e
->inst
[1] |= (qop
>> 2) << 22;
1787 load_cube_tex_coords(struct nv50_pc
*pc
, struct nv50_reg
*t
[4],
1788 struct nv50_reg
**src
, unsigned arg
, boolean proj
)
1790 int mod
[3] = { src
[0]->mod
, src
[1]->mod
, src
[2]->mod
};
1792 src
[0]->mod
|= NV50_MOD_ABS
;
1793 src
[1]->mod
|= NV50_MOD_ABS
;
1794 src
[2]->mod
|= NV50_MOD_ABS
;
1796 emit_minmax(pc
, NV50_MAX_F32
, t
[2], src
[0], src
[1]);
1797 emit_minmax(pc
, NV50_MAX_F32
, t
[2], src
[2], t
[2]);
1799 src
[0]->mod
= mod
[0];
1800 src
[1]->mod
= mod
[1];
1801 src
[2]->mod
= mod
[2];
1803 if (proj
&& 0 /* looks more correct without this */)
1804 emit_mul(pc
, t
[2], t
[2], src
[3]);
1806 if (arg
== 4) /* there is no textureProj(samplerCubeShadow) */
1807 emit_mov(pc
, t
[3], src
[3]);
1809 emit_flop(pc
, NV50_FLOP_RCP
, t
[2], t
[2]);
1811 emit_mul(pc
, t
[0], src
[0], t
[2]);
1812 emit_mul(pc
, t
[1], src
[1], t
[2]);
1813 emit_mul(pc
, t
[2], src
[2], t
[2]);
1817 load_proj_tex_coords(struct nv50_pc
*pc
, struct nv50_reg
*t
[4],
1818 struct nv50_reg
**src
, unsigned dim
, unsigned arg
)
1822 if (src
[0]->type
== P_TEMP
&& src
[0]->rhw
!= -1) {
1823 mode
= pc
->interp_mode
[src
[0]->index
] | INTERP_PERSPECTIVE
;
1825 t
[3]->rhw
= src
[3]->rhw
;
1826 emit_interp(pc
, t
[3], NULL
, (mode
& INTERP_CENTROID
));
1827 emit_flop(pc
, NV50_FLOP_RCP
, t
[3], t
[3]);
1829 for (c
= 0; c
< dim
; ++c
) {
1830 t
[c
]->rhw
= src
[c
]->rhw
;
1831 emit_interp(pc
, t
[c
], t
[3], mode
);
1833 if (arg
!= dim
) { /* depth reference value */
1834 t
[dim
]->rhw
= src
[2]->rhw
;
1835 emit_interp(pc
, t
[dim
], t
[3], mode
);
1838 /* XXX: for some reason the blob sometimes uses MAD
1839 * (mad f32 $rX $rY $rZ neg $r63)
1841 emit_flop(pc
, NV50_FLOP_RCP
, t
[3], src
[3]);
1842 for (c
= 0; c
< dim
; ++c
)
1843 emit_mul(pc
, t
[c
], src
[c
], t
[3]);
1844 if (arg
!= dim
) /* depth reference value */
1845 emit_mul(pc
, t
[dim
], src
[2], t
[3]);
1850 get_tex_dim(unsigned type
, unsigned *dim
, unsigned *arg
)
1853 case TGSI_TEXTURE_1D
:
1856 case TGSI_TEXTURE_SHADOW1D
:
1860 case TGSI_TEXTURE_UNKNOWN
:
1861 case TGSI_TEXTURE_2D
:
1862 case TGSI_TEXTURE_RECT
:
1865 case TGSI_TEXTURE_SHADOW2D
:
1866 case TGSI_TEXTURE_SHADOWRECT
:
1870 case TGSI_TEXTURE_3D
:
1871 case TGSI_TEXTURE_CUBE
:
1880 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1881 * different LOD values, so branch off groups of equal LOD.
1884 emit_texlod_sequence(struct nv50_pc
*pc
, struct nv50_reg
*tlod
,
1885 struct nv50_reg
*src
, struct nv50_program_exec
*tex
)
1887 struct nv50_program_exec
*join_at
;
1888 unsigned i
, target
= pc
->p
->exec_size
+ 9 * 2;
1890 if (pc
->p
->type
!= PIPE_SHADER_FRAGMENT
) {
1894 pc
->allow32
= FALSE
;
1896 /* Subtract lod of each pixel from lod of top left pixel, jump
1897 * texlod insn if result is 0, then repeat for 2 other pixels.
1899 join_at
= emit_joinat(pc
);
1900 emit_quadop(pc
, NULL
, 0, 0, tlod
, tlod
, 0x55);
1901 emit_branch(pc
, 0, 2)->param
.index
= target
;
1903 for (i
= 1; i
< 4; ++i
) {
1904 emit_quadop(pc
, NULL
, 0, i
, tlod
, tlod
, 0x55);
1905 emit_branch(pc
, 0, 2)->param
.index
= target
;
1908 emit_mov(pc
, tlod
, src
); /* target */
1909 emit(pc
, tex
); /* texlod */
1911 join_at
->param
.index
= target
+ 2 * 2;
1912 JOIN_ON(emit_nop(pc
)); /* join _after_ tex */
1916 emit_texbias_sequence(struct nv50_pc
*pc
, struct nv50_reg
*t
[4], unsigned arg
,
1917 struct nv50_program_exec
*tex
)
1919 struct nv50_program_exec
*e
;
1920 struct nv50_reg imm_1248
, *t123
[4][4], *r_bits
= alloc_temp(pc
, NULL
);
1922 unsigned n
, c
, i
, cc
[4] = { 0x0a, 0x13, 0x11, 0x10 };
1924 pc
->allow32
= FALSE
;
1925 ctor_reg(&imm_1248
, P_IMMD
, -1, ctor_immd_4u32(pc
, 1, 2, 4, 8) * 4);
1927 /* Subtract bias value of thread i from bias values of each thread,
1928 * store result in r_pred, and set bit i in r_bits if result was 0.
1931 for (i
= 0; i
< 4; ++i
, ++imm_1248
.hw
) {
1932 emit_quadop(pc
, NULL
, r_pred
, i
, t
[arg
], t
[arg
], 0x55);
1933 emit_mov(pc
, r_bits
, &imm_1248
);
1934 set_pred(pc
, 2, r_pred
, pc
->p
->exec_tail
);
1936 emit_mov_to_pred(pc
, r_pred
, r_bits
);
1938 /* The lanes of a quad are now grouped by the bit in r_pred they have
1939 * set. Put the input values for TEX into a new register set for each
1940 * group and execute TEX only for a specific group.
1941 * We cannot use the same register set for each group because we need
1942 * the derivatives, which are implicitly calculated, to be correct.
1944 for (i
= 1; i
< 4; ++i
) {
1945 alloc_temp4(pc
, t123
[i
], 0);
1947 for (c
= 0; c
<= arg
; ++c
)
1948 emit_mov(pc
, t123
[i
][c
], t
[c
]);
1950 *(e
= exec(pc
)) = *(tex
);
1951 e
->inst
[0] &= ~0x01fc;
1952 set_dst(pc
, t123
[i
][0], e
);
1953 set_pred(pc
, cc
[i
], r_pred
, e
);
1956 /* finally TEX on the original regs (where we kept the input) */
1957 set_pred(pc
, cc
[0], r_pred
, tex
);
1960 /* put the 3 * n other results into regs for lane 0 */
1961 n
= popcnt4(((e
->inst
[0] >> 25) & 0x3) | ((e
->inst
[1] >> 12) & 0xc));
1962 for (i
= 1; i
< 4; ++i
) {
1963 for (c
= 0; c
< n
; ++c
) {
1964 emit_mov(pc
, t
[c
], t123
[i
][c
]);
1965 set_pred(pc
, cc
[i
], r_pred
, pc
->p
->exec_tail
);
1967 free_temp4(pc
, t123
[i
]);
1971 free_temp(pc
, r_bits
);
1975 emit_tex(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1976 struct nv50_reg
**src
, unsigned unit
, unsigned type
,
1977 boolean proj
, int bias_lod
)
1979 struct nv50_reg
*t
[4];
1980 struct nv50_program_exec
*e
;
1981 unsigned c
, dim
, arg
;
1983 /* t[i] must be within a single 128 bit super-reg */
1984 alloc_temp4(pc
, t
, 0);
1987 e
->inst
[0] = 0xf0000000;
1989 set_dst(pc
, t
[0], e
);
1991 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1992 e
->inst
[0] |= (unit
<< 9) /* | (unit << 17) */;
1994 /* live flag (don't set if TEX results affect input to another TEX): */
1995 /* e->inst[0] |= 0x00000004; */
1997 get_tex_dim(type
, &dim
, &arg
);
1999 if (type
== TGSI_TEXTURE_CUBE
) {
2000 e
->inst
[0] |= 0x08000000;
2001 load_cube_tex_coords(pc
, t
, src
, arg
, proj
);
2004 load_proj_tex_coords(pc
, t
, src
, dim
, arg
);
2006 for (c
= 0; c
< dim
; c
++)
2007 emit_mov(pc
, t
[c
], src
[c
]);
2008 if (arg
!= dim
) /* depth reference value (always src.z here) */
2009 emit_mov(pc
, t
[dim
], src
[2]);
2012 e
->inst
[0] |= (mask
& 0x3) << 25;
2013 e
->inst
[1] |= (mask
& 0xc) << 12;
2016 e
->inst
[0] |= (arg
- 1) << 22;
2020 assert(pc
->p
->type
== PIPE_SHADER_FRAGMENT
);
2021 e
->inst
[0] |= arg
<< 22;
2022 e
->inst
[1] |= 0x20000000; /* texbias */
2023 emit_mov(pc
, t
[arg
], src
[3]);
2024 emit_texbias_sequence(pc
, t
, arg
, e
);
2026 e
->inst
[0] |= arg
<< 22;
2027 e
->inst
[1] |= 0x40000000; /* texlod */
2028 emit_mov(pc
, t
[arg
], src
[3]);
2029 emit_texlod_sequence(pc
, t
[arg
], src
[3], e
);
2034 if (mask
& 1) emit_mov(pc
, dst
[0], t
[c
++]);
2035 if (mask
& 2) emit_mov(pc
, dst
[1], t
[c
++]);
2036 if (mask
& 4) emit_mov(pc
, dst
[2], t
[c
++]);
2037 if (mask
& 8) emit_mov(pc
, dst
[3], t
[c
]);
2041 /* XXX: if p.e. MUL is used directly after TEX, it would still use
2042 * the texture coordinates, not the fetched values: latency ? */
2044 for (c
= 0; c
< 4; c
++) {
2045 if (mask
& (1 << c
))
2046 assimilate_temp(pc
, dst
[c
], t
[c
]);
2048 free_temp(pc
, t
[c
]);
2054 emit_ddx(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
2056 struct nv50_program_exec
*e
= exec(pc
);
2058 assert(src
->type
== P_TEMP
);
2060 e
->inst
[0] = (src
->mod
& NV50_MOD_NEG
) ? 0xc0240000 : 0xc0140000;
2061 e
->inst
[1] = (src
->mod
& NV50_MOD_NEG
) ? 0x86400000 : 0x89800000;
2063 set_dst(pc
, dst
, e
);
2064 set_src_0(pc
, src
, e
);
2065 set_src_2(pc
, src
, e
);
2071 emit_ddy(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
2073 struct nv50_program_exec
*e
= exec(pc
);
2075 assert(src
->type
== P_TEMP
);
2077 e
->inst
[0] = (src
->mod
& NV50_MOD_NEG
) ? 0xc0250000 : 0xc0150000;
2078 e
->inst
[1] = (src
->mod
& NV50_MOD_NEG
) ? 0x85800000 : 0x8a400000;
2080 set_dst(pc
, dst
, e
);
2081 set_src_0(pc
, src
, e
);
2082 set_src_2(pc
, src
, e
);
2088 convert_to_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
2090 unsigned q
= 0, m
= ~0;
2092 assert(!is_long(e
));
2094 switch (e
->inst
[0] >> 28) {
2102 /* ADD, SUB, SUBR b32 */
2103 m
= ~(0x8000 | (127 << 16));
2104 q
= ((e
->inst
[0] & (~m
)) >> 2) | (1 << 26);
2109 q
= (0x0c << 24) | ((e
->inst
[0] & (0x7f << 2)) << 12);
2113 q
= (e
->inst
[0] & (0x7f << 2)) << 12;
2116 /* INTERP (move centroid, perspective and flat bits) */
2118 q
= (e
->inst
[0] & (3 << 24)) >> (24 - 16);
2119 q
|= (e
->inst
[0] & (1 << 8)) << (18 - 8);
2127 q
= ((e
->inst
[0] & (~m
)) >> 2);
2132 q
= ((e
->inst
[0] & (~m
)) << 12);
2135 /* MAD (if src2 == dst) */
2136 q
= ((e
->inst
[0] & 0x1fc) << 12);
2150 /* Some operations support an optional negation flag. */
2152 get_supported_mods(const struct tgsi_full_instruction
*insn
, int i
)
2154 switch (insn
->Instruction
.Opcode
) {
2155 case TGSI_OPCODE_ADD
:
2156 case TGSI_OPCODE_COS
:
2157 case TGSI_OPCODE_DDX
:
2158 case TGSI_OPCODE_DDY
:
2159 case TGSI_OPCODE_DP3
:
2160 case TGSI_OPCODE_DP4
:
2161 case TGSI_OPCODE_EX2
:
2162 case TGSI_OPCODE_KIL
:
2163 case TGSI_OPCODE_LG2
:
2164 case TGSI_OPCODE_MAD
:
2165 case TGSI_OPCODE_MUL
:
2166 case TGSI_OPCODE_POW
:
2167 case TGSI_OPCODE_RCP
:
2168 case TGSI_OPCODE_RSQ
: /* ignored, RSQ = rsqrt(abs(src.x)) */
2169 case TGSI_OPCODE_SCS
:
2170 case TGSI_OPCODE_SIN
:
2171 case TGSI_OPCODE_SUB
:
2172 return NV50_MOD_NEG
;
2173 case TGSI_OPCODE_MAX
:
2174 case TGSI_OPCODE_MIN
:
2175 case TGSI_OPCODE_INEG
: /* tgsi src sign toggle/set would be stupid */
2176 return NV50_MOD_ABS
;
2177 case TGSI_OPCODE_CEIL
:
2178 case TGSI_OPCODE_FLR
:
2179 case TGSI_OPCODE_TRUNC
:
2180 return NV50_MOD_NEG
| NV50_MOD_ABS
;
2181 case TGSI_OPCODE_F2I
:
2182 case TGSI_OPCODE_F2U
:
2183 case TGSI_OPCODE_I2F
:
2184 case TGSI_OPCODE_U2F
:
2185 return NV50_MOD_NEG
| NV50_MOD_ABS
| NV50_MOD_I32
;
2186 case TGSI_OPCODE_UADD
:
2187 return NV50_MOD_NEG
| NV50_MOD_I32
;
2188 case TGSI_OPCODE_SAD
:
2189 case TGSI_OPCODE_SHL
:
2190 case TGSI_OPCODE_IMAX
:
2191 case TGSI_OPCODE_IMIN
:
2192 case TGSI_OPCODE_ISHR
:
2193 case TGSI_OPCODE_NOT
:
2194 case TGSI_OPCODE_UMAD
:
2195 case TGSI_OPCODE_UMAX
:
2196 case TGSI_OPCODE_UMIN
:
2197 case TGSI_OPCODE_UMUL
:
2198 case TGSI_OPCODE_USHR
:
2199 return NV50_MOD_I32
;
2205 /* Return a read mask for source registers deduced from opcode & write mask. */
2207 nv50_tgsi_src_mask(const struct tgsi_full_instruction
*insn
, int c
)
2209 unsigned x
, mask
= insn
->Dst
[0].Register
.WriteMask
;
2211 switch (insn
->Instruction
.Opcode
) {
2212 case TGSI_OPCODE_COS
:
2213 case TGSI_OPCODE_SIN
:
2214 return (mask
& 0x8) | ((mask
& 0x7) ? 0x1 : 0x0);
2215 case TGSI_OPCODE_DP3
:
2217 case TGSI_OPCODE_DP4
:
2218 case TGSI_OPCODE_DPH
:
2219 case TGSI_OPCODE_KIL
: /* WriteMask ignored */
2221 case TGSI_OPCODE_DST
:
2222 return mask
& (c
? 0xa : 0x6);
2223 case TGSI_OPCODE_EX2
:
2224 case TGSI_OPCODE_EXP
:
2225 case TGSI_OPCODE_LG2
:
2226 case TGSI_OPCODE_LOG
:
2227 case TGSI_OPCODE_POW
:
2228 case TGSI_OPCODE_RCP
:
2229 case TGSI_OPCODE_RSQ
:
2230 case TGSI_OPCODE_SCS
:
2232 case TGSI_OPCODE_IF
:
2234 case TGSI_OPCODE_LIT
:
2236 case TGSI_OPCODE_TEX
:
2237 case TGSI_OPCODE_TXB
:
2238 case TGSI_OPCODE_TXL
:
2239 case TGSI_OPCODE_TXP
:
2241 const struct tgsi_instruction_texture
*tex
;
2243 assert(insn
->Instruction
.Texture
);
2244 tex
= &insn
->Texture
;
2247 if (insn
->Instruction
.Opcode
!= TGSI_OPCODE_TEX
&&
2248 insn
->Instruction
.Opcode
!= TGSI_OPCODE_TXD
)
2249 mask
|= 0x8; /* bias, lod or proj */
2251 switch (tex
->Texture
) {
2252 case TGSI_TEXTURE_1D
:
2255 case TGSI_TEXTURE_SHADOW1D
:
2258 case TGSI_TEXTURE_2D
:
2266 case TGSI_OPCODE_XPD
:
2268 if (mask
& 1) x
|= 0x6;
2269 if (mask
& 2) x
|= 0x5;
2270 if (mask
& 4) x
|= 0x3;
2279 static struct nv50_reg
*
2280 tgsi_dst(struct nv50_pc
*pc
, int c
, const struct tgsi_full_dst_register
*dst
)
2282 switch (dst
->Register
.File
) {
2283 case TGSI_FILE_TEMPORARY
:
2284 return &pc
->temp
[dst
->Register
.Index
* 4 + c
];
2285 case TGSI_FILE_OUTPUT
:
2286 return &pc
->result
[dst
->Register
.Index
* 4 + c
];
2287 case TGSI_FILE_ADDRESS
:
2289 struct nv50_reg
*r
= pc
->addr
[dst
->Register
.Index
* 4 + c
];
2291 r
= get_address_reg(pc
, NULL
);
2292 r
->index
= dst
->Register
.Index
* 4 + c
;
2293 pc
->addr
[r
->index
] = r
;
2298 case TGSI_FILE_NULL
:
2300 case TGSI_FILE_SYSTEM_VALUE
:
2301 assert(pc
->sysval
[dst
->Register
.Index
].type
== P_RESULT
);
2303 return &pc
->sysval
[dst
->Register
.Index
];
2311 static struct nv50_reg
*
2312 tgsi_src(struct nv50_pc
*pc
, int chan
, const struct tgsi_full_src_register
*src
,
2315 struct nv50_reg
*r
= NULL
;
2316 struct nv50_reg
*temp
= NULL
;
2317 unsigned sgn
, c
, swz
, cvn
;
2319 if (src
->Register
.File
!= TGSI_FILE_CONSTANT
)
2320 assert(!src
->Register
.Indirect
);
2322 sgn
= tgsi_util_get_full_src_register_sign_mode(src
, chan
);
2324 c
= tgsi_util_get_full_src_register_swizzle(src
, chan
);
2326 case TGSI_SWIZZLE_X
:
2327 case TGSI_SWIZZLE_Y
:
2328 case TGSI_SWIZZLE_Z
:
2329 case TGSI_SWIZZLE_W
:
2330 switch (src
->Register
.File
) {
2331 case TGSI_FILE_INPUT
:
2332 r
= &pc
->attr
[src
->Register
.Index
* 4 + c
];
2334 if (!src
->Dimension
.Dimension
)
2336 r
= reg_instance(pc
, r
);
2337 r
->vtx
= src
->Dimension
.Index
;
2339 if (!src
->Dimension
.Indirect
)
2341 swz
= tgsi_util_get_src_register_swizzle(
2342 &src
->DimIndirect
, 0);
2344 r
->indirect
[1] = src
->DimIndirect
.Index
* 4 + swz
;
2346 case TGSI_FILE_TEMPORARY
:
2347 r
= &pc
->temp
[src
->Register
.Index
* 4 + c
];
2349 case TGSI_FILE_CONSTANT
:
2350 if (!src
->Register
.Indirect
) {
2351 r
= &pc
->param
[src
->Register
.Index
* 4 + c
];
2354 /* Indicate indirection by setting r->acc < 0 and
2355 * use the index field to select the address reg.
2357 r
= reg_instance(pc
, NULL
);
2358 ctor_reg(r
, P_CONST
, -1, src
->Register
.Index
* 4 + c
);
2360 swz
= tgsi_util_get_src_register_swizzle(
2363 r
->indirect
[0] = src
->Indirect
.Index
* 4 + swz
;
2365 case TGSI_FILE_IMMEDIATE
:
2366 r
= &pc
->immd
[src
->Register
.Index
* 4 + c
];
2368 case TGSI_FILE_SAMPLER
:
2370 case TGSI_FILE_ADDRESS
:
2371 r
= pc
->addr
[src
->Register
.Index
* 4 + c
];
2374 case TGSI_FILE_SYSTEM_VALUE
:
2376 r
= &pc
->sysval
[src
->Register
.Index
];
2388 cvn
= (mod
& NV50_MOD_I32
) ? CVT_S32_S32
: CVT_F32_F32
;
2391 case TGSI_UTIL_SIGN_CLEAR
:
2392 r
->mod
= NV50_MOD_ABS
;
2394 case TGSI_UTIL_SIGN_SET
:
2395 r
->mod
= NV50_MOD_NEG_ABS
;
2397 case TGSI_UTIL_SIGN_TOGGLE
:
2398 r
->mod
= NV50_MOD_NEG
;
2401 assert(!r
->mod
&& sgn
== TGSI_UTIL_SIGN_KEEP
);
2405 if ((r
->mod
& mod
) != r
->mod
) {
2406 temp
= temp_temp(pc
, NULL
);
2407 emit_cvt(pc
, temp
, r
, -1, cvn
);
2411 r
->mod
|= mod
& NV50_MOD_I32
;
2414 if (r
->acc
>= 0 && r
->vtx
< 0 && r
!= temp
)
2415 return reg_instance(pc
, r
); /* will clear r->mod */
2419 /* return TRUE for ops that produce only a single result */
2421 is_scalar_op(unsigned op
)
2424 case TGSI_OPCODE_COS
:
2425 case TGSI_OPCODE_DP2
:
2426 case TGSI_OPCODE_DP3
:
2427 case TGSI_OPCODE_DP4
:
2428 case TGSI_OPCODE_DPH
:
2429 case TGSI_OPCODE_EX2
:
2430 case TGSI_OPCODE_LG2
:
2431 case TGSI_OPCODE_POW
:
2432 case TGSI_OPCODE_RCP
:
2433 case TGSI_OPCODE_RSQ
:
2434 case TGSI_OPCODE_SIN
:
2436 case TGSI_OPCODE_KIL:
2437 case TGSI_OPCODE_LIT:
2438 case TGSI_OPCODE_SCS:
2446 /* Returns a bitmask indicating which dst components depend
2447 * on source s, component c (reverse of nv50_tgsi_src_mask).
2450 nv50_tgsi_dst_revdep(unsigned op
, int s
, int c
)
2452 if (is_scalar_op(op
))
2456 case TGSI_OPCODE_DST
:
2457 return (1 << c
) & (s
? 0xa : 0x6);
2458 case TGSI_OPCODE_XPD
:
2468 case TGSI_OPCODE_EXP
:
2469 case TGSI_OPCODE_LOG
:
2470 case TGSI_OPCODE_LIT
:
2471 case TGSI_OPCODE_SCS
:
2472 case TGSI_OPCODE_TEX
:
2473 case TGSI_OPCODE_TXB
:
2474 case TGSI_OPCODE_TXL
:
2475 case TGSI_OPCODE_TXP
:
2476 /* these take care of dangerous swizzles themselves */
2478 case TGSI_OPCODE_IF
:
2479 case TGSI_OPCODE_KIL
:
2480 /* don't call this function for these ops */
2484 /* linear vector instruction */
2489 static INLINE boolean
2490 has_pred(struct nv50_program_exec
*e
, unsigned cc
)
2492 if (!is_long(e
) || is_immd(e
))
2494 return ((e
->inst
[1] & 0x780) == (cc
<< 7));
2497 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2504 nv50_kill_branch(struct nv50_pc
*pc
)
2506 int lvl
= pc
->if_lvl
;
2508 if (pc
->if_insn
[lvl
]->next
!= pc
->p
->exec_tail
)
2510 if (is_immd(pc
->p
->exec_tail
))
2513 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2514 * reg may no longer be valid, since we currently always use $p0
2516 if (has_pred(pc
->if_insn
[lvl
], 0xf))
2518 assert(pc
->if_insn
[lvl
] && pc
->if_join
[lvl
]);
2520 /* We'll use the exec allocated for JOIN_AT (we can't easily
2521 * access nv50_program_exec's prev).
2523 pc
->p
->exec_size
-= 4; /* remove JOIN_AT and BRA */
2525 *pc
->if_join
[lvl
] = *pc
->p
->exec_tail
;
2527 FREE(pc
->if_insn
[lvl
]);
2528 FREE(pc
->p
->exec_tail
);
2530 pc
->p
->exec_tail
= pc
->if_join
[lvl
];
2531 pc
->p
->exec_tail
->next
= NULL
;
2532 set_pred(pc
, 0xd, 0, pc
->p
->exec_tail
);
2538 nv50_fp_move_results(struct nv50_pc
*pc
)
2540 struct nv50_reg reg
;
2543 ctor_reg(®
, P_TEMP
, -1, -1);
2545 for (i
= 0; i
< pc
->result_nr
* 4; ++i
) {
2546 if (pc
->result
[i
].rhw
< 0 || pc
->result
[i
].hw
< 0)
2548 if (pc
->result
[i
].rhw
!= pc
->result
[i
].hw
) {
2549 reg
.hw
= pc
->result
[i
].rhw
;
2550 emit_mov(pc
, ®
, &pc
->result
[i
]);
2556 nv50_program_tx_insn(struct nv50_pc
*pc
,
2557 const struct tgsi_full_instruction
*inst
)
2559 struct nv50_reg
*rdst
[4], *dst
[4], *brdc
, *src
[3][4], *temp
;
2560 unsigned mask
, sat
, unit
= 0;
2563 mask
= inst
->Dst
[0].Register
.WriteMask
;
2564 sat
= inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
;
2566 memset(src
, 0, sizeof(src
));
2568 for (c
= 0; c
< 4; c
++) {
2569 if ((mask
& (1 << c
)) && !pc
->r_dst
[c
])
2570 dst
[c
] = tgsi_dst(pc
, c
, &inst
->Dst
[0]);
2572 dst
[c
] = pc
->r_dst
[c
];
2576 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2577 const struct tgsi_full_src_register
*fs
= &inst
->Src
[i
];
2581 src_mask
= nv50_tgsi_src_mask(inst
, i
);
2582 mod_supp
= get_supported_mods(inst
, i
);
2584 if (fs
->Register
.File
== TGSI_FILE_SAMPLER
)
2585 unit
= fs
->Register
.Index
;
2587 for (c
= 0; c
< 4; c
++)
2588 if (src_mask
& (1 << c
))
2589 src
[i
][c
] = tgsi_src(pc
, c
, fs
, mod_supp
);
2592 brdc
= temp
= pc
->r_brdc
;
2593 if (brdc
&& brdc
->type
!= P_TEMP
) {
2594 temp
= temp_temp(pc
, NULL
);
2599 for (c
= 0; c
< 4; c
++) {
2600 if (!(mask
& (1 << c
)) || dst
[c
]->type
== P_TEMP
)
2602 /* rdst[c] = dst[c]; */ /* done above */
2603 dst
[c
] = temp_temp(pc
, NULL
);
2607 assert(brdc
|| !is_scalar_op(inst
->Instruction
.Opcode
));
2609 switch (inst
->Instruction
.Opcode
) {
2610 case TGSI_OPCODE_ABS
:
2611 for (c
= 0; c
< 4; c
++) {
2612 if (!(mask
& (1 << c
)))
2614 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2615 CVT_ABS
| CVT_F32_F32
);
2618 case TGSI_OPCODE_ADD
:
2619 for (c
= 0; c
< 4; c
++) {
2620 if (!(mask
& (1 << c
)))
2622 emit_add(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2625 case TGSI_OPCODE_AND
:
2626 case TGSI_OPCODE_XOR
:
2627 case TGSI_OPCODE_OR
:
2628 for (c
= 0; c
< 4; c
++) {
2629 if (!(mask
& (1 << c
)))
2631 emit_bitop2(pc
, dst
[c
], src
[0][c
], src
[1][c
],
2632 inst
->Instruction
.Opcode
);
2635 case TGSI_OPCODE_ARL
:
2636 temp
= temp_temp(pc
, NULL
);
2637 for (c
= 0; c
< 4; c
++) {
2638 if (!(mask
& (1 << c
)))
2640 emit_cvt(pc
, temp
, src
[0][c
], -1,
2641 CVT_FLOOR
| CVT_S32_F32
);
2642 emit_arl(pc
, dst
[c
], temp
, 4);
2645 case TGSI_OPCODE_BGNLOOP
:
2646 pc
->loop_brka
[pc
->loop_lvl
] = emit_breakaddr(pc
);
2647 pc
->loop_pos
[pc
->loop_lvl
++] = pc
->p
->exec_size
;
2650 case TGSI_OPCODE_BGNSUB
:
2651 assert(!pc
->in_subroutine
);
2652 pc
->in_subroutine
= TRUE
;
2653 /* probably not necessary, but align to 8 byte boundary */
2654 if (!is_long(pc
->p
->exec_tail
))
2655 convert_to_long(pc
, pc
->p
->exec_tail
);
2657 case TGSI_OPCODE_BRK
:
2658 assert(pc
->loop_lvl
> 0);
2659 emit_break(pc
, -1, 0);
2661 case TGSI_OPCODE_CAL
:
2662 assert(inst
->Label
.Label
< pc
->insn_nr
);
2663 emit_call(pc
, -1, 0)->param
.index
= inst
->Label
.Label
;
2664 /* replaced by actual offset in nv50_program_fixup_insns */
2666 case TGSI_OPCODE_CEIL
:
2667 for (c
= 0; c
< 4; c
++) {
2668 if (!(mask
& (1 << c
)))
2670 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2671 CVT_CEIL
| CVT_F32_F32
| CVT_RI
);
2674 case TGSI_OPCODE_CMP
:
2675 pc
->allow32
= FALSE
;
2676 for (c
= 0; c
< 4; c
++) {
2677 if (!(mask
& (1 << c
)))
2679 emit_cvt(pc
, NULL
, src
[0][c
], 1, CVT_F32_F32
);
2680 emit_mov(pc
, dst
[c
], src
[1][c
]);
2681 set_pred(pc
, 0x1, 1, pc
->p
->exec_tail
); /* @SF */
2682 emit_mov(pc
, dst
[c
], src
[2][c
]);
2683 set_pred(pc
, 0x6, 1, pc
->p
->exec_tail
); /* @NSF */
2686 case TGSI_OPCODE_CONT
:
2687 assert(pc
->loop_lvl
> 0);
2688 emit_branch(pc
, -1, 0)->param
.index
=
2689 pc
->loop_pos
[pc
->loop_lvl
- 1];
2691 case TGSI_OPCODE_COS
:
2693 emit_precossin(pc
, temp
, src
[0][3]);
2694 emit_flop(pc
, NV50_FLOP_COS
, dst
[3], temp
);
2698 temp
= brdc
= temp_temp(pc
, NULL
);
2700 emit_precossin(pc
, temp
, src
[0][0]);
2701 emit_flop(pc
, NV50_FLOP_COS
, brdc
, temp
);
2703 case TGSI_OPCODE_DDX
:
2704 for (c
= 0; c
< 4; c
++) {
2705 if (!(mask
& (1 << c
)))
2707 emit_ddx(pc
, dst
[c
], src
[0][c
]);
2710 case TGSI_OPCODE_DDY
:
2711 for (c
= 0; c
< 4; c
++) {
2712 if (!(mask
& (1 << c
)))
2714 emit_ddy(pc
, dst
[c
], src
[0][c
]);
2717 case TGSI_OPCODE_DP3
:
2718 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
2719 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
2720 emit_mad(pc
, brdc
, src
[0][2], src
[1][2], temp
);
2722 case TGSI_OPCODE_DP4
:
2723 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
2724 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
2725 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
2726 emit_mad(pc
, brdc
, src
[0][3], src
[1][3], temp
);
2728 case TGSI_OPCODE_DPH
:
2729 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
2730 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
2731 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
2732 emit_add(pc
, brdc
, src
[1][3], temp
);
2734 case TGSI_OPCODE_DST
:
2735 if (mask
& (1 << 1))
2736 emit_mul(pc
, dst
[1], src
[0][1], src
[1][1]);
2737 if (mask
& (1 << 2))
2738 emit_mov(pc
, dst
[2], src
[0][2]);
2739 if (mask
& (1 << 3))
2740 emit_mov(pc
, dst
[3], src
[1][3]);
2741 if (mask
& (1 << 0))
2742 emit_mov_immdval(pc
, dst
[0], 1.0f
);
2744 case TGSI_OPCODE_ELSE
:
2745 emit_branch(pc
, -1, 0);
2746 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
2747 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
2750 case TGSI_OPCODE_EMIT
:
2751 emit_prim_cmd(pc
, 1);
2753 case TGSI_OPCODE_ENDIF
:
2754 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
2756 /* try to replace branch over 1 insn with a predicated insn */
2757 if (nv50_kill_branch(pc
) == TRUE
)
2760 if (pc
->if_join
[pc
->if_lvl
]) {
2761 pc
->if_join
[pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
2762 pc
->if_join
[pc
->if_lvl
] = NULL
;
2765 /* emit a NOP as join point, we could set it on the next
2766 * one, but would have to make sure it is long and !immd
2768 JOIN_ON(emit_nop(pc
));
2770 case TGSI_OPCODE_ENDLOOP
:
2771 emit_branch(pc
, -1, 0)->param
.index
=
2772 pc
->loop_pos
[--pc
->loop_lvl
];
2773 pc
->loop_brka
[pc
->loop_lvl
]->param
.index
= pc
->p
->exec_size
;
2776 case TGSI_OPCODE_ENDPRIM
:
2777 emit_prim_cmd(pc
, 2);
2779 case TGSI_OPCODE_ENDSUB
:
2780 assert(pc
->in_subroutine
);
2782 pc
->in_subroutine
= FALSE
;
2784 case TGSI_OPCODE_EX2
:
2785 emit_preex2(pc
, temp
, src
[0][0]);
2786 emit_flop(pc
, NV50_FLOP_EX2
, brdc
, temp
);
2788 case TGSI_OPCODE_EXP
:
2790 struct nv50_reg
*t
[2];
2793 t
[0] = temp_temp(pc
, NULL
);
2794 t
[1] = temp_temp(pc
, NULL
);
2797 emit_mov(pc
, t
[0], src
[0][0]);
2799 emit_flr(pc
, t
[1], src
[0][0]);
2801 if (mask
& (1 << 1))
2802 emit_sub(pc
, dst
[1], t
[0], t
[1]);
2803 if (mask
& (1 << 0)) {
2804 emit_preex2(pc
, t
[1], t
[1]);
2805 emit_flop(pc
, NV50_FLOP_EX2
, dst
[0], t
[1]);
2807 if (mask
& (1 << 2)) {
2808 emit_preex2(pc
, t
[0], t
[0]);
2809 emit_flop(pc
, NV50_FLOP_EX2
, dst
[2], t
[0]);
2811 if (mask
& (1 << 3))
2812 emit_mov_immdval(pc
, dst
[3], 1.0f
);
2815 case TGSI_OPCODE_F2I
:
2816 for (c
= 0; c
< 4; c
++) {
2817 if (!(mask
& (1 << c
)))
2819 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2820 CVT_TRUNC
| CVT_S32_F32
);
2823 case TGSI_OPCODE_F2U
:
2824 for (c
= 0; c
< 4; c
++) {
2825 if (!(mask
& (1 << c
)))
2827 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2828 CVT_TRUNC
| CVT_U32_F32
);
2831 case TGSI_OPCODE_FLR
:
2832 for (c
= 0; c
< 4; c
++) {
2833 if (!(mask
& (1 << c
)))
2835 emit_flr(pc
, dst
[c
], src
[0][c
]);
2838 case TGSI_OPCODE_FRC
:
2839 temp
= temp_temp(pc
, NULL
);
2840 for (c
= 0; c
< 4; c
++) {
2841 if (!(mask
& (1 << c
)))
2843 emit_flr(pc
, temp
, src
[0][c
]);
2844 emit_sub(pc
, dst
[c
], src
[0][c
], temp
);
2847 case TGSI_OPCODE_I2F
:
2848 for (c
= 0; c
< 4; c
++) {
2849 if (!(mask
& (1 << c
)))
2851 emit_cvt(pc
, dst
[c
], src
[0][c
], -1, CVT_F32_S32
);
2854 case TGSI_OPCODE_IF
:
2855 assert(pc
->if_lvl
< NV50_MAX_COND_NESTING
);
2856 emit_cvt(pc
, NULL
, src
[0][0], 0, CVT_ABS
| CVT_F32_F32
);
2857 pc
->if_join
[pc
->if_lvl
] = emit_joinat(pc
);
2858 pc
->if_insn
[pc
->if_lvl
++] = emit_branch(pc
, 0, 2);;
2861 case TGSI_OPCODE_IMAX
:
2862 for (c
= 0; c
< 4; c
++) {
2863 if (!(mask
& (1 << c
)))
2865 emit_minmax(pc
, 0x08c, dst
[c
], src
[0][c
], src
[1][c
]);
2868 case TGSI_OPCODE_IMIN
:
2869 for (c
= 0; c
< 4; c
++) {
2870 if (!(mask
& (1 << c
)))
2872 emit_minmax(pc
, 0x0ac, dst
[c
], src
[0][c
], src
[1][c
]);
2875 case TGSI_OPCODE_INEG
:
2876 for (c
= 0; c
< 4; c
++) {
2877 if (!(mask
& (1 << c
)))
2879 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2880 CVT_S32_S32
| CVT_NEG
);
2883 case TGSI_OPCODE_KIL
:
2884 assert(src
[0][0] && src
[0][1] && src
[0][2] && src
[0][3]);
2885 emit_kil(pc
, src
[0][0]);
2886 emit_kil(pc
, src
[0][1]);
2887 emit_kil(pc
, src
[0][2]);
2888 emit_kil(pc
, src
[0][3]);
2890 case TGSI_OPCODE_KILP
:
2893 case TGSI_OPCODE_LIT
:
2894 emit_lit(pc
, &dst
[0], mask
, &src
[0][0]);
2896 case TGSI_OPCODE_LG2
:
2897 emit_flop(pc
, NV50_FLOP_LG2
, brdc
, src
[0][0]);
2899 case TGSI_OPCODE_LOG
:
2901 struct nv50_reg
*t
[2];
2903 t
[0] = temp_temp(pc
, NULL
);
2904 if (mask
& (1 << 1))
2905 t
[1] = temp_temp(pc
, NULL
);
2909 emit_cvt(pc
, t
[0], src
[0][0], -1, CVT_ABS
| CVT_F32_F32
);
2910 emit_flop(pc
, NV50_FLOP_LG2
, t
[1], t
[0]);
2911 if (mask
& (1 << 2))
2912 emit_mov(pc
, dst
[2], t
[1]);
2913 emit_flr(pc
, t
[1], t
[1]);
2914 if (mask
& (1 << 0))
2915 emit_mov(pc
, dst
[0], t
[1]);
2916 if (mask
& (1 << 1)) {
2917 t
[1]->mod
= NV50_MOD_NEG
;
2918 emit_preex2(pc
, t
[1], t
[1]);
2920 emit_flop(pc
, NV50_FLOP_EX2
, t
[1], t
[1]);
2921 emit_mul(pc
, dst
[1], t
[0], t
[1]);
2923 if (mask
& (1 << 3))
2924 emit_mov_immdval(pc
, dst
[3], 1.0f
);
2927 case TGSI_OPCODE_LRP
:
2928 temp
= temp_temp(pc
, NULL
);
2929 for (c
= 0; c
< 4; c
++) {
2930 if (!(mask
& (1 << c
)))
2932 emit_sub(pc
, temp
, src
[1][c
], src
[2][c
]);
2933 emit_mad(pc
, dst
[c
], temp
, src
[0][c
], src
[2][c
]);
2936 case TGSI_OPCODE_MAD
:
2937 for (c
= 0; c
< 4; c
++) {
2938 if (!(mask
& (1 << c
)))
2940 emit_mad(pc
, dst
[c
], src
[0][c
], src
[1][c
], src
[2][c
]);
2943 case TGSI_OPCODE_MAX
:
2944 for (c
= 0; c
< 4; c
++) {
2945 if (!(mask
& (1 << c
)))
2947 emit_minmax(pc
, 0x880, dst
[c
], src
[0][c
], src
[1][c
]);
2950 case TGSI_OPCODE_MIN
:
2951 for (c
= 0; c
< 4; c
++) {
2952 if (!(mask
& (1 << c
)))
2954 emit_minmax(pc
, 0x8a0, dst
[c
], src
[0][c
], src
[1][c
]);
2957 case TGSI_OPCODE_MOV
:
2958 for (c
= 0; c
< 4; c
++) {
2959 if (!(mask
& (1 << c
)))
2961 emit_mov(pc
, dst
[c
], src
[0][c
]);
2964 case TGSI_OPCODE_MUL
:
2965 for (c
= 0; c
< 4; c
++) {
2966 if (!(mask
& (1 << c
)))
2968 emit_mul(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2971 case TGSI_OPCODE_NOT
:
2972 for (c
= 0; c
< 4; c
++) {
2973 if (!(mask
& (1 << c
)))
2975 emit_not(pc
, dst
[c
], src
[0][c
]);
2978 case TGSI_OPCODE_POW
:
2979 emit_pow(pc
, brdc
, src
[0][0], src
[1][0]);
2981 case TGSI_OPCODE_RCP
:
2982 if (!sat
&& popcnt4(mask
) == 1)
2983 brdc
= dst
[ffs(mask
) - 1];
2984 emit_flop(pc
, NV50_FLOP_RCP
, brdc
, src
[0][0]);
2986 case TGSI_OPCODE_RET
:
2987 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
&& !pc
->in_subroutine
)
2988 nv50_fp_move_results(pc
);
2989 emit_ret(pc
, -1, 0);
2991 case TGSI_OPCODE_RSQ
:
2992 if (!sat
&& popcnt4(mask
) == 1)
2993 brdc
= dst
[ffs(mask
) - 1];
2994 src
[0][0]->mod
|= NV50_MOD_ABS
;
2995 emit_flop(pc
, NV50_FLOP_RSQ
, brdc
, src
[0][0]);
2997 case TGSI_OPCODE_SAD
:
2998 for (c
= 0; c
< 4; c
++) {
2999 if (!(mask
& (1 << c
)))
3001 emit_sad(pc
, dst
[c
], src
[0][c
], src
[1][c
], src
[2][c
]);
3004 case TGSI_OPCODE_SCS
:
3005 temp
= temp_temp(pc
, NULL
);
3007 emit_precossin(pc
, temp
, src
[0][0]);
3008 if (mask
& (1 << 0))
3009 emit_flop(pc
, NV50_FLOP_COS
, dst
[0], temp
);
3010 if (mask
& (1 << 1))
3011 emit_flop(pc
, NV50_FLOP_SIN
, dst
[1], temp
);
3012 if (mask
& (1 << 2))
3013 emit_mov_immdval(pc
, dst
[2], 0.0);
3014 if (mask
& (1 << 3))
3015 emit_mov_immdval(pc
, dst
[3], 1.0);
3017 case TGSI_OPCODE_SHL
:
3018 case TGSI_OPCODE_ISHR
:
3019 case TGSI_OPCODE_USHR
:
3020 for (c
= 0; c
< 4; c
++) {
3021 if (!(mask
& (1 << c
)))
3023 emit_shift(pc
, dst
[c
], src
[0][c
], src
[1][c
],
3024 inst
->Instruction
.Opcode
);
3027 case TGSI_OPCODE_SIN
:
3029 emit_precossin(pc
, temp
, src
[0][3]);
3030 emit_flop(pc
, NV50_FLOP_SIN
, dst
[3], temp
);
3034 temp
= brdc
= temp_temp(pc
, NULL
);
3036 emit_precossin(pc
, temp
, src
[0][0]);
3037 emit_flop(pc
, NV50_FLOP_SIN
, brdc
, temp
);
3039 case TGSI_OPCODE_SLT
:
3040 case TGSI_OPCODE_SGE
:
3041 case TGSI_OPCODE_SEQ
:
3042 case TGSI_OPCODE_SGT
:
3043 case TGSI_OPCODE_SLE
:
3044 case TGSI_OPCODE_SNE
:
3045 case TGSI_OPCODE_ISLT
:
3046 case TGSI_OPCODE_ISGE
:
3047 case TGSI_OPCODE_USEQ
:
3048 case TGSI_OPCODE_USGE
:
3049 case TGSI_OPCODE_USLT
:
3050 case TGSI_OPCODE_USNE
:
3054 map_tgsi_setop_hw(inst
->Instruction
.Opcode
, &cc
, &ty
);
3056 for (c
= 0; c
< 4; c
++) {
3057 if (!(mask
& (1 << c
)))
3059 emit_set(pc
, cc
, dst
[c
], -1, src
[0][c
], src
[1][c
], ty
);
3063 case TGSI_OPCODE_SUB
:
3064 for (c
= 0; c
< 4; c
++) {
3065 if (!(mask
& (1 << c
)))
3067 emit_sub(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
3070 case TGSI_OPCODE_TEX
:
3071 emit_tex(pc
, dst
, mask
, src
[0], unit
,
3072 inst
->Texture
.Texture
, FALSE
, 0);
3074 case TGSI_OPCODE_TXB
:
3075 emit_tex(pc
, dst
, mask
, src
[0], unit
,
3076 inst
->Texture
.Texture
, FALSE
, -1);
3078 case TGSI_OPCODE_TXL
:
3079 emit_tex(pc
, dst
, mask
, src
[0], unit
,
3080 inst
->Texture
.Texture
, FALSE
, 1);
3082 case TGSI_OPCODE_TXP
:
3083 emit_tex(pc
, dst
, mask
, src
[0], unit
,
3084 inst
->Texture
.Texture
, TRUE
, 0);
3086 case TGSI_OPCODE_TRUNC
:
3087 for (c
= 0; c
< 4; c
++) {
3088 if (!(mask
& (1 << c
)))
3090 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
3091 CVT_TRUNC
| CVT_F32_F32
| CVT_RI
);
3094 case TGSI_OPCODE_U2F
:
3095 for (c
= 0; c
< 4; c
++) {
3096 if (!(mask
& (1 << c
)))
3098 emit_cvt(pc
, dst
[c
], src
[0][c
], -1, CVT_F32_U32
);
3101 case TGSI_OPCODE_UADD
:
3102 for (c
= 0; c
< 4; c
++) {
3103 if (!(mask
& (1 << c
)))
3105 emit_add_b32(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
3108 case TGSI_OPCODE_UMAX
:
3109 for (c
= 0; c
< 4; c
++) {
3110 if (!(mask
& (1 << c
)))
3112 emit_minmax(pc
, 0x084, dst
[c
], src
[0][c
], src
[1][c
]);
3115 case TGSI_OPCODE_UMIN
:
3116 for (c
= 0; c
< 4; c
++) {
3117 if (!(mask
& (1 << c
)))
3119 emit_minmax(pc
, 0x0a4, dst
[c
], src
[0][c
], src
[1][c
]);
3122 case TGSI_OPCODE_UMAD
:
3125 temp
= temp_temp(pc
, NULL
);
3126 for (c
= 0; c
< 4; c
++) {
3127 if (!(mask
& (1 << c
)))
3129 emit_mul_u16(pc
, temp
, src
[0][c
], 0, src
[1][c
], 1);
3130 emit_mad_u16(pc
, temp
, src
[0][c
], 1, src
[1][c
], 0,
3132 emit_shl_imm(pc
, temp
, temp
, 16);
3133 emit_mad_u16(pc
, temp
, src
[0][c
], 0, src
[1][c
], 0,
3135 emit_add_b32(pc
, dst
[c
], temp
, src
[2][c
]);
3139 case TGSI_OPCODE_UMUL
:
3142 temp
= temp_temp(pc
, NULL
);
3143 for (c
= 0; c
< 4; c
++) {
3144 if (!(mask
& (1 << c
)))
3146 emit_mul_u16(pc
, temp
, src
[0][c
], 0, src
[1][c
], 1);
3147 emit_mad_u16(pc
, temp
, src
[0][c
], 1, src
[1][c
], 0,
3149 emit_shl_imm(pc
, temp
, temp
, 16);
3150 emit_mad_u16(pc
, dst
[c
], src
[0][c
], 0, src
[1][c
], 0,
3155 case TGSI_OPCODE_XPD
:
3156 temp
= temp_temp(pc
, NULL
);
3157 if (mask
& (1 << 0)) {
3158 emit_mul(pc
, temp
, src
[0][2], src
[1][1]);
3159 emit_msb(pc
, dst
[0], src
[0][1], src
[1][2], temp
);
3161 if (mask
& (1 << 1)) {
3162 emit_mul(pc
, temp
, src
[0][0], src
[1][2]);
3163 emit_msb(pc
, dst
[1], src
[0][2], src
[1][0], temp
);
3165 if (mask
& (1 << 2)) {
3166 emit_mul(pc
, temp
, src
[0][1], src
[1][0]);
3167 emit_msb(pc
, dst
[2], src
[0][0], src
[1][1], temp
);
3169 if (mask
& (1 << 3))
3170 emit_mov_immdval(pc
, dst
[3], 1.0);
3172 case TGSI_OPCODE_END
:
3173 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
)
3174 nv50_fp_move_results(pc
);
3176 if (!pc
->p
->exec_tail
||
3177 is_immd(pc
->p
->exec_tail
) ||
3178 is_join(pc
->p
->exec_tail
) ||
3179 is_control_flow(pc
->p
->exec_tail
))
3182 /* last insn must be long so it can have the exit bit set */
3183 if (!is_long(pc
->p
->exec_tail
))
3184 convert_to_long(pc
, pc
->p
->exec_tail
);
3186 pc
->p
->exec_tail
->inst
[1] |= 1; /* set exit bit */
3191 NOUVEAU_ERR("invalid opcode %d\n", inst
->Instruction
.Opcode
);
3197 emit_sat(pc
, brdc
, brdc
);
3198 for (c
= 0; c
< 4; c
++)
3199 if ((mask
& (1 << c
)) && dst
[c
] != brdc
)
3200 emit_mov(pc
, dst
[c
], brdc
);
3203 for (c
= 0; c
< 4; c
++) {
3204 if (!(mask
& (1 << c
)))
3206 /* In this case we saturate later, and dst[c] won't
3207 * be another temp_temp (and thus lost), since rdst
3208 * already is TEMP (see above). */
3209 if (rdst
[c
]->type
== P_TEMP
&& rdst
[c
]->index
< 0)
3211 emit_sat(pc
, rdst
[c
], dst
[c
]);
3215 kill_temp_temp(pc
, NULL
);
3216 pc
->reg_instance_nr
= 0;
3222 prep_inspect_insn(struct nv50_pc
*pc
, const struct tgsi_full_instruction
*insn
)
3224 struct nv50_reg
*r
, *reg
= NULL
;
3225 const struct tgsi_full_src_register
*src
;
3226 const struct tgsi_dst_register
*dst
;
3227 unsigned i
, c
, k
, mask
;
3229 dst
= &insn
->Dst
[0].Register
;
3230 mask
= dst
->WriteMask
;
3232 if (dst
->File
== TGSI_FILE_TEMPORARY
)
3235 if (dst
->File
== TGSI_FILE_OUTPUT
) {
3238 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_MOV
&&
3239 dst
->Index
== pc
->edgeflag_out
&&
3240 insn
->Src
[0].Register
.File
== TGSI_FILE_INPUT
)
3241 pc
->p
->cfg
.edgeflag_in
= insn
->Src
[0].Register
.Index
;
3245 for (c
= 0; c
< 4; c
++) {
3246 if (!(mask
& (1 << c
)))
3248 reg
[dst
->Index
* 4 + c
].acc
= pc
->insn_nr
;
3252 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
3253 src
= &insn
->Src
[i
];
3255 if (src
->Register
.File
== TGSI_FILE_TEMPORARY
)
3258 if (src
->Register
.File
== TGSI_FILE_INPUT
)
3263 mask
= nv50_tgsi_src_mask(insn
, i
);
3265 for (c
= 0; c
< 4; c
++) {
3266 if (!(mask
& (1 << c
)))
3268 k
= tgsi_util_get_full_src_register_swizzle(src
, c
);
3270 r
= ®
[src
->Register
.Index
* 4 + k
];
3272 /* If used before written, pre-allocate the reg,
3273 * lest we overwrite results from a subroutine.
3275 if (!r
->acc
&& r
->type
== P_TEMP
)
3278 r
->acc
= pc
->insn_nr
;
3283 /* Returns a bitmask indicating which dst components need to be
3284 * written to temporaries first to avoid 'corrupting' sources.
3286 * m[i] (out) indicate component to write in the i-th position
3287 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
3290 nv50_revdep_reorder(unsigned m
[4], unsigned rdep
[4])
3292 unsigned i
, c
, x
, unsafe
= 0;
3294 for (c
= 0; c
< 4; c
++)
3297 /* Swap as long as a dst component written earlier is depended on
3298 * by one written later, but the next one isn't depended on by it.
3300 for (c
= 0; c
< 3; c
++) {
3301 if (rdep
[m
[c
+ 1]] & (1 << m
[c
]))
3302 continue; /* if next one is depended on by us */
3303 for (i
= c
+ 1; i
< 4; i
++)
3304 /* if we are depended on by a later one */
3305 if (rdep
[m
[c
]] & (1 << m
[i
]))
3318 /* mark dependencies that could not be resolved by reordering */
3319 for (i
= 0; i
< 3; ++i
)
3320 for (c
= i
+ 1; c
< 4; ++c
)
3321 if (rdep
[m
[i
]] & (1 << m
[c
]))
3324 /* NOTE: $unsafe is with respect to order, not component */
3328 /* Select a suitable dst register for broadcasting scalar results,
3329 * or return NULL if we have to allocate an extra TEMP.
3331 * If e.g. only 1 component is written, we may also emit the final
3332 * result to a write-only register.
3334 static struct nv50_reg
*
3335 tgsi_broadcast_dst(struct nv50_pc
*pc
,
3336 const struct tgsi_full_dst_register
*fd
, unsigned mask
)
3338 if (fd
->Register
.File
== TGSI_FILE_TEMPORARY
) {
3339 int c
= ffs(~mask
& fd
->Register
.WriteMask
);
3341 return tgsi_dst(pc
, c
- 1, fd
);
3343 int c
= ffs(fd
->Register
.WriteMask
) - 1;
3344 if ((1 << c
) == fd
->Register
.WriteMask
)
3345 return tgsi_dst(pc
, c
, fd
);
3351 /* Scan source swizzles and return a bitmask indicating dst regs that
3352 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
3355 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction
*insn
,
3358 const struct tgsi_full_dst_register
*fd
= &insn
->Dst
[0];
3359 const struct tgsi_full_src_register
*fs
;
3360 unsigned i
, deqs
= 0;
3362 for (i
= 0; i
< 4; ++i
)
3365 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
3366 unsigned chn
, mask
= nv50_tgsi_src_mask(insn
, i
);
3367 int ms
= get_supported_mods(insn
, i
);
3370 if (fs
->Register
.File
!= fd
->Register
.File
||
3371 fs
->Register
.Index
!= fd
->Register
.Index
)
3374 for (chn
= 0; chn
< 4; ++chn
) {
3377 if (!(mask
& (1 << chn
))) /* src is not read */
3379 c
= tgsi_util_get_full_src_register_swizzle(fs
, chn
);
3380 s
= tgsi_util_get_full_src_register_sign_mode(fs
, chn
);
3382 if (!(fd
->Register
.WriteMask
& (1 << c
)))
3385 if (s
== TGSI_UTIL_SIGN_TOGGLE
&& !(ms
& NV50_MOD_NEG
))
3387 if (s
== TGSI_UTIL_SIGN_CLEAR
&& !(ms
& NV50_MOD_ABS
))
3389 if ((s
== TGSI_UTIL_SIGN_SET
) && ((ms
& 3) != 3))
3392 rdep
[c
] |= nv50_tgsi_dst_revdep(
3393 insn
->Instruction
.Opcode
, i
, chn
);
3402 nv50_tgsi_insn(struct nv50_pc
*pc
, const union tgsi_full_token
*tok
)
3404 struct tgsi_full_instruction insn
= tok
->FullInstruction
;
3405 const struct tgsi_full_dst_register
*fd
;
3406 unsigned i
, deqs
, rdep
[4], m
[4];
3408 fd
= &tok
->FullInstruction
.Dst
[0];
3409 deqs
= nv50_tgsi_scan_swizzle(&insn
, rdep
);
3411 if (is_scalar_op(insn
.Instruction
.Opcode
)) {
3412 pc
->r_brdc
= tgsi_broadcast_dst(pc
, fd
, deqs
);
3414 pc
->r_brdc
= temp_temp(pc
, NULL
);
3415 return nv50_program_tx_insn(pc
, &insn
);
3419 if (!deqs
|| (!rdep
[0] && !rdep
[1] && !rdep
[2] && !rdep
[3]))
3420 return nv50_program_tx_insn(pc
, &insn
);
3422 deqs
= nv50_revdep_reorder(m
, rdep
);
3424 for (i
= 0; i
< 4; ++i
) {
3425 assert(pc
->r_dst
[m
[i
]] == NULL
);
3427 insn
.Dst
[0].Register
.WriteMask
=
3428 fd
->Register
.WriteMask
& (1 << m
[i
]);
3430 if (!insn
.Dst
[0].Register
.WriteMask
)
3433 if (deqs
& (1 << i
))
3434 pc
->r_dst
[m
[i
]] = alloc_temp(pc
, NULL
);
3436 if (!nv50_program_tx_insn(pc
, &insn
))
3440 for (i
= 0; i
< 4; i
++) {
3441 struct nv50_reg
*reg
= pc
->r_dst
[i
];
3444 pc
->r_dst
[i
] = NULL
;
3446 if (insn
.Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
)
3447 emit_sat(pc
, tgsi_dst(pc
, i
, fd
), reg
);
3449 emit_mov(pc
, tgsi_dst(pc
, i
, fd
), reg
);
3457 load_interpolant(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
3459 struct nv50_reg
*iv
, **ppiv
;
3460 unsigned mode
= pc
->interp_mode
[reg
->index
];
3462 ppiv
= (mode
& INTERP_CENTROID
) ? &pc
->iv_c
: &pc
->iv_p
;
3465 if ((mode
& INTERP_PERSPECTIVE
) && !iv
) {
3466 iv
= *ppiv
= alloc_temp(pc
, NULL
);
3467 iv
->rhw
= popcnt4(pc
->p
->cfg
.regs
[1] >> 24) - 1;
3469 emit_interp(pc
, iv
, NULL
, mode
& INTERP_CENTROID
);
3470 emit_flop(pc
, NV50_FLOP_RCP
, iv
, iv
);
3472 /* XXX: when loading interpolants dynamically, move these
3473 * to the program head, or make sure it can't be skipped.
3477 emit_interp(pc
, reg
, iv
, mode
);
3480 /* The face input is always at v[255] (varying space), with a
3481 * value of 0 for back-facing, and 0xffffffff for front-facing.
3484 load_frontfacing(struct nv50_pc
*pc
, struct nv50_reg
*sv
)
3486 struct nv50_reg
*temp
= alloc_temp(pc
, NULL
);
3490 emit_interp(pc
, temp
, NULL
, INTERP_FLAT
);
3492 emit_cvt(pc
, sv
, temp
, r_pred
, CVT_ABS
| CVT_F32_S32
);
3494 emit_not(pc
, temp
, temp
);
3495 set_pred(pc
, 0x2, r_pred
, pc
->p
->exec_tail
);
3496 emit_cvt(pc
, sv
, temp
, -1, CVT_F32_S32
);
3497 set_pred(pc
, 0x2, r_pred
, pc
->p
->exec_tail
);
3499 free_temp(pc
, temp
);
3503 load_instance_id(struct nv50_pc
*pc
, unsigned index
)
3505 struct nv50_reg reg
, mem
;
3507 ctor_reg(®
, P_TEMP
, -1, -1);
3508 ctor_reg(&mem
, P_CONST
, -1, 24); /* startInstance */
3511 emit_add_b32(pc
, ®
, &pc
->sysval
[index
], &mem
);
3512 pc
->sysval
[index
] = reg
;
3516 copy_semantic_info(struct nv50_program
*p
)
3520 for (i
= 0; i
< p
->cfg
.in_nr
; ++i
) {
3521 id
= p
->cfg
.in
[i
].id
;
3522 p
->cfg
.in
[i
].sn
= p
->info
.input_semantic_name
[id
];
3523 p
->cfg
.in
[i
].si
= p
->info
.input_semantic_index
[id
];
3526 for (i
= 0; i
< p
->cfg
.out_nr
; ++i
) {
3527 id
= p
->cfg
.out
[i
].id
;
3528 p
->cfg
.out
[i
].sn
= p
->info
.output_semantic_name
[id
];
3529 p
->cfg
.out
[i
].si
= p
->info
.output_semantic_index
[id
];
3534 nv50_program_tx_prep(struct nv50_pc
*pc
)
3536 struct tgsi_parse_context tp
;
3537 struct nv50_program
*p
= pc
->p
;
3538 boolean ret
= FALSE
;
3539 unsigned i
, c
, instance_id
= 0, vertex_id
= 0, flat_nr
= 0;
3541 tgsi_parse_init(&tp
, pc
->p
->pipe
.tokens
);
3542 while (!tgsi_parse_end_of_tokens(&tp
)) {
3543 const union tgsi_full_token
*tok
= &tp
.FullToken
;
3545 tgsi_parse_token(&tp
);
3546 switch (tok
->Token
.Type
) {
3547 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3549 const struct tgsi_full_immediate
*imm
=
3550 &tp
.FullToken
.FullImmediate
;
3552 ctor_immd_4f32(pc
, imm
->u
[0].Float
,
3558 case TGSI_TOKEN_TYPE_DECLARATION
:
3560 const struct tgsi_full_declaration
*d
;
3561 unsigned si
, last
, first
, mode
;
3563 d
= &tp
.FullToken
.FullDeclaration
;
3564 first
= d
->Range
.First
;
3565 last
= d
->Range
.Last
;
3567 switch (d
->Declaration
.File
) {
3568 case TGSI_FILE_TEMPORARY
:
3570 case TGSI_FILE_OUTPUT
:
3571 if (!d
->Declaration
.Semantic
||
3572 p
->type
== PIPE_SHADER_FRAGMENT
)
3575 si
= d
->Semantic
.Index
;
3576 switch (d
->Semantic
.Name
) {
3577 case TGSI_SEMANTIC_BCOLOR
:
3578 p
->cfg
.two_side
[si
].hw
= first
;
3579 if (p
->cfg
.out_nr
> first
)
3580 p
->cfg
.out_nr
= first
;
3582 case TGSI_SEMANTIC_PSIZE
:
3583 p
->cfg
.psiz
= first
;
3584 if (p
->cfg
.out_nr
> first
)
3585 p
->cfg
.out_nr
= first
;
3587 case TGSI_SEMANTIC_EDGEFLAG
:
3588 pc
->edgeflag_out
= first
;
3591 case TGSI_SEMANTIC_CLIP_DISTANCE:
3592 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3599 case TGSI_FILE_INPUT
:
3601 if (p
->type
!= PIPE_SHADER_FRAGMENT
)
3604 switch (d
->Declaration
.Interpolate
) {
3605 case TGSI_INTERPOLATE_CONSTANT
:
3609 case TGSI_INTERPOLATE_PERSPECTIVE
:
3610 mode
= INTERP_PERSPECTIVE
;
3611 p
->cfg
.regs
[1] |= 0x08 << 24;
3614 mode
= INTERP_LINEAR
;
3617 if (d
->Declaration
.Centroid
)
3618 mode
|= INTERP_CENTROID
;
3621 for (i
= first
; i
<= last
; i
++)
3622 pc
->interp_mode
[i
] = mode
;
3625 case TGSI_FILE_SYSTEM_VALUE
:
3626 assert(d
->Declaration
.Semantic
);
3627 switch (d
->Semantic
.Name
) {
3628 case TGSI_SEMANTIC_FACE
:
3629 assert(p
->type
== PIPE_SHADER_FRAGMENT
);
3630 load_frontfacing(pc
,
3631 &pc
->sysval
[first
]);
3633 case TGSI_SEMANTIC_INSTANCEID
:
3634 assert(p
->type
== PIPE_SHADER_VERTEX
);
3635 instance_id
= first
;
3636 p
->cfg
.regs
[0] |= (1 << 4);
3638 case TGSI_SEMANTIC_PRIMID
:
3639 assert(p
->type
!= PIPE_SHADER_VERTEX
);
3640 p
->cfg
.prim_id
= first
;
3643 case TGSI_SEMANTIC_PRIMIDIN:
3644 assert(p->type == PIPE_SHADER_GEOMETRY);
3645 pc->sysval[first].hw = 6;
3646 p->cfg.regs[0] |= (1 << 8);
3648 case TGSI_SEMANTIC_VERTEXID:
3649 assert(p->type == PIPE_SHADER_VERTEX);
3651 p->cfg.regs[0] |= (1 << 12) | (1 << 0);
3656 case TGSI_FILE_ADDRESS
:
3657 case TGSI_FILE_CONSTANT
:
3658 case TGSI_FILE_SAMPLER
:
3661 NOUVEAU_ERR("bad decl file %d\n",
3662 d
->Declaration
.File
);
3667 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3669 prep_inspect_insn(pc
, &tok
->FullInstruction
);
3676 if (p
->type
== PIPE_SHADER_VERTEX
|| p
->type
== PIPE_SHADER_GEOMETRY
) {
3679 if (p
->type
== PIPE_SHADER_GEOMETRY
) {
3680 for (i
= 0; i
< pc
->attr_nr
; ++i
) {
3681 p
->cfg
.in
[i
].hw
= rid
;
3682 p
->cfg
.in
[i
].id
= i
;
3684 for (c
= 0; c
< 4; ++c
) {
3686 if (!pc
->attr
[n
].acc
)
3688 pc
->attr
[n
].hw
= rid
++;
3689 p
->cfg
.in
[i
].mask
|= 1 << c
;
3693 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
) {
3694 if (pc
->attr
[i
].acc
) {
3695 pc
->attr
[i
].hw
= rid
++;
3696 p
->cfg
.attr
[i
/ 32] |= 1 << (i
% 32);
3699 if (p
->cfg
.regs
[0] & (1 << 0))
3700 pc
->sysval
[vertex_id
].hw
= rid
++;
3701 if (p
->cfg
.regs
[0] & (1 << 4)) {
3702 pc
->sysval
[instance_id
].hw
= rid
++;
3703 load_instance_id(pc
, instance_id
);
3707 for (i
= 0, rid
= 0; i
< pc
->result_nr
; ++i
) {
3708 p
->cfg
.out
[i
].hw
= rid
;
3709 p
->cfg
.out
[i
].id
= i
;
3711 for (c
= 0; c
< 4; ++c
) {
3713 if (!pc
->result
[n
].acc
)
3715 pc
->result
[n
].hw
= rid
++;
3716 p
->cfg
.out
[i
].mask
|= 1 << c
;
3719 if (p
->cfg
.prim_id
< 0x40) {
3720 /* GP has to write to PrimitiveID */
3721 ctor_reg(&pc
->sysval
[p
->cfg
.prim_id
],
3722 P_RESULT
, p
->cfg
.prim_id
, rid
);
3723 p
->cfg
.prim_id
= rid
++;
3726 for (c
= 0; c
< 2; ++c
)
3727 if (p
->cfg
.two_side
[c
].hw
< 0x40)
3728 p
->cfg
.two_side
[c
] = p
->cfg
.out
[
3729 p
->cfg
.two_side
[c
].hw
];
3731 if (p
->cfg
.psiz
< 0x40)
3732 p
->cfg
.psiz
= p
->cfg
.out
[p
->cfg
.psiz
].hw
;
3734 copy_semantic_info(p
);
3736 if (p
->type
== PIPE_SHADER_FRAGMENT
) {
3738 unsigned n
= 0, m
= pc
->attr_nr
- flat_nr
;
3742 /* do we read FragCoord ? */
3744 p
->info
.input_semantic_name
[0] == TGSI_SEMANTIC_POSITION
) {
3745 /* select FCRD components we want accessible */
3746 for (c
= 0; c
< 4; ++c
)
3747 if (pc
->attr
[c
].acc
)
3748 p
->cfg
.regs
[1] |= 1 << (24 + c
);
3750 } else /* offset by 1 if FCRD.w is needed for pinterp */
3751 aid
= popcnt4(p
->cfg
.regs
[1] >> 24);
3753 /* non-flat interpolants have to be mapped to
3754 * the lower hardware IDs, so sort them:
3756 for (i
= 0; i
< pc
->attr_nr
; i
++) {
3757 if (pc
->interp_mode
[i
] == INTERP_FLAT
)
3758 p
->cfg
.in
[m
++].id
= i
;
3760 if (!(pc
->interp_mode
[i
] & INTERP_PERSPECTIVE
))
3761 p
->cfg
.in
[n
].linear
= TRUE
;
3762 p
->cfg
.in
[n
++].id
= i
;
3765 copy_semantic_info(p
);
3767 for (n
= 0; n
< pc
->attr_nr
; ++n
) {
3768 p
->cfg
.in
[n
].hw
= rid
= aid
;
3769 i
= p
->cfg
.in
[n
].id
;
3771 if (p
->info
.input_semantic_name
[i
] ==
3772 TGSI_SEMANTIC_FACE
) {
3773 load_frontfacing(pc
, &pc
->attr
[i
* 4]);
3777 for (c
= 0; c
< 4; ++c
) {
3778 if (!pc
->attr
[i
* 4 + c
].acc
)
3780 pc
->attr
[i
* 4 + c
].rhw
= rid
++;
3781 p
->cfg
.in
[n
].mask
|= 1 << c
;
3783 load_interpolant(pc
, &pc
->attr
[i
* 4 + c
]);
3785 aid
+= popcnt4(p
->cfg
.in
[n
].mask
);
3788 m
= popcnt4(p
->cfg
.regs
[1] >> 24);
3790 /* set count of non-position inputs and of non-flat
3791 * non-position inputs for FP_INTERPOLANT_CTRL
3793 p
->cfg
.regs
[1] |= aid
- m
;
3796 i
= p
->cfg
.in
[pc
->attr_nr
- flat_nr
].hw
;
3797 p
->cfg
.regs
[1] |= (i
- m
) << 16;
3799 p
->cfg
.regs
[1] |= p
->cfg
.regs
[1] << 16;
3801 /* mark color semantic for light-twoside */
3803 for (i
= 0; i
< p
->cfg
.in_nr
; i
++) {
3804 if (p
->cfg
.in
[i
].sn
== TGSI_SEMANTIC_COLOR
) {
3805 n
= MIN2(n
, p
->cfg
.in
[i
].hw
- m
);
3806 p
->cfg
.two_side
[p
->cfg
.in
[i
].si
] = p
->cfg
.in
[i
];
3808 p
->cfg
.regs
[0] += /* increase colour count */
3809 popcnt4(p
->cfg
.in
[i
].mask
) << 16;
3813 p
->cfg
.regs
[0] += n
;
3815 if (p
->cfg
.prim_id
< 0x40) {
3816 pc
->sysval
[p
->cfg
.prim_id
].rhw
= rid
++;
3817 emit_interp(pc
, &pc
->sysval
[p
->cfg
.prim_id
], NULL
,
3819 /* increase FP_INTERPOLANT_CTRL_COUNT */
3820 p
->cfg
.regs
[1] += 1;
3823 /* Initialize FP results:
3824 * FragDepth is always first TGSI and last hw output
3826 i
= p
->info
.writes_z
? 4 : 0;
3827 for (rid
= 0; i
< pc
->result_nr
* 4; i
++)
3828 pc
->result
[i
].rhw
= rid
++;
3829 if (p
->info
.writes_z
)
3830 pc
->result
[2].rhw
= rid
++;
3832 p
->cfg
.high_result
= rid
;
3834 /* separate/different colour results for MRTs ? */
3835 if (pc
->result_nr
- (p
->info
.writes_z
? 1 : 0) > 1)
3836 p
->cfg
.regs
[2] |= 1;
3842 pc
->immd
= MALLOC(pc
->immd_nr
* 4 * sizeof(struct nv50_reg
));
3846 for (i
= 0; i
< pc
->immd_nr
; i
++) {
3847 for (c
= 0; c
< 4; c
++, rid
++)
3848 ctor_reg(&pc
->immd
[rid
], P_IMMD
, i
, rid
);
3855 free_temp(pc
, pc
->iv_p
);
3857 free_temp(pc
, pc
->iv_c
);
3859 tgsi_parse_free(&tp
);
3864 free_nv50_pc(struct nv50_pc
*pc
)
3884 static INLINE
uint32_t
3885 nv50_map_gs_output_prim(unsigned pprim
)
3888 case PIPE_PRIM_POINTS
:
3889 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_POINTS
;
3890 case PIPE_PRIM_LINE_STRIP
:
3891 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP
;
3892 case PIPE_PRIM_TRIANGLE_STRIP
:
3893 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP
;
3895 NOUVEAU_ERR("invalid GS_OUTPUT_PRIMITIVE: %u\n", pprim
);
3902 ctor_nv50_pc(struct nv50_pc
*pc
, struct nv50_program
*p
)
3905 unsigned rtype
[2] = { P_ATTR
, P_RESULT
};
3908 pc
->temp_nr
= p
->info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
3909 pc
->attr_nr
= p
->info
.file_max
[TGSI_FILE_INPUT
] + 1;
3910 pc
->result_nr
= p
->info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
3911 pc
->param_nr
= p
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
3912 pc
->addr_nr
= p
->info
.file_max
[TGSI_FILE_ADDRESS
] + 1;
3913 assert(pc
->addr_nr
<= 2);
3914 pc
->sysval_nr
= p
->info
.file_max
[TGSI_FILE_SYSTEM_VALUE
] + 1;
3916 p
->cfg
.high_temp
= 4;
3918 p
->cfg
.two_side
[0].hw
= 0x40;
3919 p
->cfg
.two_side
[1].hw
= 0x40;
3920 p
->cfg
.prim_id
= 0x40;
3922 p
->cfg
.edgeflag_in
= pc
->edgeflag_out
= 0xff;
3924 for (i
= 0; i
< p
->info
.num_properties
; ++i
) {
3925 unsigned *data
= &p
->info
.properties
[i
].data
[0];
3927 switch (p
->info
.properties
[i
].name
) {
3928 case TGSI_PROPERTY_GS_OUTPUT_PRIM
:
3929 p
->cfg
.prim_type
= nv50_map_gs_output_prim(data
[0]);
3931 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
:
3932 p
->cfg
.vert_count
= data
[0];
3940 case PIPE_SHADER_VERTEX
:
3943 p
->cfg
.out_nr
= pc
->result_nr
;
3945 case PIPE_SHADER_GEOMETRY
:
3946 assert(p
->cfg
.prim_type
);
3947 assert(p
->cfg
.vert_count
);
3951 p
->cfg
.prim_id
= 0x80;
3952 p
->cfg
.out_nr
= pc
->result_nr
;
3953 p
->cfg
.in_nr
= pc
->attr_nr
;
3955 p
->cfg
.two_side
[0].hw
= 0x80;
3956 p
->cfg
.two_side
[1].hw
= 0x80;
3958 case PIPE_SHADER_FRAGMENT
:
3959 rtype
[0] = rtype
[1] = P_TEMP
;
3961 p
->cfg
.regs
[0] = 0x01000004;
3962 p
->cfg
.in_nr
= pc
->attr_nr
;
3964 if (p
->info
.writes_z
) {
3965 p
->cfg
.regs
[2] |= 0x00000100;
3966 p
->cfg
.regs
[3] |= 0x00000011;
3968 if (p
->info
.uses_kill
)
3969 p
->cfg
.regs
[2] |= 0x00100000;
3974 pc
->temp
= MALLOC(pc
->temp_nr
* 4 * sizeof(struct nv50_reg
));
3978 for (i
= 0; i
< pc
->temp_nr
* 4; ++i
)
3979 ctor_reg(&pc
->temp
[i
], P_TEMP
, i
/ 4, -1);
3983 pc
->attr
= MALLOC(pc
->attr_nr
* 4 * sizeof(struct nv50_reg
));
3987 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
)
3988 ctor_reg(&pc
->attr
[i
], rtype
[0], i
/ 4, -1);
3991 if (pc
->result_nr
) {
3992 unsigned nr
= pc
->result_nr
* 4;
3994 pc
->result
= MALLOC(nr
* sizeof(struct nv50_reg
));
3998 for (i
= 0; i
< nr
; ++i
)
3999 ctor_reg(&pc
->result
[i
], rtype
[1], i
/ 4, -1);
4005 pc
->param
= MALLOC(pc
->param_nr
* 4 * sizeof(struct nv50_reg
));
4009 for (i
= 0; i
< pc
->param_nr
; ++i
)
4010 for (c
= 0; c
< 4; ++c
, ++rid
)
4011 ctor_reg(&pc
->param
[rid
], P_CONST
, i
, rid
);
4015 pc
->addr
= CALLOC(pc
->addr_nr
* 4, sizeof(struct nv50_reg
*));
4019 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
4020 ctor_reg(&pc
->r_addr
[i
], P_ADDR
, -1, i
+ 1);
4022 if (pc
->sysval_nr
) {
4023 pc
->sysval
= CALLOC(pc
->sysval_nr
, sizeof(struct nv50_reg
*));
4026 /* will only ever use SYSTEM_VALUE[i].x (hopefully) */
4027 for (i
= 0; i
< pc
->sysval_nr
; ++i
)
4028 ctor_reg(&pc
->sysval
[i
], rtype
[0], i
, -1);
4035 nv50_program_fixup_insns(struct nv50_pc
*pc
)
4037 struct nv50_program_exec
*e
, **bra_list
;
4040 bra_list
= CALLOC(pc
->p
->exec_size
, sizeof(struct nv50_program_exec
*));
4042 /* Collect branch instructions, we need to adjust their offsets
4043 * when converting 32 bit instructions to 64 bit ones
4045 for (n
= 0, e
= pc
->p
->exec_head
; e
; e
= e
->next
)
4046 if (e
->param
.index
>= 0 && !e
->param
.mask
)
4049 /* Make sure we don't have any single 32 bit instructions. */
4050 for (e
= pc
->p
->exec_head
, pos
= 0; e
; e
= e
->next
) {
4051 pos
+= is_long(e
) ? 2 : 1;
4053 if ((pos
& 1) && (!e
->next
|| is_long(e
->next
))) {
4054 for (i
= 0; i
< n
; ++i
)
4055 if (bra_list
[i
]->param
.index
>= pos
)
4056 bra_list
[i
]->param
.index
+= 1;
4057 for (i
= 0; i
< pc
->insn_nr
; ++i
)
4058 if (pc
->insn_pos
[i
] >= pos
)
4059 pc
->insn_pos
[i
] += 1;
4060 convert_to_long(pc
, e
);
4067 if (!pc
->p
->info
.opcode_count
[TGSI_OPCODE_CAL
])
4070 /* fill in CALL offsets */
4071 for (e
= pc
->p
->exec_head
; e
; e
= e
->next
) {
4072 if ((e
->inst
[0] & 2) && (e
->inst
[0] >> 28) == 0x2)
4073 e
->param
.index
= pc
->insn_pos
[e
->param
.index
];
4078 nv50_program_tx(struct nv50_program
*p
)
4080 struct tgsi_parse_context parse
;
4084 pc
= CALLOC_STRUCT(nv50_pc
);
4088 ret
= ctor_nv50_pc(pc
, p
);
4092 ret
= nv50_program_tx_prep(pc
);
4096 pc
->insn_pos
= MALLOC(pc
->insn_nr
* sizeof(unsigned));
4098 tgsi_parse_init(&parse
, pc
->p
->pipe
.tokens
);
4099 while (!tgsi_parse_end_of_tokens(&parse
)) {
4100 const union tgsi_full_token
*tok
= &parse
.FullToken
;
4102 /* previously allow32 was FALSE for first & last instruction */
4105 tgsi_parse_token(&parse
);
4107 switch (tok
->Token
.Type
) {
4108 case TGSI_TOKEN_TYPE_INSTRUCTION
:
4109 pc
->insn_pos
[pc
->insn_cur
] = pc
->p
->exec_size
;
4111 ret
= nv50_tgsi_insn(pc
, tok
);
4120 nv50_program_fixup_insns(pc
);
4122 p
->param_nr
= pc
->param_nr
* 4;
4123 p
->immd_nr
= pc
->immd_nr
* 4;
4124 p
->immd
= pc
->immd_buf
;
4127 tgsi_parse_free(&parse
);
4135 nv50_program_validate(struct nv50_context
*nv50
, struct nv50_program
*p
)
4137 if (nv50_program_tx(p
) == FALSE
)
4139 p
->translated
= TRUE
;
4143 nv50_program_upload_data(struct nv50_context
*nv50
, uint32_t *map
,
4144 unsigned start
, unsigned count
, unsigned cbuf
)
4146 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
4147 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
4150 unsigned nr
= count
> 2047 ? 2047 : count
;
4152 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 1);
4153 OUT_RING (chan
, (cbuf
<< 0) | (start
<< 8));
4154 BEGIN_RING(chan
, tesla
, NV50TCL_CB_DATA(0) | 0x40000000, nr
);
4155 OUT_RINGp (chan
, map
, nr
);
4164 nv50_program_validate_data(struct nv50_context
*nv50
, struct nv50_program
*p
)
4166 struct pipe_context
*pipe
= &nv50
->pipe
;
4167 struct pipe_transfer
*transfer
;
4169 if (!p
->data
[0] && p
->immd_nr
) {
4170 struct nouveau_resource
*heap
= nv50
->screen
->immd_heap
;
4172 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
, &p
->data
[0])) {
4173 while (heap
->next
&& heap
->size
< p
->immd_nr
) {
4174 struct nv50_program
*evict
= heap
->next
->priv
;
4175 nouveau_resource_free(&evict
->data
[0]);
4178 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
,
4183 /* immediates only need to be uploaded again when freed */
4184 nv50_program_upload_data(nv50
, p
->immd
, p
->data
[0]->start
,
4185 p
->immd_nr
, NV50_CB_PMISC
);
4188 assert(p
->param_nr
<= 16384);
4192 uint32_t *map
= pipe_buffer_map(pipe
,
4193 nv50
->constbuf
[p
->type
],
4197 case PIPE_SHADER_GEOMETRY
: cb
= NV50_CB_PGP
; break;
4198 case PIPE_SHADER_FRAGMENT
: cb
= NV50_CB_PFP
; break;
4201 assert(p
->type
== PIPE_SHADER_VERTEX
);
4205 nv50_program_upload_data(nv50
, map
, 0, p
->param_nr
, cb
);
4206 pipe_buffer_unmap(pipe
, nv50
->constbuf
[p
->type
],
4212 nv50_program_validate_code(struct nv50_context
*nv50
, struct nv50_program
*p
)
4214 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
4215 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
4216 struct nv50_program_exec
*e
;
4218 boolean upload
= FALSE
;
4223 nouveau_bo_new(chan
->device
, NOUVEAU_BO_VRAM
, 0x100,
4224 p
->exec_size
* 4, &p
->bo
);
4228 if (p
->data
[0] && p
->data
[0]->start
!= p
->data_start
[0])
4234 up
= MALLOC(p
->exec_size
* 4);
4236 for (i
= 0, e
= p
->exec_head
; e
; e
= e
->next
) {
4237 unsigned ei
, ci
, bs
;
4239 if (e
->param
.index
>= 0 && e
->param
.mask
) {
4240 bs
= (e
->inst
[1] >> 22) & 0x07;
4242 ei
= e
->param
.shift
>> 5;
4243 ci
= e
->param
.index
;
4245 ci
+= p
->data
[bs
]->start
;
4247 e
->inst
[ei
] &= ~e
->param
.mask
;
4248 e
->inst
[ei
] |= (ci
<< e
->param
.shift
);
4250 if (e
->param
.index
>= 0) {
4251 /* zero mask means param is a jump/branch offset */
4252 assert(!(e
->param
.index
& 1));
4253 /* seem to be 8 byte steps */
4254 ei
= (e
->param
.index
>> 1) + 0 /* START_ID */;
4256 e
->inst
[0] &= 0xf0000fff;
4257 e
->inst
[0] |= ei
<< 12;
4260 up
[i
++] = e
->inst
[0];
4262 up
[i
++] = e
->inst
[1];
4264 assert(i
== p
->exec_size
);
4267 p
->data_start
[0] = p
->data
[0]->start
;
4269 #ifdef NV50_PROGRAM_DUMP
4270 NOUVEAU_ERR("-------\n");
4271 for (e
= p
->exec_head
; e
; e
= e
->next
) {
4272 NOUVEAU_ERR("0x%08x\n", e
->inst
[0]);
4274 NOUVEAU_ERR("0x%08x\n", e
->inst
[1]);
4278 /* SIFC_HEIGHT/SIFC_WIDTH of 65536 do not work, and are not reported
4279 * as data error either. hw bug ? */
4280 #define SIFC_MAX_WIDTH (65536 - 256)
4282 width
= p
->exec_size
* 4;
4284 nv50_upload_sifc(nv50
, p
->bo
, offset
, NOUVEAU_BO_VRAM
,
4285 NV50_2D_DST_FORMAT_R8_UNORM
, 65536, 1, 262144,
4286 &up
[offset
/ 4], NV50_2D_SIFC_FORMAT_R8_UNORM
,
4287 0, 0, 0, MIN2(SIFC_MAX_WIDTH
, width
), 1, 1);
4288 width
-= SIFC_MAX_WIDTH
;
4289 offset
+= SIFC_MAX_WIDTH
;
4291 BEGIN_RING(chan
, tesla
, NV50TCL_CODE_CB_FLUSH
, 1);
4297 struct nouveau_stateobj
*
4298 nv50_vertprog_validate(struct nv50_context
*nv50
)
4300 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
4301 struct nv50_program
*p
= nv50
->vertprog
;
4302 struct nouveau_stateobj
*so
;
4304 if (!p
->translated
) {
4305 nv50_program_validate(nv50
, p
);
4310 nv50_program_validate_data(nv50
, p
);
4311 nv50_program_validate_code(nv50
, p
);
4313 if (!(nv50
->dirty
& NV50_NEW_VERTPROG
))
4316 so
= so_new(5, 7, 2);
4317 so_method(so
, tesla
, NV50TCL_VP_ADDRESS_HIGH
, 2);
4318 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
4319 NOUVEAU_BO_HIGH
, 0, 0);
4320 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
4321 NOUVEAU_BO_LOW
, 0, 0);
4322 so_method(so
, tesla
, NV50TCL_VP_ATTR_EN_0
, 2);
4323 so_data (so
, p
->cfg
.attr
[0]);
4324 so_data (so
, p
->cfg
.attr
[1]);
4325 so_method(so
, tesla
, NV50TCL_VP_REG_ALLOC_RESULT
, 1);
4326 so_data (so
, p
->cfg
.high_result
);
4327 so_method(so
, tesla
, NV50TCL_VP_REG_ALLOC_TEMP
, 1);
4328 so_data (so
, p
->cfg
.high_temp
);
4329 so_method(so
, tesla
, NV50TCL_VP_START_ID
, 1);
4330 so_data (so
, 0); /* program start offset */
4334 struct nouveau_stateobj
*
4335 nv50_fragprog_validate(struct nv50_context
*nv50
)
4337 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
4338 struct nv50_program
*p
= nv50
->fragprog
;
4339 struct nouveau_stateobj
*so
;
4341 if (!p
->translated
) {
4342 nv50_program_validate(nv50
, p
);
4347 nv50_program_validate_data(nv50
, p
);
4348 nv50_program_validate_code(nv50
, p
);
4350 if (!(nv50
->dirty
& NV50_NEW_FRAGPROG
))
4353 so
= so_new(6, 7, 2);
4354 so_method(so
, tesla
, NV50TCL_FP_ADDRESS_HIGH
, 2);
4355 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
4356 NOUVEAU_BO_HIGH
, 0, 0);
4357 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
4358 NOUVEAU_BO_LOW
, 0, 0);
4359 so_method(so
, tesla
, NV50TCL_FP_REG_ALLOC_TEMP
, 1);
4360 so_data (so
, p
->cfg
.high_temp
);
4361 so_method(so
, tesla
, NV50TCL_FP_RESULT_COUNT
, 1);
4362 so_data (so
, p
->cfg
.high_result
);
4363 so_method(so
, tesla
, NV50TCL_FP_CONTROL
, 1);
4364 so_data (so
, p
->cfg
.regs
[2]);
4365 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK196C
, 1);
4366 so_data (so
, p
->cfg
.regs
[3]);
4367 so_method(so
, tesla
, NV50TCL_FP_START_ID
, 1);
4368 so_data (so
, 0); /* program start offset */
4372 struct nouveau_stateobj
*
4373 nv50_geomprog_validate(struct nv50_context
*nv50
)
4375 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
4376 struct nv50_program
*p
= nv50
->geomprog
;
4377 struct nouveau_stateobj
*so
;
4379 if (!p
->translated
) {
4380 nv50_program_validate(nv50
, p
);
4385 nv50_program_validate_data(nv50
, p
);
4386 nv50_program_validate_code(nv50
, p
);
4388 if (!(nv50
->dirty
& NV50_NEW_GEOMPROG
))
4391 so
= so_new(6, 7, 2);
4392 so_method(so
, tesla
, NV50TCL_GP_ADDRESS_HIGH
, 2);
4393 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
4394 NOUVEAU_BO_HIGH
, 0, 0);
4395 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
4396 NOUVEAU_BO_LOW
, 0, 0);
4397 so_method(so
, tesla
, NV50TCL_GP_REG_ALLOC_TEMP
, 1);
4398 so_data (so
, p
->cfg
.high_temp
);
4399 so_method(so
, tesla
, NV50TCL_GP_REG_ALLOC_RESULT
, 1);
4400 so_data (so
, p
->cfg
.high_result
);
4401 so_method(so
, tesla
, NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE
, 1);
4402 so_data (so
, p
->cfg
.prim_type
);
4403 so_method(so
, tesla
, NV50TCL_GP_VERTEX_OUTPUT_COUNT
, 1);
4404 so_data (so
, p
->cfg
.vert_count
);
4405 so_method(so
, tesla
, NV50TCL_GP_START_ID
, 1);
4411 nv50_pntc_replace(struct nv50_context
*nv50
, uint32_t pntc
[8], unsigned base
)
4413 struct nv50_program
*vp
;
4414 struct nv50_program
*fp
= nv50
->fragprog
;
4415 unsigned i
, c
, m
= base
;
4416 uint32_t origin
= 0x00000010;
4418 vp
= nv50
->geomprog
? nv50
->geomprog
: nv50
->vertprog
;
4420 /* XXX: this might not work correctly in all cases yet - we'll
4421 * just assume that an FP generic input that is not written in
4422 * the VP is PointCoord.
4424 memset(pntc
, 0, 8 * sizeof(uint32_t));
4426 for (i
= 0; i
< fp
->cfg
.in_nr
; i
++) {
4427 unsigned j
, n
= popcnt4(fp
->cfg
.in
[i
].mask
);
4429 if (fp
->cfg
.in
[i
].sn
!= TGSI_SEMANTIC_GENERIC
) {
4434 for (j
= 0; j
< vp
->cfg
.out_nr
; ++j
)
4435 if (vp
->cfg
.out
[j
].sn
== fp
->cfg
.in
[i
].sn
&&
4436 vp
->cfg
.out
[j
].si
== fp
->cfg
.in
[i
].si
)
4439 if (j
< vp
->info
.num_outputs
) {
4441 (nv50
->rasterizer
->pipe
.sprite_coord_enable
>> vp
->cfg
.out
[j
].si
) & 1;
4449 /* this is either PointCoord or replaced by sprite coords */
4450 for (c
= 0; c
< 4; c
++) {
4451 if (!(fp
->cfg
.in
[i
].mask
& (1 << c
)))
4453 pntc
[m
/ 8] |= (c
+ 1) << ((m
% 8) * 4);
4457 return (nv50
->rasterizer
->pipe
.sprite_coord_mode
== PIPE_SPRITE_COORD_LOWER_LEFT
? 0 : origin
);
4461 nv50_vec4_map(uint32_t *map32
, int mid
, uint8_t zval
, uint32_t lin
[4],
4462 struct nv50_sreg4
*fpi
, struct nv50_sreg4
*vpo
)
4465 uint8_t mv
= vpo
->mask
, mf
= fpi
->mask
, oid
= vpo
->hw
;
4466 uint8_t *map
= (uint8_t *)map32
;
4468 for (c
= 0; c
< 4; ++c
) {
4470 if (fpi
->linear
== TRUE
)
4471 lin
[mid
/ 32] |= 1 << (mid
% 32);
4475 map
[mid
] = (c
== 3) ? (zval
+ 1) : zval
;
4487 struct nouveau_stateobj
*
4488 nv50_fp_linkage_validate(struct nv50_context
*nv50
)
4490 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
4491 struct nv50_program
*vp
= nv50
->vertprog
;
4492 struct nv50_program
*fp
= nv50
->fragprog
;
4493 struct nouveau_stateobj
*so
;
4494 struct nv50_sreg4 dummy
;
4496 uint32_t map
[16], lin
[4], reg
[6], pcrd
[8];
4497 uint8_t zval
= 0x40;
4499 if (nv50
->geomprog
) {
4500 vp
= nv50
->geomprog
;
4503 memset(map
, 0, sizeof(map
));
4504 memset(lin
, 0, sizeof(lin
));
4506 reg
[1] = 0x00000004; /* low and high clip distance map ids */
4507 reg
[2] = 0x00000000; /* layer index map id (disabled, GP only) */
4508 reg
[3] = 0x00000000; /* point size map id & enable */
4509 reg
[5] = 0x00000000; /* primitive ID map slot */
4510 reg
[0] = fp
->cfg
.regs
[0]; /* colour semantic reg */
4511 reg
[4] = fp
->cfg
.regs
[1]; /* interpolant info */
4513 dummy
.linear
= FALSE
;
4514 dummy
.mask
= 0xf; /* map all components of HPOS */
4515 m
= nv50_vec4_map(map
, m
, zval
, lin
, &dummy
, &vp
->cfg
.out
[0]);
4519 if (vp
->cfg
.clpd
< 0x40) {
4520 for (c
= 0; c
< vp
->cfg
.clpd_nr
; ++c
) {
4521 map
[m
/ 4] |= (vp
->cfg
.clpd
+ c
) << ((m
% 4) * 8);
4527 reg
[0] |= m
<< 8; /* adjust BFC0 id */
4529 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
4530 if (nv50
->rasterizer
->pipe
.light_twoside
) {
4531 struct nv50_sreg4
*vpo
= &vp
->cfg
.two_side
[0];
4532 struct nv50_sreg4
*fpi
= &fp
->cfg
.two_side
[0];
4534 m
= nv50_vec4_map(map
, m
, zval
, lin
, &fpi
[0], &vpo
[0]);
4535 m
= nv50_vec4_map(map
, m
, zval
, lin
, &fpi
[1], &vpo
[1]);
4538 reg
[0] += m
- 4; /* adjust FFC0 id */
4539 reg
[4] |= m
<< 8; /* set mid where 'normal' FP inputs start */
4541 for (i
= 0; i
< fp
->cfg
.in_nr
; i
++) {
4542 /* maybe even remove these from cfg.io */
4543 if (fp
->cfg
.in
[i
].sn
== TGSI_SEMANTIC_POSITION
||
4544 fp
->cfg
.in
[i
].sn
== TGSI_SEMANTIC_FACE
)
4547 for (n
= 0; n
< vp
->cfg
.out_nr
; ++n
)
4548 if (vp
->cfg
.out
[n
].sn
== fp
->cfg
.in
[i
].sn
&&
4549 vp
->cfg
.out
[n
].si
== fp
->cfg
.in
[i
].si
)
4552 m
= nv50_vec4_map(map
, m
, zval
, lin
, &fp
->cfg
.in
[i
],
4553 (n
< vp
->cfg
.out_nr
) ?
4554 &vp
->cfg
.out
[n
] : &dummy
);
4556 /* PrimitiveID either is replaced by the system value, or
4557 * written by the geometry shader into an output register
4559 if (fp
->cfg
.prim_id
< 0x40) {
4560 map
[m
/ 4] |= vp
->cfg
.prim_id
<< ((m
% 4) * 8);
4564 if (nv50
->rasterizer
->pipe
.point_size_per_vertex
) {
4565 map
[m
/ 4] |= vp
->cfg
.psiz
<< ((m
% 4) * 8);
4566 reg
[3] = (m
++ << 4) | 1;
4569 /* now fill the stateobj (at most 28 so_data) */
4570 so
= so_new(10, 54, 0);
4574 if (vp
->type
== PIPE_SHADER_GEOMETRY
) {
4575 so_method(so
, tesla
, NV50TCL_GP_RESULT_MAP_SIZE
, 1);
4577 so_method(so
, tesla
, NV50TCL_GP_RESULT_MAP(0), n
);
4578 so_datap (so
, map
, n
);
4580 so_method(so
, tesla
, NV50TCL_VP_GP_BUILTIN_ATTR_EN
, 1);
4581 so_data (so
, vp
->cfg
.regs
[0]);
4583 so_method(so
, tesla
, NV50TCL_MAP_SEMANTIC_4
, 1);
4584 so_data (so
, reg
[5]);
4586 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 1);
4588 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP(0), n
);
4589 so_datap (so
, map
, n
);
4592 so_method(so
, tesla
, NV50TCL_MAP_SEMANTIC_0
, 4);
4593 so_datap (so
, reg
, 4);
4595 so_method(so
, tesla
, NV50TCL_FP_INTERPOLANT_CTRL
, 1);
4596 so_data (so
, reg
[4]);
4598 so_method(so
, tesla
, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
4599 so_datap (so
, lin
, 4);
4601 if (nv50
->rasterizer
->pipe
.sprite_coord_enable
) {
4602 so_method(so
, tesla
, NV50TCL_POINT_SPRITE_CTRL
, 1);
4604 nv50_pntc_replace(nv50
, pcrd
, (reg
[4] >> 8) & 0xff));
4606 so_method(so
, tesla
, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
4607 so_datap (so
, pcrd
, 8);
4610 so_method(so
, tesla
, NV50TCL_GP_ENABLE
, 1);
4611 so_data (so
, (vp
->type
== PIPE_SHADER_GEOMETRY
) ? 1 : 0);
4617 construct_vp_gp_mapping(uint32_t *map32
, int m
,
4618 struct nv50_program
*vp
, struct nv50_program
*gp
)
4620 uint8_t *map
= (uint8_t *)map32
;
4623 for (i
= 0; i
< gp
->cfg
.in_nr
; ++i
) {
4624 uint8_t oid
= 0, mv
= 0, mg
= gp
->cfg
.in
[i
].mask
;
4626 for (j
= 0; j
< vp
->cfg
.out_nr
; ++j
) {
4627 if (vp
->cfg
.out
[j
].sn
== gp
->cfg
.in
[i
].sn
&&
4628 vp
->cfg
.out
[j
].si
== gp
->cfg
.in
[i
].si
) {
4629 mv
= vp
->cfg
.out
[j
].mask
;
4630 oid
= vp
->cfg
.out
[j
].hw
;
4635 for (c
= 0; c
< 4; ++c
, mv
>>= 1, mg
>>= 1) {
4640 map
[m
++] = (c
== 3) ? 0x41 : 0x40;
4647 struct nouveau_stateobj
*
4648 nv50_gp_linkage_validate(struct nv50_context
*nv50
)
4650 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
4651 struct nouveau_stateobj
*so
;
4652 struct nv50_program
*vp
= nv50
->vertprog
;
4653 struct nv50_program
*gp
= nv50
->geomprog
;
4659 memset(map
, 0, sizeof(map
));
4661 m
= construct_vp_gp_mapping(map
, m
, vp
, gp
);
4663 so
= so_new(3, 24 - 3, 0);
4665 so_method(so
, tesla
, NV50TCL_VP_GP_BUILTIN_ATTR_EN
, 1);
4666 so_data (so
, vp
->cfg
.regs
[0] | gp
->cfg
.regs
[0]);
4669 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 1);
4673 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP(0), m
);
4674 so_datap (so
, map
, m
);
4680 nv50_program_destroy(struct nv50_context
*nv50
, struct nv50_program
*p
)
4682 while (p
->exec_head
) {
4683 struct nv50_program_exec
*e
= p
->exec_head
;
4685 p
->exec_head
= e
->next
;
4688 p
->exec_tail
= NULL
;
4691 nouveau_bo_ref(NULL
, &p
->bo
);
4694 nouveau_resource_free(&p
->data
[0]);