2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
32 #include "nv50_context.h"
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
40 /* ARL - gallium craps itself on progs/vp/arl.txt
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
93 int rhw
; /* result hw for FP outputs, or interpolant index */
94 int acc
; /* instruction where this reg is last read (first insn == 1) */
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_SAT 4
101 /* arbitrary limits */
102 #define MAX_IF_DEPTH 4
103 #define MAX_LOOP_DEPTH 4
106 struct nv50_program
*p
;
109 struct nv50_reg
*r_temp
[NV50_SU_MAX_TEMP
];
110 struct nv50_reg r_addr
[NV50_SU_MAX_ADDR
];
113 struct nv50_reg
*temp
;
115 struct nv50_reg
*attr
;
117 struct nv50_reg
*result
;
119 struct nv50_reg
*param
;
121 struct nv50_reg
*immd
;
124 struct nv50_reg
**addr
;
127 struct nv50_reg
*temp_temp
[16];
128 unsigned temp_temp_nr
;
130 /* broadcast and destination replacement regs */
131 struct nv50_reg
*r_brdc
;
132 struct nv50_reg
*r_dst
[4];
134 unsigned interp_mode
[32];
135 /* perspective interpolation registers */
136 struct nv50_reg
*iv_p
;
137 struct nv50_reg
*iv_c
;
139 struct nv50_program_exec
*if_cond
;
140 struct nv50_program_exec
*if_insn
[MAX_IF_DEPTH
];
141 struct nv50_program_exec
*br_join
[MAX_IF_DEPTH
];
142 struct nv50_program_exec
*br_loop
[MAX_LOOP_DEPTH
]; /* for BRK branch */
143 int if_lvl
, loop_lvl
;
144 unsigned loop_pos
[MAX_LOOP_DEPTH
];
146 /* current instruction and total number of insns */
154 ctor_reg(struct nv50_reg
*reg
, unsigned type
, int index
, int hw
)
164 static INLINE
unsigned
165 popcnt4(uint32_t val
)
167 static const unsigned cnt
[16]
168 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
169 return cnt
[val
& 0xf];
173 terminate_mbb(struct nv50_pc
*pc
)
177 /* remove records of temporary address register values */
178 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
179 if (pc
->r_addr
[i
].index
< 0)
180 pc
->r_addr
[i
].rhw
= -1;
184 alloc_reg(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
188 if (reg
->type
== P_RESULT
) {
189 if (pc
->p
->cfg
.high_result
< (reg
->hw
+ 1))
190 pc
->p
->cfg
.high_result
= reg
->hw
+ 1;
193 if (reg
->type
!= P_TEMP
)
197 /*XXX: do this here too to catch FP temp-as-attr usage..
198 * not clean, but works */
199 if (pc
->p
->cfg
.high_temp
< (reg
->hw
+ 1))
200 pc
->p
->cfg
.high_temp
= reg
->hw
+ 1;
204 if (reg
->rhw
!= -1) {
205 /* try to allocate temporary with index rhw first */
206 if (!(pc
->r_temp
[reg
->rhw
])) {
207 pc
->r_temp
[reg
->rhw
] = reg
;
209 if (pc
->p
->cfg
.high_temp
< (reg
->rhw
+ 1))
210 pc
->p
->cfg
.high_temp
= reg
->rhw
+ 1;
213 /* make sure we don't get things like $r0 needs to go
214 * in $r1 and $r1 in $r0
216 i
= pc
->result_nr
* 4;
219 for (; i
< NV50_SU_MAX_TEMP
; i
++) {
220 if (!(pc
->r_temp
[i
])) {
223 if (pc
->p
->cfg
.high_temp
< (i
+ 1))
224 pc
->p
->cfg
.high_temp
= i
+ 1;
232 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
233 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
234 * lest we risk temp_temps overwriting regs alloc'd "later".
236 static struct nv50_reg
*
237 alloc_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
)
242 if (dst
&& dst
->type
== P_TEMP
&& dst
->hw
== -1)
245 for (i
= 0; i
< NV50_SU_MAX_TEMP
; i
++) {
246 if (!pc
->r_temp
[i
]) {
247 r
= MALLOC_STRUCT(nv50_reg
);
248 ctor_reg(r
, P_TEMP
, -1, i
);
258 /* Assign the hw of the discarded temporary register src
259 * to the tgsi register dst and free src.
262 assimilate_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
264 assert(src
->index
== -1 && src
->hw
!= -1);
267 pc
->r_temp
[dst
->hw
] = NULL
;
268 pc
->r_temp
[src
->hw
] = dst
;
274 /* release the hardware resource held by r */
276 release_hw(struct nv50_pc
*pc
, struct nv50_reg
*r
)
278 assert(r
->type
== P_TEMP
);
282 assert(pc
->r_temp
[r
->hw
] == r
);
283 pc
->r_temp
[r
->hw
] = NULL
;
291 free_temp(struct nv50_pc
*pc
, struct nv50_reg
*r
)
293 if (r
->index
== -1) {
296 FREE(pc
->r_temp
[hw
]);
297 pc
->r_temp
[hw
] = NULL
;
302 alloc_temp4(struct nv50_pc
*pc
, struct nv50_reg
*dst
[4], int idx
)
306 if ((idx
+ 4) >= NV50_SU_MAX_TEMP
)
309 if (pc
->r_temp
[idx
] || pc
->r_temp
[idx
+ 1] ||
310 pc
->r_temp
[idx
+ 2] || pc
->r_temp
[idx
+ 3])
311 return alloc_temp4(pc
, dst
, idx
+ 4);
313 for (i
= 0; i
< 4; i
++) {
314 dst
[i
] = MALLOC_STRUCT(nv50_reg
);
315 ctor_reg(dst
[i
], P_TEMP
, -1, idx
+ i
);
316 pc
->r_temp
[idx
+ i
] = dst
[i
];
323 free_temp4(struct nv50_pc
*pc
, struct nv50_reg
*reg
[4])
327 for (i
= 0; i
< 4; i
++)
328 free_temp(pc
, reg
[i
]);
331 static struct nv50_reg
*
332 temp_temp(struct nv50_pc
*pc
)
334 if (pc
->temp_temp_nr
>= 16)
337 pc
->temp_temp
[pc
->temp_temp_nr
] = alloc_temp(pc
, NULL
);
338 return pc
->temp_temp
[pc
->temp_temp_nr
++];
342 kill_temp_temp(struct nv50_pc
*pc
)
346 for (i
= 0; i
< pc
->temp_temp_nr
; i
++)
347 free_temp(pc
, pc
->temp_temp
[i
]);
348 pc
->temp_temp_nr
= 0;
352 ctor_immd(struct nv50_pc
*pc
, float x
, float y
, float z
, float w
)
354 pc
->immd_buf
= REALLOC(pc
->immd_buf
, (pc
->immd_nr
* 4 * sizeof(float)),
355 (pc
->immd_nr
+ 1) * 4 * sizeof(float));
356 pc
->immd_buf
[(pc
->immd_nr
* 4) + 0] = x
;
357 pc
->immd_buf
[(pc
->immd_nr
* 4) + 1] = y
;
358 pc
->immd_buf
[(pc
->immd_nr
* 4) + 2] = z
;
359 pc
->immd_buf
[(pc
->immd_nr
* 4) + 3] = w
;
361 return pc
->immd_nr
++;
364 static struct nv50_reg
*
365 alloc_immd(struct nv50_pc
*pc
, float f
)
367 struct nv50_reg
*r
= MALLOC_STRUCT(nv50_reg
);
370 for (hw
= 0; hw
< pc
->immd_nr
* 4; hw
++)
371 if (pc
->immd_buf
[hw
] == f
)
374 if (hw
== pc
->immd_nr
* 4)
375 hw
= ctor_immd(pc
, f
, -f
, 0.5 * f
, 0) * 4;
377 ctor_reg(r
, P_IMMD
, -1, hw
);
381 static struct nv50_program_exec
*
382 exec(struct nv50_pc
*pc
)
384 struct nv50_program_exec
*e
= CALLOC_STRUCT(nv50_program_exec
);
391 emit(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
393 struct nv50_program
*p
= pc
->p
;
396 p
->exec_tail
->next
= e
;
400 p
->exec_size
+= (e
->inst
[0] & 1) ? 2 : 1;
403 static INLINE
void set_long(struct nv50_pc
*, struct nv50_program_exec
*);
406 is_long(struct nv50_program_exec
*e
)
414 is_immd(struct nv50_program_exec
*e
)
416 if (is_long(e
) && (e
->inst
[1] & 3) == 3)
422 set_pred(struct nv50_pc
*pc
, unsigned pred
, unsigned idx
,
423 struct nv50_program_exec
*e
)
426 e
->inst
[1] &= ~((0x1f << 7) | (0x3 << 12));
427 e
->inst
[1] |= (pred
<< 7) | (idx
<< 12);
431 set_pred_wr(struct nv50_pc
*pc
, unsigned on
, unsigned idx
,
432 struct nv50_program_exec
*e
)
435 e
->inst
[1] &= ~((0x3 << 4) | (1 << 6));
436 e
->inst
[1] |= (idx
<< 4) | (on
<< 6);
440 set_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
446 set_pred(pc
, 0xf, 0, e
);
447 set_pred_wr(pc
, 0, 0, e
);
451 set_dst(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_program_exec
*e
)
453 if (dst
->type
== P_RESULT
) {
455 e
->inst
[1] |= 0x00000008;
461 e
->inst
[0] |= (dst
->hw
<< 2);
465 set_immd(struct nv50_pc
*pc
, struct nv50_reg
*imm
, struct nv50_program_exec
*e
)
468 float f
= pc
->immd_buf
[imm
->hw
];
470 if (imm
->mod
& NV50_MOD_ABS
)
472 val
= fui((imm
->mod
& NV50_MOD_NEG
) ? -f
: f
);
475 /*XXX: can't be predicated - bits overlap.. catch cases where both
476 * are required and avoid them. */
477 set_pred(pc
, 0, 0, e
);
478 set_pred_wr(pc
, 0, 0, e
);
480 e
->inst
[1] |= 0x00000002 | 0x00000001;
481 e
->inst
[0] |= (val
& 0x3f) << 16;
482 e
->inst
[1] |= (val
>> 6) << 2;
486 set_addr(struct nv50_program_exec
*e
, struct nv50_reg
*a
)
488 assert(!(e
->inst
[0] & 0x0c000000));
489 assert(!(e
->inst
[1] & 0x00000004));
491 e
->inst
[0] |= (a
->hw
& 3) << 26;
492 e
->inst
[1] |= (a
->hw
>> 2) << 2;
496 emit_add_addr_imm(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
497 struct nv50_reg
*src0
, uint16_t src1_val
)
499 struct nv50_program_exec
*e
= exec(pc
);
501 e
->inst
[0] = 0xd0000000 | (src1_val
<< 9);
502 e
->inst
[1] = 0x20000000;
504 e
->inst
[0] |= dst
->hw
<< 2;
505 if (src0
) /* otherwise will add to $a0, which is always 0 */
511 static struct nv50_reg
*
512 alloc_addr(struct nv50_pc
*pc
, struct nv50_reg
*ref
)
515 struct nv50_reg
*a_tgsi
= NULL
, *a
= NULL
;
518 /* allocate for TGSI address reg */
519 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
) {
520 if (pc
->r_addr
[i
].index
>= 0)
522 if (pc
->r_addr
[i
].rhw
>= 0 &&
523 pc
->r_addr
[i
].acc
== pc
->insn_cur
)
526 pc
->r_addr
[i
].rhw
= -1;
527 pc
->r_addr
[i
].index
= i
;
528 return &pc
->r_addr
[i
];
534 /* Allocate and set an address reg so we can access 'ref'.
536 * If and r_addr has index < 0, it is not reserved for TGSI,
537 * and index will be the negative of the TGSI addr index the
538 * value in rhw is relative to, or -256 if rhw is an offset
539 * from 0. If rhw < 0, the reg has not been initialized.
541 for (i
= NV50_SU_MAX_ADDR
- 1; i
>= 0; --i
) {
542 if (pc
->r_addr
[i
].index
>= 0) /* occupied for TGSI */
544 if (pc
->r_addr
[i
].rhw
< 0) { /* unused */
548 if (!a
&& pc
->r_addr
[i
].acc
!= pc
->insn_cur
)
551 if (ref
->hw
- pc
->r_addr
[i
].rhw
>= 128)
554 if ((ref
->acc
>= 0 && pc
->r_addr
[i
].index
== -256) ||
555 (ref
->acc
< 0 && -pc
->r_addr
[i
].index
== ref
->index
)) {
556 pc
->r_addr
[i
].acc
= pc
->insn_cur
;
557 return &pc
->r_addr
[i
];
563 a_tgsi
= pc
->addr
[ref
->index
];
565 emit_add_addr_imm(pc
, a
, a_tgsi
, (ref
->hw
& ~0x7f) * 4);
567 a
->rhw
= ref
->hw
& ~0x7f;
568 a
->acc
= pc
->insn_cur
;
569 a
->index
= a_tgsi
? -ref
->index
: -256;
573 #define INTERP_LINEAR 0
574 #define INTERP_FLAT 1
575 #define INTERP_PERSPECTIVE 2
576 #define INTERP_CENTROID 4
578 /* interpolant index has been stored in dst->rhw */
580 emit_interp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*iv
,
583 assert(dst
->rhw
!= -1);
584 struct nv50_program_exec
*e
= exec(pc
);
586 e
->inst
[0] |= 0x80000000;
588 e
->inst
[0] |= (dst
->rhw
<< 16);
590 if (mode
& INTERP_FLAT
) {
591 e
->inst
[0] |= (1 << 8);
593 if (mode
& INTERP_PERSPECTIVE
) {
594 e
->inst
[0] |= (1 << 25);
596 e
->inst
[0] |= (iv
->hw
<< 9);
599 if (mode
& INTERP_CENTROID
)
600 e
->inst
[0] |= (1 << 24);
607 set_data(struct nv50_pc
*pc
, struct nv50_reg
*src
, unsigned m
, unsigned s
,
608 struct nv50_program_exec
*e
)
612 e
->param
.index
= src
->hw
& 127;
614 e
->param
.mask
= m
<< (s
% 32);
617 set_addr(e
, alloc_addr(pc
, src
));
620 assert(src
->type
== P_CONST
);
621 set_addr(e
, pc
->addr
[src
->index
]);
624 e
->inst
[1] |= (((src
->type
== P_IMMD
) ? 0 : 1) << 22);
628 emit_mov(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
630 struct nv50_program_exec
*e
= exec(pc
);
632 e
->inst
[0] = 0x10000000;
638 if (!is_long(e
) && src
->type
== P_IMMD
) {
639 set_immd(pc
, src
, e
);
640 /*XXX: 32-bit, but steals part of "half" reg space - need to
641 * catch and handle this case if/when we do half-regs
644 if (src
->type
== P_IMMD
|| src
->type
== P_CONST
) {
646 set_data(pc
, src
, 0x7f, 9, e
);
647 e
->inst
[1] |= 0x20000000; /* src0 const? */
649 if (src
->type
== P_ATTR
) {
651 e
->inst
[1] |= 0x00200000;
657 e
->inst
[0] |= (src
->hw
<< 9);
660 if (is_long(e
) && !is_immd(e
)) {
661 e
->inst
[1] |= 0x04000000; /* 32-bit */
662 e
->inst
[1] |= 0x0000c000; /* "subsubop" 0x3 */
663 if (!(e
->inst
[1] & 0x20000000))
664 e
->inst
[1] |= 0x00030000; /* "subsubop" 0xf */
666 e
->inst
[0] |= 0x00008000;
672 emit_mov_immdval(struct nv50_pc
*pc
, struct nv50_reg
*dst
, float f
)
674 struct nv50_reg
*imm
= alloc_immd(pc
, f
);
675 emit_mov(pc
, dst
, imm
);
680 check_swap_src_0_1(struct nv50_pc
*pc
,
681 struct nv50_reg
**s0
, struct nv50_reg
**s1
)
683 struct nv50_reg
*src0
= *s0
, *src1
= *s1
;
685 if (src0
->type
== P_CONST
) {
686 if (src1
->type
!= P_CONST
) {
692 if (src1
->type
== P_ATTR
) {
693 if (src0
->type
!= P_ATTR
) {
704 set_src_0_restricted(struct nv50_pc
*pc
, struct nv50_reg
*src
,
705 struct nv50_program_exec
*e
)
707 struct nv50_reg
*temp
;
709 if (src
->type
!= P_TEMP
) {
710 temp
= temp_temp(pc
);
711 emit_mov(pc
, temp
, src
);
718 e
->inst
[0] |= (src
->hw
<< 9);
722 set_src_0(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
724 if (src
->type
== P_ATTR
) {
726 e
->inst
[1] |= 0x00200000;
728 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
729 struct nv50_reg
*temp
= temp_temp(pc
);
731 emit_mov(pc
, temp
, src
);
738 e
->inst
[0] |= (src
->hw
<< 9);
742 set_src_1(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
744 if (src
->type
== P_ATTR
) {
745 struct nv50_reg
*temp
= temp_temp(pc
);
747 emit_mov(pc
, temp
, src
);
750 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
751 assert(!(e
->inst
[0] & 0x00800000));
752 if (e
->inst
[0] & 0x01000000) {
753 struct nv50_reg
*temp
= temp_temp(pc
);
755 emit_mov(pc
, temp
, src
);
758 set_data(pc
, src
, 0x7f, 16, e
);
759 e
->inst
[0] |= 0x00800000;
766 e
->inst
[0] |= ((src
->hw
& 127) << 16);
770 set_src_2(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
774 if (src
->type
== P_ATTR
) {
775 struct nv50_reg
*temp
= temp_temp(pc
);
777 emit_mov(pc
, temp
, src
);
780 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
781 assert(!(e
->inst
[0] & 0x01000000));
782 if (e
->inst
[0] & 0x00800000) {
783 struct nv50_reg
*temp
= temp_temp(pc
);
785 emit_mov(pc
, temp
, src
);
788 set_data(pc
, src
, 0x7f, 32+14, e
);
789 e
->inst
[0] |= 0x01000000;
794 e
->inst
[1] |= ((src
->hw
& 127) << 14);
798 emit_mul(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
799 struct nv50_reg
*src1
)
801 struct nv50_program_exec
*e
= exec(pc
);
803 e
->inst
[0] |= 0xc0000000;
808 check_swap_src_0_1(pc
, &src0
, &src1
);
810 set_src_0(pc
, src0
, e
);
811 if (src1
->type
== P_IMMD
&& !is_long(e
)) {
812 if (src0
->mod
& NV50_MOD_NEG
)
813 e
->inst
[0] |= 0x00008000;
814 set_immd(pc
, src1
, e
);
816 set_src_1(pc
, src1
, e
);
817 if ((src0
->mod
^ src1
->mod
) & NV50_MOD_NEG
) {
819 e
->inst
[1] |= 0x08000000;
821 e
->inst
[0] |= 0x00008000;
829 emit_add(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
830 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
832 struct nv50_program_exec
*e
= exec(pc
);
834 e
->inst
[0] = 0xb0000000;
837 check_swap_src_0_1(pc
, &src0
, &src1
);
839 if (!pc
->allow32
|| (src0
->mod
| src1
->mod
) || src1
->hw
> 63) {
841 e
->inst
[1] |= ((src0
->mod
& NV50_MOD_NEG
) << 26) |
842 ((src1
->mod
& NV50_MOD_NEG
) << 27);
846 set_src_0(pc
, src0
, e
);
847 if (src1
->type
== P_CONST
|| src1
->type
== P_ATTR
|| is_long(e
))
848 set_src_2(pc
, src1
, e
);
850 if (src1
->type
== P_IMMD
)
851 set_immd(pc
, src1
, e
);
853 set_src_1(pc
, src1
, e
);
859 emit_arl(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
862 struct nv50_program_exec
*e
= exec(pc
);
865 e
->inst
[1] |= 0xc0000000;
867 e
->inst
[0] |= dst
->hw
<< 2;
868 e
->inst
[0] |= s
<< 16; /* shift left */
869 set_src_0_restricted(pc
, src
, e
);
875 emit_minmax(struct nv50_pc
*pc
, unsigned sub
, struct nv50_reg
*dst
,
876 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
878 struct nv50_program_exec
*e
= exec(pc
);
881 e
->inst
[0] |= 0xb0000000;
882 e
->inst
[1] |= (sub
<< 29);
884 check_swap_src_0_1(pc
, &src0
, &src1
);
886 set_src_0(pc
, src0
, e
);
887 set_src_1(pc
, src1
, e
);
889 if (src0
->mod
& NV50_MOD_ABS
)
890 e
->inst
[1] |= 0x00100000;
891 if (src1
->mod
& NV50_MOD_ABS
)
892 e
->inst
[1] |= 0x00080000;
898 emit_sub(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
899 struct nv50_reg
*src1
)
901 assert(src0
!= src1
);
902 src1
->mod
^= NV50_MOD_NEG
;
903 emit_add(pc
, dst
, src0
, src1
);
904 src1
->mod
^= NV50_MOD_NEG
;
908 emit_bitop2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
909 struct nv50_reg
*src1
, unsigned op
)
911 struct nv50_program_exec
*e
= exec(pc
);
913 e
->inst
[0] = 0xd0000000;
916 check_swap_src_0_1(pc
, &src0
, &src1
);
918 set_src_0(pc
, src0
, e
);
920 if (op
!= TGSI_OPCODE_AND
&& op
!= TGSI_OPCODE_OR
&&
921 op
!= TGSI_OPCODE_XOR
)
922 assert(!"invalid bit op");
924 if (src1
->type
== P_IMMD
&& src0
->type
== P_TEMP
&& pc
->allow32
) {
925 set_immd(pc
, src1
, e
);
926 if (op
== TGSI_OPCODE_OR
)
927 e
->inst
[0] |= 0x0100;
929 if (op
== TGSI_OPCODE_XOR
)
930 e
->inst
[0] |= 0x8000;
932 set_src_1(pc
, src1
, e
);
933 e
->inst
[1] |= 0x04000000; /* 32 bit */
934 if (op
== TGSI_OPCODE_OR
)
935 e
->inst
[1] |= 0x4000;
937 if (op
== TGSI_OPCODE_XOR
)
938 e
->inst
[1] |= 0x8000;
945 emit_mad(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
946 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
948 struct nv50_program_exec
*e
= exec(pc
);
950 e
->inst
[0] |= 0xe0000000;
952 check_swap_src_0_1(pc
, &src0
, &src1
);
954 set_src_0(pc
, src0
, e
);
955 set_src_1(pc
, src1
, e
);
956 set_src_2(pc
, src2
, e
);
958 if ((src0
->mod
^ src1
->mod
) & NV50_MOD_NEG
)
959 e
->inst
[1] |= 0x04000000;
960 if (src2
->mod
& NV50_MOD_NEG
)
961 e
->inst
[1] |= 0x08000000;
967 emit_msb(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
968 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
970 assert(src2
!= src0
&& src2
!= src1
);
971 src2
->mod
^= NV50_MOD_NEG
;
972 emit_mad(pc
, dst
, src0
, src1
, src2
);
973 src2
->mod
^= NV50_MOD_NEG
;
977 emit_flop(struct nv50_pc
*pc
, unsigned sub
,
978 struct nv50_reg
*dst
, struct nv50_reg
*src
)
980 struct nv50_program_exec
*e
= exec(pc
);
982 e
->inst
[0] |= 0x90000000;
985 e
->inst
[1] |= (sub
<< 29);
990 if (sub
== 0 || sub
== 2)
991 set_src_0_restricted(pc
, src
, e
);
993 set_src_0(pc
, src
, e
);
999 emit_preex2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1001 struct nv50_program_exec
*e
= exec(pc
);
1003 e
->inst
[0] |= 0xb0000000;
1005 set_dst(pc
, dst
, e
);
1006 set_src_0(pc
, src
, e
);
1008 e
->inst
[1] |= (6 << 29) | 0x00004000;
1014 emit_precossin(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1016 struct nv50_program_exec
*e
= exec(pc
);
1018 e
->inst
[0] |= 0xb0000000;
1020 set_dst(pc
, dst
, e
);
1021 set_src_0(pc
, src
, e
);
1023 e
->inst
[1] |= (6 << 29);
1028 #define CVTOP_RN 0x01
1029 #define CVTOP_FLOOR 0x03
1030 #define CVTOP_CEIL 0x05
1031 #define CVTOP_TRUNC 0x07
1032 #define CVTOP_SAT 0x08
1033 #define CVTOP_ABS 0x10
1035 /* 0x04 == 32 bit dst */
1036 /* 0x40 == dst is float */
1037 /* 0x80 == src is float */
1038 #define CVT_F32_F32 0xc4
1039 #define CVT_F32_S32 0x44
1040 #define CVT_S32_F32 0x8c
1041 #define CVT_S32_S32 0x0c
1042 #define CVT_NEG 0x20
1046 emit_cvt(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
1047 int wp
, unsigned cvn
, unsigned fmt
)
1049 struct nv50_program_exec
*e
;
1054 e
->inst
[0] |= 0xa0000000;
1055 e
->inst
[1] |= 0x00004000; /* 32 bit src */
1056 e
->inst
[1] |= (cvn
<< 16);
1057 e
->inst
[1] |= (fmt
<< 24);
1058 set_src_0(pc
, src
, e
);
1061 set_pred_wr(pc
, 1, wp
, e
);
1064 set_dst(pc
, dst
, e
);
1066 e
->inst
[0] |= 0x000001fc;
1067 e
->inst
[1] |= 0x00000008;
1073 /* nv50 Condition codes:
1080 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1081 * 0x8 = unordered bit (allows NaN)
1084 emit_set(struct nv50_pc
*pc
, unsigned ccode
, struct nv50_reg
*dst
, int wp
,
1085 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
1087 static const unsigned cc_swapped
[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1089 struct nv50_program_exec
*e
= exec(pc
);
1090 struct nv50_reg
*rdst
;
1093 if (check_swap_src_0_1(pc
, &src0
, &src1
))
1094 ccode
= cc_swapped
[ccode
& 7] | (ccode
& 8);
1097 if (dst
&& dst
->type
!= P_TEMP
)
1098 dst
= alloc_temp(pc
, NULL
);
1102 e
->inst
[0] |= 0xb0000000;
1103 e
->inst
[1] |= 0x60000000 | (ccode
<< 14);
1105 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1106 * that doesn't seem to match what the hw actually does
1107 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1111 set_pred_wr(pc
, 1, wp
, e
);
1113 set_dst(pc
, dst
, e
);
1115 e
->inst
[0] |= 0x000001fc;
1116 e
->inst
[1] |= 0x00000008;
1119 set_src_0(pc
, src0
, e
);
1120 set_src_1(pc
, src1
, e
);
1123 pc
->if_cond
= pc
->p
->exec_tail
; /* record for OPCODE_IF */
1125 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1127 emit_cvt(pc
, rdst
, dst
, -1, CVTOP_ABS
| CVTOP_RN
, CVT_F32_S32
);
1128 if (rdst
&& rdst
!= dst
)
1132 static INLINE
unsigned
1133 map_tgsi_setop_cc(unsigned op
)
1136 case TGSI_OPCODE_SLT
: return 0x1;
1137 case TGSI_OPCODE_SGE
: return 0x6;
1138 case TGSI_OPCODE_SEQ
: return 0x2;
1139 case TGSI_OPCODE_SGT
: return 0x4;
1140 case TGSI_OPCODE_SLE
: return 0x3;
1141 case TGSI_OPCODE_SNE
: return 0xd;
1149 emit_flr(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1151 emit_cvt(pc
, dst
, src
, -1, CVTOP_FLOOR
, CVT_F32_F32
| CVT_RI
);
1155 emit_pow(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1156 struct nv50_reg
*v
, struct nv50_reg
*e
)
1158 struct nv50_reg
*temp
= alloc_temp(pc
, NULL
);
1160 emit_flop(pc
, 3, temp
, v
);
1161 emit_mul(pc
, temp
, temp
, e
);
1162 emit_preex2(pc
, temp
, temp
);
1163 emit_flop(pc
, 6, dst
, temp
);
1165 free_temp(pc
, temp
);
1169 emit_abs(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1171 emit_cvt(pc
, dst
, src
, -1, CVTOP_ABS
, CVT_F32_F32
);
1175 emit_sat(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1177 emit_cvt(pc
, dst
, src
, -1, CVTOP_SAT
, CVT_F32_F32
);
1181 emit_lit(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1182 struct nv50_reg
**src
)
1184 struct nv50_reg
*one
= alloc_immd(pc
, 1.0);
1185 struct nv50_reg
*zero
= alloc_immd(pc
, 0.0);
1186 struct nv50_reg
*neg128
= alloc_immd(pc
, -127.999999);
1187 struct nv50_reg
*pos128
= alloc_immd(pc
, 127.999999);
1188 struct nv50_reg
*tmp
[4];
1189 boolean allow32
= pc
->allow32
;
1191 pc
->allow32
= FALSE
;
1193 if (mask
& (3 << 1)) {
1194 tmp
[0] = alloc_temp(pc
, NULL
);
1195 emit_minmax(pc
, 4, tmp
[0], src
[0], zero
);
1198 if (mask
& (1 << 2)) {
1199 set_pred_wr(pc
, 1, 0, pc
->p
->exec_tail
);
1201 tmp
[1] = temp_temp(pc
);
1202 emit_minmax(pc
, 4, tmp
[1], src
[1], zero
);
1204 tmp
[3] = temp_temp(pc
);
1205 emit_minmax(pc
, 4, tmp
[3], src
[3], neg128
);
1206 emit_minmax(pc
, 5, tmp
[3], tmp
[3], pos128
);
1208 emit_pow(pc
, dst
[2], tmp
[1], tmp
[3]);
1209 emit_mov(pc
, dst
[2], zero
);
1210 set_pred(pc
, 3, 0, pc
->p
->exec_tail
);
1213 if (mask
& (1 << 1))
1214 assimilate_temp(pc
, dst
[1], tmp
[0]);
1216 if (mask
& (1 << 2))
1217 free_temp(pc
, tmp
[0]);
1219 pc
->allow32
= allow32
;
1221 /* do this last, in case src[i,j] == dst[0,3] */
1222 if (mask
& (1 << 0))
1223 emit_mov(pc
, dst
[0], one
);
1225 if (mask
& (1 << 3))
1226 emit_mov(pc
, dst
[3], one
);
1235 emit_neg(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1237 emit_cvt(pc
, dst
, src
, -1, CVTOP_RN
, CVT_F32_F32
| CVT_NEG
);
1241 emit_kil(struct nv50_pc
*pc
, struct nv50_reg
*src
)
1243 struct nv50_program_exec
*e
;
1244 const int r_pred
= 1;
1245 unsigned cvn
= CVT_F32_F32
;
1247 if (src
->mod
& NV50_MOD_NEG
)
1249 /* write predicate reg */
1250 emit_cvt(pc
, NULL
, src
, r_pred
, CVTOP_RN
, cvn
);
1252 /* conditional discard */
1254 e
->inst
[0] = 0x00000002;
1256 set_pred(pc
, 0x1 /* LT */, r_pred
, e
);
1261 load_cube_tex_coords(struct nv50_pc
*pc
, struct nv50_reg
*t
[4],
1262 struct nv50_reg
**src
, boolean proj
)
1264 int mod
[3] = { src
[0]->mod
, src
[1]->mod
, src
[2]->mod
};
1266 src
[0]->mod
|= NV50_MOD_ABS
;
1267 src
[1]->mod
|= NV50_MOD_ABS
;
1268 src
[2]->mod
|= NV50_MOD_ABS
;
1270 emit_minmax(pc
, 4, t
[2], src
[0], src
[1]);
1271 emit_minmax(pc
, 4, t
[2], src
[2], t
[2]);
1273 src
[0]->mod
= mod
[0];
1274 src
[1]->mod
= mod
[1];
1275 src
[2]->mod
= mod
[2];
1277 if (proj
&& 0 /* looks more correct without this */)
1278 emit_mul(pc
, t
[2], t
[2], src
[3]);
1279 emit_flop(pc
, 0, t
[2], t
[2]);
1281 emit_mul(pc
, t
[0], src
[0], t
[2]);
1282 emit_mul(pc
, t
[1], src
[1], t
[2]);
1283 emit_mul(pc
, t
[2], src
[2], t
[2]);
1287 emit_tex(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1288 struct nv50_reg
**src
, unsigned unit
, unsigned type
, boolean proj
)
1290 struct nv50_reg
*t
[4];
1291 struct nv50_program_exec
*e
;
1293 unsigned c
, mode
, dim
;
1296 case TGSI_TEXTURE_1D
:
1299 case TGSI_TEXTURE_UNKNOWN
:
1300 case TGSI_TEXTURE_2D
:
1301 case TGSI_TEXTURE_SHADOW1D
: /* XXX: x, z */
1302 case TGSI_TEXTURE_RECT
:
1305 case TGSI_TEXTURE_3D
:
1306 case TGSI_TEXTURE_CUBE
:
1307 case TGSI_TEXTURE_SHADOW2D
:
1308 case TGSI_TEXTURE_SHADOWRECT
: /* XXX */
1316 /* some cards need t[0]'s hw index to be a multiple of 4 */
1317 alloc_temp4(pc
, t
, 0);
1319 if (type
== TGSI_TEXTURE_CUBE
) {
1320 load_cube_tex_coords(pc
, t
, src
, proj
);
1323 if (src
[0]->type
== P_TEMP
&& src
[0]->rhw
!= -1) {
1324 mode
= pc
->interp_mode
[src
[0]->index
];
1326 t
[3]->rhw
= src
[3]->rhw
;
1327 emit_interp(pc
, t
[3], NULL
, (mode
& INTERP_CENTROID
));
1328 emit_flop(pc
, 0, t
[3], t
[3]);
1330 for (c
= 0; c
< dim
; c
++) {
1331 t
[c
]->rhw
= src
[c
]->rhw
;
1332 emit_interp(pc
, t
[c
], t
[3],
1333 (mode
| INTERP_PERSPECTIVE
));
1336 emit_flop(pc
, 0, t
[3], src
[3]);
1337 for (c
= 0; c
< dim
; c
++)
1338 emit_mul(pc
, t
[c
], src
[c
], t
[3]);
1340 /* XXX: for some reason the blob sometimes uses MAD:
1341 * emit_mad(pc, t[c], src[0][c], t[3], t[3])
1342 * pc->p->exec_tail->inst[1] |= 0x080fc000;
1346 for (c
= 0; c
< dim
; c
++)
1347 emit_mov(pc
, t
[c
], src
[c
]);
1352 e
->inst
[0] |= 0xf0000000;
1353 e
->inst
[1] |= 0x00000004;
1354 set_dst(pc
, t
[0], e
);
1355 e
->inst
[0] |= (unit
<< 9);
1358 e
->inst
[0] |= 0x00400000;
1361 e
->inst
[0] |= 0x00800000;
1362 if (type
== TGSI_TEXTURE_CUBE
)
1363 e
->inst
[0] |= 0x08000000;
1366 e
->inst
[0] |= (mask
& 0x3) << 25;
1367 e
->inst
[1] |= (mask
& 0xc) << 12;
1372 if (mask
& 1) emit_mov(pc
, dst
[0], t
[c
++]);
1373 if (mask
& 2) emit_mov(pc
, dst
[1], t
[c
++]);
1374 if (mask
& 4) emit_mov(pc
, dst
[2], t
[c
++]);
1375 if (mask
& 8) emit_mov(pc
, dst
[3], t
[c
]);
1379 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1380 * the texture coordinates, not the fetched values: latency ? */
1382 for (c
= 0; c
< 4; c
++) {
1383 if (mask
& (1 << c
))
1384 assimilate_temp(pc
, dst
[c
], t
[c
]);
1386 free_temp(pc
, t
[c
]);
1392 emit_branch(struct nv50_pc
*pc
, int pred
, unsigned cc
,
1393 struct nv50_program_exec
**join
)
1395 struct nv50_program_exec
*e
= exec(pc
);
1399 e
->inst
[0] |= 0xa0000002;
1406 e
->inst
[0] |= 0x10000002;
1408 set_pred(pc
, cc
, pred
, e
);
1413 emit_nop(struct nv50_pc
*pc
)
1415 struct nv50_program_exec
*e
= exec(pc
);
1417 e
->inst
[0] = 0xf0000000;
1419 e
->inst
[1] = 0xe0000000;
1424 emit_ddx(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1426 struct nv50_program_exec
*e
= exec(pc
);
1428 assert(src
->type
== P_TEMP
);
1430 e
->inst
[0] = 0xc0140000;
1431 e
->inst
[1] = 0x89800000;
1433 set_dst(pc
, dst
, e
);
1434 set_src_0(pc
, src
, e
);
1435 set_src_2(pc
, src
, e
);
1441 emit_ddy(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1443 struct nv50_program_exec
*e
= exec(pc
);
1445 assert(src
->type
== P_TEMP
);
1447 if (!(src
->mod
& NV50_MOD_NEG
)) /* ! double negation */
1448 emit_neg(pc
, src
, src
);
1450 e
->inst
[0] = 0xc0150000;
1451 e
->inst
[1] = 0x8a400000;
1453 set_dst(pc
, dst
, e
);
1454 set_src_0(pc
, src
, e
);
1455 set_src_2(pc
, src
, e
);
1461 convert_to_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
1463 unsigned q
= 0, m
= ~0;
1465 assert(!is_long(e
));
1467 switch (e
->inst
[0] >> 28) {
1474 /* INTERP (move centroid, perspective and flat bits) */
1476 q
= (e
->inst
[0] & (3 << 24)) >> (24 - 16);
1477 q
|= (e
->inst
[0] & (1 << 8)) << (18 - 8);
1485 q
= ((e
->inst
[0] & (~m
)) >> 2);
1490 q
= ((e
->inst
[0] & (~m
)) << 12);
1493 /* MAD (if src2 == dst) */
1494 q
= ((e
->inst
[0] & 0x1fc) << 12);
1508 /* Some operations support an optional negation flag. */
1510 negate_supported(const struct tgsi_full_instruction
*insn
, int i
)
1514 switch (insn
->Instruction
.Opcode
) {
1515 case TGSI_OPCODE_DDY
:
1516 case TGSI_OPCODE_DP3
:
1517 case TGSI_OPCODE_DP4
:
1518 case TGSI_OPCODE_MUL
:
1519 case TGSI_OPCODE_KIL
:
1520 case TGSI_OPCODE_ADD
:
1521 case TGSI_OPCODE_SUB
:
1522 case TGSI_OPCODE_MAD
:
1524 case TGSI_OPCODE_POW
:
1532 /* Watch out for possible multiple uses of an nv50_reg, we
1533 * can't use nv50_reg::neg in these cases.
1535 for (s
= 0; s
< insn
->Instruction
.NumSrcRegs
; ++s
) {
1538 if ((insn
->FullSrcRegisters
[s
].SrcRegister
.Index
==
1539 insn
->FullSrcRegisters
[i
].SrcRegister
.Index
) &&
1540 (insn
->FullSrcRegisters
[s
].SrcRegister
.File
==
1541 insn
->FullSrcRegisters
[i
].SrcRegister
.File
))
1548 /* Return a read mask for source registers deduced from opcode & write mask. */
1550 nv50_tgsi_src_mask(const struct tgsi_full_instruction
*insn
, int c
)
1552 unsigned x
, mask
= insn
->FullDstRegisters
[0].DstRegister
.WriteMask
;
1554 switch (insn
->Instruction
.Opcode
) {
1555 case TGSI_OPCODE_COS
:
1556 case TGSI_OPCODE_SIN
:
1557 return (mask
& 0x8) | ((mask
& 0x7) ? 0x1 : 0x0);
1558 case TGSI_OPCODE_DP3
:
1560 case TGSI_OPCODE_DP4
:
1561 case TGSI_OPCODE_DPH
:
1562 case TGSI_OPCODE_KIL
: /* WriteMask ignored */
1564 case TGSI_OPCODE_DST
:
1565 return mask
& (c
? 0xa : 0x6);
1566 case TGSI_OPCODE_EX2
:
1567 case TGSI_OPCODE_LG2
:
1568 case TGSI_OPCODE_POW
:
1569 case TGSI_OPCODE_RCP
:
1570 case TGSI_OPCODE_RSQ
:
1571 case TGSI_OPCODE_SCS
:
1573 case TGSI_OPCODE_LIT
:
1575 case TGSI_OPCODE_TEX
:
1576 case TGSI_OPCODE_TXP
:
1578 const struct tgsi_instruction_ext_texture
*tex
;
1580 assert(insn
->Instruction
.Extended
);
1581 tex
= &insn
->InstructionExtTexture
;
1584 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_TXP
)
1587 switch (tex
->Texture
) {
1588 case TGSI_TEXTURE_1D
:
1591 case TGSI_TEXTURE_2D
:
1599 case TGSI_OPCODE_XPD
:
1601 if (mask
& 1) x
|= 0x6;
1602 if (mask
& 2) x
|= 0x5;
1603 if (mask
& 4) x
|= 0x3;
1612 static struct nv50_reg
*
1613 tgsi_dst(struct nv50_pc
*pc
, int c
, const struct tgsi_full_dst_register
*dst
)
1615 switch (dst
->DstRegister
.File
) {
1616 case TGSI_FILE_TEMPORARY
:
1617 return &pc
->temp
[dst
->DstRegister
.Index
* 4 + c
];
1618 case TGSI_FILE_OUTPUT
:
1619 return &pc
->result
[dst
->DstRegister
.Index
* 4 + c
];
1620 case TGSI_FILE_ADDRESS
:
1622 struct nv50_reg
*r
= pc
->addr
[dst
->DstRegister
.Index
* 4 + c
];
1624 r
= alloc_addr(pc
, NULL
);
1625 pc
->addr
[dst
->DstRegister
.Index
* 4 + c
] = r
;
1630 case TGSI_FILE_NULL
:
1639 static struct nv50_reg
*
1640 tgsi_src(struct nv50_pc
*pc
, int chan
, const struct tgsi_full_src_register
*src
,
1643 struct nv50_reg
*r
= NULL
;
1644 struct nv50_reg
*temp
;
1645 unsigned sgn
, c
, swz
;
1647 if (src
->SrcRegister
.File
!= TGSI_FILE_CONSTANT
)
1648 assert(!src
->SrcRegister
.Indirect
);
1650 sgn
= tgsi_util_get_full_src_register_sign_mode(src
, chan
);
1652 c
= tgsi_util_get_full_src_register_swizzle(src
, chan
);
1654 case TGSI_SWIZZLE_X
:
1655 case TGSI_SWIZZLE_Y
:
1656 case TGSI_SWIZZLE_Z
:
1657 case TGSI_SWIZZLE_W
:
1658 switch (src
->SrcRegister
.File
) {
1659 case TGSI_FILE_INPUT
:
1660 r
= &pc
->attr
[src
->SrcRegister
.Index
* 4 + c
];
1662 case TGSI_FILE_TEMPORARY
:
1663 r
= &pc
->temp
[src
->SrcRegister
.Index
* 4 + c
];
1665 case TGSI_FILE_CONSTANT
:
1666 if (!src
->SrcRegister
.Indirect
) {
1667 r
= &pc
->param
[src
->SrcRegister
.Index
* 4 + c
];
1670 /* Indicate indirection by setting r->acc < 0 and
1671 * use the index field to select the address reg.
1673 r
= MALLOC_STRUCT(nv50_reg
);
1674 swz
= tgsi_util_get_src_register_swizzle(
1675 &src
->SrcRegisterInd
, 0);
1676 ctor_reg(r
, P_CONST
,
1677 src
->SrcRegisterInd
.Index
* 4 + swz
,
1678 src
->SrcRegister
.Index
* 4 + c
);
1681 case TGSI_FILE_IMMEDIATE
:
1682 r
= &pc
->immd
[src
->SrcRegister
.Index
* 4 + c
];
1684 case TGSI_FILE_SAMPLER
:
1686 case TGSI_FILE_ADDRESS
:
1687 r
= pc
->addr
[src
->SrcRegister
.Index
* 4 + c
];
1701 case TGSI_UTIL_SIGN_KEEP
:
1703 case TGSI_UTIL_SIGN_CLEAR
:
1704 temp
= temp_temp(pc
);
1705 emit_abs(pc
, temp
, r
);
1708 case TGSI_UTIL_SIGN_TOGGLE
:
1710 r
->mod
= NV50_MOD_NEG
;
1712 temp
= temp_temp(pc
);
1713 emit_neg(pc
, temp
, r
);
1717 case TGSI_UTIL_SIGN_SET
:
1718 temp
= temp_temp(pc
);
1719 emit_cvt(pc
, temp
, r
, -1, CVTOP_ABS
, CVT_F32_F32
| CVT_NEG
);
1730 /* return TRUE for ops that produce only a single result */
1732 is_scalar_op(unsigned op
)
1735 case TGSI_OPCODE_COS
:
1736 case TGSI_OPCODE_DP2
:
1737 case TGSI_OPCODE_DP3
:
1738 case TGSI_OPCODE_DP4
:
1739 case TGSI_OPCODE_DPH
:
1740 case TGSI_OPCODE_EX2
:
1741 case TGSI_OPCODE_LG2
:
1742 case TGSI_OPCODE_POW
:
1743 case TGSI_OPCODE_RCP
:
1744 case TGSI_OPCODE_RSQ
:
1745 case TGSI_OPCODE_SIN
:
1747 case TGSI_OPCODE_KIL:
1748 case TGSI_OPCODE_LIT:
1749 case TGSI_OPCODE_SCS:
1757 /* Returns a bitmask indicating which dst components depend
1758 * on source s, component c (reverse of nv50_tgsi_src_mask).
1761 nv50_tgsi_dst_revdep(unsigned op
, int s
, int c
)
1763 if (is_scalar_op(op
))
1767 case TGSI_OPCODE_DST
:
1768 return (1 << c
) & (s
? 0xa : 0x6);
1769 case TGSI_OPCODE_XPD
:
1779 case TGSI_OPCODE_LIT
:
1780 case TGSI_OPCODE_SCS
:
1781 case TGSI_OPCODE_TEX
:
1782 case TGSI_OPCODE_TXP
:
1783 /* these take care of dangerous swizzles themselves */
1785 case TGSI_OPCODE_IF
:
1786 case TGSI_OPCODE_KIL
:
1787 /* don't call this function for these ops */
1791 /* linear vector instruction */
1796 static INLINE boolean
1797 has_pred(struct nv50_program_exec
*e
, unsigned cc
)
1799 if (!is_long(e
) || is_immd(e
))
1801 return ((e
->inst
[1] & 0x780) == (cc
<< 7));
1804 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
1811 nv50_kill_branch(struct nv50_pc
*pc
)
1813 int lvl
= pc
->if_lvl
;
1815 if (pc
->if_insn
[lvl
]->next
!= pc
->p
->exec_tail
)
1818 /* if ccode == 'true', the BRA is from an ELSE and the predicate
1819 * reg may no longer be valid, since we currently always use $p0
1821 if (has_pred(pc
->if_insn
[lvl
], 0xf))
1823 assert(pc
->if_insn
[lvl
] && pc
->br_join
[lvl
]);
1825 /* We'll use the exec allocated for JOIN_AT (as we can't easily
1826 * update prev's next); if exec_tail is BRK, update the pointer.
1828 if (pc
->loop_lvl
&& pc
->br_loop
[pc
->loop_lvl
- 1] == pc
->p
->exec_tail
)
1829 pc
->br_loop
[pc
->loop_lvl
- 1] = pc
->br_join
[lvl
];
1831 pc
->p
->exec_size
-= 4; /* remove JOIN_AT and BRA */
1833 *pc
->br_join
[lvl
] = *pc
->p
->exec_tail
;
1835 FREE(pc
->if_insn
[lvl
]);
1836 FREE(pc
->p
->exec_tail
);
1838 pc
->p
->exec_tail
= pc
->br_join
[lvl
];
1839 pc
->p
->exec_tail
->next
= NULL
;
1840 set_pred(pc
, 0xd, 0, pc
->p
->exec_tail
);
1846 nv50_program_tx_insn(struct nv50_pc
*pc
,
1847 const struct tgsi_full_instruction
*inst
)
1849 struct nv50_reg
*rdst
[4], *dst
[4], *brdc
, *src
[3][4], *temp
;
1850 unsigned mask
, sat
, unit
;
1853 mask
= inst
->FullDstRegisters
[0].DstRegister
.WriteMask
;
1854 sat
= inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
;
1856 memset(src
, 0, sizeof(src
));
1858 for (c
= 0; c
< 4; c
++) {
1859 if ((mask
& (1 << c
)) && !pc
->r_dst
[c
])
1860 dst
[c
] = tgsi_dst(pc
, c
, &inst
->FullDstRegisters
[0]);
1862 dst
[c
] = pc
->r_dst
[c
];
1866 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1867 const struct tgsi_full_src_register
*fs
= &inst
->FullSrcRegisters
[i
];
1871 src_mask
= nv50_tgsi_src_mask(inst
, i
);
1872 neg_supp
= negate_supported(inst
, i
);
1874 if (fs
->SrcRegister
.File
== TGSI_FILE_SAMPLER
)
1875 unit
= fs
->SrcRegister
.Index
;
1877 for (c
= 0; c
< 4; c
++)
1878 if (src_mask
& (1 << c
))
1879 src
[i
][c
] = tgsi_src(pc
, c
, fs
, neg_supp
);
1882 brdc
= temp
= pc
->r_brdc
;
1883 if (brdc
&& brdc
->type
!= P_TEMP
) {
1884 temp
= temp_temp(pc
);
1889 for (c
= 0; c
< 4; c
++) {
1890 if (!(mask
& (1 << c
)) || dst
[c
]->type
== P_TEMP
)
1892 /* rdst[c] = dst[c]; */ /* done above */
1893 dst
[c
] = temp_temp(pc
);
1897 assert(brdc
|| !is_scalar_op(inst
->Instruction
.Opcode
));
1899 switch (inst
->Instruction
.Opcode
) {
1900 case TGSI_OPCODE_ABS
:
1901 for (c
= 0; c
< 4; c
++) {
1902 if (!(mask
& (1 << c
)))
1904 emit_abs(pc
, dst
[c
], src
[0][c
]);
1907 case TGSI_OPCODE_ADD
:
1908 for (c
= 0; c
< 4; c
++) {
1909 if (!(mask
& (1 << c
)))
1911 emit_add(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
1914 case TGSI_OPCODE_AND
:
1915 case TGSI_OPCODE_XOR
:
1916 case TGSI_OPCODE_OR
:
1917 for (c
= 0; c
< 4; c
++) {
1918 if (!(mask
& (1 << c
)))
1920 emit_bitop2(pc
, dst
[c
], src
[0][c
], src
[1][c
],
1921 inst
->Instruction
.Opcode
);
1924 case TGSI_OPCODE_ARL
:
1926 temp
= temp_temp(pc
);
1927 emit_cvt(pc
, temp
, src
[0][0], -1, CVTOP_FLOOR
, CVT_S32_F32
);
1928 emit_arl(pc
, dst
[0], temp
, 4);
1930 case TGSI_OPCODE_BGNLOOP
:
1931 pc
->loop_pos
[pc
->loop_lvl
++] = pc
->p
->exec_size
;
1934 case TGSI_OPCODE_BRK
:
1935 emit_branch(pc
, -1, 0, NULL
);
1936 assert(pc
->loop_lvl
> 0);
1937 pc
->br_loop
[pc
->loop_lvl
- 1] = pc
->p
->exec_tail
;
1939 case TGSI_OPCODE_CEIL
:
1940 for (c
= 0; c
< 4; c
++) {
1941 if (!(mask
& (1 << c
)))
1943 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
1944 CVTOP_CEIL
, CVT_F32_F32
| CVT_RI
);
1947 case TGSI_OPCODE_CMP
:
1948 pc
->allow32
= FALSE
;
1949 for (c
= 0; c
< 4; c
++) {
1950 if (!(mask
& (1 << c
)))
1952 emit_cvt(pc
, NULL
, src
[0][c
], 1, CVTOP_RN
, CVT_F32_F32
);
1953 emit_mov(pc
, dst
[c
], src
[1][c
]);
1954 set_pred(pc
, 0x1, 1, pc
->p
->exec_tail
); /* @SF */
1955 emit_mov(pc
, dst
[c
], src
[2][c
]);
1956 set_pred(pc
, 0x6, 1, pc
->p
->exec_tail
); /* @NSF */
1959 case TGSI_OPCODE_COS
:
1961 emit_precossin(pc
, temp
, src
[0][3]);
1962 emit_flop(pc
, 5, dst
[3], temp
);
1966 temp
= brdc
= temp_temp(pc
);
1968 emit_precossin(pc
, temp
, src
[0][0]);
1969 emit_flop(pc
, 5, brdc
, temp
);
1971 case TGSI_OPCODE_DDX
:
1972 for (c
= 0; c
< 4; c
++) {
1973 if (!(mask
& (1 << c
)))
1975 emit_ddx(pc
, dst
[c
], src
[0][c
]);
1978 case TGSI_OPCODE_DDY
:
1979 for (c
= 0; c
< 4; c
++) {
1980 if (!(mask
& (1 << c
)))
1982 emit_ddy(pc
, dst
[c
], src
[0][c
]);
1985 case TGSI_OPCODE_DP3
:
1986 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1987 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1988 emit_mad(pc
, brdc
, src
[0][2], src
[1][2], temp
);
1990 case TGSI_OPCODE_DP4
:
1991 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1992 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1993 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
1994 emit_mad(pc
, brdc
, src
[0][3], src
[1][3], temp
);
1996 case TGSI_OPCODE_DPH
:
1997 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1998 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1999 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
2000 emit_add(pc
, brdc
, src
[1][3], temp
);
2002 case TGSI_OPCODE_DST
:
2003 if (mask
& (1 << 1))
2004 emit_mul(pc
, dst
[1], src
[0][1], src
[1][1]);
2005 if (mask
& (1 << 2))
2006 emit_mov(pc
, dst
[2], src
[0][2]);
2007 if (mask
& (1 << 3))
2008 emit_mov(pc
, dst
[3], src
[1][3]);
2009 if (mask
& (1 << 0))
2010 emit_mov_immdval(pc
, dst
[0], 1.0f
);
2012 case TGSI_OPCODE_ELSE
:
2013 emit_branch(pc
, -1, 0, NULL
);
2014 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
2015 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
2018 case TGSI_OPCODE_ENDIF
:
2019 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
2021 /* try to replace branch over 1 insn with a predicated insn */
2022 if (nv50_kill_branch(pc
) == TRUE
)
2025 if (pc
->br_join
[pc
->if_lvl
]) {
2026 pc
->br_join
[pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
2027 pc
->br_join
[pc
->if_lvl
] = NULL
;
2030 /* emit a NOP as join point, we could set it on the next
2031 * one, but would have to make sure it is long and !immd
2034 pc
->p
->exec_tail
->inst
[1] |= 2;
2036 case TGSI_OPCODE_ENDLOOP
:
2037 emit_branch(pc
, -1, 0, NULL
);
2038 pc
->p
->exec_tail
->param
.index
= pc
->loop_pos
[--pc
->loop_lvl
];
2039 pc
->br_loop
[pc
->loop_lvl
]->param
.index
= pc
->p
->exec_size
;
2042 case TGSI_OPCODE_EX2
:
2043 emit_preex2(pc
, temp
, src
[0][0]);
2044 emit_flop(pc
, 6, brdc
, temp
);
2046 case TGSI_OPCODE_FLR
:
2047 for (c
= 0; c
< 4; c
++) {
2048 if (!(mask
& (1 << c
)))
2050 emit_flr(pc
, dst
[c
], src
[0][c
]);
2053 case TGSI_OPCODE_FRC
:
2054 temp
= temp_temp(pc
);
2055 for (c
= 0; c
< 4; c
++) {
2056 if (!(mask
& (1 << c
)))
2058 emit_flr(pc
, temp
, src
[0][c
]);
2059 emit_sub(pc
, dst
[c
], src
[0][c
], temp
);
2062 case TGSI_OPCODE_IF
:
2063 /* emitting a join_at may not be necessary */
2064 assert(pc
->if_lvl
< MAX_IF_DEPTH
);
2065 /* set_pred_wr(pc, 1, 0, pc->if_cond); */
2066 emit_cvt(pc
, NULL
, src
[0][0], 0, CVTOP_ABS
| CVTOP_RN
,
2068 emit_branch(pc
, 0, 2, &pc
->br_join
[pc
->if_lvl
]);
2069 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
2072 case TGSI_OPCODE_KIL
:
2073 emit_kil(pc
, src
[0][0]);
2074 emit_kil(pc
, src
[0][1]);
2075 emit_kil(pc
, src
[0][2]);
2076 emit_kil(pc
, src
[0][3]);
2078 case TGSI_OPCODE_LIT
:
2079 emit_lit(pc
, &dst
[0], mask
, &src
[0][0]);
2081 case TGSI_OPCODE_LG2
:
2082 emit_flop(pc
, 3, brdc
, src
[0][0]);
2084 case TGSI_OPCODE_LRP
:
2085 temp
= temp_temp(pc
);
2086 for (c
= 0; c
< 4; c
++) {
2087 if (!(mask
& (1 << c
)))
2089 emit_sub(pc
, temp
, src
[1][c
], src
[2][c
]);
2090 emit_mad(pc
, dst
[c
], temp
, src
[0][c
], src
[2][c
]);
2093 case TGSI_OPCODE_MAD
:
2094 for (c
= 0; c
< 4; c
++) {
2095 if (!(mask
& (1 << c
)))
2097 emit_mad(pc
, dst
[c
], src
[0][c
], src
[1][c
], src
[2][c
]);
2100 case TGSI_OPCODE_MAX
:
2101 for (c
= 0; c
< 4; c
++) {
2102 if (!(mask
& (1 << c
)))
2104 emit_minmax(pc
, 4, dst
[c
], src
[0][c
], src
[1][c
]);
2107 case TGSI_OPCODE_MIN
:
2108 for (c
= 0; c
< 4; c
++) {
2109 if (!(mask
& (1 << c
)))
2111 emit_minmax(pc
, 5, dst
[c
], src
[0][c
], src
[1][c
]);
2114 case TGSI_OPCODE_MOV
:
2115 for (c
= 0; c
< 4; c
++) {
2116 if (!(mask
& (1 << c
)))
2118 emit_mov(pc
, dst
[c
], src
[0][c
]);
2121 case TGSI_OPCODE_MUL
:
2122 for (c
= 0; c
< 4; c
++) {
2123 if (!(mask
& (1 << c
)))
2125 emit_mul(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2128 case TGSI_OPCODE_POW
:
2129 emit_pow(pc
, brdc
, src
[0][0], src
[1][0]);
2131 case TGSI_OPCODE_RCP
:
2132 emit_flop(pc
, 0, brdc
, src
[0][0]);
2134 case TGSI_OPCODE_RSQ
:
2135 emit_flop(pc
, 2, brdc
, src
[0][0]);
2137 case TGSI_OPCODE_SCS
:
2138 temp
= temp_temp(pc
);
2140 emit_precossin(pc
, temp
, src
[0][0]);
2141 if (mask
& (1 << 0))
2142 emit_flop(pc
, 5, dst
[0], temp
);
2143 if (mask
& (1 << 1))
2144 emit_flop(pc
, 4, dst
[1], temp
);
2145 if (mask
& (1 << 2))
2146 emit_mov_immdval(pc
, dst
[2], 0.0);
2147 if (mask
& (1 << 3))
2148 emit_mov_immdval(pc
, dst
[3], 1.0);
2150 case TGSI_OPCODE_SIN
:
2152 emit_precossin(pc
, temp
, src
[0][3]);
2153 emit_flop(pc
, 4, dst
[3], temp
);
2157 temp
= brdc
= temp_temp(pc
);
2159 emit_precossin(pc
, temp
, src
[0][0]);
2160 emit_flop(pc
, 4, brdc
, temp
);
2162 case TGSI_OPCODE_SLT
:
2163 case TGSI_OPCODE_SGE
:
2164 case TGSI_OPCODE_SEQ
:
2165 case TGSI_OPCODE_SGT
:
2166 case TGSI_OPCODE_SLE
:
2167 case TGSI_OPCODE_SNE
:
2168 i
= map_tgsi_setop_cc(inst
->Instruction
.Opcode
);
2169 for (c
= 0; c
< 4; c
++) {
2170 if (!(mask
& (1 << c
)))
2172 emit_set(pc
, i
, dst
[c
], -1, src
[0][c
], src
[1][c
]);
2175 case TGSI_OPCODE_SUB
:
2176 for (c
= 0; c
< 4; c
++) {
2177 if (!(mask
& (1 << c
)))
2179 emit_sub(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2182 case TGSI_OPCODE_TEX
:
2183 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2184 inst
->InstructionExtTexture
.Texture
, FALSE
);
2186 case TGSI_OPCODE_TXP
:
2187 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2188 inst
->InstructionExtTexture
.Texture
, TRUE
);
2190 case TGSI_OPCODE_TRUNC
:
2191 for (c
= 0; c
< 4; c
++) {
2192 if (!(mask
& (1 << c
)))
2194 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2195 CVTOP_TRUNC
, CVT_F32_F32
| CVT_RI
);
2198 case TGSI_OPCODE_XPD
:
2199 temp
= temp_temp(pc
);
2200 if (mask
& (1 << 0)) {
2201 emit_mul(pc
, temp
, src
[0][2], src
[1][1]);
2202 emit_msb(pc
, dst
[0], src
[0][1], src
[1][2], temp
);
2204 if (mask
& (1 << 1)) {
2205 emit_mul(pc
, temp
, src
[0][0], src
[1][2]);
2206 emit_msb(pc
, dst
[1], src
[0][2], src
[1][0], temp
);
2208 if (mask
& (1 << 2)) {
2209 emit_mul(pc
, temp
, src
[0][1], src
[1][0]);
2210 emit_msb(pc
, dst
[2], src
[0][0], src
[1][1], temp
);
2212 if (mask
& (1 << 3))
2213 emit_mov_immdval(pc
, dst
[3], 1.0);
2215 case TGSI_OPCODE_END
:
2218 NOUVEAU_ERR("invalid opcode %d\n", inst
->Instruction
.Opcode
);
2224 emit_sat(pc
, brdc
, brdc
);
2225 for (c
= 0; c
< 4; c
++)
2226 if ((mask
& (1 << c
)) && dst
[c
] != brdc
)
2227 emit_mov(pc
, dst
[c
], brdc
);
2230 for (c
= 0; c
< 4; c
++) {
2231 if (!(mask
& (1 << c
)))
2233 /* In this case we saturate later, and dst[c] won't
2234 * be another temp_temp (and thus lost), since rdst
2235 * already is TEMP (see above). */
2236 if (rdst
[c
]->type
== P_TEMP
&& rdst
[c
]->index
< 0)
2238 emit_sat(pc
, rdst
[c
], dst
[c
]);
2242 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2243 for (c
= 0; c
< 4; c
++) {
2247 if (src
[i
][c
]->index
== -1 && src
[i
][c
]->type
== P_IMMD
)
2250 if (src
[i
][c
]->acc
< 0 && src
[i
][c
]->type
== P_CONST
)
2251 FREE(src
[i
][c
]); /* indirect constant */
2260 prep_inspect_insn(struct nv50_pc
*pc
, const struct tgsi_full_instruction
*insn
)
2262 struct nv50_reg
*reg
= NULL
;
2263 const struct tgsi_full_src_register
*src
;
2264 const struct tgsi_dst_register
*dst
;
2265 unsigned i
, c
, k
, mask
;
2267 dst
= &insn
->FullDstRegisters
[0].DstRegister
;
2268 mask
= dst
->WriteMask
;
2270 if (dst
->File
== TGSI_FILE_TEMPORARY
)
2273 if (dst
->File
== TGSI_FILE_OUTPUT
)
2277 for (c
= 0; c
< 4; c
++) {
2278 if (!(mask
& (1 << c
)))
2280 reg
[dst
->Index
* 4 + c
].acc
= pc
->insn_nr
;
2284 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
2285 src
= &insn
->FullSrcRegisters
[i
];
2287 if (src
->SrcRegister
.File
== TGSI_FILE_TEMPORARY
)
2290 if (src
->SrcRegister
.File
== TGSI_FILE_INPUT
)
2295 mask
= nv50_tgsi_src_mask(insn
, i
);
2297 for (c
= 0; c
< 4; c
++) {
2298 if (!(mask
& (1 << c
)))
2300 k
= tgsi_util_get_full_src_register_swizzle(src
, c
);
2302 reg
[src
->SrcRegister
.Index
* 4 + k
].acc
= pc
->insn_nr
;
2307 /* Returns a bitmask indicating which dst components need to be
2308 * written to temporaries first to avoid 'corrupting' sources.
2310 * m[i] (out) indicate component to write in the i-th position
2311 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2314 nv50_revdep_reorder(unsigned m
[4], unsigned rdep
[4])
2316 unsigned i
, c
, x
, unsafe
;
2318 for (c
= 0; c
< 4; c
++)
2321 /* Swap as long as a dst component written earlier is depended on
2322 * by one written later, but the next one isn't depended on by it.
2324 for (c
= 0; c
< 3; c
++) {
2325 if (rdep
[m
[c
+ 1]] & (1 << m
[c
]))
2326 continue; /* if next one is depended on by us */
2327 for (i
= c
+ 1; i
< 4; i
++)
2328 /* if we are depended on by a later one */
2329 if (rdep
[m
[c
]] & (1 << m
[i
]))
2342 /* mark dependencies that could not be resolved by reordering */
2343 for (i
= 0; i
< 3; ++i
)
2344 for (c
= i
+ 1; c
< 4; ++c
)
2345 if (rdep
[m
[i
]] & (1 << m
[c
]))
2348 /* NOTE: $unsafe is with respect to order, not component */
2352 /* Select a suitable dst register for broadcasting scalar results,
2353 * or return NULL if we have to allocate an extra TEMP.
2355 * If e.g. only 1 component is written, we may also emit the final
2356 * result to a write-only register.
2358 static struct nv50_reg
*
2359 tgsi_broadcast_dst(struct nv50_pc
*pc
,
2360 const struct tgsi_full_dst_register
*fd
, unsigned mask
)
2362 if (fd
->DstRegister
.File
== TGSI_FILE_TEMPORARY
) {
2363 int c
= ffs(~mask
& fd
->DstRegister
.WriteMask
);
2365 return tgsi_dst(pc
, c
- 1, fd
);
2367 int c
= ffs(fd
->DstRegister
.WriteMask
) - 1;
2368 if ((1 << c
) == fd
->DstRegister
.WriteMask
)
2369 return tgsi_dst(pc
, c
, fd
);
2375 /* Scan source swizzles and return a bitmask indicating dst regs that
2376 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2379 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction
*insn
,
2382 const struct tgsi_full_dst_register
*fd
= &insn
->FullDstRegisters
[0];
2383 const struct tgsi_full_src_register
*fs
;
2384 unsigned i
, deqs
= 0;
2386 for (i
= 0; i
< 4; ++i
)
2389 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
2390 unsigned chn
, mask
= nv50_tgsi_src_mask(insn
, i
);
2391 boolean neg_supp
= negate_supported(insn
, i
);
2393 fs
= &insn
->FullSrcRegisters
[i
];
2394 if (fs
->SrcRegister
.File
!= fd
->DstRegister
.File
||
2395 fs
->SrcRegister
.Index
!= fd
->DstRegister
.Index
)
2398 for (chn
= 0; chn
< 4; ++chn
) {
2401 if (!(mask
& (1 << chn
))) /* src is not read */
2403 c
= tgsi_util_get_full_src_register_swizzle(fs
, chn
);
2404 s
= tgsi_util_get_full_src_register_sign_mode(fs
, chn
);
2406 if (!(fd
->DstRegister
.WriteMask
& (1 << c
)))
2409 /* no danger if src is copied to TEMP first */
2410 if ((s
!= TGSI_UTIL_SIGN_KEEP
) &&
2411 (s
!= TGSI_UTIL_SIGN_TOGGLE
|| !neg_supp
))
2414 rdep
[c
] |= nv50_tgsi_dst_revdep(
2415 insn
->Instruction
.Opcode
, i
, chn
);
2424 nv50_tgsi_insn(struct nv50_pc
*pc
, const union tgsi_full_token
*tok
)
2426 struct tgsi_full_instruction insn
= tok
->FullInstruction
;
2427 const struct tgsi_full_dst_register
*fd
;
2428 unsigned i
, deqs
, rdep
[4], m
[4];
2430 fd
= &tok
->FullInstruction
.FullDstRegisters
[0];
2431 deqs
= nv50_tgsi_scan_swizzle(&insn
, rdep
);
2433 if (is_scalar_op(insn
.Instruction
.Opcode
)) {
2434 pc
->r_brdc
= tgsi_broadcast_dst(pc
, fd
, deqs
);
2436 pc
->r_brdc
= temp_temp(pc
);
2437 return nv50_program_tx_insn(pc
, &insn
);
2442 return nv50_program_tx_insn(pc
, &insn
);
2444 deqs
= nv50_revdep_reorder(m
, rdep
);
2446 for (i
= 0; i
< 4; ++i
) {
2447 assert(pc
->r_dst
[m
[i
]] == NULL
);
2449 insn
.FullDstRegisters
[0].DstRegister
.WriteMask
=
2450 fd
->DstRegister
.WriteMask
& (1 << m
[i
]);
2452 if (!insn
.FullDstRegisters
[0].DstRegister
.WriteMask
)
2455 if (deqs
& (1 << i
))
2456 pc
->r_dst
[m
[i
]] = alloc_temp(pc
, NULL
);
2458 if (!nv50_program_tx_insn(pc
, &insn
))
2462 for (i
= 0; i
< 4; i
++) {
2463 struct nv50_reg
*reg
= pc
->r_dst
[i
];
2466 pc
->r_dst
[i
] = NULL
;
2468 if (insn
.Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
)
2469 emit_sat(pc
, tgsi_dst(pc
, i
, fd
), reg
);
2471 emit_mov(pc
, tgsi_dst(pc
, i
, fd
), reg
);
2479 load_interpolant(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
2481 struct nv50_reg
*iv
, **ppiv
;
2482 unsigned mode
= pc
->interp_mode
[reg
->index
];
2484 ppiv
= (mode
& INTERP_CENTROID
) ? &pc
->iv_c
: &pc
->iv_p
;
2487 if ((mode
& INTERP_PERSPECTIVE
) && !iv
) {
2488 iv
= *ppiv
= alloc_temp(pc
, NULL
);
2489 iv
->rhw
= popcnt4(pc
->p
->cfg
.regs
[1] >> 24) - 1;
2491 emit_interp(pc
, iv
, NULL
, mode
& INTERP_CENTROID
);
2492 emit_flop(pc
, 0, iv
, iv
);
2494 /* XXX: when loading interpolants dynamically, move these
2495 * to the program head, or make sure it can't be skipped.
2499 emit_interp(pc
, reg
, iv
, mode
);
2502 /* The face input is always at v[255] (varying space), with a
2503 * value of 0 for back-facing, and 0xffffffff for front-facing.
2506 load_frontfacing(struct nv50_pc
*pc
, struct nv50_reg
*a
)
2508 struct nv50_reg
*one
= alloc_immd(pc
, 1.0f
);
2510 assert(a
->rhw
== -1);
2511 alloc_reg(pc
, a
); /* do this before rhw is set */
2513 load_interpolant(pc
, a
);
2514 emit_bitop2(pc
, a
, a
, one
, TGSI_OPCODE_AND
);
2520 nv50_program_tx_prep(struct nv50_pc
*pc
)
2522 struct tgsi_parse_context tp
;
2523 struct nv50_program
*p
= pc
->p
;
2524 boolean ret
= FALSE
;
2525 unsigned i
, c
, flat_nr
= 0;
2527 tgsi_parse_init(&tp
, pc
->p
->pipe
.tokens
);
2528 while (!tgsi_parse_end_of_tokens(&tp
)) {
2529 const union tgsi_full_token
*tok
= &tp
.FullToken
;
2531 tgsi_parse_token(&tp
);
2532 switch (tok
->Token
.Type
) {
2533 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2535 const struct tgsi_full_immediate
*imm
=
2536 &tp
.FullToken
.FullImmediate
;
2538 ctor_immd(pc
, imm
->u
[0].Float
,
2544 case TGSI_TOKEN_TYPE_DECLARATION
:
2546 const struct tgsi_full_declaration
*d
;
2547 unsigned si
, last
, first
, mode
;
2549 d
= &tp
.FullToken
.FullDeclaration
;
2550 first
= d
->DeclarationRange
.First
;
2551 last
= d
->DeclarationRange
.Last
;
2553 switch (d
->Declaration
.File
) {
2554 case TGSI_FILE_TEMPORARY
:
2556 case TGSI_FILE_OUTPUT
:
2557 if (!d
->Declaration
.Semantic
||
2558 p
->type
== PIPE_SHADER_FRAGMENT
)
2561 si
= d
->Semantic
.SemanticIndex
;
2562 switch (d
->Semantic
.SemanticName
) {
2563 case TGSI_SEMANTIC_BCOLOR
:
2564 p
->cfg
.two_side
[si
].hw
= first
;
2565 if (p
->cfg
.io_nr
> first
)
2566 p
->cfg
.io_nr
= first
;
2568 case TGSI_SEMANTIC_PSIZE
:
2569 p
->cfg
.psiz
= first
;
2570 if (p
->cfg
.io_nr
> first
)
2571 p
->cfg
.io_nr
= first
;
2574 case TGSI_SEMANTIC_CLIP_DISTANCE:
2575 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2582 case TGSI_FILE_INPUT
:
2584 if (p
->type
!= PIPE_SHADER_FRAGMENT
)
2587 switch (d
->Declaration
.Interpolate
) {
2588 case TGSI_INTERPOLATE_CONSTANT
:
2592 case TGSI_INTERPOLATE_PERSPECTIVE
:
2593 mode
= INTERP_PERSPECTIVE
;
2594 p
->cfg
.regs
[1] |= 0x08 << 24;
2597 mode
= INTERP_LINEAR
;
2600 if (d
->Declaration
.Centroid
)
2601 mode
|= INTERP_CENTROID
;
2604 for (i
= first
; i
<= last
; i
++)
2605 pc
->interp_mode
[i
] = mode
;
2608 case TGSI_FILE_ADDRESS
:
2609 case TGSI_FILE_CONSTANT
:
2610 case TGSI_FILE_SAMPLER
:
2613 NOUVEAU_ERR("bad decl file %d\n",
2614 d
->Declaration
.File
);
2619 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2621 prep_inspect_insn(pc
, &tok
->FullInstruction
);
2628 if (p
->type
== PIPE_SHADER_VERTEX
) {
2631 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
) {
2632 if (pc
->attr
[i
].acc
) {
2633 pc
->attr
[i
].hw
= rid
++;
2634 p
->cfg
.attr
[i
/ 32] |= 1 << (i
% 32);
2638 for (i
= 0, rid
= 0; i
< pc
->result_nr
; ++i
) {
2639 p
->cfg
.io
[i
].hw
= rid
;
2640 p
->cfg
.io
[i
].id_vp
= i
;
2642 for (c
= 0; c
< 4; ++c
) {
2644 if (!pc
->result
[n
].acc
)
2646 pc
->result
[n
].hw
= rid
++;
2647 p
->cfg
.io
[i
].mask
|= 1 << c
;
2651 for (c
= 0; c
< 2; ++c
)
2652 if (p
->cfg
.two_side
[c
].hw
< 0x40)
2653 p
->cfg
.two_side
[c
] = p
->cfg
.io
[
2654 p
->cfg
.two_side
[c
].hw
];
2656 if (p
->cfg
.psiz
< 0x40)
2657 p
->cfg
.psiz
= p
->cfg
.io
[p
->cfg
.psiz
].hw
;
2659 if (p
->type
== PIPE_SHADER_FRAGMENT
) {
2661 unsigned n
= 0, m
= pc
->attr_nr
- flat_nr
;
2665 int base
= (TGSI_SEMANTIC_POSITION
==
2666 p
->info
.input_semantic_name
[0]) ? 0 : 1;
2668 /* non-flat interpolants have to be mapped to
2669 * the lower hardware IDs, so sort them:
2671 for (i
= 0; i
< pc
->attr_nr
; i
++) {
2672 if (pc
->interp_mode
[i
] == INTERP_FLAT
) {
2673 p
->cfg
.io
[m
].id_vp
= i
+ base
;
2674 p
->cfg
.io
[m
++].id_fp
= i
;
2676 if (!(pc
->interp_mode
[i
] & INTERP_PERSPECTIVE
))
2677 p
->cfg
.io
[n
].linear
= TRUE
;
2678 p
->cfg
.io
[n
].id_vp
= i
+ base
;
2679 p
->cfg
.io
[n
++].id_fp
= i
;
2683 if (!base
) /* set w-coordinate mask from perspective interp */
2684 p
->cfg
.io
[0].mask
|= p
->cfg
.regs
[1] >> 24;
2686 aid
= popcnt4( /* if fcrd isn't contained in cfg.io */
2687 base
? (p
->cfg
.regs
[1] >> 24) : p
->cfg
.io
[0].mask
);
2689 for (n
= 0; n
< pc
->attr_nr
; ++n
) {
2690 p
->cfg
.io
[n
].hw
= rid
= aid
;
2691 i
= p
->cfg
.io
[n
].id_fp
;
2693 if (p
->info
.input_semantic_name
[n
] ==
2694 TGSI_SEMANTIC_FACE
) {
2695 load_frontfacing(pc
, &pc
->attr
[i
* 4]);
2699 for (c
= 0; c
< 4; ++c
) {
2700 if (!pc
->attr
[i
* 4 + c
].acc
)
2702 pc
->attr
[i
* 4 + c
].rhw
= rid
++;
2703 p
->cfg
.io
[n
].mask
|= 1 << c
;
2705 load_interpolant(pc
, &pc
->attr
[i
* 4 + c
]);
2707 aid
+= popcnt4(p
->cfg
.io
[n
].mask
);
2711 p
->cfg
.regs
[1] |= p
->cfg
.io
[0].mask
<< 24;
2713 m
= popcnt4(p
->cfg
.regs
[1] >> 24);
2715 /* set count of non-position inputs and of non-flat
2716 * non-position inputs for FP_INTERPOLANT_CTRL
2718 p
->cfg
.regs
[1] |= aid
- m
;
2721 i
= p
->cfg
.io
[pc
->attr_nr
- flat_nr
].hw
;
2722 p
->cfg
.regs
[1] |= (i
- m
) << 16;
2724 p
->cfg
.regs
[1] |= p
->cfg
.regs
[1] << 16;
2726 /* mark color semantic for light-twoside */
2728 for (i
= 0; i
< pc
->attr_nr
; i
++) {
2731 sn
= p
->info
.input_semantic_name
[p
->cfg
.io
[i
].id_fp
];
2732 si
= p
->info
.input_semantic_index
[p
->cfg
.io
[i
].id_fp
];
2734 if (sn
== TGSI_SEMANTIC_COLOR
) {
2735 p
->cfg
.two_side
[si
] = p
->cfg
.io
[i
];
2737 /* increase colour count */
2738 p
->cfg
.regs
[0] += popcnt4(
2739 p
->cfg
.two_side
[si
].mask
) << 16;
2741 n
= MIN2(n
, p
->cfg
.io
[i
].hw
- m
);
2745 p
->cfg
.regs
[0] += n
;
2747 /* Initialize FP results:
2748 * FragDepth is always first TGSI and last hw output
2750 i
= p
->info
.writes_z
? 4 : 0;
2751 for (rid
= 0; i
< pc
->result_nr
* 4; i
++)
2752 pc
->result
[i
].rhw
= rid
++;
2753 if (p
->info
.writes_z
)
2754 pc
->result
[2].rhw
= rid
;
2756 p
->cfg
.high_result
= rid
;
2758 /* separate/different colour results for MRTs ? */
2759 if (pc
->result_nr
- (p
->info
.writes_z
? 1 : 0) > 1)
2760 p
->cfg
.regs
[2] |= 1;
2766 pc
->immd
= MALLOC(pc
->immd_nr
* 4 * sizeof(struct nv50_reg
));
2770 for (i
= 0; i
< pc
->immd_nr
; i
++) {
2771 for (c
= 0; c
< 4; c
++, rid
++)
2772 ctor_reg(&pc
->immd
[rid
], P_IMMD
, i
, rid
);
2779 free_temp(pc
, pc
->iv_p
);
2781 free_temp(pc
, pc
->iv_c
);
2783 tgsi_parse_free(&tp
);
2788 free_nv50_pc(struct nv50_pc
*pc
)
2805 ctor_nv50_pc(struct nv50_pc
*pc
, struct nv50_program
*p
)
2808 unsigned rtype
[2] = { P_ATTR
, P_RESULT
};
2811 pc
->temp_nr
= p
->info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
2812 pc
->attr_nr
= p
->info
.file_max
[TGSI_FILE_INPUT
] + 1;
2813 pc
->result_nr
= p
->info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
2814 pc
->param_nr
= p
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
2815 pc
->addr_nr
= p
->info
.file_max
[TGSI_FILE_ADDRESS
] + 1;
2816 assert(pc
->addr_nr
<= 2);
2818 p
->cfg
.high_temp
= 4;
2820 p
->cfg
.two_side
[0].hw
= 0x40;
2821 p
->cfg
.two_side
[1].hw
= 0x40;
2824 case PIPE_SHADER_VERTEX
:
2827 p
->cfg
.io_nr
= pc
->result_nr
;
2829 case PIPE_SHADER_FRAGMENT
:
2830 rtype
[0] = rtype
[1] = P_TEMP
;
2832 p
->cfg
.regs
[0] = 0x01000004;
2833 p
->cfg
.io_nr
= pc
->attr_nr
;
2835 if (p
->info
.writes_z
) {
2836 p
->cfg
.regs
[2] |= 0x00000100;
2837 p
->cfg
.regs
[3] |= 0x00000011;
2839 if (p
->info
.uses_kill
)
2840 p
->cfg
.regs
[2] |= 0x00100000;
2845 pc
->temp
= MALLOC(pc
->temp_nr
* 4 * sizeof(struct nv50_reg
));
2849 for (i
= 0; i
< pc
->temp_nr
* 4; ++i
)
2850 ctor_reg(&pc
->temp
[i
], P_TEMP
, i
/ 4, -1);
2854 pc
->attr
= MALLOC(pc
->attr_nr
* 4 * sizeof(struct nv50_reg
));
2858 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
)
2859 ctor_reg(&pc
->attr
[i
], rtype
[0], i
/ 4, -1);
2862 if (pc
->result_nr
) {
2863 unsigned nr
= pc
->result_nr
* 4;
2865 pc
->result
= MALLOC(nr
* sizeof(struct nv50_reg
));
2869 for (i
= 0; i
< nr
; ++i
)
2870 ctor_reg(&pc
->result
[i
], rtype
[1], i
/ 4, -1);
2876 pc
->param
= MALLOC(pc
->param_nr
* 4 * sizeof(struct nv50_reg
));
2880 for (i
= 0; i
< pc
->param_nr
; ++i
)
2881 for (c
= 0; c
< 4; ++c
, ++rid
)
2882 ctor_reg(&pc
->param
[rid
], P_CONST
, i
, rid
);
2886 pc
->addr
= CALLOC(pc
->addr_nr
* 4, sizeof(struct nv50_reg
*));
2890 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
2891 ctor_reg(&pc
->r_addr
[i
], P_ADDR
, -256, i
+ 1);
2897 nv50_fp_move_results(struct nv50_pc
*pc
)
2899 struct nv50_reg reg
;
2902 ctor_reg(®
, P_TEMP
, -1, -1);
2904 for (i
= 0; i
< pc
->result_nr
* 4; ++i
) {
2905 if (pc
->result
[i
].rhw
< 0 || pc
->result
[i
].hw
< 0)
2907 if (pc
->result
[i
].rhw
!= pc
->result
[i
].hw
) {
2908 reg
.hw
= pc
->result
[i
].rhw
;
2909 emit_mov(pc
, ®
, &pc
->result
[i
]);
2915 nv50_program_fixup_insns(struct nv50_pc
*pc
)
2917 struct nv50_program_exec
*e
, *prev
= NULL
, **bra_list
;
2920 bra_list
= CALLOC(pc
->p
->exec_size
, sizeof(struct nv50_program_exec
*));
2922 /* Collect branch instructions, we need to adjust their offsets
2923 * when converting 32 bit instructions to 64 bit ones
2925 for (n
= 0, e
= pc
->p
->exec_head
; e
; e
= e
->next
)
2926 if (e
->param
.index
>= 0 && !e
->param
.mask
)
2929 /* Make sure we don't have any single 32 bit instructions. */
2930 for (e
= pc
->p
->exec_head
, pos
= 0; e
; e
= e
->next
) {
2931 pos
+= is_long(e
) ? 2 : 1;
2933 if ((pos
& 1) && (!e
->next
|| is_long(e
->next
))) {
2934 for (i
= 0; i
< n
; ++i
)
2935 if (bra_list
[i
]->param
.index
>= pos
)
2936 bra_list
[i
]->param
.index
+= 1;
2937 convert_to_long(pc
, e
);
2944 assert(!is_immd(pc
->p
->exec_head
));
2945 assert(!is_immd(pc
->p
->exec_tail
));
2947 /* last instruction must be long so it can have the end bit set */
2948 if (!is_long(pc
->p
->exec_tail
)) {
2949 convert_to_long(pc
, pc
->p
->exec_tail
);
2951 convert_to_long(pc
, prev
);
2953 assert(!(pc
->p
->exec_tail
->inst
[1] & 2));
2954 /* set the end-bit */
2955 pc
->p
->exec_tail
->inst
[1] |= 1;
2961 nv50_program_tx(struct nv50_program
*p
)
2963 struct tgsi_parse_context parse
;
2967 pc
= CALLOC_STRUCT(nv50_pc
);
2971 ret
= ctor_nv50_pc(pc
, p
);
2975 ret
= nv50_program_tx_prep(pc
);
2979 tgsi_parse_init(&parse
, pc
->p
->pipe
.tokens
);
2980 while (!tgsi_parse_end_of_tokens(&parse
)) {
2981 const union tgsi_full_token
*tok
= &parse
.FullToken
;
2983 /* don't allow half insn/immd on first and last instruction */
2985 if (pc
->insn_cur
== 0 || pc
->insn_cur
+ 2 == pc
->insn_nr
)
2986 pc
->allow32
= FALSE
;
2988 tgsi_parse_token(&parse
);
2990 switch (tok
->Token
.Type
) {
2991 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2993 ret
= nv50_tgsi_insn(pc
, tok
);
3002 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
)
3003 nv50_fp_move_results(pc
);
3005 nv50_program_fixup_insns(pc
);
3007 p
->param_nr
= pc
->param_nr
* 4;
3008 p
->immd_nr
= pc
->immd_nr
* 4;
3009 p
->immd
= pc
->immd_buf
;
3012 tgsi_parse_free(&parse
);
3020 nv50_program_validate(struct nv50_context
*nv50
, struct nv50_program
*p
)
3022 if (nv50_program_tx(p
) == FALSE
)
3024 p
->translated
= TRUE
;
3028 nv50_program_upload_data(struct nv50_context
*nv50
, float *map
,
3029 unsigned start
, unsigned count
, unsigned cbuf
)
3031 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
3032 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3035 unsigned nr
= count
> 2047 ? 2047 : count
;
3037 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 1);
3038 OUT_RING (chan
, (cbuf
<< 0) | (start
<< 8));
3039 BEGIN_RING(chan
, tesla
, NV50TCL_CB_DATA(0) | 0x40000000, nr
);
3040 OUT_RINGp (chan
, map
, nr
);
3049 nv50_program_validate_data(struct nv50_context
*nv50
, struct nv50_program
*p
)
3051 struct pipe_screen
*pscreen
= nv50
->pipe
.screen
;
3053 if (!p
->data
[0] && p
->immd_nr
) {
3054 struct nouveau_resource
*heap
= nv50
->screen
->immd_heap
[0];
3056 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
, &p
->data
[0])) {
3057 while (heap
->next
&& heap
->size
< p
->immd_nr
) {
3058 struct nv50_program
*evict
= heap
->next
->priv
;
3059 nouveau_resource_free(&evict
->data
[0]);
3062 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
,
3067 /* immediates only need to be uploaded again when freed */
3068 nv50_program_upload_data(nv50
, p
->immd
, p
->data
[0]->start
,
3069 p
->immd_nr
, NV50_CB_PMISC
);
3072 assert(p
->param_nr
<= 512);
3076 float *map
= pipe_buffer_map(pscreen
, nv50
->constbuf
[p
->type
],
3077 PIPE_BUFFER_USAGE_CPU_READ
);
3079 if (p
->type
== PIPE_SHADER_VERTEX
)
3084 nv50_program_upload_data(nv50
, map
, 0, p
->param_nr
, cb
);
3085 pipe_buffer_unmap(pscreen
, nv50
->constbuf
[p
->type
]);
3090 nv50_program_validate_code(struct nv50_context
*nv50
, struct nv50_program
*p
)
3092 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
3093 struct nv50_program_exec
*e
;
3095 boolean upload
= FALSE
;
3098 nouveau_bo_new(chan
->device
, NOUVEAU_BO_VRAM
, 0x100,
3099 p
->exec_size
* 4, &p
->bo
);
3103 if (p
->data
[0] && p
->data
[0]->start
!= p
->data_start
[0])
3109 up
= MALLOC(p
->exec_size
* 4);
3111 for (i
= 0, e
= p
->exec_head
; e
; e
= e
->next
) {
3112 unsigned ei
, ci
, bs
;
3114 if (e
->param
.index
>= 0 && e
->param
.mask
) {
3115 bs
= (e
->inst
[1] >> 22) & 0x07;
3117 ei
= e
->param
.shift
>> 5;
3118 ci
= e
->param
.index
;
3120 ci
+= p
->data
[bs
]->start
;
3122 e
->inst
[ei
] &= ~e
->param
.mask
;
3123 e
->inst
[ei
] |= (ci
<< e
->param
.shift
);
3125 if (e
->param
.index
>= 0) {
3126 /* zero mask means param is a jump/branch offset */
3127 assert(!(e
->param
.index
& 1));
3128 /* seem to be 8 byte steps */
3129 ei
= (e
->param
.index
>> 1) + 0 /* START_ID */;
3131 e
->inst
[0] &= 0xf0000fff;
3132 e
->inst
[0] |= ei
<< 12;
3135 up
[i
++] = e
->inst
[0];
3137 up
[i
++] = e
->inst
[1];
3139 assert(i
== p
->exec_size
);
3142 p
->data_start
[0] = p
->data
[0]->start
;
3144 #ifdef NV50_PROGRAM_DUMP
3145 NOUVEAU_ERR("-------\n");
3146 for (e
= p
->exec_head
; e
; e
= e
->next
) {
3147 NOUVEAU_ERR("0x%08x\n", e
->inst
[0]);
3149 NOUVEAU_ERR("0x%08x\n", e
->inst
[1]);
3152 nv50_upload_sifc(nv50
, p
->bo
, 0, NOUVEAU_BO_VRAM
,
3153 NV50_2D_DST_FORMAT_R8_UNORM
, 65536, 1, 262144,
3154 up
, NV50_2D_SIFC_FORMAT_R8_UNORM
, 0,
3155 0, 0, p
->exec_size
* 4, 1, 1);
3161 nv50_vertprog_validate(struct nv50_context
*nv50
)
3163 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3164 struct nv50_program
*p
= nv50
->vertprog
;
3165 struct nouveau_stateobj
*so
;
3167 if (!p
->translated
) {
3168 nv50_program_validate(nv50
, p
);
3173 nv50_program_validate_data(nv50
, p
);
3174 nv50_program_validate_code(nv50
, p
);
3177 so_method(so
, tesla
, NV50TCL_VP_ADDRESS_HIGH
, 2);
3178 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3179 NOUVEAU_BO_HIGH
, 0, 0);
3180 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3181 NOUVEAU_BO_LOW
, 0, 0);
3182 so_method(so
, tesla
, NV50TCL_VP_ATTR_EN_0
, 2);
3183 so_data (so
, p
->cfg
.attr
[0]);
3184 so_data (so
, p
->cfg
.attr
[1]);
3185 so_method(so
, tesla
, NV50TCL_VP_REG_ALLOC_RESULT
, 1);
3186 so_data (so
, p
->cfg
.high_result
);
3187 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 2);
3188 so_data (so
, p
->cfg
.high_result
); //8);
3189 so_data (so
, p
->cfg
.high_temp
);
3190 so_method(so
, tesla
, NV50TCL_VP_START_ID
, 1);
3191 so_data (so
, 0); /* program start offset */
3192 so_ref(so
, &nv50
->state
.vertprog
);
3197 nv50_fragprog_validate(struct nv50_context
*nv50
)
3199 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3200 struct nv50_program
*p
= nv50
->fragprog
;
3201 struct nouveau_stateobj
*so
;
3203 if (!p
->translated
) {
3204 nv50_program_validate(nv50
, p
);
3209 nv50_program_validate_data(nv50
, p
);
3210 nv50_program_validate_code(nv50
, p
);
3213 so_method(so
, tesla
, NV50TCL_FP_ADDRESS_HIGH
, 2);
3214 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3215 NOUVEAU_BO_HIGH
, 0, 0);
3216 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3217 NOUVEAU_BO_LOW
, 0, 0);
3218 so_method(so
, tesla
, NV50TCL_FP_REG_ALLOC_TEMP
, 1);
3219 so_data (so
, p
->cfg
.high_temp
);
3220 so_method(so
, tesla
, NV50TCL_FP_RESULT_COUNT
, 1);
3221 so_data (so
, p
->cfg
.high_result
);
3222 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK19A8
, 1);
3223 so_data (so
, p
->cfg
.regs
[2]);
3224 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK196C
, 1);
3225 so_data (so
, p
->cfg
.regs
[3]);
3226 so_method(so
, tesla
, NV50TCL_FP_START_ID
, 1);
3227 so_data (so
, 0); /* program start offset */
3228 so_ref(so
, &nv50
->state
.fragprog
);
3233 nv50_pntc_replace(struct nv50_context
*nv50
, uint32_t pntc
[8], unsigned base
)
3235 struct nv50_program
*fp
= nv50
->fragprog
;
3236 struct nv50_program
*vp
= nv50
->vertprog
;
3237 unsigned i
, c
, m
= base
;
3239 /* XXX: This can't work correctly in all cases yet, we either
3240 * have to create TGSI_SEMANTIC_PNTC or sprite_coord_mode has
3241 * to be per FP input instead of per VP output
3243 memset(pntc
, 0, 8 * sizeof(uint32_t));
3245 for (i
= 0; i
< fp
->cfg
.io_nr
; i
++) {
3247 uint8_t j
= fp
->cfg
.io
[i
].id_vp
, k
= fp
->cfg
.io
[i
].id_fp
;
3248 unsigned n
= popcnt4(fp
->cfg
.io
[i
].mask
);
3250 if (fp
->info
.input_semantic_name
[k
] != TGSI_SEMANTIC_GENERIC
) {
3255 sn
= vp
->info
.input_semantic_name
[j
];
3256 si
= vp
->info
.input_semantic_index
[j
];
3258 if (j
< fp
->cfg
.io_nr
&& sn
== TGSI_SEMANTIC_GENERIC
) {
3260 nv50
->rasterizer
->pipe
.sprite_coord_mode
[si
];
3262 if (mode
== PIPE_SPRITE_COORD_NONE
) {
3268 /* this is either PointCoord or replaced by sprite coords */
3269 for (c
= 0; c
< 4; c
++) {
3270 if (!(fp
->cfg
.io
[i
].mask
& (1 << c
)))
3272 pntc
[m
/ 8] |= (c
+ 1) << ((m
% 8) * 4);
3279 nv50_sreg4_map(uint32_t *p_map
, int mid
, uint32_t lin
[4],
3280 struct nv50_sreg4
*fpi
, struct nv50_sreg4
*vpo
)
3283 uint8_t mv
= vpo
->mask
, mf
= fpi
->mask
, oid
= vpo
->hw
;
3284 uint8_t *map
= (uint8_t *)p_map
;
3286 for (c
= 0; c
< 4; ++c
) {
3288 if (fpi
->linear
== TRUE
)
3289 lin
[mid
/ 32] |= 1 << (mid
% 32);
3290 map
[mid
++] = (mv
& 1) ? oid
: ((c
== 3) ? 0x41 : 0x40);
3302 nv50_linkage_validate(struct nv50_context
*nv50
)
3304 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3305 struct nv50_program
*vp
= nv50
->vertprog
;
3306 struct nv50_program
*fp
= nv50
->fragprog
;
3307 struct nouveau_stateobj
*so
;
3308 struct nv50_sreg4 dummy
, *vpo
;
3310 uint32_t map
[16], lin
[4], reg
[5], pcrd
[8];
3312 memset(map
, 0, sizeof(map
));
3313 memset(lin
, 0, sizeof(lin
));
3315 reg
[1] = 0x00000004; /* low and high clip distance map ids */
3316 reg
[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3317 reg
[3] = 0x00000000; /* point size map id & enable */
3318 reg
[0] = fp
->cfg
.regs
[0]; /* colour semantic reg */
3319 reg
[4] = fp
->cfg
.regs
[1]; /* interpolant info */
3321 dummy
.linear
= FALSE
;
3322 dummy
.mask
= 0xf; /* map all components of HPOS */
3323 m
= nv50_sreg4_map(map
, m
, lin
, &dummy
, &vp
->cfg
.io
[0]);
3327 if (vp
->cfg
.clpd
< 0x40) {
3328 for (c
= 0; c
< vp
->cfg
.clpd_nr
; ++c
)
3329 map
[m
++] = vp
->cfg
.clpd
+ c
;
3333 reg
[0] |= m
<< 8; /* adjust BFC0 id */
3335 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3336 if (nv50
->rasterizer
->pipe
.light_twoside
) {
3337 vpo
= &vp
->cfg
.two_side
[0];
3339 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[0], &vpo
[0]);
3340 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[1], &vpo
[1]);
3343 reg
[0] += m
- 4; /* adjust FFC0 id */
3344 reg
[4] |= m
<< 8; /* set mid where 'normal' FP inputs start */
3347 if (fp
->info
.input_semantic_name
[0] == TGSI_SEMANTIC_POSITION
)
3349 for (; i
< fp
->cfg
.io_nr
; i
++) {
3350 ubyte sn
= fp
->info
.input_semantic_name
[fp
->cfg
.io
[i
].id_fp
];
3351 ubyte si
= fp
->info
.input_semantic_index
[fp
->cfg
.io
[i
].id_fp
];
3353 n
= fp
->cfg
.io
[i
].id_vp
;
3354 if (n
>= vp
->cfg
.io_nr
||
3355 vp
->info
.output_semantic_name
[n
] != sn
||
3356 vp
->info
.output_semantic_index
[n
] != si
)
3359 vpo
= &vp
->cfg
.io
[n
];
3361 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.io
[i
], vpo
);
3364 if (nv50
->rasterizer
->pipe
.point_size_per_vertex
) {
3365 map
[m
/ 4] |= vp
->cfg
.psiz
<< ((m
% 4) * 8);
3366 reg
[3] = (m
++ << 4) | 1;
3369 /* now fill the stateobj */
3373 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 1);
3375 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP(0), n
);
3376 so_datap (so
, map
, n
);
3378 so_method(so
, tesla
, NV50TCL_MAP_SEMANTIC_0
, 4);
3379 so_datap (so
, reg
, 4);
3381 so_method(so
, tesla
, NV50TCL_FP_INTERPOLANT_CTRL
, 1);
3382 so_data (so
, reg
[4]);
3384 so_method(so
, tesla
, 0x1540, 4);
3385 so_datap (so
, lin
, 4);
3387 if (nv50
->rasterizer
->pipe
.point_sprite
) {
3388 nv50_pntc_replace(nv50
, pcrd
, (reg
[4] >> 8) & 0xff);
3390 so_method(so
, tesla
, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3391 so_datap (so
, pcrd
, 8);
3394 so_ref(so
, &nv50
->state
.programs
);
3399 nv50_program_destroy(struct nv50_context
*nv50
, struct nv50_program
*p
)
3401 while (p
->exec_head
) {
3402 struct nv50_program_exec
*e
= p
->exec_head
;
3404 p
->exec_head
= e
->next
;
3407 p
->exec_tail
= NULL
;
3410 nouveau_bo_ref(NULL
, &p
->bo
);
3412 nouveau_resource_free(&p
->data
[0]);