2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
32 #include "nv50_context.h"
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
40 /* ARL - gallium craps itself on progs/vp/arl.txt
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
93 int rhw
; /* result hw for FP outputs, or interpolant index */
94 int acc
; /* instruction where this reg is last read (first insn == 1) */
97 /* arbitrary limits */
98 #define MAX_IF_DEPTH 4
99 #define MAX_LOOP_DEPTH 4
102 struct nv50_program
*p
;
105 struct nv50_reg
*r_temp
[NV50_SU_MAX_TEMP
];
106 struct nv50_reg r_addr
[NV50_SU_MAX_ADDR
];
109 struct nv50_reg
*temp
;
111 struct nv50_reg
*attr
;
113 struct nv50_reg
*result
;
115 struct nv50_reg
*param
;
117 struct nv50_reg
*immd
;
120 struct nv50_reg
**addr
;
123 struct nv50_reg
*temp_temp
[16];
124 unsigned temp_temp_nr
;
126 /* broadcast and destination replacement regs */
127 struct nv50_reg
*r_brdc
;
128 struct nv50_reg
*r_dst
[4];
130 unsigned interp_mode
[32];
131 /* perspective interpolation registers */
132 struct nv50_reg
*iv_p
;
133 struct nv50_reg
*iv_c
;
135 struct nv50_program_exec
*if_cond
;
136 struct nv50_program_exec
*if_insn
[MAX_IF_DEPTH
];
137 struct nv50_program_exec
*br_join
[MAX_IF_DEPTH
];
138 struct nv50_program_exec
*br_loop
[MAX_LOOP_DEPTH
]; /* for BRK branch */
139 int if_lvl
, loop_lvl
;
140 unsigned loop_pos
[MAX_LOOP_DEPTH
];
142 /* current instruction and total number of insns */
150 ctor_reg(struct nv50_reg
*reg
, unsigned type
, int index
, int hw
)
160 static INLINE
unsigned
161 popcnt4(uint32_t val
)
163 static const unsigned cnt
[16]
164 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
165 return cnt
[val
& 0xf];
169 terminate_mbb(struct nv50_pc
*pc
)
173 /* remove records of temporary address register values */
174 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
175 if (pc
->r_addr
[i
].index
< 0)
176 pc
->r_addr
[i
].rhw
= -1;
180 alloc_reg(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
184 if (reg
->type
== P_RESULT
) {
185 if (pc
->p
->cfg
.high_result
< (reg
->hw
+ 1))
186 pc
->p
->cfg
.high_result
= reg
->hw
+ 1;
189 if (reg
->type
!= P_TEMP
)
193 /*XXX: do this here too to catch FP temp-as-attr usage..
194 * not clean, but works */
195 if (pc
->p
->cfg
.high_temp
< (reg
->hw
+ 1))
196 pc
->p
->cfg
.high_temp
= reg
->hw
+ 1;
200 if (reg
->rhw
!= -1) {
201 /* try to allocate temporary with index rhw first */
202 if (!(pc
->r_temp
[reg
->rhw
])) {
203 pc
->r_temp
[reg
->rhw
] = reg
;
205 if (pc
->p
->cfg
.high_temp
< (reg
->rhw
+ 1))
206 pc
->p
->cfg
.high_temp
= reg
->rhw
+ 1;
209 /* make sure we don't get things like $r0 needs to go
210 * in $r1 and $r1 in $r0
212 i
= pc
->result_nr
* 4;
215 for (; i
< NV50_SU_MAX_TEMP
; i
++) {
216 if (!(pc
->r_temp
[i
])) {
219 if (pc
->p
->cfg
.high_temp
< (i
+ 1))
220 pc
->p
->cfg
.high_temp
= i
+ 1;
228 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
229 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
230 * lest we risk temp_temps overwriting regs alloc'd "later".
232 static struct nv50_reg
*
233 alloc_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
)
238 if (dst
&& dst
->type
== P_TEMP
&& dst
->hw
== -1)
241 for (i
= 0; i
< NV50_SU_MAX_TEMP
; i
++) {
242 if (!pc
->r_temp
[i
]) {
243 r
= MALLOC_STRUCT(nv50_reg
);
244 ctor_reg(r
, P_TEMP
, -1, i
);
254 /* Assign the hw of the discarded temporary register src
255 * to the tgsi register dst and free src.
258 assimilate_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
260 assert(src
->index
== -1 && src
->hw
!= -1);
263 pc
->r_temp
[dst
->hw
] = NULL
;
264 pc
->r_temp
[src
->hw
] = dst
;
270 /* release the hardware resource held by r */
272 release_hw(struct nv50_pc
*pc
, struct nv50_reg
*r
)
274 assert(r
->type
== P_TEMP
);
278 assert(pc
->r_temp
[r
->hw
] == r
);
279 pc
->r_temp
[r
->hw
] = NULL
;
287 free_temp(struct nv50_pc
*pc
, struct nv50_reg
*r
)
289 if (r
->index
== -1) {
292 FREE(pc
->r_temp
[hw
]);
293 pc
->r_temp
[hw
] = NULL
;
298 alloc_temp4(struct nv50_pc
*pc
, struct nv50_reg
*dst
[4], int idx
)
302 if ((idx
+ 4) >= NV50_SU_MAX_TEMP
)
305 if (pc
->r_temp
[idx
] || pc
->r_temp
[idx
+ 1] ||
306 pc
->r_temp
[idx
+ 2] || pc
->r_temp
[idx
+ 3])
307 return alloc_temp4(pc
, dst
, idx
+ 4);
309 for (i
= 0; i
< 4; i
++) {
310 dst
[i
] = MALLOC_STRUCT(nv50_reg
);
311 ctor_reg(dst
[i
], P_TEMP
, -1, idx
+ i
);
312 pc
->r_temp
[idx
+ i
] = dst
[i
];
319 free_temp4(struct nv50_pc
*pc
, struct nv50_reg
*reg
[4])
323 for (i
= 0; i
< 4; i
++)
324 free_temp(pc
, reg
[i
]);
327 static struct nv50_reg
*
328 temp_temp(struct nv50_pc
*pc
)
330 if (pc
->temp_temp_nr
>= 16)
333 pc
->temp_temp
[pc
->temp_temp_nr
] = alloc_temp(pc
, NULL
);
334 return pc
->temp_temp
[pc
->temp_temp_nr
++];
338 kill_temp_temp(struct nv50_pc
*pc
)
342 for (i
= 0; i
< pc
->temp_temp_nr
; i
++)
343 free_temp(pc
, pc
->temp_temp
[i
]);
344 pc
->temp_temp_nr
= 0;
348 ctor_immd(struct nv50_pc
*pc
, float x
, float y
, float z
, float w
)
350 pc
->immd_buf
= REALLOC(pc
->immd_buf
, (pc
->immd_nr
* 4 * sizeof(float)),
351 (pc
->immd_nr
+ 1) * 4 * sizeof(float));
352 pc
->immd_buf
[(pc
->immd_nr
* 4) + 0] = x
;
353 pc
->immd_buf
[(pc
->immd_nr
* 4) + 1] = y
;
354 pc
->immd_buf
[(pc
->immd_nr
* 4) + 2] = z
;
355 pc
->immd_buf
[(pc
->immd_nr
* 4) + 3] = w
;
357 return pc
->immd_nr
++;
360 static struct nv50_reg
*
361 alloc_immd(struct nv50_pc
*pc
, float f
)
363 struct nv50_reg
*r
= MALLOC_STRUCT(nv50_reg
);
366 for (hw
= 0; hw
< pc
->immd_nr
* 4; hw
++)
367 if (pc
->immd_buf
[hw
] == f
)
370 if (hw
== pc
->immd_nr
* 4)
371 hw
= ctor_immd(pc
, f
, -f
, 0.5 * f
, 0) * 4;
373 ctor_reg(r
, P_IMMD
, -1, hw
);
377 static struct nv50_program_exec
*
378 exec(struct nv50_pc
*pc
)
380 struct nv50_program_exec
*e
= CALLOC_STRUCT(nv50_program_exec
);
387 emit(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
389 struct nv50_program
*p
= pc
->p
;
392 p
->exec_tail
->next
= e
;
396 p
->exec_size
+= (e
->inst
[0] & 1) ? 2 : 1;
399 static INLINE
void set_long(struct nv50_pc
*, struct nv50_program_exec
*);
402 is_long(struct nv50_program_exec
*e
)
410 is_immd(struct nv50_program_exec
*e
)
412 if (is_long(e
) && (e
->inst
[1] & 3) == 3)
418 set_pred(struct nv50_pc
*pc
, unsigned pred
, unsigned idx
,
419 struct nv50_program_exec
*e
)
422 e
->inst
[1] &= ~((0x1f << 7) | (0x3 << 12));
423 e
->inst
[1] |= (pred
<< 7) | (idx
<< 12);
427 set_pred_wr(struct nv50_pc
*pc
, unsigned on
, unsigned idx
,
428 struct nv50_program_exec
*e
)
431 e
->inst
[1] &= ~((0x3 << 4) | (1 << 6));
432 e
->inst
[1] |= (idx
<< 4) | (on
<< 6);
436 set_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
442 set_pred(pc
, 0xf, 0, e
);
443 set_pred_wr(pc
, 0, 0, e
);
447 set_dst(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_program_exec
*e
)
449 if (dst
->type
== P_RESULT
) {
451 e
->inst
[1] |= 0x00000008;
457 e
->inst
[0] |= (dst
->hw
<< 2);
461 set_immd(struct nv50_pc
*pc
, struct nv50_reg
*imm
, struct nv50_program_exec
*e
)
463 float f
= pc
->immd_buf
[imm
->hw
];
464 unsigned val
= fui(imm
->neg
? -f
: f
);
467 /*XXX: can't be predicated - bits overlap.. catch cases where both
468 * are required and avoid them. */
469 set_pred(pc
, 0, 0, e
);
470 set_pred_wr(pc
, 0, 0, e
);
472 e
->inst
[1] |= 0x00000002 | 0x00000001;
473 e
->inst
[0] |= (val
& 0x3f) << 16;
474 e
->inst
[1] |= (val
>> 6) << 2;
478 set_addr(struct nv50_program_exec
*e
, struct nv50_reg
*a
)
480 assert(!(e
->inst
[0] & 0x0c000000));
481 assert(!(e
->inst
[1] & 0x00000004));
483 e
->inst
[0] |= (a
->hw
& 3) << 26;
484 e
->inst
[1] |= (a
->hw
>> 2) << 2;
488 emit_add_addr_imm(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
489 struct nv50_reg
*src0
, uint16_t src1_val
)
491 struct nv50_program_exec
*e
= exec(pc
);
493 e
->inst
[0] = 0xd0000000 | (src1_val
<< 9);
494 e
->inst
[1] = 0x20000000;
496 e
->inst
[0] |= dst
->hw
<< 2;
497 if (src0
) /* otherwise will add to $a0, which is always 0 */
503 static struct nv50_reg
*
504 alloc_addr(struct nv50_pc
*pc
, struct nv50_reg
*ref
)
507 struct nv50_reg
*a_tgsi
= NULL
, *a
= NULL
;
510 /* allocate for TGSI address reg */
511 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
) {
512 if (pc
->r_addr
[i
].index
>= 0)
514 if (pc
->r_addr
[i
].rhw
>= 0 &&
515 pc
->r_addr
[i
].acc
== pc
->insn_cur
)
518 pc
->r_addr
[i
].rhw
= -1;
519 pc
->r_addr
[i
].index
= i
;
520 return &pc
->r_addr
[i
];
526 /* Allocate and set an address reg so we can access 'ref'.
528 * If and r_addr has index < 0, it is not reserved for TGSI,
529 * and index will be the negative of the TGSI addr index the
530 * value in rhw is relative to, or -256 if rhw is an offset
531 * from 0. If rhw < 0, the reg has not been initialized.
533 for (i
= NV50_SU_MAX_ADDR
- 1; i
>= 0; --i
) {
534 if (pc
->r_addr
[i
].index
>= 0) /* occupied for TGSI */
536 if (pc
->r_addr
[i
].rhw
< 0) { /* unused */
540 if (!a
&& pc
->r_addr
[i
].acc
!= pc
->insn_cur
)
543 if (ref
->hw
- pc
->r_addr
[i
].rhw
>= 128)
546 if ((ref
->acc
>= 0 && pc
->r_addr
[i
].index
== -256) ||
547 (ref
->acc
< 0 && -pc
->r_addr
[i
].index
== ref
->index
)) {
548 pc
->r_addr
[i
].acc
= pc
->insn_cur
;
549 return &pc
->r_addr
[i
];
555 a_tgsi
= pc
->addr
[ref
->index
];
557 emit_add_addr_imm(pc
, a
, a_tgsi
, (ref
->hw
& ~0x7f) * 4);
559 a
->rhw
= ref
->hw
& ~0x7f;
560 a
->acc
= pc
->insn_cur
;
561 a
->index
= a_tgsi
? -ref
->index
: -256;
565 #define INTERP_LINEAR 0
566 #define INTERP_FLAT 1
567 #define INTERP_PERSPECTIVE 2
568 #define INTERP_CENTROID 4
570 /* interpolant index has been stored in dst->rhw */
572 emit_interp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*iv
,
575 assert(dst
->rhw
!= -1);
576 struct nv50_program_exec
*e
= exec(pc
);
578 e
->inst
[0] |= 0x80000000;
580 e
->inst
[0] |= (dst
->rhw
<< 16);
582 if (mode
& INTERP_FLAT
) {
583 e
->inst
[0] |= (1 << 8);
585 if (mode
& INTERP_PERSPECTIVE
) {
586 e
->inst
[0] |= (1 << 25);
588 e
->inst
[0] |= (iv
->hw
<< 9);
591 if (mode
& INTERP_CENTROID
)
592 e
->inst
[0] |= (1 << 24);
599 set_data(struct nv50_pc
*pc
, struct nv50_reg
*src
, unsigned m
, unsigned s
,
600 struct nv50_program_exec
*e
)
604 e
->param
.index
= src
->hw
& 127;
606 e
->param
.mask
= m
<< (s
% 32);
609 set_addr(e
, alloc_addr(pc
, src
));
612 assert(src
->type
== P_CONST
);
613 set_addr(e
, pc
->addr
[src
->index
]);
616 e
->inst
[1] |= (((src
->type
== P_IMMD
) ? 0 : 1) << 22);
620 emit_mov(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
622 struct nv50_program_exec
*e
= exec(pc
);
624 e
->inst
[0] = 0x10000000;
630 if (!is_long(e
) && src
->type
== P_IMMD
) {
631 set_immd(pc
, src
, e
);
632 /*XXX: 32-bit, but steals part of "half" reg space - need to
633 * catch and handle this case if/when we do half-regs
636 if (src
->type
== P_IMMD
|| src
->type
== P_CONST
) {
638 set_data(pc
, src
, 0x7f, 9, e
);
639 e
->inst
[1] |= 0x20000000; /* src0 const? */
641 if (src
->type
== P_ATTR
) {
643 e
->inst
[1] |= 0x00200000;
649 e
->inst
[0] |= (src
->hw
<< 9);
652 if (is_long(e
) && !is_immd(e
)) {
653 e
->inst
[1] |= 0x04000000; /* 32-bit */
654 e
->inst
[1] |= 0x0000c000; /* "subsubop" 0x3 */
655 if (!(e
->inst
[1] & 0x20000000))
656 e
->inst
[1] |= 0x00030000; /* "subsubop" 0xf */
658 e
->inst
[0] |= 0x00008000;
664 emit_mov_immdval(struct nv50_pc
*pc
, struct nv50_reg
*dst
, float f
)
666 struct nv50_reg
*imm
= alloc_immd(pc
, f
);
667 emit_mov(pc
, dst
, imm
);
672 check_swap_src_0_1(struct nv50_pc
*pc
,
673 struct nv50_reg
**s0
, struct nv50_reg
**s1
)
675 struct nv50_reg
*src0
= *s0
, *src1
= *s1
;
677 if (src0
->type
== P_CONST
) {
678 if (src1
->type
!= P_CONST
) {
684 if (src1
->type
== P_ATTR
) {
685 if (src0
->type
!= P_ATTR
) {
696 set_src_0_restricted(struct nv50_pc
*pc
, struct nv50_reg
*src
,
697 struct nv50_program_exec
*e
)
699 struct nv50_reg
*temp
;
701 if (src
->type
!= P_TEMP
) {
702 temp
= temp_temp(pc
);
703 emit_mov(pc
, temp
, src
);
710 e
->inst
[0] |= (src
->hw
<< 9);
714 set_src_0(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
716 if (src
->type
== P_ATTR
) {
718 e
->inst
[1] |= 0x00200000;
720 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
721 struct nv50_reg
*temp
= temp_temp(pc
);
723 emit_mov(pc
, temp
, src
);
730 e
->inst
[0] |= (src
->hw
<< 9);
734 set_src_1(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
736 if (src
->type
== P_ATTR
) {
737 struct nv50_reg
*temp
= temp_temp(pc
);
739 emit_mov(pc
, temp
, src
);
742 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
743 assert(!(e
->inst
[0] & 0x00800000));
744 if (e
->inst
[0] & 0x01000000) {
745 struct nv50_reg
*temp
= temp_temp(pc
);
747 emit_mov(pc
, temp
, src
);
750 set_data(pc
, src
, 0x7f, 16, e
);
751 e
->inst
[0] |= 0x00800000;
758 e
->inst
[0] |= ((src
->hw
& 127) << 16);
762 set_src_2(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
766 if (src
->type
== P_ATTR
) {
767 struct nv50_reg
*temp
= temp_temp(pc
);
769 emit_mov(pc
, temp
, src
);
772 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
773 assert(!(e
->inst
[0] & 0x01000000));
774 if (e
->inst
[0] & 0x00800000) {
775 struct nv50_reg
*temp
= temp_temp(pc
);
777 emit_mov(pc
, temp
, src
);
780 set_data(pc
, src
, 0x7f, 32+14, e
);
781 e
->inst
[0] |= 0x01000000;
786 e
->inst
[1] |= ((src
->hw
& 127) << 14);
790 emit_mul(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
791 struct nv50_reg
*src1
)
793 struct nv50_program_exec
*e
= exec(pc
);
795 e
->inst
[0] |= 0xc0000000;
800 check_swap_src_0_1(pc
, &src0
, &src1
);
802 set_src_0(pc
, src0
, e
);
803 if (src1
->type
== P_IMMD
&& !is_long(e
)) {
805 e
->inst
[0] |= 0x00008000;
806 set_immd(pc
, src1
, e
);
808 set_src_1(pc
, src1
, e
);
809 if (src0
->neg
^ src1
->neg
) {
811 e
->inst
[1] |= 0x08000000;
813 e
->inst
[0] |= 0x00008000;
821 emit_add(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
822 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
824 struct nv50_program_exec
*e
= exec(pc
);
826 e
->inst
[0] = 0xb0000000;
829 check_swap_src_0_1(pc
, &src0
, &src1
);
831 if (!pc
->allow32
|| (src0
->neg
| src1
->neg
) || src1
->hw
> 63) {
833 e
->inst
[1] |= (src0
->neg
<< 26) | (src1
->neg
<< 27);
837 set_src_0(pc
, src0
, e
);
838 if (src1
->type
== P_CONST
|| src1
->type
== P_ATTR
|| is_long(e
))
839 set_src_2(pc
, src1
, e
);
841 if (src1
->type
== P_IMMD
)
842 set_immd(pc
, src1
, e
);
844 set_src_1(pc
, src1
, e
);
850 emit_arl(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
853 struct nv50_program_exec
*e
= exec(pc
);
856 e
->inst
[1] |= 0xc0000000;
858 e
->inst
[0] |= dst
->hw
<< 2;
859 e
->inst
[0] |= s
<< 16; /* shift left */
860 set_src_0_restricted(pc
, src
, e
);
866 emit_minmax(struct nv50_pc
*pc
, unsigned sub
, struct nv50_reg
*dst
,
867 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
869 struct nv50_program_exec
*e
= exec(pc
);
872 e
->inst
[0] |= 0xb0000000;
873 e
->inst
[1] |= (sub
<< 29);
875 check_swap_src_0_1(pc
, &src0
, &src1
);
877 set_src_0(pc
, src0
, e
);
878 set_src_1(pc
, src1
, e
);
884 emit_sub(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
885 struct nv50_reg
*src1
)
887 assert(src0
!= src1
);
889 emit_add(pc
, dst
, src0
, src1
);
894 emit_mad(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
895 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
897 struct nv50_program_exec
*e
= exec(pc
);
899 e
->inst
[0] |= 0xe0000000;
901 check_swap_src_0_1(pc
, &src0
, &src1
);
903 set_src_0(pc
, src0
, e
);
904 set_src_1(pc
, src1
, e
);
905 set_src_2(pc
, src2
, e
);
907 if (src0
->neg
^ src1
->neg
)
908 e
->inst
[1] |= 0x04000000;
910 e
->inst
[1] |= 0x08000000;
916 emit_msb(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
917 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
919 assert(src2
!= src0
&& src2
!= src1
);
921 emit_mad(pc
, dst
, src0
, src1
, src2
);
926 emit_flop(struct nv50_pc
*pc
, unsigned sub
,
927 struct nv50_reg
*dst
, struct nv50_reg
*src
)
929 struct nv50_program_exec
*e
= exec(pc
);
931 e
->inst
[0] |= 0x90000000;
934 e
->inst
[1] |= (sub
<< 29);
939 if (sub
== 0 || sub
== 2)
940 set_src_0_restricted(pc
, src
, e
);
942 set_src_0(pc
, src
, e
);
948 emit_preex2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
950 struct nv50_program_exec
*e
= exec(pc
);
952 e
->inst
[0] |= 0xb0000000;
955 set_src_0(pc
, src
, e
);
957 e
->inst
[1] |= (6 << 29) | 0x00004000;
963 emit_precossin(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
965 struct nv50_program_exec
*e
= exec(pc
);
967 e
->inst
[0] |= 0xb0000000;
970 set_src_0(pc
, src
, e
);
972 e
->inst
[1] |= (6 << 29);
977 #define CVTOP_RN 0x01
978 #define CVTOP_FLOOR 0x03
979 #define CVTOP_CEIL 0x05
980 #define CVTOP_TRUNC 0x07
981 #define CVTOP_SAT 0x08
982 #define CVTOP_ABS 0x10
984 /* 0x04 == 32 bit dst */
985 /* 0x40 == dst is float */
986 /* 0x80 == src is float */
987 #define CVT_F32_F32 0xc4
988 #define CVT_F32_S32 0x44
989 #define CVT_S32_F32 0x8c
990 #define CVT_S32_S32 0x0c
995 emit_cvt(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
996 int wp
, unsigned cvn
, unsigned fmt
)
998 struct nv50_program_exec
*e
;
1003 e
->inst
[0] |= 0xa0000000;
1004 e
->inst
[1] |= 0x00004000; /* 32 bit src */
1005 e
->inst
[1] |= (cvn
<< 16);
1006 e
->inst
[1] |= (fmt
<< 24);
1007 set_src_0(pc
, src
, e
);
1010 set_pred_wr(pc
, 1, wp
, e
);
1013 set_dst(pc
, dst
, e
);
1015 e
->inst
[0] |= 0x000001fc;
1016 e
->inst
[1] |= 0x00000008;
1022 /* nv50 Condition codes:
1029 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1030 * 0x8 = unordered bit (allows NaN)
1033 emit_set(struct nv50_pc
*pc
, unsigned ccode
, struct nv50_reg
*dst
, int wp
,
1034 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
1036 static const unsigned cc_swapped
[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1038 struct nv50_program_exec
*e
= exec(pc
);
1039 struct nv50_reg
*rdst
;
1042 if (check_swap_src_0_1(pc
, &src0
, &src1
))
1043 ccode
= cc_swapped
[ccode
& 7] | (ccode
& 8);
1046 if (dst
&& dst
->type
!= P_TEMP
)
1047 dst
= alloc_temp(pc
, NULL
);
1051 e
->inst
[0] |= 0xb0000000;
1052 e
->inst
[1] |= 0x60000000 | (ccode
<< 14);
1054 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1055 * that doesn't seem to match what the hw actually does
1056 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1060 set_pred_wr(pc
, 1, wp
, e
);
1062 set_dst(pc
, dst
, e
);
1064 e
->inst
[0] |= 0x000001fc;
1065 e
->inst
[1] |= 0x00000008;
1068 set_src_0(pc
, src0
, e
);
1069 set_src_1(pc
, src1
, e
);
1072 pc
->if_cond
= pc
->p
->exec_tail
; /* record for OPCODE_IF */
1074 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1076 emit_cvt(pc
, rdst
, dst
, -1, CVTOP_ABS
| CVTOP_RN
, CVT_F32_S32
);
1077 if (rdst
&& rdst
!= dst
)
1081 static INLINE
unsigned
1082 map_tgsi_setop_cc(unsigned op
)
1085 case TGSI_OPCODE_SLT
: return 0x1;
1086 case TGSI_OPCODE_SGE
: return 0x6;
1087 case TGSI_OPCODE_SEQ
: return 0x2;
1088 case TGSI_OPCODE_SGT
: return 0x4;
1089 case TGSI_OPCODE_SLE
: return 0x3;
1090 case TGSI_OPCODE_SNE
: return 0xd;
1098 emit_flr(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1100 emit_cvt(pc
, dst
, src
, -1, CVTOP_FLOOR
, CVT_F32_F32
| CVT_RI
);
1104 emit_pow(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1105 struct nv50_reg
*v
, struct nv50_reg
*e
)
1107 struct nv50_reg
*temp
= alloc_temp(pc
, NULL
);
1109 emit_flop(pc
, 3, temp
, v
);
1110 emit_mul(pc
, temp
, temp
, e
);
1111 emit_preex2(pc
, temp
, temp
);
1112 emit_flop(pc
, 6, dst
, temp
);
1114 free_temp(pc
, temp
);
1118 emit_abs(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1120 emit_cvt(pc
, dst
, src
, -1, CVTOP_ABS
, CVT_F32_F32
);
1124 emit_sat(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1126 emit_cvt(pc
, dst
, src
, -1, CVTOP_SAT
, CVT_F32_F32
);
1130 emit_lit(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1131 struct nv50_reg
**src
)
1133 struct nv50_reg
*one
= alloc_immd(pc
, 1.0);
1134 struct nv50_reg
*zero
= alloc_immd(pc
, 0.0);
1135 struct nv50_reg
*neg128
= alloc_immd(pc
, -127.999999);
1136 struct nv50_reg
*pos128
= alloc_immd(pc
, 127.999999);
1137 struct nv50_reg
*tmp
[4];
1138 boolean allow32
= pc
->allow32
;
1140 pc
->allow32
= FALSE
;
1142 if (mask
& (3 << 1)) {
1143 tmp
[0] = alloc_temp(pc
, NULL
);
1144 emit_minmax(pc
, 4, tmp
[0], src
[0], zero
);
1147 if (mask
& (1 << 2)) {
1148 set_pred_wr(pc
, 1, 0, pc
->p
->exec_tail
);
1150 tmp
[1] = temp_temp(pc
);
1151 emit_minmax(pc
, 4, tmp
[1], src
[1], zero
);
1153 tmp
[3] = temp_temp(pc
);
1154 emit_minmax(pc
, 4, tmp
[3], src
[3], neg128
);
1155 emit_minmax(pc
, 5, tmp
[3], tmp
[3], pos128
);
1157 emit_pow(pc
, dst
[2], tmp
[1], tmp
[3]);
1158 emit_mov(pc
, dst
[2], zero
);
1159 set_pred(pc
, 3, 0, pc
->p
->exec_tail
);
1162 if (mask
& (1 << 1))
1163 assimilate_temp(pc
, dst
[1], tmp
[0]);
1165 if (mask
& (1 << 2))
1166 free_temp(pc
, tmp
[0]);
1168 pc
->allow32
= allow32
;
1170 /* do this last, in case src[i,j] == dst[0,3] */
1171 if (mask
& (1 << 0))
1172 emit_mov(pc
, dst
[0], one
);
1174 if (mask
& (1 << 3))
1175 emit_mov(pc
, dst
[3], one
);
1184 emit_neg(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1186 emit_cvt(pc
, dst
, src
, -1, CVTOP_RN
, CVT_F32_F32
| CVT_NEG
);
1190 emit_kil(struct nv50_pc
*pc
, struct nv50_reg
*src
)
1192 struct nv50_program_exec
*e
;
1193 const int r_pred
= 1;
1194 unsigned cvn
= CVT_F32_F32
;
1198 /* write predicate reg */
1199 emit_cvt(pc
, NULL
, src
, r_pred
, CVTOP_RN
, cvn
);
1201 /* conditional discard */
1203 e
->inst
[0] = 0x00000002;
1205 set_pred(pc
, 0x1 /* LT */, r_pred
, e
);
1210 emit_tex(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1211 struct nv50_reg
**src
, unsigned unit
, unsigned type
, boolean proj
)
1213 struct nv50_reg
*temp
, *t
[4];
1214 struct nv50_program_exec
*e
;
1216 unsigned c
, mode
, dim
;
1219 case TGSI_TEXTURE_1D
:
1222 case TGSI_TEXTURE_UNKNOWN
:
1223 case TGSI_TEXTURE_2D
:
1224 case TGSI_TEXTURE_SHADOW1D
: /* XXX: x, z */
1225 case TGSI_TEXTURE_RECT
:
1228 case TGSI_TEXTURE_3D
:
1229 case TGSI_TEXTURE_CUBE
:
1230 case TGSI_TEXTURE_SHADOW2D
:
1231 case TGSI_TEXTURE_SHADOWRECT
: /* XXX */
1239 /* some cards need t[0]'s hw index to be a multiple of 4 */
1240 alloc_temp4(pc
, t
, 0);
1243 if (src
[0]->type
== P_TEMP
&& src
[0]->rhw
!= -1) {
1244 mode
= pc
->interp_mode
[src
[0]->index
];
1246 t
[3]->rhw
= src
[3]->rhw
;
1247 emit_interp(pc
, t
[3], NULL
, (mode
& INTERP_CENTROID
));
1248 emit_flop(pc
, 0, t
[3], t
[3]);
1250 for (c
= 0; c
< dim
; c
++) {
1251 t
[c
]->rhw
= src
[c
]->rhw
;
1252 emit_interp(pc
, t
[c
], t
[3],
1253 (mode
| INTERP_PERSPECTIVE
));
1256 emit_flop(pc
, 0, t
[3], src
[3]);
1257 for (c
= 0; c
< dim
; c
++)
1258 emit_mul(pc
, t
[c
], src
[c
], t
[3]);
1260 /* XXX: for some reason the blob sometimes uses MAD:
1261 * emit_mad(pc, t[c], src[0][c], t[3], t[3])
1262 * pc->p->exec_tail->inst[1] |= 0x080fc000;
1266 if (type
== TGSI_TEXTURE_CUBE
) {
1267 temp
= temp_temp(pc
);
1268 emit_minmax(pc
, 4, temp
, src
[0], src
[1]);
1269 emit_minmax(pc
, 4, temp
, temp
, src
[2]);
1270 emit_flop(pc
, 0, temp
, temp
);
1271 for (c
= 0; c
< 3; c
++)
1272 emit_mul(pc
, t
[c
], src
[c
], temp
);
1274 for (c
= 0; c
< dim
; c
++)
1275 emit_mov(pc
, t
[c
], src
[c
]);
1281 e
->inst
[0] |= 0xf0000000;
1282 e
->inst
[1] |= 0x00000004;
1283 set_dst(pc
, t
[0], e
);
1284 e
->inst
[0] |= (unit
<< 9);
1287 e
->inst
[0] |= 0x00400000;
1290 e
->inst
[0] |= 0x00800000;
1292 e
->inst
[0] |= (mask
& 0x3) << 25;
1293 e
->inst
[1] |= (mask
& 0xc) << 12;
1299 if (mask
& 1) emit_mov(pc
, dst
[0], t
[c
++]);
1300 if (mask
& 2) emit_mov(pc
, dst
[1], t
[c
++]);
1301 if (mask
& 4) emit_mov(pc
, dst
[2], t
[c
++]);
1302 if (mask
& 8) emit_mov(pc
, dst
[3], t
[c
]);
1306 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1307 * the texture coordinates, not the fetched values: latency ? */
1309 for (c
= 0; c
< 4; c
++) {
1310 if (mask
& (1 << c
))
1311 assimilate_temp(pc
, dst
[c
], t
[c
]);
1313 free_temp(pc
, t
[c
]);
1319 emit_branch(struct nv50_pc
*pc
, int pred
, unsigned cc
,
1320 struct nv50_program_exec
**join
)
1322 struct nv50_program_exec
*e
= exec(pc
);
1326 e
->inst
[0] |= 0xa0000002;
1333 e
->inst
[0] |= 0x10000002;
1335 set_pred(pc
, cc
, pred
, e
);
1340 emit_nop(struct nv50_pc
*pc
)
1342 struct nv50_program_exec
*e
= exec(pc
);
1344 e
->inst
[0] = 0xf0000000;
1346 e
->inst
[1] = 0xe0000000;
1351 emit_ddx(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1353 struct nv50_program_exec
*e
= exec(pc
);
1355 assert(src
->type
== P_TEMP
);
1357 e
->inst
[0] = 0xc0140000;
1358 e
->inst
[1] = 0x89800000;
1360 set_dst(pc
, dst
, e
);
1361 set_src_0(pc
, src
, e
);
1362 set_src_2(pc
, src
, e
);
1368 emit_ddy(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1370 struct nv50_program_exec
*e
= exec(pc
);
1372 assert(src
->type
== P_TEMP
);
1374 if (!src
->neg
) /* ! double negation */
1375 emit_neg(pc
, src
, src
);
1377 e
->inst
[0] = 0xc0150000;
1378 e
->inst
[1] = 0x8a400000;
1380 set_dst(pc
, dst
, e
);
1381 set_src_0(pc
, src
, e
);
1382 set_src_2(pc
, src
, e
);
1388 convert_to_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
1390 unsigned q
= 0, m
= ~0;
1392 assert(!is_long(e
));
1394 switch (e
->inst
[0] >> 28) {
1401 /* INTERP (move centroid, perspective and flat bits) */
1403 q
= (e
->inst
[0] & (3 << 24)) >> (24 - 16);
1404 q
|= (e
->inst
[0] & (1 << 8)) << (18 - 8);
1412 q
= ((e
->inst
[0] & (~m
)) >> 2);
1417 q
= ((e
->inst
[0] & (~m
)) << 12);
1420 /* MAD (if src2 == dst) */
1421 q
= ((e
->inst
[0] & 0x1fc) << 12);
1435 /* Some operations support an optional negation flag. */
1437 negate_supported(const struct tgsi_full_instruction
*insn
, int i
)
1441 switch (insn
->Instruction
.Opcode
) {
1442 case TGSI_OPCODE_DDY
:
1443 case TGSI_OPCODE_DP3
:
1444 case TGSI_OPCODE_DP4
:
1445 case TGSI_OPCODE_MUL
:
1446 case TGSI_OPCODE_KIL
:
1447 case TGSI_OPCODE_ADD
:
1448 case TGSI_OPCODE_SUB
:
1449 case TGSI_OPCODE_MAD
:
1451 case TGSI_OPCODE_POW
:
1459 /* Watch out for possible multiple uses of an nv50_reg, we
1460 * can't use nv50_reg::neg in these cases.
1462 for (s
= 0; s
< insn
->Instruction
.NumSrcRegs
; ++s
) {
1465 if ((insn
->FullSrcRegisters
[s
].SrcRegister
.Index
==
1466 insn
->FullSrcRegisters
[i
].SrcRegister
.Index
) &&
1467 (insn
->FullSrcRegisters
[s
].SrcRegister
.File
==
1468 insn
->FullSrcRegisters
[i
].SrcRegister
.File
))
1475 /* Return a read mask for source registers deduced from opcode & write mask. */
1477 nv50_tgsi_src_mask(const struct tgsi_full_instruction
*insn
, int c
)
1479 unsigned x
, mask
= insn
->FullDstRegisters
[0].DstRegister
.WriteMask
;
1481 switch (insn
->Instruction
.Opcode
) {
1482 case TGSI_OPCODE_COS
:
1483 case TGSI_OPCODE_SIN
:
1484 return (mask
& 0x8) | ((mask
& 0x7) ? 0x1 : 0x0);
1485 case TGSI_OPCODE_DP3
:
1487 case TGSI_OPCODE_DP4
:
1488 case TGSI_OPCODE_DPH
:
1489 case TGSI_OPCODE_KIL
: /* WriteMask ignored */
1491 case TGSI_OPCODE_DST
:
1492 return mask
& (c
? 0xa : 0x6);
1493 case TGSI_OPCODE_EX2
:
1494 case TGSI_OPCODE_LG2
:
1495 case TGSI_OPCODE_POW
:
1496 case TGSI_OPCODE_RCP
:
1497 case TGSI_OPCODE_RSQ
:
1498 case TGSI_OPCODE_SCS
:
1500 case TGSI_OPCODE_LIT
:
1502 case TGSI_OPCODE_TEX
:
1503 case TGSI_OPCODE_TXP
:
1505 const struct tgsi_instruction_ext_texture
*tex
;
1507 assert(insn
->Instruction
.Extended
);
1508 tex
= &insn
->InstructionExtTexture
;
1511 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_TXP
)
1514 switch (tex
->Texture
) {
1515 case TGSI_TEXTURE_1D
:
1518 case TGSI_TEXTURE_2D
:
1526 case TGSI_OPCODE_XPD
:
1528 if (mask
& 1) x
|= 0x6;
1529 if (mask
& 2) x
|= 0x5;
1530 if (mask
& 4) x
|= 0x3;
1539 static struct nv50_reg
*
1540 tgsi_dst(struct nv50_pc
*pc
, int c
, const struct tgsi_full_dst_register
*dst
)
1542 switch (dst
->DstRegister
.File
) {
1543 case TGSI_FILE_TEMPORARY
:
1544 return &pc
->temp
[dst
->DstRegister
.Index
* 4 + c
];
1545 case TGSI_FILE_OUTPUT
:
1546 return &pc
->result
[dst
->DstRegister
.Index
* 4 + c
];
1547 case TGSI_FILE_ADDRESS
:
1549 struct nv50_reg
*r
= pc
->addr
[dst
->DstRegister
.Index
* 4 + c
];
1551 r
= alloc_addr(pc
, NULL
);
1552 pc
->addr
[dst
->DstRegister
.Index
* 4 + c
] = r
;
1557 case TGSI_FILE_NULL
:
1566 static struct nv50_reg
*
1567 tgsi_src(struct nv50_pc
*pc
, int chan
, const struct tgsi_full_src_register
*src
,
1570 struct nv50_reg
*r
= NULL
;
1571 struct nv50_reg
*temp
;
1572 unsigned sgn
, c
, swz
;
1574 if (src
->SrcRegister
.File
!= TGSI_FILE_CONSTANT
)
1575 assert(!src
->SrcRegister
.Indirect
);
1577 sgn
= tgsi_util_get_full_src_register_sign_mode(src
, chan
);
1579 c
= tgsi_util_get_full_src_register_swizzle(src
, chan
);
1581 case TGSI_SWIZZLE_X
:
1582 case TGSI_SWIZZLE_Y
:
1583 case TGSI_SWIZZLE_Z
:
1584 case TGSI_SWIZZLE_W
:
1585 switch (src
->SrcRegister
.File
) {
1586 case TGSI_FILE_INPUT
:
1587 r
= &pc
->attr
[src
->SrcRegister
.Index
* 4 + c
];
1589 case TGSI_FILE_TEMPORARY
:
1590 r
= &pc
->temp
[src
->SrcRegister
.Index
* 4 + c
];
1592 case TGSI_FILE_CONSTANT
:
1593 if (!src
->SrcRegister
.Indirect
) {
1594 r
= &pc
->param
[src
->SrcRegister
.Index
* 4 + c
];
1597 /* Indicate indirection by setting r->acc < 0 and
1598 * use the index field to select the address reg.
1600 r
= MALLOC_STRUCT(nv50_reg
);
1601 swz
= tgsi_util_get_src_register_swizzle(
1602 &src
->SrcRegisterInd
, 0);
1603 ctor_reg(r
, P_CONST
,
1604 src
->SrcRegisterInd
.Index
* 4 + swz
,
1605 src
->SrcRegister
.Index
* 4 + c
);
1608 case TGSI_FILE_IMMEDIATE
:
1609 r
= &pc
->immd
[src
->SrcRegister
.Index
* 4 + c
];
1611 case TGSI_FILE_SAMPLER
:
1613 case TGSI_FILE_ADDRESS
:
1614 r
= pc
->addr
[src
->SrcRegister
.Index
* 4 + c
];
1628 case TGSI_UTIL_SIGN_KEEP
:
1630 case TGSI_UTIL_SIGN_CLEAR
:
1631 temp
= temp_temp(pc
);
1632 emit_abs(pc
, temp
, r
);
1635 case TGSI_UTIL_SIGN_TOGGLE
:
1639 temp
= temp_temp(pc
);
1640 emit_neg(pc
, temp
, r
);
1644 case TGSI_UTIL_SIGN_SET
:
1645 temp
= temp_temp(pc
);
1646 emit_cvt(pc
, temp
, r
, -1, CVTOP_ABS
, CVT_F32_F32
| CVT_NEG
);
1657 /* return TRUE for ops that produce only a single result */
1659 is_scalar_op(unsigned op
)
1662 case TGSI_OPCODE_COS
:
1663 case TGSI_OPCODE_DP2
:
1664 case TGSI_OPCODE_DP3
:
1665 case TGSI_OPCODE_DP4
:
1666 case TGSI_OPCODE_DPH
:
1667 case TGSI_OPCODE_EX2
:
1668 case TGSI_OPCODE_LG2
:
1669 case TGSI_OPCODE_POW
:
1670 case TGSI_OPCODE_RCP
:
1671 case TGSI_OPCODE_RSQ
:
1672 case TGSI_OPCODE_SIN
:
1674 case TGSI_OPCODE_KIL:
1675 case TGSI_OPCODE_LIT:
1676 case TGSI_OPCODE_SCS:
1684 /* Returns a bitmask indicating which dst components depend
1685 * on source s, component c (reverse of nv50_tgsi_src_mask).
1688 nv50_tgsi_dst_revdep(unsigned op
, int s
, int c
)
1690 if (is_scalar_op(op
))
1694 case TGSI_OPCODE_DST
:
1695 return (1 << c
) & (s
? 0xa : 0x6);
1696 case TGSI_OPCODE_XPD
:
1706 case TGSI_OPCODE_LIT
:
1707 case TGSI_OPCODE_SCS
:
1708 case TGSI_OPCODE_TEX
:
1709 case TGSI_OPCODE_TXP
:
1710 /* these take care of dangerous swizzles themselves */
1712 case TGSI_OPCODE_IF
:
1713 case TGSI_OPCODE_KIL
:
1714 /* don't call this function for these ops */
1718 /* linear vector instruction */
1723 static INLINE boolean
1724 has_pred(struct nv50_program_exec
*e
, unsigned cc
)
1726 if (!is_long(e
) || is_immd(e
))
1728 return ((e
->inst
[1] & 0x780) == (cc
<< 7));
1731 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
1738 nv50_kill_branch(struct nv50_pc
*pc
)
1740 int lvl
= pc
->if_lvl
;
1742 if (pc
->if_insn
[lvl
]->next
!= pc
->p
->exec_tail
)
1745 /* if ccode == 'true', the BRA is from an ELSE and the predicate
1746 * reg may no longer be valid, since we currently always use $p0
1748 if (has_pred(pc
->if_insn
[lvl
], 0xf))
1750 assert(pc
->if_insn
[lvl
] && pc
->br_join
[lvl
]);
1752 /* We'll use the exec allocated for JOIN_AT (as we can't easily
1753 * update prev's next); if exec_tail is BRK, update the pointer.
1755 if (pc
->loop_lvl
&& pc
->br_loop
[pc
->loop_lvl
- 1] == pc
->p
->exec_tail
)
1756 pc
->br_loop
[pc
->loop_lvl
- 1] = pc
->br_join
[lvl
];
1758 pc
->p
->exec_size
-= 4; /* remove JOIN_AT and BRA */
1760 *pc
->br_join
[lvl
] = *pc
->p
->exec_tail
;
1762 FREE(pc
->if_insn
[lvl
]);
1763 FREE(pc
->p
->exec_tail
);
1765 pc
->p
->exec_tail
= pc
->br_join
[lvl
];
1766 pc
->p
->exec_tail
->next
= NULL
;
1767 set_pred(pc
, 0xd, 0, pc
->p
->exec_tail
);
1773 nv50_program_tx_insn(struct nv50_pc
*pc
,
1774 const struct tgsi_full_instruction
*inst
)
1776 struct nv50_reg
*rdst
[4], *dst
[4], *brdc
, *src
[3][4], *temp
;
1777 unsigned mask
, sat
, unit
;
1780 mask
= inst
->FullDstRegisters
[0].DstRegister
.WriteMask
;
1781 sat
= inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
;
1783 memset(src
, 0, sizeof(src
));
1785 for (c
= 0; c
< 4; c
++) {
1786 if ((mask
& (1 << c
)) && !pc
->r_dst
[c
])
1787 dst
[c
] = tgsi_dst(pc
, c
, &inst
->FullDstRegisters
[0]);
1789 dst
[c
] = pc
->r_dst
[c
];
1793 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1794 const struct tgsi_full_src_register
*fs
= &inst
->FullSrcRegisters
[i
];
1798 src_mask
= nv50_tgsi_src_mask(inst
, i
);
1799 neg_supp
= negate_supported(inst
, i
);
1801 if (fs
->SrcRegister
.File
== TGSI_FILE_SAMPLER
)
1802 unit
= fs
->SrcRegister
.Index
;
1804 for (c
= 0; c
< 4; c
++)
1805 if (src_mask
& (1 << c
))
1806 src
[i
][c
] = tgsi_src(pc
, c
, fs
, neg_supp
);
1809 brdc
= temp
= pc
->r_brdc
;
1810 if (brdc
&& brdc
->type
!= P_TEMP
) {
1811 temp
= temp_temp(pc
);
1816 for (c
= 0; c
< 4; c
++) {
1817 if (!(mask
& (1 << c
)) || dst
[c
]->type
== P_TEMP
)
1819 /* rdst[c] = dst[c]; */ /* done above */
1820 dst
[c
] = temp_temp(pc
);
1824 assert(brdc
|| !is_scalar_op(inst
->Instruction
.Opcode
));
1826 switch (inst
->Instruction
.Opcode
) {
1827 case TGSI_OPCODE_ABS
:
1828 for (c
= 0; c
< 4; c
++) {
1829 if (!(mask
& (1 << c
)))
1831 emit_abs(pc
, dst
[c
], src
[0][c
]);
1834 case TGSI_OPCODE_ADD
:
1835 for (c
= 0; c
< 4; c
++) {
1836 if (!(mask
& (1 << c
)))
1838 emit_add(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
1841 case TGSI_OPCODE_ARL
:
1843 temp
= temp_temp(pc
);
1844 emit_cvt(pc
, temp
, src
[0][0], -1, CVTOP_FLOOR
, CVT_S32_F32
);
1845 emit_arl(pc
, dst
[0], temp
, 4);
1847 case TGSI_OPCODE_BGNLOOP
:
1848 pc
->loop_pos
[pc
->loop_lvl
++] = pc
->p
->exec_size
;
1851 case TGSI_OPCODE_BRK
:
1852 emit_branch(pc
, -1, 0, NULL
);
1853 assert(pc
->loop_lvl
> 0);
1854 pc
->br_loop
[pc
->loop_lvl
- 1] = pc
->p
->exec_tail
;
1856 case TGSI_OPCODE_CEIL
:
1857 for (c
= 0; c
< 4; c
++) {
1858 if (!(mask
& (1 << c
)))
1860 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
1861 CVTOP_CEIL
, CVT_F32_F32
| CVT_RI
);
1864 case TGSI_OPCODE_CMP
:
1865 pc
->allow32
= FALSE
;
1866 for (c
= 0; c
< 4; c
++) {
1867 if (!(mask
& (1 << c
)))
1869 emit_cvt(pc
, NULL
, src
[0][c
], 1, CVTOP_RN
, CVT_F32_F32
);
1870 emit_mov(pc
, dst
[c
], src
[1][c
]);
1871 set_pred(pc
, 0x1, 1, pc
->p
->exec_tail
); /* @SF */
1872 emit_mov(pc
, dst
[c
], src
[2][c
]);
1873 set_pred(pc
, 0x6, 1, pc
->p
->exec_tail
); /* @NSF */
1876 case TGSI_OPCODE_COS
:
1878 emit_precossin(pc
, temp
, src
[0][3]);
1879 emit_flop(pc
, 5, dst
[3], temp
);
1883 temp
= brdc
= temp_temp(pc
);
1885 emit_precossin(pc
, temp
, src
[0][0]);
1886 emit_flop(pc
, 5, brdc
, temp
);
1888 case TGSI_OPCODE_DDX
:
1889 for (c
= 0; c
< 4; c
++) {
1890 if (!(mask
& (1 << c
)))
1892 emit_ddx(pc
, dst
[c
], src
[0][c
]);
1895 case TGSI_OPCODE_DDY
:
1896 for (c
= 0; c
< 4; c
++) {
1897 if (!(mask
& (1 << c
)))
1899 emit_ddy(pc
, dst
[c
], src
[0][c
]);
1902 case TGSI_OPCODE_DP3
:
1903 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1904 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1905 emit_mad(pc
, brdc
, src
[0][2], src
[1][2], temp
);
1907 case TGSI_OPCODE_DP4
:
1908 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1909 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1910 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
1911 emit_mad(pc
, brdc
, src
[0][3], src
[1][3], temp
);
1913 case TGSI_OPCODE_DPH
:
1914 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1915 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1916 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
1917 emit_add(pc
, brdc
, src
[1][3], temp
);
1919 case TGSI_OPCODE_DST
:
1920 if (mask
& (1 << 1))
1921 emit_mul(pc
, dst
[1], src
[0][1], src
[1][1]);
1922 if (mask
& (1 << 2))
1923 emit_mov(pc
, dst
[2], src
[0][2]);
1924 if (mask
& (1 << 3))
1925 emit_mov(pc
, dst
[3], src
[1][3]);
1926 if (mask
& (1 << 0))
1927 emit_mov_immdval(pc
, dst
[0], 1.0f
);
1929 case TGSI_OPCODE_ELSE
:
1930 emit_branch(pc
, -1, 0, NULL
);
1931 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
1932 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
1935 case TGSI_OPCODE_ENDIF
:
1936 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
1938 /* try to replace branch over 1 insn with a predicated insn */
1939 if (nv50_kill_branch(pc
) == TRUE
)
1942 if (pc
->br_join
[pc
->if_lvl
]) {
1943 pc
->br_join
[pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
1944 pc
->br_join
[pc
->if_lvl
] = NULL
;
1947 /* emit a NOP as join point, we could set it on the next
1948 * one, but would have to make sure it is long and !immd
1951 pc
->p
->exec_tail
->inst
[1] |= 2;
1953 case TGSI_OPCODE_ENDLOOP
:
1954 emit_branch(pc
, -1, 0, NULL
);
1955 pc
->p
->exec_tail
->param
.index
= pc
->loop_pos
[--pc
->loop_lvl
];
1956 pc
->br_loop
[pc
->loop_lvl
]->param
.index
= pc
->p
->exec_size
;
1959 case TGSI_OPCODE_EX2
:
1960 emit_preex2(pc
, temp
, src
[0][0]);
1961 emit_flop(pc
, 6, brdc
, temp
);
1963 case TGSI_OPCODE_FLR
:
1964 for (c
= 0; c
< 4; c
++) {
1965 if (!(mask
& (1 << c
)))
1967 emit_flr(pc
, dst
[c
], src
[0][c
]);
1970 case TGSI_OPCODE_FRC
:
1971 temp
= temp_temp(pc
);
1972 for (c
= 0; c
< 4; c
++) {
1973 if (!(mask
& (1 << c
)))
1975 emit_flr(pc
, temp
, src
[0][c
]);
1976 emit_sub(pc
, dst
[c
], src
[0][c
], temp
);
1979 case TGSI_OPCODE_IF
:
1980 /* emitting a join_at may not be necessary */
1981 assert(pc
->if_lvl
< MAX_IF_DEPTH
);
1982 set_pred_wr(pc
, 1, 0, pc
->if_cond
);
1983 emit_branch(pc
, 0, 2, &pc
->br_join
[pc
->if_lvl
]);
1984 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
1987 case TGSI_OPCODE_KIL
:
1988 emit_kil(pc
, src
[0][0]);
1989 emit_kil(pc
, src
[0][1]);
1990 emit_kil(pc
, src
[0][2]);
1991 emit_kil(pc
, src
[0][3]);
1993 case TGSI_OPCODE_LIT
:
1994 emit_lit(pc
, &dst
[0], mask
, &src
[0][0]);
1996 case TGSI_OPCODE_LG2
:
1997 emit_flop(pc
, 3, brdc
, src
[0][0]);
1999 case TGSI_OPCODE_LRP
:
2000 temp
= temp_temp(pc
);
2001 for (c
= 0; c
< 4; c
++) {
2002 if (!(mask
& (1 << c
)))
2004 emit_sub(pc
, temp
, src
[1][c
], src
[2][c
]);
2005 emit_mad(pc
, dst
[c
], temp
, src
[0][c
], src
[2][c
]);
2008 case TGSI_OPCODE_MAD
:
2009 for (c
= 0; c
< 4; c
++) {
2010 if (!(mask
& (1 << c
)))
2012 emit_mad(pc
, dst
[c
], src
[0][c
], src
[1][c
], src
[2][c
]);
2015 case TGSI_OPCODE_MAX
:
2016 for (c
= 0; c
< 4; c
++) {
2017 if (!(mask
& (1 << c
)))
2019 emit_minmax(pc
, 4, dst
[c
], src
[0][c
], src
[1][c
]);
2022 case TGSI_OPCODE_MIN
:
2023 for (c
= 0; c
< 4; c
++) {
2024 if (!(mask
& (1 << c
)))
2026 emit_minmax(pc
, 5, dst
[c
], src
[0][c
], src
[1][c
]);
2029 case TGSI_OPCODE_MOV
:
2030 for (c
= 0; c
< 4; c
++) {
2031 if (!(mask
& (1 << c
)))
2033 emit_mov(pc
, dst
[c
], src
[0][c
]);
2036 case TGSI_OPCODE_MUL
:
2037 for (c
= 0; c
< 4; c
++) {
2038 if (!(mask
& (1 << c
)))
2040 emit_mul(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2043 case TGSI_OPCODE_POW
:
2044 emit_pow(pc
, brdc
, src
[0][0], src
[1][0]);
2046 case TGSI_OPCODE_RCP
:
2047 emit_flop(pc
, 0, brdc
, src
[0][0]);
2049 case TGSI_OPCODE_RSQ
:
2050 emit_flop(pc
, 2, brdc
, src
[0][0]);
2052 case TGSI_OPCODE_SCS
:
2053 temp
= temp_temp(pc
);
2055 emit_precossin(pc
, temp
, src
[0][0]);
2056 if (mask
& (1 << 0))
2057 emit_flop(pc
, 5, dst
[0], temp
);
2058 if (mask
& (1 << 1))
2059 emit_flop(pc
, 4, dst
[1], temp
);
2060 if (mask
& (1 << 2))
2061 emit_mov_immdval(pc
, dst
[2], 0.0);
2062 if (mask
& (1 << 3))
2063 emit_mov_immdval(pc
, dst
[3], 1.0);
2065 case TGSI_OPCODE_SIN
:
2067 emit_precossin(pc
, temp
, src
[0][3]);
2068 emit_flop(pc
, 4, dst
[3], temp
);
2072 temp
= brdc
= temp_temp(pc
);
2074 emit_precossin(pc
, temp
, src
[0][0]);
2075 emit_flop(pc
, 4, brdc
, temp
);
2077 case TGSI_OPCODE_SLT
:
2078 case TGSI_OPCODE_SGE
:
2079 case TGSI_OPCODE_SEQ
:
2080 case TGSI_OPCODE_SGT
:
2081 case TGSI_OPCODE_SLE
:
2082 case TGSI_OPCODE_SNE
:
2083 i
= map_tgsi_setop_cc(inst
->Instruction
.Opcode
);
2084 for (c
= 0; c
< 4; c
++) {
2085 if (!(mask
& (1 << c
)))
2087 emit_set(pc
, i
, dst
[c
], -1, src
[0][c
], src
[1][c
]);
2090 case TGSI_OPCODE_SUB
:
2091 for (c
= 0; c
< 4; c
++) {
2092 if (!(mask
& (1 << c
)))
2094 emit_sub(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2097 case TGSI_OPCODE_TEX
:
2098 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2099 inst
->InstructionExtTexture
.Texture
, FALSE
);
2101 case TGSI_OPCODE_TXP
:
2102 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2103 inst
->InstructionExtTexture
.Texture
, TRUE
);
2105 case TGSI_OPCODE_TRUNC
:
2106 for (c
= 0; c
< 4; c
++) {
2107 if (!(mask
& (1 << c
)))
2109 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2110 CVTOP_TRUNC
, CVT_F32_F32
| CVT_RI
);
2113 case TGSI_OPCODE_XPD
:
2114 temp
= temp_temp(pc
);
2115 if (mask
& (1 << 0)) {
2116 emit_mul(pc
, temp
, src
[0][2], src
[1][1]);
2117 emit_msb(pc
, dst
[0], src
[0][1], src
[1][2], temp
);
2119 if (mask
& (1 << 1)) {
2120 emit_mul(pc
, temp
, src
[0][0], src
[1][2]);
2121 emit_msb(pc
, dst
[1], src
[0][2], src
[1][0], temp
);
2123 if (mask
& (1 << 2)) {
2124 emit_mul(pc
, temp
, src
[0][1], src
[1][0]);
2125 emit_msb(pc
, dst
[2], src
[0][0], src
[1][1], temp
);
2127 if (mask
& (1 << 3))
2128 emit_mov_immdval(pc
, dst
[3], 1.0);
2130 case TGSI_OPCODE_END
:
2133 NOUVEAU_ERR("invalid opcode %d\n", inst
->Instruction
.Opcode
);
2139 emit_sat(pc
, brdc
, brdc
);
2140 for (c
= 0; c
< 4; c
++)
2141 if ((mask
& (1 << c
)) && dst
[c
] != brdc
)
2142 emit_mov(pc
, dst
[c
], brdc
);
2145 for (c
= 0; c
< 4; c
++) {
2146 if (!(mask
& (1 << c
)))
2148 /* In this case we saturate later, and dst[c] won't
2149 * be another temp_temp (and thus lost), since rdst
2150 * already is TEMP (see above). */
2151 if (rdst
[c
]->type
== P_TEMP
&& rdst
[c
]->index
< 0)
2153 emit_sat(pc
, rdst
[c
], dst
[c
]);
2157 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2158 for (c
= 0; c
< 4; c
++) {
2162 if (src
[i
][c
]->index
== -1 && src
[i
][c
]->type
== P_IMMD
)
2165 if (src
[i
][c
]->acc
< 0 && src
[i
][c
]->type
== P_CONST
)
2166 FREE(src
[i
][c
]); /* indirect constant */
2175 prep_inspect_insn(struct nv50_pc
*pc
, const struct tgsi_full_instruction
*insn
)
2177 struct nv50_reg
*reg
= NULL
;
2178 const struct tgsi_full_src_register
*src
;
2179 const struct tgsi_dst_register
*dst
;
2180 unsigned i
, c
, k
, mask
;
2182 dst
= &insn
->FullDstRegisters
[0].DstRegister
;
2183 mask
= dst
->WriteMask
;
2185 if (dst
->File
== TGSI_FILE_TEMPORARY
)
2188 if (dst
->File
== TGSI_FILE_OUTPUT
)
2192 for (c
= 0; c
< 4; c
++) {
2193 if (!(mask
& (1 << c
)))
2195 reg
[dst
->Index
* 4 + c
].acc
= pc
->insn_nr
;
2199 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
2200 src
= &insn
->FullSrcRegisters
[i
];
2202 if (src
->SrcRegister
.File
== TGSI_FILE_TEMPORARY
)
2205 if (src
->SrcRegister
.File
== TGSI_FILE_INPUT
)
2210 mask
= nv50_tgsi_src_mask(insn
, i
);
2212 for (c
= 0; c
< 4; c
++) {
2213 if (!(mask
& (1 << c
)))
2215 k
= tgsi_util_get_full_src_register_swizzle(src
, c
);
2217 reg
[src
->SrcRegister
.Index
* 4 + k
].acc
= pc
->insn_nr
;
2222 /* Returns a bitmask indicating which dst components need to be
2223 * written to temporaries first to avoid 'corrupting' sources.
2225 * m[i] (out) indicate component to write in the i-th position
2226 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2229 nv50_revdep_reorder(unsigned m
[4], unsigned rdep
[4])
2231 unsigned i
, c
, x
, unsafe
;
2233 for (c
= 0; c
< 4; c
++)
2236 /* Swap as long as a dst component written earlier is depended on
2237 * by one written later, but the next one isn't depended on by it.
2239 for (c
= 0; c
< 3; c
++) {
2240 if (rdep
[m
[c
+ 1]] & (1 << m
[c
]))
2241 continue; /* if next one is depended on by us */
2242 for (i
= c
+ 1; i
< 4; i
++)
2243 /* if we are depended on by a later one */
2244 if (rdep
[m
[c
]] & (1 << m
[i
]))
2257 /* mark dependencies that could not be resolved by reordering */
2258 for (i
= 0; i
< 3; ++i
)
2259 for (c
= i
+ 1; c
< 4; ++c
)
2260 if (rdep
[m
[i
]] & (1 << m
[c
]))
2263 /* NOTE: $unsafe is with respect to order, not component */
2267 /* Select a suitable dst register for broadcasting scalar results,
2268 * or return NULL if we have to allocate an extra TEMP.
2270 * If e.g. only 1 component is written, we may also emit the final
2271 * result to a write-only register.
2273 static struct nv50_reg
*
2274 tgsi_broadcast_dst(struct nv50_pc
*pc
,
2275 const struct tgsi_full_dst_register
*fd
, unsigned mask
)
2277 if (fd
->DstRegister
.File
== TGSI_FILE_TEMPORARY
) {
2278 int c
= ffs(~mask
& fd
->DstRegister
.WriteMask
);
2280 return tgsi_dst(pc
, c
- 1, fd
);
2282 int c
= ffs(fd
->DstRegister
.WriteMask
) - 1;
2283 if ((1 << c
) == fd
->DstRegister
.WriteMask
)
2284 return tgsi_dst(pc
, c
, fd
);
2290 /* Scan source swizzles and return a bitmask indicating dst regs that
2291 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2294 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction
*insn
,
2297 const struct tgsi_full_dst_register
*fd
= &insn
->FullDstRegisters
[0];
2298 const struct tgsi_full_src_register
*fs
;
2299 unsigned i
, deqs
= 0;
2301 for (i
= 0; i
< 4; ++i
)
2304 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
2305 unsigned chn
, mask
= nv50_tgsi_src_mask(insn
, i
);
2306 boolean neg_supp
= negate_supported(insn
, i
);
2308 fs
= &insn
->FullSrcRegisters
[i
];
2309 if (fs
->SrcRegister
.File
!= fd
->DstRegister
.File
||
2310 fs
->SrcRegister
.Index
!= fd
->DstRegister
.Index
)
2313 for (chn
= 0; chn
< 4; ++chn
) {
2316 if (!(mask
& (1 << chn
))) /* src is not read */
2318 c
= tgsi_util_get_full_src_register_swizzle(fs
, chn
);
2319 s
= tgsi_util_get_full_src_register_sign_mode(fs
, chn
);
2321 if (!(fd
->DstRegister
.WriteMask
& (1 << c
)))
2324 /* no danger if src is copied to TEMP first */
2325 if ((s
!= TGSI_UTIL_SIGN_KEEP
) &&
2326 (s
!= TGSI_UTIL_SIGN_TOGGLE
|| !neg_supp
))
2329 rdep
[c
] |= nv50_tgsi_dst_revdep(
2330 insn
->Instruction
.Opcode
, i
, chn
);
2339 nv50_tgsi_insn(struct nv50_pc
*pc
, const union tgsi_full_token
*tok
)
2341 struct tgsi_full_instruction insn
= tok
->FullInstruction
;
2342 const struct tgsi_full_dst_register
*fd
;
2343 unsigned i
, deqs
, rdep
[4], m
[4];
2345 fd
= &tok
->FullInstruction
.FullDstRegisters
[0];
2346 deqs
= nv50_tgsi_scan_swizzle(&insn
, rdep
);
2348 if (is_scalar_op(insn
.Instruction
.Opcode
)) {
2349 pc
->r_brdc
= tgsi_broadcast_dst(pc
, fd
, deqs
);
2351 pc
->r_brdc
= temp_temp(pc
);
2352 return nv50_program_tx_insn(pc
, &insn
);
2357 return nv50_program_tx_insn(pc
, &insn
);
2359 deqs
= nv50_revdep_reorder(m
, rdep
);
2361 for (i
= 0; i
< 4; ++i
) {
2362 assert(pc
->r_dst
[m
[i
]] == NULL
);
2364 insn
.FullDstRegisters
[0].DstRegister
.WriteMask
=
2365 fd
->DstRegister
.WriteMask
& (1 << m
[i
]);
2367 if (!insn
.FullDstRegisters
[0].DstRegister
.WriteMask
)
2370 if (deqs
& (1 << i
))
2371 pc
->r_dst
[m
[i
]] = alloc_temp(pc
, NULL
);
2373 if (!nv50_program_tx_insn(pc
, &insn
))
2377 for (i
= 0; i
< 4; i
++) {
2378 struct nv50_reg
*reg
= pc
->r_dst
[i
];
2381 pc
->r_dst
[i
] = NULL
;
2383 if (insn
.Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
)
2384 emit_sat(pc
, tgsi_dst(pc
, i
, fd
), reg
);
2386 emit_mov(pc
, tgsi_dst(pc
, i
, fd
), reg
);
2394 load_interpolant(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
2396 struct nv50_reg
*iv
, **ppiv
;
2397 unsigned mode
= pc
->interp_mode
[reg
->index
];
2399 ppiv
= (mode
& INTERP_CENTROID
) ? &pc
->iv_c
: &pc
->iv_p
;
2402 if ((mode
& INTERP_PERSPECTIVE
) && !iv
) {
2403 iv
= *ppiv
= alloc_temp(pc
, NULL
);
2404 iv
->rhw
= popcnt4(pc
->p
->cfg
.regs
[1] >> 24) - 1;
2406 emit_interp(pc
, iv
, NULL
, mode
& INTERP_CENTROID
);
2407 emit_flop(pc
, 0, iv
, iv
);
2409 /* XXX: when loading interpolants dynamically, move these
2410 * to the program head, or make sure it can't be skipped.
2414 emit_interp(pc
, reg
, iv
, mode
);
2418 nv50_program_tx_prep(struct nv50_pc
*pc
)
2420 struct tgsi_parse_context tp
;
2421 struct nv50_program
*p
= pc
->p
;
2422 boolean ret
= FALSE
;
2423 unsigned i
, c
, flat_nr
= 0;
2425 tgsi_parse_init(&tp
, pc
->p
->pipe
.tokens
);
2426 while (!tgsi_parse_end_of_tokens(&tp
)) {
2427 const union tgsi_full_token
*tok
= &tp
.FullToken
;
2429 tgsi_parse_token(&tp
);
2430 switch (tok
->Token
.Type
) {
2431 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2433 const struct tgsi_full_immediate
*imm
=
2434 &tp
.FullToken
.FullImmediate
;
2436 ctor_immd(pc
, imm
->u
[0].Float
,
2442 case TGSI_TOKEN_TYPE_DECLARATION
:
2444 const struct tgsi_full_declaration
*d
;
2445 unsigned si
, last
, first
, mode
;
2447 d
= &tp
.FullToken
.FullDeclaration
;
2448 first
= d
->DeclarationRange
.First
;
2449 last
= d
->DeclarationRange
.Last
;
2451 switch (d
->Declaration
.File
) {
2452 case TGSI_FILE_TEMPORARY
:
2454 case TGSI_FILE_OUTPUT
:
2455 if (!d
->Declaration
.Semantic
||
2456 p
->type
== PIPE_SHADER_FRAGMENT
)
2459 si
= d
->Semantic
.SemanticIndex
;
2460 switch (d
->Semantic
.SemanticName
) {
2461 case TGSI_SEMANTIC_BCOLOR
:
2462 p
->cfg
.two_side
[si
].hw
= first
;
2463 if (p
->cfg
.io_nr
> first
)
2464 p
->cfg
.io_nr
= first
;
2466 case TGSI_SEMANTIC_PSIZE
:
2467 p
->cfg
.psiz
= first
;
2468 if (p
->cfg
.io_nr
> first
)
2469 p
->cfg
.io_nr
= first
;
2472 case TGSI_SEMANTIC_CLIP_DISTANCE:
2473 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2480 case TGSI_FILE_INPUT
:
2482 if (p
->type
!= PIPE_SHADER_FRAGMENT
)
2485 switch (d
->Declaration
.Interpolate
) {
2486 case TGSI_INTERPOLATE_CONSTANT
:
2490 case TGSI_INTERPOLATE_PERSPECTIVE
:
2491 mode
= INTERP_PERSPECTIVE
;
2492 p
->cfg
.regs
[1] |= 0x08 << 24;
2495 mode
= INTERP_LINEAR
;
2498 if (d
->Declaration
.Centroid
)
2499 mode
|= INTERP_CENTROID
;
2502 for (i
= first
; i
<= last
; i
++)
2503 pc
->interp_mode
[i
] = mode
;
2506 case TGSI_FILE_ADDRESS
:
2507 case TGSI_FILE_CONSTANT
:
2508 case TGSI_FILE_SAMPLER
:
2511 NOUVEAU_ERR("bad decl file %d\n",
2512 d
->Declaration
.File
);
2517 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2519 prep_inspect_insn(pc
, &tok
->FullInstruction
);
2526 if (p
->type
== PIPE_SHADER_VERTEX
) {
2529 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
) {
2530 if (pc
->attr
[i
].acc
) {
2531 pc
->attr
[i
].hw
= rid
++;
2532 p
->cfg
.attr
[i
/ 32] |= 1 << (i
% 32);
2536 for (i
= 0, rid
= 0; i
< pc
->result_nr
; ++i
) {
2537 p
->cfg
.io
[i
].hw
= rid
;
2538 p
->cfg
.io
[i
].id_vp
= i
;
2540 for (c
= 0; c
< 4; ++c
) {
2542 if (!pc
->result
[n
].acc
)
2544 pc
->result
[n
].hw
= rid
++;
2545 p
->cfg
.io
[i
].mask
|= 1 << c
;
2549 for (c
= 0; c
< 2; ++c
)
2550 if (p
->cfg
.two_side
[c
].hw
< 0x40)
2551 p
->cfg
.two_side
[c
] = p
->cfg
.io
[
2552 p
->cfg
.two_side
[c
].hw
];
2554 if (p
->cfg
.psiz
< 0x40)
2555 p
->cfg
.psiz
= p
->cfg
.io
[p
->cfg
.psiz
].hw
;
2557 if (p
->type
== PIPE_SHADER_FRAGMENT
) {
2559 unsigned n
= 0, m
= pc
->attr_nr
- flat_nr
;
2561 int base
= (TGSI_SEMANTIC_POSITION
==
2562 p
->info
.input_semantic_name
[0]) ? 0 : 1;
2564 /* non-flat interpolants have to be mapped to
2565 * the lower hardware IDs, so sort them:
2567 for (i
= 0; i
< pc
->attr_nr
; i
++) {
2568 if (pc
->interp_mode
[i
] == INTERP_FLAT
) {
2569 p
->cfg
.io
[m
].id_vp
= i
+ base
;
2570 p
->cfg
.io
[m
++].id_fp
= i
;
2572 if (!(pc
->interp_mode
[i
] & INTERP_PERSPECTIVE
))
2573 p
->cfg
.io
[n
].linear
= TRUE
;
2574 p
->cfg
.io
[n
].id_vp
= i
+ base
;
2575 p
->cfg
.io
[n
++].id_fp
= i
;
2579 if (!base
) /* set w-coordinate mask from perspective interp */
2580 p
->cfg
.io
[0].mask
|= p
->cfg
.regs
[1] >> 24;
2582 aid
= popcnt4( /* if fcrd isn't contained in cfg.io */
2583 base
? (p
->cfg
.regs
[1] >> 24) : p
->cfg
.io
[0].mask
);
2585 for (n
= 0; n
< pc
->attr_nr
; ++n
) {
2586 p
->cfg
.io
[n
].hw
= rid
= aid
;
2587 i
= p
->cfg
.io
[n
].id_fp
;
2589 for (c
= 0; c
< 4; ++c
) {
2590 if (!pc
->attr
[i
* 4 + c
].acc
)
2592 pc
->attr
[i
* 4 + c
].rhw
= rid
++;
2593 p
->cfg
.io
[n
].mask
|= 1 << c
;
2595 load_interpolant(pc
, &pc
->attr
[i
* 4 + c
]);
2597 aid
+= popcnt4(p
->cfg
.io
[n
].mask
);
2601 p
->cfg
.regs
[1] |= p
->cfg
.io
[0].mask
<< 24;
2603 m
= popcnt4(p
->cfg
.regs
[1] >> 24);
2605 /* set count of non-position inputs and of non-flat
2606 * non-position inputs for FP_INTERPOLANT_CTRL
2608 p
->cfg
.regs
[1] |= aid
- m
;
2611 i
= p
->cfg
.io
[pc
->attr_nr
- flat_nr
].hw
;
2612 p
->cfg
.regs
[1] |= (i
- m
) << 16;
2614 p
->cfg
.regs
[1] |= p
->cfg
.regs
[1] << 16;
2616 /* mark color semantic for light-twoside */
2618 for (i
= 0; i
< pc
->attr_nr
; i
++) {
2621 sn
= p
->info
.input_semantic_name
[p
->cfg
.io
[i
].id_fp
];
2622 si
= p
->info
.input_semantic_index
[p
->cfg
.io
[i
].id_fp
];
2624 if (sn
== TGSI_SEMANTIC_COLOR
) {
2625 p
->cfg
.two_side
[si
] = p
->cfg
.io
[i
];
2627 /* increase colour count */
2628 p
->cfg
.regs
[0] += popcnt4(
2629 p
->cfg
.two_side
[si
].mask
) << 16;
2631 n
= MIN2(n
, p
->cfg
.io
[i
].hw
- m
);
2635 p
->cfg
.regs
[0] += n
;
2637 /* Initialize FP results:
2638 * FragDepth is always first TGSI and last hw output
2640 i
= p
->info
.writes_z
? 4 : 0;
2641 for (rid
= 0; i
< pc
->result_nr
* 4; i
++)
2642 pc
->result
[i
].rhw
= rid
++;
2643 if (p
->info
.writes_z
)
2644 pc
->result
[2].rhw
= rid
;
2646 p
->cfg
.high_result
= rid
;
2652 pc
->immd
= MALLOC(pc
->immd_nr
* 4 * sizeof(struct nv50_reg
));
2656 for (i
= 0; i
< pc
->immd_nr
; i
++) {
2657 for (c
= 0; c
< 4; c
++, rid
++)
2658 ctor_reg(&pc
->immd
[rid
], P_IMMD
, i
, rid
);
2665 free_temp(pc
, pc
->iv_p
);
2667 free_temp(pc
, pc
->iv_c
);
2669 tgsi_parse_free(&tp
);
2674 free_nv50_pc(struct nv50_pc
*pc
)
2691 ctor_nv50_pc(struct nv50_pc
*pc
, struct nv50_program
*p
)
2694 unsigned rtype
[2] = { P_ATTR
, P_RESULT
};
2697 pc
->temp_nr
= p
->info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
2698 pc
->attr_nr
= p
->info
.file_max
[TGSI_FILE_INPUT
] + 1;
2699 pc
->result_nr
= p
->info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
2700 pc
->param_nr
= p
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
2701 pc
->addr_nr
= p
->info
.file_max
[TGSI_FILE_ADDRESS
] + 1;
2702 assert(pc
->addr_nr
<= 2);
2704 p
->cfg
.high_temp
= 4;
2706 p
->cfg
.two_side
[0].hw
= 0x40;
2707 p
->cfg
.two_side
[1].hw
= 0x40;
2710 case PIPE_SHADER_VERTEX
:
2713 p
->cfg
.io_nr
= pc
->result_nr
;
2715 case PIPE_SHADER_FRAGMENT
:
2716 rtype
[0] = rtype
[1] = P_TEMP
;
2718 p
->cfg
.regs
[0] = 0x01000004;
2719 p
->cfg
.io_nr
= pc
->attr_nr
;
2721 if (p
->info
.writes_z
) {
2722 p
->cfg
.regs
[2] |= 0x00000100;
2723 p
->cfg
.regs
[3] |= 0x00000011;
2725 if (p
->info
.uses_kill
)
2726 p
->cfg
.regs
[2] |= 0x00100000;
2731 pc
->temp
= MALLOC(pc
->temp_nr
* 4 * sizeof(struct nv50_reg
));
2735 for (i
= 0; i
< pc
->temp_nr
* 4; ++i
)
2736 ctor_reg(&pc
->temp
[i
], P_TEMP
, i
/ 4, -1);
2740 pc
->attr
= MALLOC(pc
->attr_nr
* 4 * sizeof(struct nv50_reg
));
2744 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
)
2745 ctor_reg(&pc
->attr
[i
], rtype
[0], i
/ 4, -1);
2748 if (pc
->result_nr
) {
2749 unsigned nr
= pc
->result_nr
* 4;
2751 pc
->result
= MALLOC(nr
* sizeof(struct nv50_reg
));
2755 for (i
= 0; i
< nr
; ++i
)
2756 ctor_reg(&pc
->result
[i
], rtype
[1], i
/ 4, -1);
2762 pc
->param
= MALLOC(pc
->param_nr
* 4 * sizeof(struct nv50_reg
));
2766 for (i
= 0; i
< pc
->param_nr
; ++i
)
2767 for (c
= 0; c
< 4; ++c
, ++rid
)
2768 ctor_reg(&pc
->param
[rid
], P_CONST
, i
, rid
);
2772 pc
->addr
= CALLOC(pc
->addr_nr
* 4, sizeof(struct nv50_reg
*));
2776 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
2777 ctor_reg(&pc
->r_addr
[i
], P_ADDR
, -256, i
+ 1);
2783 nv50_fp_move_results(struct nv50_pc
*pc
)
2785 struct nv50_reg reg
;
2788 ctor_reg(®
, P_TEMP
, -1, -1);
2790 for (i
= 0; i
< pc
->result_nr
* 4; ++i
) {
2791 if (pc
->result
[i
].rhw
< 0 || pc
->result
[i
].hw
< 0)
2793 if (pc
->result
[i
].rhw
!= pc
->result
[i
].hw
) {
2794 reg
.hw
= pc
->result
[i
].rhw
;
2795 emit_mov(pc
, ®
, &pc
->result
[i
]);
2801 nv50_program_fixup_insns(struct nv50_pc
*pc
)
2803 struct nv50_program_exec
*e
, *prev
= NULL
, **bra_list
;
2806 bra_list
= CALLOC(pc
->p
->exec_size
, sizeof(struct nv50_program_exec
*));
2808 /* Collect branch instructions, we need to adjust their offsets
2809 * when converting 32 bit instructions to 64 bit ones
2811 for (n
= 0, e
= pc
->p
->exec_head
; e
; e
= e
->next
)
2812 if (e
->param
.index
>= 0 && !e
->param
.mask
)
2815 /* Make sure we don't have any single 32 bit instructions. */
2816 for (e
= pc
->p
->exec_head
, pos
= 0; e
; e
= e
->next
) {
2817 pos
+= is_long(e
) ? 2 : 1;
2819 if ((pos
& 1) && (!e
->next
|| is_long(e
->next
))) {
2820 for (i
= 0; i
< n
; ++i
)
2821 if (bra_list
[i
]->param
.index
>= pos
)
2822 bra_list
[i
]->param
.index
+= 1;
2823 convert_to_long(pc
, e
);
2830 assert(!is_immd(pc
->p
->exec_head
));
2831 assert(!is_immd(pc
->p
->exec_tail
));
2833 /* last instruction must be long so it can have the end bit set */
2834 if (!is_long(pc
->p
->exec_tail
)) {
2835 convert_to_long(pc
, pc
->p
->exec_tail
);
2837 convert_to_long(pc
, prev
);
2839 assert(!(pc
->p
->exec_tail
->inst
[1] & 2));
2840 /* set the end-bit */
2841 pc
->p
->exec_tail
->inst
[1] |= 1;
2847 nv50_program_tx(struct nv50_program
*p
)
2849 struct tgsi_parse_context parse
;
2853 pc
= CALLOC_STRUCT(nv50_pc
);
2857 ret
= ctor_nv50_pc(pc
, p
);
2861 ret
= nv50_program_tx_prep(pc
);
2865 tgsi_parse_init(&parse
, pc
->p
->pipe
.tokens
);
2866 while (!tgsi_parse_end_of_tokens(&parse
)) {
2867 const union tgsi_full_token
*tok
= &parse
.FullToken
;
2869 /* don't allow half insn/immd on first and last instruction */
2871 if (pc
->insn_cur
== 0 || pc
->insn_cur
+ 2 == pc
->insn_nr
)
2872 pc
->allow32
= FALSE
;
2874 tgsi_parse_token(&parse
);
2876 switch (tok
->Token
.Type
) {
2877 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2879 ret
= nv50_tgsi_insn(pc
, tok
);
2888 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
)
2889 nv50_fp_move_results(pc
);
2891 nv50_program_fixup_insns(pc
);
2893 p
->param_nr
= pc
->param_nr
* 4;
2894 p
->immd_nr
= pc
->immd_nr
* 4;
2895 p
->immd
= pc
->immd_buf
;
2898 tgsi_parse_free(&parse
);
2906 nv50_program_validate(struct nv50_context
*nv50
, struct nv50_program
*p
)
2908 if (nv50_program_tx(p
) == FALSE
)
2910 p
->translated
= TRUE
;
2914 nv50_program_upload_data(struct nv50_context
*nv50
, float *map
,
2915 unsigned start
, unsigned count
, unsigned cbuf
)
2917 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
2918 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
2921 unsigned nr
= count
> 2047 ? 2047 : count
;
2923 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 1);
2924 OUT_RING (chan
, (cbuf
<< 0) | (start
<< 8));
2925 BEGIN_RING(chan
, tesla
, NV50TCL_CB_DATA(0) | 0x40000000, nr
);
2926 OUT_RINGp (chan
, map
, nr
);
2935 nv50_program_validate_data(struct nv50_context
*nv50
, struct nv50_program
*p
)
2937 struct pipe_screen
*pscreen
= nv50
->pipe
.screen
;
2939 if (!p
->data
[0] && p
->immd_nr
) {
2940 struct nouveau_resource
*heap
= nv50
->screen
->immd_heap
[0];
2942 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
, &p
->data
[0])) {
2943 while (heap
->next
&& heap
->size
< p
->immd_nr
) {
2944 struct nv50_program
*evict
= heap
->next
->priv
;
2945 nouveau_resource_free(&evict
->data
[0]);
2948 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
,
2953 /* immediates only need to be uploaded again when freed */
2954 nv50_program_upload_data(nv50
, p
->immd
, p
->data
[0]->start
,
2955 p
->immd_nr
, NV50_CB_PMISC
);
2958 assert(p
->param_nr
<= 512);
2962 float *map
= pipe_buffer_map(pscreen
, nv50
->constbuf
[p
->type
],
2963 PIPE_BUFFER_USAGE_CPU_READ
);
2965 if (p
->type
== PIPE_SHADER_VERTEX
)
2970 nv50_program_upload_data(nv50
, map
, 0, p
->param_nr
, cb
);
2971 pipe_buffer_unmap(pscreen
, nv50
->constbuf
[p
->type
]);
2976 nv50_program_validate_code(struct nv50_context
*nv50
, struct nv50_program
*p
)
2978 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
2979 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
2980 struct nv50_program_exec
*e
;
2981 struct nouveau_stateobj
*so
;
2982 const unsigned flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
;
2983 unsigned start
, count
, *up
, *ptr
;
2984 boolean upload
= FALSE
;
2987 nouveau_bo_new(chan
->device
, NOUVEAU_BO_VRAM
, 0x100,
2988 p
->exec_size
* 4, &p
->bo
);
2992 if (p
->data
[0] && p
->data
[0]->start
!= p
->data_start
[0])
2998 for (e
= p
->exec_head
; e
; e
= e
->next
) {
2999 unsigned ei
, ci
, bs
;
3001 if (e
->param
.index
< 0)
3004 if (e
->param
.mask
== 0) {
3005 assert(!(e
->param
.index
& 1));
3006 /* seem to be 8 byte steps */
3007 ei
= (e
->param
.index
>> 1) + 0 /* START_ID */;
3009 e
->inst
[0] &= 0xf0000fff;
3010 e
->inst
[0] |= ei
<< 12;
3014 bs
= (e
->inst
[1] >> 22) & 0x07;
3016 ei
= e
->param
.shift
>> 5;
3017 ci
= e
->param
.index
;
3019 ci
+= p
->data
[bs
]->start
;
3021 e
->inst
[ei
] &= ~e
->param
.mask
;
3022 e
->inst
[ei
] |= (ci
<< e
->param
.shift
);
3026 p
->data_start
[0] = p
->data
[0]->start
;
3028 #ifdef NV50_PROGRAM_DUMP
3029 NOUVEAU_ERR("-------\n");
3030 for (e
= p
->exec_head
; e
; e
= e
->next
) {
3031 NOUVEAU_ERR("0x%08x\n", e
->inst
[0]);
3033 NOUVEAU_ERR("0x%08x\n", e
->inst
[1]);
3037 up
= ptr
= MALLOC(p
->exec_size
* 4);
3038 for (e
= p
->exec_head
; e
; e
= e
->next
) {
3039 *(ptr
++) = e
->inst
[0];
3041 *(ptr
++) = e
->inst
[1];
3045 so_method(so
, nv50
->screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
3046 so_reloc (so
, p
->bo
, 0, flags
| NOUVEAU_BO_HIGH
, 0, 0);
3047 so_reloc (so
, p
->bo
, 0, flags
| NOUVEAU_BO_LOW
, 0, 0);
3048 so_data (so
, (NV50_CB_PUPLOAD
<< 16) | 0x0800); //(p->exec_size * 4));
3050 start
= 0; count
= p
->exec_size
;
3052 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
3057 nr
= MIN2(count
, 2047);
3058 nr
= MIN2(chan
->pushbuf
->remaining
, nr
);
3059 if (chan
->pushbuf
->remaining
< (nr
+ 3)) {
3064 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 1);
3065 OUT_RING (chan
, (start
<< 8) | NV50_CB_PUPLOAD
);
3066 BEGIN_RING(chan
, tesla
, NV50TCL_CB_DATA(0) | 0x40000000, nr
);
3067 OUT_RINGp (chan
, up
+ start
, nr
);
3078 nv50_vertprog_validate(struct nv50_context
*nv50
)
3080 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3081 struct nv50_program
*p
= nv50
->vertprog
;
3082 struct nouveau_stateobj
*so
;
3084 if (!p
->translated
) {
3085 nv50_program_validate(nv50
, p
);
3090 nv50_program_validate_data(nv50
, p
);
3091 nv50_program_validate_code(nv50
, p
);
3094 so_method(so
, tesla
, NV50TCL_VP_ADDRESS_HIGH
, 2);
3095 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3096 NOUVEAU_BO_HIGH
, 0, 0);
3097 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3098 NOUVEAU_BO_LOW
, 0, 0);
3099 so_method(so
, tesla
, NV50TCL_VP_ATTR_EN_0
, 2);
3100 so_data (so
, p
->cfg
.attr
[0]);
3101 so_data (so
, p
->cfg
.attr
[1]);
3102 so_method(so
, tesla
, NV50TCL_VP_REG_ALLOC_RESULT
, 1);
3103 so_data (so
, p
->cfg
.high_result
);
3104 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 2);
3105 so_data (so
, p
->cfg
.high_result
); //8);
3106 so_data (so
, p
->cfg
.high_temp
);
3107 so_method(so
, tesla
, NV50TCL_VP_START_ID
, 1);
3108 so_data (so
, 0); /* program start offset */
3109 so_ref(so
, &nv50
->state
.vertprog
);
3114 nv50_fragprog_validate(struct nv50_context
*nv50
)
3116 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3117 struct nv50_program
*p
= nv50
->fragprog
;
3118 struct nouveau_stateobj
*so
;
3120 if (!p
->translated
) {
3121 nv50_program_validate(nv50
, p
);
3126 nv50_program_validate_data(nv50
, p
);
3127 nv50_program_validate_code(nv50
, p
);
3130 so_method(so
, tesla
, NV50TCL_FP_ADDRESS_HIGH
, 2);
3131 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3132 NOUVEAU_BO_HIGH
, 0, 0);
3133 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3134 NOUVEAU_BO_LOW
, 0, 0);
3135 so_method(so
, tesla
, NV50TCL_FP_REG_ALLOC_TEMP
, 1);
3136 so_data (so
, p
->cfg
.high_temp
);
3137 so_method(so
, tesla
, NV50TCL_FP_RESULT_COUNT
, 1);
3138 so_data (so
, p
->cfg
.high_result
);
3139 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK19A8
, 1);
3140 so_data (so
, p
->cfg
.regs
[2]);
3141 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK196C
, 1);
3142 so_data (so
, p
->cfg
.regs
[3]);
3143 so_method(so
, tesla
, NV50TCL_FP_START_ID
, 1);
3144 so_data (so
, 0); /* program start offset */
3145 so_ref(so
, &nv50
->state
.fragprog
);
3150 nv50_pntc_replace(struct nv50_context
*nv50
, uint32_t pntc
[8], unsigned base
)
3152 struct nv50_program
*fp
= nv50
->fragprog
;
3153 struct nv50_program
*vp
= nv50
->vertprog
;
3154 unsigned i
, c
, m
= base
;
3156 /* XXX: This can't work correctly in all cases yet, we either
3157 * have to create TGSI_SEMANTIC_PNTC or sprite_coord_mode has
3158 * to be per FP input instead of per VP output
3160 memset(pntc
, 0, 8 * sizeof(uint32_t));
3162 for (i
= 0; i
< fp
->cfg
.io_nr
; i
++) {
3164 uint8_t j
= fp
->cfg
.io
[i
].id_vp
, k
= fp
->cfg
.io
[i
].id_fp
;
3165 unsigned n
= popcnt4(fp
->cfg
.io
[i
].mask
);
3167 if (fp
->info
.input_semantic_name
[k
] != TGSI_SEMANTIC_GENERIC
) {
3172 sn
= vp
->info
.input_semantic_name
[j
];
3173 si
= vp
->info
.input_semantic_index
[j
];
3175 if (j
< fp
->cfg
.io_nr
&& sn
== TGSI_SEMANTIC_GENERIC
) {
3177 nv50
->rasterizer
->pipe
.sprite_coord_mode
[si
];
3179 if (mode
== PIPE_SPRITE_COORD_NONE
) {
3185 /* this is either PointCoord or replaced by sprite coords */
3186 for (c
= 0; c
< 4; c
++) {
3187 if (!(fp
->cfg
.io
[i
].mask
& (1 << c
)))
3189 pntc
[m
/ 8] |= (c
+ 1) << ((m
% 8) * 4);
3196 nv50_sreg4_map(uint32_t *p_map
, int mid
, uint32_t lin
[4],
3197 struct nv50_sreg4
*fpi
, struct nv50_sreg4
*vpo
)
3200 uint8_t mv
= vpo
->mask
, mf
= fpi
->mask
, oid
= vpo
->hw
;
3201 uint8_t *map
= (uint8_t *)p_map
;
3203 for (c
= 0; c
< 4; ++c
) {
3205 if (fpi
->linear
== TRUE
)
3206 lin
[mid
/ 32] |= 1 << (mid
% 32);
3207 map
[mid
++] = (mv
& 1) ? oid
: ((c
== 3) ? 0x41 : 0x40);
3219 nv50_linkage_validate(struct nv50_context
*nv50
)
3221 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3222 struct nv50_program
*vp
= nv50
->vertprog
;
3223 struct nv50_program
*fp
= nv50
->fragprog
;
3224 struct nouveau_stateobj
*so
;
3225 struct nv50_sreg4 dummy
, *vpo
;
3227 uint32_t map
[16], lin
[4], reg
[5], pcrd
[8];
3229 memset(map
, 0, sizeof(map
));
3230 memset(lin
, 0, sizeof(lin
));
3232 reg
[1] = 0x00000004; /* low and high clip distance map ids */
3233 reg
[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3234 reg
[3] = 0x00000000; /* point size map id & enable */
3235 reg
[0] = fp
->cfg
.regs
[0]; /* colour semantic reg */
3236 reg
[4] = fp
->cfg
.regs
[1]; /* interpolant info */
3238 dummy
.linear
= FALSE
;
3239 dummy
.mask
= 0xf; /* map all components of HPOS */
3240 m
= nv50_sreg4_map(map
, m
, lin
, &dummy
, &vp
->cfg
.io
[0]);
3244 if (vp
->cfg
.clpd
< 0x40) {
3245 for (c
= 0; c
< vp
->cfg
.clpd_nr
; ++c
)
3246 map
[m
++] = vp
->cfg
.clpd
+ c
;
3250 reg
[0] |= m
<< 8; /* adjust BFC0 id */
3252 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3253 if (nv50
->rasterizer
->pipe
.light_twoside
) {
3254 vpo
= &vp
->cfg
.two_side
[0];
3256 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[0], &vpo
[0]);
3257 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[1], &vpo
[1]);
3260 reg
[0] += m
- 4; /* adjust FFC0 id */
3261 reg
[4] |= m
<< 8; /* set mid where 'normal' FP inputs start */
3264 if (fp
->info
.input_semantic_name
[0] == TGSI_SEMANTIC_POSITION
)
3266 for (; i
< fp
->cfg
.io_nr
; i
++) {
3267 ubyte sn
= fp
->info
.input_semantic_name
[fp
->cfg
.io
[i
].id_fp
];
3268 ubyte si
= fp
->info
.input_semantic_index
[fp
->cfg
.io
[i
].id_fp
];
3270 n
= fp
->cfg
.io
[i
].id_vp
;
3271 if (n
>= vp
->cfg
.io_nr
||
3272 vp
->info
.output_semantic_name
[n
] != sn
||
3273 vp
->info
.output_semantic_index
[n
] != si
)
3276 vpo
= &vp
->cfg
.io
[n
];
3278 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.io
[i
], vpo
);
3281 if (nv50
->rasterizer
->pipe
.point_size_per_vertex
) {
3282 map
[m
/ 4] |= vp
->cfg
.psiz
<< ((m
% 4) * 8);
3283 reg
[3] = (m
++ << 4) | 1;
3286 /* now fill the stateobj */
3290 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 1);
3292 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP(0), n
);
3293 so_datap (so
, map
, n
);
3295 so_method(so
, tesla
, NV50TCL_MAP_SEMANTIC_0
, 4);
3296 so_datap (so
, reg
, 4);
3298 so_method(so
, tesla
, NV50TCL_FP_INTERPOLANT_CTRL
, 1);
3299 so_data (so
, reg
[4]);
3301 so_method(so
, tesla
, 0x1540, 4);
3302 so_datap (so
, lin
, 4);
3304 if (nv50
->rasterizer
->pipe
.point_sprite
) {
3305 nv50_pntc_replace(nv50
, pcrd
, (reg
[4] >> 8) & 0xff);
3307 so_method(so
, tesla
, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3308 so_datap (so
, pcrd
, 8);
3311 so_ref(so
, &nv50
->state
.programs
);
3316 nv50_program_destroy(struct nv50_context
*nv50
, struct nv50_program
*p
)
3318 while (p
->exec_head
) {
3319 struct nv50_program_exec
*e
= p
->exec_head
;
3321 p
->exec_head
= e
->next
;
3324 p
->exec_tail
= NULL
;
3327 nouveau_bo_ref(NULL
, &p
->bo
);
3329 nouveau_resource_free(&p
->data
[0]);