2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
32 #include "nv50_context.h"
34 #define NV50_SU_MAX_TEMP 64
35 #define NV50_PROGRAM_DUMP
37 /* ARL - gallium craps itself on progs/vp/arl.txt
39 * MSB - Like MAD, but MUL+SUB
40 * - Fuck it off, introduce a way to negate args for ops that
43 * Look into inlining IMMD for ops other than MOV (make it general?)
44 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
45 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
47 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
48 * case, if the emit_src() causes the inst to suddenly become long.
50 * Verify half-insns work where expected - and force disable them where they
51 * don't work - MUL has it forcibly disabled atm as it fixes POW..
53 * FUCK! watch dst==src vectors, can overwrite components that are needed.
54 * ie. SUB R0, R0.yzxw, R0
56 * Things to check with renouveau:
57 * FP attr/result assignment - how?
59 * - 0x16bc maps vp output onto fp hpos
60 * - 0x16c0 maps vp output onto fp col0
64 * 0x16bc->0x16e8 --> some binding between vp/fp regs
65 * 0x16b8 --> VP output count
67 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
68 * "MOV rcol.x, fcol.y" = 0x00000004
69 * 0x19a8 --> as above but 0x00000100 and 0x00000000
70 * - 0x00100000 used when KIL used
71 * 0x196c --> as above but 0x00000011 and 0x00000000
73 * 0x1988 --> 0xXXNNNNNN
74 * - XX == FP high something
91 struct nv50_program
*p
;
94 struct nv50_reg
*r_temp
[NV50_SU_MAX_TEMP
];
97 struct nv50_reg
*temp
;
99 struct nv50_reg
*attr
;
101 struct nv50_reg
*result
;
103 struct nv50_reg
*param
;
105 struct nv50_reg
*immd
;
109 struct nv50_reg
*temp_temp
[16];
110 unsigned temp_temp_nr
;
114 alloc_reg(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
118 if (reg
->type
== P_RESULT
) {
119 if (pc
->p
->cfg
.high_result
< (reg
->hw
+ 1))
120 pc
->p
->cfg
.high_result
= reg
->hw
+ 1;
123 if (reg
->type
!= P_TEMP
)
127 /*XXX: do this here too to catch FP temp-as-attr usage..
128 * not clean, but works */
129 if (pc
->p
->cfg
.high_temp
< (reg
->hw
+ 1))
130 pc
->p
->cfg
.high_temp
= reg
->hw
+ 1;
134 for (i
= 0; i
< NV50_SU_MAX_TEMP
; i
++) {
135 if (!(pc
->r_temp
[i
])) {
138 if (pc
->p
->cfg
.high_temp
< (i
+ 1))
139 pc
->p
->cfg
.high_temp
= i
+ 1;
147 static struct nv50_reg
*
148 alloc_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
)
153 if (dst
&& dst
->type
== P_TEMP
&& dst
->hw
== -1)
156 for (i
= 0; i
< NV50_SU_MAX_TEMP
; i
++) {
157 if (!pc
->r_temp
[i
]) {
158 r
= CALLOC_STRUCT(nv50_reg
);
172 free_temp(struct nv50_pc
*pc
, struct nv50_reg
*r
)
174 if (r
->index
== -1) {
177 FREE(pc
->r_temp
[hw
]);
178 pc
->r_temp
[hw
] = NULL
;
183 alloc_temp4(struct nv50_pc
*pc
, struct nv50_reg
*dst
[4], int idx
)
187 if ((idx
+ 4) >= NV50_SU_MAX_TEMP
)
190 if (pc
->r_temp
[idx
] || pc
->r_temp
[idx
+ 1] ||
191 pc
->r_temp
[idx
+ 2] || pc
->r_temp
[idx
+ 3])
192 return alloc_temp4(pc
, dst
, idx
+ 1);
194 for (i
= 0; i
< 4; i
++) {
195 dst
[i
] = CALLOC_STRUCT(nv50_reg
);
196 dst
[i
]->type
= P_TEMP
;
198 dst
[i
]->hw
= idx
+ i
;
199 pc
->r_temp
[idx
+ i
] = dst
[i
];
206 free_temp4(struct nv50_pc
*pc
, struct nv50_reg
*reg
[4])
210 for (i
= 0; i
< 4; i
++)
211 free_temp(pc
, reg
[i
]);
214 static struct nv50_reg
*
215 temp_temp(struct nv50_pc
*pc
)
217 if (pc
->temp_temp_nr
>= 16)
220 pc
->temp_temp
[pc
->temp_temp_nr
] = alloc_temp(pc
, NULL
);
221 return pc
->temp_temp
[pc
->temp_temp_nr
++];
225 kill_temp_temp(struct nv50_pc
*pc
)
229 for (i
= 0; i
< pc
->temp_temp_nr
; i
++)
230 free_temp(pc
, pc
->temp_temp
[i
]);
231 pc
->temp_temp_nr
= 0;
235 ctor_immd(struct nv50_pc
*pc
, float x
, float y
, float z
, float w
)
237 pc
->immd_buf
= REALLOC(pc
->immd_buf
, (pc
->immd_nr
* r
* sizeof(float)),
238 (pc
->immd_nr
+ 1) * 4 * sizeof(float));
239 pc
->immd_buf
[(pc
->immd_nr
* 4) + 0] = x
;
240 pc
->immd_buf
[(pc
->immd_nr
* 4) + 1] = y
;
241 pc
->immd_buf
[(pc
->immd_nr
* 4) + 2] = z
;
242 pc
->immd_buf
[(pc
->immd_nr
* 4) + 3] = w
;
244 return pc
->immd_nr
++;
247 static struct nv50_reg
*
248 alloc_immd(struct nv50_pc
*pc
, float f
)
250 struct nv50_reg
*r
= CALLOC_STRUCT(nv50_reg
);
253 hw
= ctor_immd(pc
, f
, 0, 0, 0) * 4;
260 static struct nv50_program_exec
*
261 exec(struct nv50_pc
*pc
)
263 struct nv50_program_exec
*e
= CALLOC_STRUCT(nv50_program_exec
);
270 emit(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
272 struct nv50_program
*p
= pc
->p
;
275 p
->exec_tail
->next
= e
;
279 p
->exec_size
+= (e
->inst
[0] & 1) ? 2 : 1;
282 static INLINE
void set_long(struct nv50_pc
*, struct nv50_program_exec
*);
285 is_long(struct nv50_program_exec
*e
)
293 is_immd(struct nv50_program_exec
*e
)
295 if (is_long(e
) && (e
->inst
[1] & 3) == 3)
301 set_pred(struct nv50_pc
*pc
, unsigned pred
, unsigned idx
,
302 struct nv50_program_exec
*e
)
305 e
->inst
[1] &= ~((0x1f << 7) | (0x3 << 12));
306 e
->inst
[1] |= (pred
<< 7) | (idx
<< 12);
310 set_pred_wr(struct nv50_pc
*pc
, unsigned on
, unsigned idx
,
311 struct nv50_program_exec
*e
)
314 e
->inst
[1] &= ~((0x3 << 4) | (1 << 6));
315 e
->inst
[1] |= (idx
<< 4) | (on
<< 6);
319 set_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
325 set_pred(pc
, 0xf, 0, e
);
326 set_pred_wr(pc
, 0, 0, e
);
330 set_dst(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_program_exec
*e
)
332 if (dst
->type
== P_RESULT
) {
334 e
->inst
[1] |= 0x00000008;
338 e
->inst
[0] |= (dst
->hw
<< 2);
342 set_immd(struct nv50_pc
*pc
, struct nv50_reg
*imm
, struct nv50_program_exec
*e
)
344 unsigned val
= fui(pc
->immd_buf
[imm
->hw
]); /* XXX */
347 /*XXX: can't be predicated - bits overlap.. catch cases where both
348 * are required and avoid them. */
349 set_pred(pc
, 0, 0, e
);
350 set_pred_wr(pc
, 0, 0, e
);
352 e
->inst
[1] |= 0x00000002 | 0x00000001;
353 e
->inst
[0] |= (val
& 0x3f) << 16;
354 e
->inst
[1] |= (val
>> 6) << 2;
358 emit_interp(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
359 struct nv50_reg
*src
, struct nv50_reg
*iv
)
361 struct nv50_program_exec
*e
= exec(pc
);
363 e
->inst
[0] |= 0x80000000;
366 e
->inst
[0] |= (src
->hw
<< 16);
368 e
->inst
[0] |= (1 << 25);
370 e
->inst
[0] |= (iv
->hw
<< 9);
377 set_data(struct nv50_pc
*pc
, struct nv50_reg
*src
, unsigned m
, unsigned s
,
378 struct nv50_program_exec
*e
)
382 e
->inst
[1] |= (1 << 22);
384 if (src
->type
== P_IMMD
) {
385 e
->inst
[1] |= (NV50_CB_PMISC
<< 22);
387 if (pc
->p
->type
== PIPE_SHADER_VERTEX
)
388 e
->inst
[1] |= (NV50_CB_PVP
<< 22);
390 e
->inst
[1] |= (NV50_CB_PFP
<< 22);
394 e
->param
.index
= src
->hw
;
396 e
->param
.mask
= m
<< (s
% 32);
400 emit_mov(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
402 struct nv50_program_exec
*e
= exec(pc
);
404 e
->inst
[0] |= 0x10000000;
408 if (0 && dst
->type
!= P_RESULT
&& src
->type
== P_IMMD
) {
409 set_immd(pc
, src
, e
);
410 /*XXX: 32-bit, but steals part of "half" reg space - need to
411 * catch and handle this case if/when we do half-regs
413 e
->inst
[0] |= 0x00008000;
415 if (src
->type
== P_IMMD
|| src
->type
== P_CONST
) {
417 set_data(pc
, src
, 0x7f, 9, e
);
418 e
->inst
[1] |= 0x20000000; /* src0 const? */
420 if (src
->type
== P_ATTR
) {
422 e
->inst
[1] |= 0x00200000;
426 e
->inst
[0] |= (src
->hw
<< 9);
429 /* We really should support "half" instructions here at some point,
430 * but I don't feel confident enough about them yet.
433 if (is_long(e
) && !is_immd(e
)) {
434 e
->inst
[1] |= 0x04000000; /* 32-bit */
435 e
->inst
[1] |= 0x0003c000; /* "subsubop" 0xf == mov */
442 check_swap_src_0_1(struct nv50_pc
*pc
,
443 struct nv50_reg
**s0
, struct nv50_reg
**s1
)
445 struct nv50_reg
*src0
= *s0
, *src1
= *s1
;
447 if (src0
->type
== P_CONST
) {
448 if (src1
->type
!= P_CONST
) {
454 if (src1
->type
== P_ATTR
) {
455 if (src0
->type
!= P_ATTR
) {
466 set_src_0(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
468 if (src
->type
== P_ATTR
) {
470 e
->inst
[1] |= 0x00200000;
472 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
473 struct nv50_reg
*temp
= temp_temp(pc
);
475 emit_mov(pc
, temp
, src
);
480 e
->inst
[0] |= (src
->hw
<< 9);
484 set_src_1(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
486 if (src
->type
== P_ATTR
) {
487 struct nv50_reg
*temp
= temp_temp(pc
);
489 emit_mov(pc
, temp
, src
);
492 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
493 assert(!(e
->inst
[0] & 0x00800000));
494 if (e
->inst
[0] & 0x01000000) {
495 struct nv50_reg
*temp
= temp_temp(pc
);
497 emit_mov(pc
, temp
, src
);
500 set_data(pc
, src
, 0x7f, 16, e
);
501 e
->inst
[0] |= 0x00800000;
506 e
->inst
[0] |= (src
->hw
<< 16);
510 set_src_2(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
514 if (src
->type
== P_ATTR
) {
515 struct nv50_reg
*temp
= temp_temp(pc
);
517 emit_mov(pc
, temp
, src
);
520 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
521 assert(!(e
->inst
[0] & 0x01000000));
522 if (e
->inst
[0] & 0x00800000) {
523 struct nv50_reg
*temp
= temp_temp(pc
);
525 emit_mov(pc
, temp
, src
);
528 set_data(pc
, src
, 0x7f, 32+14, e
);
529 e
->inst
[0] |= 0x01000000;
534 e
->inst
[1] |= (src
->hw
<< 14);
538 emit_mul(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
539 struct nv50_reg
*src1
)
541 struct nv50_program_exec
*e
= exec(pc
);
543 e
->inst
[0] |= 0xc0000000;
546 check_swap_src_0_1(pc
, &src0
, &src1
);
548 set_src_0(pc
, src0
, e
);
549 set_src_1(pc
, src1
, e
);
555 emit_add(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
556 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
558 struct nv50_program_exec
*e
= exec(pc
);
560 e
->inst
[0] |= 0xb0000000;
562 check_swap_src_0_1(pc
, &src0
, &src1
);
564 set_src_0(pc
, src0
, e
);
566 set_src_2(pc
, src1
, e
);
568 set_src_1(pc
, src1
, e
);
574 emit_minmax(struct nv50_pc
*pc
, unsigned sub
, struct nv50_reg
*dst
,
575 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
577 struct nv50_program_exec
*e
= exec(pc
);
580 e
->inst
[0] |= 0xb0000000;
581 e
->inst
[1] |= (sub
<< 29);
583 check_swap_src_0_1(pc
, &src0
, &src1
);
585 set_src_0(pc
, src0
, e
);
586 set_src_1(pc
, src1
, e
);
592 emit_sub(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
593 struct nv50_reg
*src1
)
595 struct nv50_program_exec
*e
= exec(pc
);
597 e
->inst
[0] |= 0xb0000000;
600 if (check_swap_src_0_1(pc
, &src0
, &src1
))
601 e
->inst
[1] |= 0x04000000;
603 e
->inst
[1] |= 0x08000000;
606 set_src_0(pc
, src0
, e
);
607 set_src_2(pc
, src1
, e
);
613 emit_mad(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
614 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
616 struct nv50_program_exec
*e
= exec(pc
);
618 e
->inst
[0] |= 0xe0000000;
620 check_swap_src_0_1(pc
, &src0
, &src1
);
622 set_src_0(pc
, src0
, e
);
623 set_src_1(pc
, src1
, e
);
624 set_src_2(pc
, src2
, e
);
630 emit_msb(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
631 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
633 struct nv50_program_exec
*e
= exec(pc
);
635 e
->inst
[0] |= 0xe0000000;
637 e
->inst
[1] |= 0x08000000; /* src0 * src1 - src2 */
639 check_swap_src_0_1(pc
, &src0
, &src1
);
641 set_src_0(pc
, src0
, e
);
642 set_src_1(pc
, src1
, e
);
643 set_src_2(pc
, src2
, e
);
649 emit_flop(struct nv50_pc
*pc
, unsigned sub
,
650 struct nv50_reg
*dst
, struct nv50_reg
*src
)
652 struct nv50_program_exec
*e
= exec(pc
);
654 e
->inst
[0] |= 0x90000000;
657 e
->inst
[1] |= (sub
<< 29);
661 set_src_0(pc
, src
, e
);
667 emit_preex2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
669 struct nv50_program_exec
*e
= exec(pc
);
671 e
->inst
[0] |= 0xb0000000;
674 set_src_0(pc
, src
, e
);
676 e
->inst
[1] |= (6 << 29) | 0x00004000;
682 emit_precossin(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
684 struct nv50_program_exec
*e
= exec(pc
);
686 e
->inst
[0] |= 0xb0000000;
689 set_src_0(pc
, src
, e
);
691 e
->inst
[1] |= (6 << 29);
697 emit_set(struct nv50_pc
*pc
, unsigned c_op
, struct nv50_reg
*dst
,
698 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
700 struct nv50_program_exec
*e
= exec(pc
);
701 unsigned inv_cop
[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
702 struct nv50_reg
*rdst
;
705 if (check_swap_src_0_1(pc
, &src0
, &src1
))
706 c_op
= inv_cop
[c_op
];
709 if (dst
->type
!= P_TEMP
)
710 dst
= alloc_temp(pc
, NULL
);
714 e
->inst
[0] |= 0xb0000000;
715 e
->inst
[1] |= (3 << 29);
716 e
->inst
[1] |= (c_op
<< 14);
717 /*XXX: breaks things, .u32 by default?
718 * decuda will disasm as .u16 and use .lo/.hi regs, but this
719 * doesn't seem to match what the hw actually does.
720 inst[1] |= 0x04000000; << breaks things.. .u32 by default?
723 set_src_0(pc
, src0
, e
);
724 set_src_1(pc
, src1
, e
);
729 e
->inst
[0] = 0xa0000001;
730 e
->inst
[1] = 0x64014780;
731 set_dst(pc
, rdst
, e
);
732 set_src_0(pc
, dst
, e
);
740 emit_flr(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
742 struct nv50_program_exec
*e
= exec(pc
);
744 e
->inst
[0] = 0xa0000000; /* cvt */
746 e
->inst
[1] |= (6 << 29); /* cvt */
747 e
->inst
[1] |= 0x08000000; /* integer mode */
748 e
->inst
[1] |= 0x04000000; /* 32 bit */
749 e
->inst
[1] |= ((0x1 << 3)) << 14; /* .rn */
750 e
->inst
[1] |= (1 << 14); /* src .f32 */
752 set_src_0(pc
, src
, e
);
758 emit_pow(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
759 struct nv50_reg
*v
, struct nv50_reg
*e
)
761 struct nv50_reg
*temp
= alloc_temp(pc
, NULL
);
763 emit_flop(pc
, 3, temp
, v
);
764 emit_mul(pc
, temp
, temp
, e
);
765 emit_preex2(pc
, temp
, temp
);
766 emit_flop(pc
, 6, dst
, temp
);
772 emit_abs(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
774 struct nv50_program_exec
*e
= exec(pc
);
776 e
->inst
[0] = 0xa0000000; /* cvt */
778 e
->inst
[1] |= (6 << 29); /* cvt */
779 e
->inst
[1] |= 0x04000000; /* 32 bit */
780 e
->inst
[1] |= (1 << 14); /* src .f32 */
781 e
->inst
[1] |= ((1 << 6) << 14); /* .abs */
783 set_src_0(pc
, src
, e
);
789 emit_lit(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
790 struct nv50_reg
**src
)
792 struct nv50_reg
*one
= alloc_immd(pc
, 1.0);
793 struct nv50_reg
*zero
= alloc_immd(pc
, 0.0);
794 struct nv50_reg
*neg128
= alloc_immd(pc
, -127.999999);
795 struct nv50_reg
*pos128
= alloc_immd(pc
, 127.999999);
796 struct nv50_reg
*tmp
[4];
799 emit_mov(pc
, dst
[0], one
);
802 emit_mov(pc
, dst
[3], one
);
804 if (mask
& (3 << 1)) {
808 tmp
[0] = temp_temp(pc
);
809 emit_minmax(pc
, 4, tmp
[0], src
[0], zero
);
812 if (mask
& (1 << 2)) {
813 set_pred_wr(pc
, 1, 0, pc
->p
->exec_tail
);
815 tmp
[1] = temp_temp(pc
);
816 emit_minmax(pc
, 4, tmp
[1], src
[1], zero
);
818 tmp
[3] = temp_temp(pc
);
819 emit_minmax(pc
, 4, tmp
[3], src
[3], neg128
);
820 emit_minmax(pc
, 5, tmp
[3], tmp
[3], pos128
);
822 emit_pow(pc
, dst
[2], tmp
[1], tmp
[3]);
823 emit_mov(pc
, dst
[2], zero
);
824 set_pred(pc
, 3, 0, pc
->p
->exec_tail
);
829 emit_neg(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
831 struct nv50_program_exec
*e
= exec(pc
);
834 e
->inst
[0] |= 0xa0000000; /* delta */
835 e
->inst
[1] |= (7 << 29); /* delta */
836 e
->inst
[1] |= 0x04000000; /* negate arg0? probably not */
837 e
->inst
[1] |= (1 << 14); /* src .f32 */
839 set_src_0(pc
, src
, e
);
844 static struct nv50_reg
*
845 tgsi_dst(struct nv50_pc
*pc
, int c
, const struct tgsi_full_dst_register
*dst
)
847 switch (dst
->DstRegister
.File
) {
848 case TGSI_FILE_TEMPORARY
:
849 return &pc
->temp
[dst
->DstRegister
.Index
* 4 + c
];
850 case TGSI_FILE_OUTPUT
:
851 return &pc
->result
[dst
->DstRegister
.Index
* 4 + c
];
861 static struct nv50_reg
*
862 tgsi_src(struct nv50_pc
*pc
, int chan
, const struct tgsi_full_src_register
*src
)
864 struct nv50_reg
*r
= NULL
;
865 struct nv50_reg
*temp
;
868 c
= tgsi_util_get_full_src_register_extswizzle(src
, chan
);
870 case TGSI_EXTSWIZZLE_X
:
871 case TGSI_EXTSWIZZLE_Y
:
872 case TGSI_EXTSWIZZLE_Z
:
873 case TGSI_EXTSWIZZLE_W
:
874 switch (src
->SrcRegister
.File
) {
875 case TGSI_FILE_INPUT
:
876 r
= &pc
->attr
[src
->SrcRegister
.Index
* 4 + c
];
878 case TGSI_FILE_TEMPORARY
:
879 r
= &pc
->temp
[src
->SrcRegister
.Index
* 4 + c
];
881 case TGSI_FILE_CONSTANT
:
882 r
= &pc
->param
[src
->SrcRegister
.Index
* 4 + c
];
884 case TGSI_FILE_IMMEDIATE
:
885 r
= &pc
->immd
[src
->SrcRegister
.Index
* 4 + c
];
887 case TGSI_FILE_SAMPLER
:
894 case TGSI_EXTSWIZZLE_ZERO
:
895 r
= alloc_immd(pc
, 0.0);
897 case TGSI_EXTSWIZZLE_ONE
:
898 r
= alloc_immd(pc
, 1.0);
905 switch (tgsi_util_get_full_src_register_sign_mode(src
, chan
)) {
906 case TGSI_UTIL_SIGN_KEEP
:
908 case TGSI_UTIL_SIGN_CLEAR
:
909 temp
= temp_temp(pc
);
910 emit_abs(pc
, temp
, r
);
913 case TGSI_UTIL_SIGN_TOGGLE
:
914 temp
= temp_temp(pc
);
915 emit_neg(pc
, temp
, r
);
918 case TGSI_UTIL_SIGN_SET
:
919 temp
= temp_temp(pc
);
920 emit_abs(pc
, temp
, r
);
921 emit_neg(pc
, temp
, r
);
933 nv50_program_tx_insn(struct nv50_pc
*pc
, const union tgsi_full_token
*tok
)
935 const struct tgsi_full_instruction
*inst
= &tok
->FullInstruction
;
936 struct nv50_reg
*rdst
[4], *dst
[4], *src
[3][4], *temp
;
940 mask
= inst
->FullDstRegisters
[0].DstRegister
.WriteMask
;
941 sat
= inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
;
943 for (c
= 0; c
< 4; c
++) {
945 dst
[c
] = tgsi_dst(pc
, c
, &inst
->FullDstRegisters
[0]);
950 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
951 for (c
= 0; c
< 4; c
++)
952 src
[i
][c
] = tgsi_src(pc
, c
, &inst
->FullSrcRegisters
[i
]);
956 for (c
= 0; c
< 4; c
++) {
958 dst
[c
] = temp_temp(pc
);
962 switch (inst
->Instruction
.Opcode
) {
963 case TGSI_OPCODE_ABS
:
964 for (c
= 0; c
< 4; c
++) {
965 if (!(mask
& (1 << c
)))
967 emit_abs(pc
, dst
[c
], src
[0][c
]);
970 case TGSI_OPCODE_ADD
:
971 for (c
= 0; c
< 4; c
++) {
972 if (!(mask
& (1 << c
)))
974 emit_add(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
977 case TGSI_OPCODE_COS
:
978 temp
= alloc_temp(pc
, NULL
);
979 emit_precossin(pc
, temp
, src
[0][0]);
980 emit_flop(pc
, 5, temp
, temp
);
981 for (c
= 0; c
< 4; c
++) {
982 if (!(mask
& (1 << c
)))
984 emit_mov(pc
, dst
[c
], temp
);
987 case TGSI_OPCODE_DP3
:
988 temp
= alloc_temp(pc
, NULL
);
989 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
990 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
991 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
992 for (c
= 0; c
< 4; c
++) {
993 if (!(mask
& (1 << c
)))
995 emit_mov(pc
, dst
[c
], temp
);
999 case TGSI_OPCODE_DP4
:
1000 temp
= alloc_temp(pc
, NULL
);
1001 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1002 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1003 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
1004 emit_mad(pc
, temp
, src
[0][3], src
[1][3], temp
);
1005 for (c
= 0; c
< 4; c
++) {
1006 if (!(mask
& (1 << c
)))
1008 emit_mov(pc
, dst
[c
], temp
);
1010 free_temp(pc
, temp
);
1012 case TGSI_OPCODE_DPH
:
1013 temp
= alloc_temp(pc
, NULL
);
1014 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1015 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1016 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
1017 emit_add(pc
, temp
, src
[1][3], temp
);
1018 for (c
= 0; c
< 4; c
++) {
1019 if (!(mask
& (1 << c
)))
1021 emit_mov(pc
, dst
[c
], temp
);
1023 free_temp(pc
, temp
);
1025 case TGSI_OPCODE_DST
:
1027 struct nv50_reg
*one
= alloc_immd(pc
, 1.0);
1028 if (mask
& (1 << 0))
1029 emit_mov(pc
, dst
[0], one
);
1030 if (mask
& (1 << 1))
1031 emit_mul(pc
, dst
[1], src
[0][1], src
[1][1]);
1032 if (mask
& (1 << 2))
1033 emit_mov(pc
, dst
[2], src
[0][2]);
1034 if (mask
& (1 << 3))
1035 emit_mov(pc
, dst
[3], src
[1][3]);
1039 case TGSI_OPCODE_EX2
:
1040 temp
= alloc_temp(pc
, NULL
);
1041 emit_preex2(pc
, temp
, src
[0][0]);
1042 emit_flop(pc
, 6, temp
, temp
);
1043 for (c
= 0; c
< 4; c
++) {
1044 if (!(mask
& (1 << c
)))
1046 emit_mov(pc
, dst
[c
], temp
);
1048 free_temp(pc
, temp
);
1050 case TGSI_OPCODE_FLR
:
1051 for (c
= 0; c
< 4; c
++) {
1052 if (!(mask
& (1 << c
)))
1054 emit_flr(pc
, dst
[c
], src
[0][c
]);
1057 case TGSI_OPCODE_FRC
:
1058 temp
= alloc_temp(pc
, NULL
);
1059 for (c
= 0; c
< 4; c
++) {
1060 if (!(mask
& (1 << c
)))
1062 emit_flr(pc
, temp
, src
[0][c
]);
1063 emit_sub(pc
, dst
[c
], src
[0][c
], temp
);
1065 free_temp(pc
, temp
);
1067 case TGSI_OPCODE_LIT
:
1068 emit_lit(pc
, &dst
[0], mask
, &src
[0][0]);
1070 case TGSI_OPCODE_LG2
:
1071 temp
= alloc_temp(pc
, NULL
);
1072 emit_flop(pc
, 3, temp
, src
[0][0]);
1073 for (c
= 0; c
< 4; c
++) {
1074 if (!(mask
& (1 << c
)))
1076 emit_mov(pc
, dst
[c
], temp
);
1079 case TGSI_OPCODE_LRP
:
1080 for (c
= 0; c
< 4; c
++) {
1081 if (!(mask
& (1 << c
)))
1083 /*XXX: we can do better than this */
1084 temp
= alloc_temp(pc
, NULL
);
1085 emit_neg(pc
, temp
, src
[0][c
]);
1086 emit_mad(pc
, temp
, temp
, src
[2][c
], src
[2][c
]);
1087 emit_mad(pc
, dst
[c
], src
[0][c
], src
[1][c
], temp
);
1088 free_temp(pc
, temp
);
1091 case TGSI_OPCODE_MAD
:
1092 for (c
= 0; c
< 4; c
++) {
1093 if (!(mask
& (1 << c
)))
1095 emit_mad(pc
, dst
[c
], src
[0][c
], src
[1][c
], src
[2][c
]);
1098 case TGSI_OPCODE_MAX
:
1099 for (c
= 0; c
< 4; c
++) {
1100 if (!(mask
& (1 << c
)))
1102 emit_minmax(pc
, 4, dst
[c
], src
[0][c
], src
[1][c
]);
1105 case TGSI_OPCODE_MIN
:
1106 for (c
= 0; c
< 4; c
++) {
1107 if (!(mask
& (1 << c
)))
1109 emit_minmax(pc
, 5, dst
[c
], src
[0][c
], src
[1][c
]);
1112 case TGSI_OPCODE_MOV
:
1113 for (c
= 0; c
< 4; c
++) {
1114 if (!(mask
& (1 << c
)))
1116 emit_mov(pc
, dst
[c
], src
[0][c
]);
1119 case TGSI_OPCODE_MUL
:
1120 for (c
= 0; c
< 4; c
++) {
1121 if (!(mask
& (1 << c
)))
1123 emit_mul(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
1126 case TGSI_OPCODE_POW
:
1127 temp
= alloc_temp(pc
, NULL
);
1128 emit_pow(pc
, temp
, src
[0][0], src
[1][0]);
1129 for (c
= 0; c
< 4; c
++) {
1130 if (!(mask
& (1 << c
)))
1132 emit_mov(pc
, dst
[c
], temp
);
1134 free_temp(pc
, temp
);
1136 case TGSI_OPCODE_RCP
:
1137 for (c
= 0; c
< 4; c
++) {
1138 if (!(mask
& (1 << c
)))
1140 emit_flop(pc
, 0, dst
[c
], src
[0][0]);
1143 case TGSI_OPCODE_RSQ
:
1144 for (c
= 0; c
< 4; c
++) {
1145 if (!(mask
& (1 << c
)))
1147 emit_flop(pc
, 2, dst
[c
], src
[0][0]);
1150 case TGSI_OPCODE_SCS
:
1151 temp
= alloc_temp(pc
, NULL
);
1152 emit_precossin(pc
, temp
, src
[0][0]);
1153 if (mask
& (1 << 0))
1154 emit_flop(pc
, 5, dst
[0], temp
);
1155 if (mask
& (1 << 1))
1156 emit_flop(pc
, 4, dst
[1], temp
);
1158 case TGSI_OPCODE_SGE
:
1159 for (c
= 0; c
< 4; c
++) {
1160 if (!(mask
& (1 << c
)))
1162 emit_set(pc
, 6, dst
[c
], src
[0][c
], src
[1][c
]);
1165 case TGSI_OPCODE_SIN
:
1166 temp
= alloc_temp(pc
, NULL
);
1167 emit_precossin(pc
, temp
, src
[0][0]);
1168 emit_flop(pc
, 4, temp
, temp
);
1169 for (c
= 0; c
< 4; c
++) {
1170 if (!(mask
& (1 << c
)))
1172 emit_mov(pc
, dst
[c
], temp
);
1175 case TGSI_OPCODE_SLT
:
1176 for (c
= 0; c
< 4; c
++) {
1177 if (!(mask
& (1 << c
)))
1179 emit_set(pc
, 1, dst
[c
], src
[0][c
], src
[1][c
]);
1182 case TGSI_OPCODE_SUB
:
1183 for (c
= 0; c
< 4; c
++) {
1184 if (!(mask
& (1 << c
)))
1186 emit_sub(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
1189 case TGSI_OPCODE_TEX
:
1190 case TGSI_OPCODE_TXP
:
1192 struct nv50_reg
*t
[4];
1193 struct nv50_program_exec
*e
;
1195 alloc_temp4(pc
, t
, 0);
1196 emit_mov(pc
, t
[0], src
[0][0]);
1197 emit_mov(pc
, t
[1], src
[0][1]);
1200 e
->inst
[0] = 0xf6400000;
1202 e
->inst
[1] |= 0x0000c004;
1203 set_dst(pc
, t
[0], e
);
1206 if (mask
& (1 << 0)) emit_mov(pc
, dst
[0], t
[0]);
1207 if (mask
& (1 << 1)) emit_mov(pc
, dst
[1], t
[1]);
1208 if (mask
& (1 << 2)) emit_mov(pc
, dst
[2], t
[2]);
1209 if (mask
& (1 << 3)) emit_mov(pc
, dst
[3], t
[3]);
1214 case TGSI_OPCODE_XPD
:
1215 temp
= alloc_temp(pc
, NULL
);
1216 if (mask
& (1 << 0)) {
1217 emit_mul(pc
, temp
, src
[0][2], src
[1][1]);
1218 emit_msb(pc
, dst
[0], src
[0][1], src
[1][2], temp
);
1220 if (mask
& (1 << 1)) {
1221 emit_mul(pc
, temp
, src
[0][0], src
[1][2]);
1222 emit_msb(pc
, dst
[1], src
[0][2], src
[1][0], temp
);
1224 if (mask
& (1 << 2)) {
1225 emit_mul(pc
, temp
, src
[0][1], src
[1][0]);
1226 emit_msb(pc
, dst
[2], src
[0][0], src
[1][1], temp
);
1228 free_temp(pc
, temp
);
1230 case TGSI_OPCODE_END
:
1233 NOUVEAU_ERR("invalid opcode %d\n", inst
->Instruction
.Opcode
);
1238 for (c
= 0; c
< 4; c
++) {
1239 struct nv50_program_exec
*e
;
1241 if (!(mask
& (1 << c
)))
1245 e
->inst
[0] = 0xa0000000; /* cvt */
1247 e
->inst
[1] |= (6 << 29); /* cvt */
1248 e
->inst
[1] |= 0x04000000; /* 32 bit */
1249 e
->inst
[1] |= (1 << 14); /* src .f32 */
1250 e
->inst
[1] |= ((1 << 5) << 14); /* .sat */
1251 set_dst(pc
, rdst
[c
], e
);
1252 set_src_0(pc
, dst
[c
], e
);
1262 nv50_program_tx_prep(struct nv50_pc
*pc
)
1264 struct tgsi_parse_context p
;
1265 boolean ret
= FALSE
;
1268 tgsi_parse_init(&p
, pc
->p
->pipe
.tokens
);
1269 while (!tgsi_parse_end_of_tokens(&p
)) {
1270 const union tgsi_full_token
*tok
= &p
.FullToken
;
1272 tgsi_parse_token(&p
);
1273 switch (tok
->Token
.Type
) {
1274 case TGSI_TOKEN_TYPE_IMMEDIATE
:
1276 const struct tgsi_full_immediate
*imm
=
1277 &p
.FullToken
.FullImmediate
;
1279 ctor_immd(pc
, imm
->u
.ImmediateFloat32
[0].Float
,
1280 imm
->u
.ImmediateFloat32
[1].Float
,
1281 imm
->u
.ImmediateFloat32
[2].Float
,
1282 imm
->u
.ImmediateFloat32
[3].Float
);
1285 case TGSI_TOKEN_TYPE_DECLARATION
:
1287 const struct tgsi_full_declaration
*d
;
1290 d
= &p
.FullToken
.FullDeclaration
;
1291 last
= d
->DeclarationRange
.Last
;
1293 switch (d
->Declaration
.File
) {
1294 case TGSI_FILE_TEMPORARY
:
1295 if (pc
->temp_nr
< (last
+ 1))
1296 pc
->temp_nr
= last
+ 1;
1298 case TGSI_FILE_OUTPUT
:
1299 if (pc
->result_nr
< (last
+ 1))
1300 pc
->result_nr
= last
+ 1;
1302 case TGSI_FILE_INPUT
:
1303 if (pc
->attr_nr
< (last
+ 1))
1304 pc
->attr_nr
= last
+ 1;
1306 case TGSI_FILE_CONSTANT
:
1307 if (pc
->param_nr
< (last
+ 1))
1308 pc
->param_nr
= last
+ 1;
1310 case TGSI_FILE_SAMPLER
:
1313 NOUVEAU_ERR("bad decl file %d\n",
1314 d
->Declaration
.File
);
1319 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1327 pc
->temp
= CALLOC(pc
->temp_nr
* 4, sizeof(struct nv50_reg
));
1331 for (i
= 0; i
< pc
->temp_nr
; i
++) {
1332 for (c
= 0; c
< 4; c
++) {
1333 pc
->temp
[i
*4+c
].type
= P_TEMP
;
1334 pc
->temp
[i
*4+c
].hw
= -1;
1335 pc
->temp
[i
*4+c
].index
= i
;
1341 struct nv50_reg
*iv
= NULL
;
1344 pc
->attr
= CALLOC(pc
->attr_nr
* 4, sizeof(struct nv50_reg
));
1348 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
) {
1349 iv
= alloc_temp(pc
, NULL
);
1350 emit_interp(pc
, iv
, iv
, NULL
);
1351 emit_flop(pc
, 0, iv
, iv
);
1355 for (i
= 0; i
< pc
->attr_nr
; i
++) {
1356 struct nv50_reg
*a
= &pc
->attr
[i
*4];
1358 for (c
= 0; c
< 4; c
++) {
1359 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
) {
1360 struct nv50_reg
*at
=
1361 alloc_temp(pc
, NULL
);
1362 pc
->attr
[i
*4+c
].type
= at
->type
;
1363 pc
->attr
[i
*4+c
].hw
= at
->hw
;
1364 pc
->attr
[i
*4+c
].index
= at
->index
;
1366 pc
->p
->cfg
.vp
.attr
[aid
/32] |=
1368 pc
->attr
[i
*4+c
].type
= P_ATTR
;
1369 pc
->attr
[i
*4+c
].hw
= aid
++;
1370 pc
->attr
[i
*4+c
].index
= i
;
1374 if (pc
->p
->type
!= PIPE_SHADER_FRAGMENT
)
1377 emit_interp(pc
, &a
[0], &a
[0], iv
);
1378 emit_interp(pc
, &a
[1], &a
[1], iv
);
1379 emit_interp(pc
, &a
[2], &a
[2], iv
);
1380 emit_interp(pc
, &a
[3], &a
[3], iv
);
1387 if (pc
->result_nr
) {
1390 pc
->result
= CALLOC(pc
->result_nr
* 4, sizeof(struct nv50_reg
));
1394 for (i
= 0; i
< pc
->result_nr
; i
++) {
1395 for (c
= 0; c
< 4; c
++) {
1396 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
) {
1397 pc
->result
[i
*4+c
].type
= P_TEMP
;
1398 pc
->result
[i
*4+c
].hw
= -1;
1400 pc
->result
[i
*4+c
].type
= P_RESULT
;
1401 pc
->result
[i
*4+c
].hw
= rid
++;
1403 pc
->result
[i
*4+c
].index
= i
;
1411 pc
->param
= CALLOC(pc
->param_nr
* 4, sizeof(struct nv50_reg
));
1415 for (i
= 0; i
< pc
->param_nr
; i
++) {
1416 for (c
= 0; c
< 4; c
++) {
1417 pc
->param
[i
*4+c
].type
= P_CONST
;
1418 pc
->param
[i
*4+c
].hw
= rid
++;
1419 pc
->param
[i
*4+c
].index
= i
;
1425 int rid
= pc
->param_nr
* 4;
1427 pc
->immd
= CALLOC(pc
->immd_nr
* 4, sizeof(struct nv50_reg
));
1431 for (i
= 0; i
< pc
->immd_nr
; i
++) {
1432 for (c
= 0; c
< 4; c
++) {
1433 pc
->immd
[i
*4+c
].type
= P_IMMD
;
1434 pc
->immd
[i
*4+c
].hw
= rid
++;
1435 pc
->immd
[i
*4+c
].index
= i
;
1442 tgsi_parse_free(&p
);
1447 nv50_program_tx(struct nv50_program
*p
)
1449 struct tgsi_parse_context parse
;
1453 pc
= CALLOC_STRUCT(nv50_pc
);
1457 pc
->p
->cfg
.high_temp
= 4;
1459 ret
= nv50_program_tx_prep(pc
);
1463 tgsi_parse_init(&parse
, pc
->p
->pipe
.tokens
);
1464 while (!tgsi_parse_end_of_tokens(&parse
)) {
1465 const union tgsi_full_token
*tok
= &parse
.FullToken
;
1467 tgsi_parse_token(&parse
);
1469 switch (tok
->Token
.Type
) {
1470 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1471 ret
= nv50_program_tx_insn(pc
, tok
);
1480 if (p
->type
== PIPE_SHADER_FRAGMENT
) {
1481 struct nv50_reg out
;
1484 for (out
.hw
= 0; out
.hw
< pc
->result_nr
* 4; out
.hw
++)
1485 emit_mov(pc
, &out
, &pc
->result
[out
.hw
]);
1488 assert(is_long(pc
->p
->exec_tail
) && !is_immd(pc
->p
->exec_head
));
1489 pc
->p
->exec_tail
->inst
[1] |= 0x00000001;
1491 p
->param_nr
= pc
->param_nr
* 4;
1492 p
->immd_nr
= pc
->immd_nr
* 4;
1493 p
->immd
= pc
->immd_buf
;
1496 tgsi_parse_free(&parse
);
1503 nv50_program_validate(struct nv50_context
*nv50
, struct nv50_program
*p
)
1505 if (nv50_program_tx(p
) == FALSE
)
1507 p
->translated
= TRUE
;
1511 nv50_program_upload_data(struct nv50_context
*nv50
, float *map
,
1512 unsigned start
, unsigned count
)
1515 unsigned nr
= count
> 2047 ? 2047 : count
;
1517 BEGIN_RING(tesla
, 0x00000f00, 1);
1518 OUT_RING ((NV50_CB_PMISC
<< 0) | (start
<< 8));
1519 BEGIN_RING(tesla
, 0x40000f04, nr
);
1520 OUT_RINGp (map
, nr
);
1529 nv50_program_validate_data(struct nv50_context
*nv50
, struct nv50_program
*p
)
1531 struct nouveau_winsys
*nvws
= nv50
->screen
->nvws
;
1532 struct pipe_winsys
*ws
= nv50
->pipe
.winsys
;
1533 unsigned nr
= p
->param_nr
+ p
->immd_nr
;
1535 if (!p
->data
&& nr
) {
1536 struct nouveau_resource
*heap
= nv50
->screen
->vp_data_heap
;
1538 if (nvws
->res_alloc(heap
, nr
, p
, &p
->data
)) {
1539 while (heap
->next
&& heap
->size
< nr
) {
1540 struct nv50_program
*evict
= heap
->next
->priv
;
1541 nvws
->res_free(&evict
->data
);
1544 if (nvws
->res_alloc(heap
, nr
, p
, &p
->data
))
1550 float *map
= ws
->buffer_map(ws
, nv50
->constbuf
[p
->type
],
1551 PIPE_BUFFER_USAGE_CPU_READ
);
1552 nv50_program_upload_data(nv50
, map
, p
->data
->start
,
1554 ws
->buffer_unmap(ws
, nv50
->constbuf
[p
->type
]);
1558 nv50_program_upload_data(nv50
, p
->immd
,
1559 p
->data
->start
+ p
->param_nr
,
1565 nv50_program_validate_code(struct nv50_context
*nv50
, struct nv50_program
*p
)
1567 struct pipe_winsys
*ws
= nv50
->pipe
.winsys
;
1568 struct nv50_program_exec
*e
;
1569 struct nouveau_stateobj
*so
;
1570 const unsigned flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_WR
;
1571 unsigned start
, count
, *up
, *ptr
;
1572 boolean upload
= FALSE
;
1575 p
->buffer
= ws
->buffer_create(ws
, 0x100, 0, p
->exec_size
* 4);
1579 if (p
->data
&& p
->data
->start
!= p
->data_start
) {
1580 for (e
= p
->exec_head
; e
; e
= e
->next
) {
1583 if (e
->param
.index
< 0)
1585 ei
= e
->param
.shift
>> 5;
1586 ci
= e
->param
.index
+ p
->data
->start
;
1588 e
->inst
[ei
] &= ~e
->param
.mask
;
1589 e
->inst
[ei
] |= (ci
<< e
->param
.shift
);
1592 p
->data_start
= p
->data
->start
;
1599 NOUVEAU_ERR("-------\n");
1600 up
= ptr
= MALLOC(p
->exec_size
* 4);
1601 for (e
= p
->exec_head
; e
; e
= e
->next
) {
1602 NOUVEAU_ERR("0x%08x\n", e
->inst
[0]);
1604 NOUVEAU_ERR("0x%08x\n", e
->inst
[1]);
1606 *(ptr
++) = e
->inst
[0];
1608 *(ptr
++) = e
->inst
[1];
1612 so_method(so
, nv50
->screen
->tesla
, 0x1280, 3);
1613 so_reloc (so
, p
->buffer
, 0, flags
| NOUVEAU_BO_HIGH
, 0, 0);
1614 so_reloc (so
, p
->buffer
, 0, flags
| NOUVEAU_BO_LOW
, 0, 0);
1615 so_data (so
, (NV50_CB_PUPLOAD
<< 16) | 0x0800); //(p->exec_size * 4));
1617 start
= 0; count
= p
->exec_size
;
1619 struct nouveau_winsys
*nvws
= nv50
->screen
->nvws
;
1624 nr
= MIN2(count
, 2047);
1625 nr
= MIN2(nvws
->channel
->pushbuf
->remaining
, nr
);
1626 if (nvws
->channel
->pushbuf
->remaining
< (nr
+ 3)) {
1631 BEGIN_RING(tesla
, 0x0f00, 1);
1632 OUT_RING ((start
<< 8) | NV50_CB_PUPLOAD
);
1633 BEGIN_RING(tesla
, 0x40000f04, nr
);
1634 OUT_RINGp (up
+ start
, nr
);
1645 nv50_vertprog_validate(struct nv50_context
*nv50
)
1647 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
1648 struct nv50_program
*p
= nv50
->vertprog
;
1649 struct nouveau_stateobj
*so
;
1651 if (!p
->translated
) {
1652 nv50_program_validate(nv50
, p
);
1657 nv50_program_validate_data(nv50
, p
);
1658 nv50_program_validate_code(nv50
, p
);
1661 so_method(so
, tesla
, NV50TCL_VP_ADDRESS_HIGH
, 2);
1662 so_reloc (so
, p
->buffer
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
1663 NOUVEAU_BO_HIGH
, 0, 0);
1664 so_reloc (so
, p
->buffer
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
1665 NOUVEAU_BO_LOW
, 0, 0);
1666 so_method(so
, tesla
, 0x1650, 2);
1667 so_data (so
, p
->cfg
.vp
.attr
[0]);
1668 so_data (so
, p
->cfg
.vp
.attr
[1]);
1669 so_method(so
, tesla
, 0x16b8, 1);
1670 so_data (so
, p
->cfg
.high_result
);
1671 so_method(so
, tesla
, 0x16ac, 2);
1672 so_data (so
, p
->cfg
.high_result
); //8);
1673 so_data (so
, p
->cfg
.high_temp
);
1674 so_method(so
, tesla
, 0x140c, 1);
1675 so_data (so
, 0); /* program start offset */
1676 so_ref(so
, &nv50
->state
.vertprog
);
1680 nv50_fragprog_validate(struct nv50_context
*nv50
)
1682 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
1683 struct nv50_program
*p
= nv50
->fragprog
;
1684 struct nouveau_stateobj
*so
;
1686 if (!p
->translated
) {
1687 nv50_program_validate(nv50
, p
);
1692 nv50_program_validate_data(nv50
, p
);
1693 nv50_program_validate_code(nv50
, p
);
1696 so_method(so
, tesla
, NV50TCL_FP_ADDRESS_HIGH
, 2);
1697 so_reloc (so
, p
->buffer
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
1698 NOUVEAU_BO_HIGH
, 0, 0);
1699 so_reloc (so
, p
->buffer
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
1700 NOUVEAU_BO_LOW
, 0, 0);
1701 so_method(so
, tesla
, 0x1904, 4);
1702 so_data (so
, 0x01040404); /* p: 0x01000404 */
1703 so_data (so
, 0x00000004);
1704 so_data (so
, 0x00000000);
1705 so_data (so
, 0x00000000);
1706 so_method(so
, tesla
, 0x16bc, 3); /*XXX: fixme */
1707 so_data (so
, 0x03020100);
1708 so_data (so
, 0x07060504);
1709 so_data (so
, 0x0b0a0908);
1710 so_method(so
, tesla
, 0x1988, 2);
1711 so_data (so
, 0x08080408); //0x08040404); /* p: 0x0f000401 */
1712 so_data (so
, p
->cfg
.high_temp
);
1713 so_method(so
, tesla
, 0x1414, 1);
1714 so_data (so
, 0); /* program start offset */
1715 so_ref(so
, &nv50
->state
.fragprog
);
1719 nv50_program_destroy(struct nv50_context
*nv50
, struct nv50_program
*p
)
1721 struct pipe_winsys
*ws
= nv50
->pipe
.winsys
;
1723 while (p
->exec_head
) {
1724 struct nv50_program_exec
*e
= p
->exec_head
;
1726 p
->exec_head
= e
->next
;
1729 p
->exec_tail
= NULL
;
1733 pipe_buffer_reference(ws
, &p
->buffer
, NULL
);
1735 nv50
->screen
->nvws
->res_free(&p
->data
);