2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
32 #include "nv50_context.h"
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
40 /* ARL - gallium craps itself on progs/vp/arl.txt
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
93 int rhw
; /* result hw for FP outputs, or interpolant index */
94 int acc
; /* instruction where this reg is last read (first insn == 1) */
97 /* arbitrary limits */
98 #define MAX_IF_DEPTH 4
99 #define MAX_LOOP_DEPTH 4
102 struct nv50_program
*p
;
105 struct nv50_reg
*r_temp
[NV50_SU_MAX_TEMP
];
106 struct nv50_reg r_addr
[NV50_SU_MAX_ADDR
];
109 struct nv50_reg
*temp
;
111 struct nv50_reg
*attr
;
113 struct nv50_reg
*result
;
115 struct nv50_reg
*param
;
117 struct nv50_reg
*immd
;
120 struct nv50_reg
**addr
;
123 struct nv50_reg
*temp_temp
[16];
124 unsigned temp_temp_nr
;
126 /* broadcast and destination replacement regs */
127 struct nv50_reg
*r_brdc
;
128 struct nv50_reg
*r_dst
[4];
130 unsigned interp_mode
[32];
131 /* perspective interpolation registers */
132 struct nv50_reg
*iv_p
;
133 struct nv50_reg
*iv_c
;
135 struct nv50_program_exec
*if_cond
;
136 struct nv50_program_exec
*if_insn
[MAX_IF_DEPTH
];
137 struct nv50_program_exec
*br_join
[MAX_IF_DEPTH
];
138 struct nv50_program_exec
*br_loop
[MAX_LOOP_DEPTH
]; /* for BRK branch */
139 int if_lvl
, loop_lvl
;
140 unsigned loop_pos
[MAX_LOOP_DEPTH
];
142 /* current instruction and total number of insns */
150 ctor_reg(struct nv50_reg
*reg
, unsigned type
, int index
, int hw
)
160 static INLINE
unsigned
161 popcnt4(uint32_t val
)
163 static const unsigned cnt
[16]
164 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
165 return cnt
[val
& 0xf];
169 terminate_mbb(struct nv50_pc
*pc
)
173 /* remove records of temporary address register values */
174 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
175 if (pc
->r_addr
[i
].index
< 0)
176 pc
->r_addr
[i
].rhw
= -1;
180 alloc_reg(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
184 if (reg
->type
== P_RESULT
) {
185 if (pc
->p
->cfg
.high_result
< (reg
->hw
+ 1))
186 pc
->p
->cfg
.high_result
= reg
->hw
+ 1;
189 if (reg
->type
!= P_TEMP
)
193 /*XXX: do this here too to catch FP temp-as-attr usage..
194 * not clean, but works */
195 if (pc
->p
->cfg
.high_temp
< (reg
->hw
+ 1))
196 pc
->p
->cfg
.high_temp
= reg
->hw
+ 1;
200 if (reg
->rhw
!= -1) {
201 /* try to allocate temporary with index rhw first */
202 if (!(pc
->r_temp
[reg
->rhw
])) {
203 pc
->r_temp
[reg
->rhw
] = reg
;
205 if (pc
->p
->cfg
.high_temp
< (reg
->rhw
+ 1))
206 pc
->p
->cfg
.high_temp
= reg
->rhw
+ 1;
209 /* make sure we don't get things like $r0 needs to go
210 * in $r1 and $r1 in $r0
212 i
= pc
->result_nr
* 4;
215 for (; i
< NV50_SU_MAX_TEMP
; i
++) {
216 if (!(pc
->r_temp
[i
])) {
219 if (pc
->p
->cfg
.high_temp
< (i
+ 1))
220 pc
->p
->cfg
.high_temp
= i
+ 1;
228 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
229 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
230 * lest we risk temp_temps overwriting regs alloc'd "later".
232 static struct nv50_reg
*
233 alloc_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
)
238 if (dst
&& dst
->type
== P_TEMP
&& dst
->hw
== -1)
241 for (i
= 0; i
< NV50_SU_MAX_TEMP
; i
++) {
242 if (!pc
->r_temp
[i
]) {
243 r
= MALLOC_STRUCT(nv50_reg
);
244 ctor_reg(r
, P_TEMP
, -1, i
);
254 /* Assign the hw of the discarded temporary register src
255 * to the tgsi register dst and free src.
258 assimilate_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
260 assert(src
->index
== -1 && src
->hw
!= -1);
263 pc
->r_temp
[dst
->hw
] = NULL
;
264 pc
->r_temp
[src
->hw
] = dst
;
270 /* release the hardware resource held by r */
272 release_hw(struct nv50_pc
*pc
, struct nv50_reg
*r
)
274 assert(r
->type
== P_TEMP
);
278 assert(pc
->r_temp
[r
->hw
] == r
);
279 pc
->r_temp
[r
->hw
] = NULL
;
287 free_temp(struct nv50_pc
*pc
, struct nv50_reg
*r
)
289 if (r
->index
== -1) {
292 FREE(pc
->r_temp
[hw
]);
293 pc
->r_temp
[hw
] = NULL
;
298 alloc_temp4(struct nv50_pc
*pc
, struct nv50_reg
*dst
[4], int idx
)
302 if ((idx
+ 4) >= NV50_SU_MAX_TEMP
)
305 if (pc
->r_temp
[idx
] || pc
->r_temp
[idx
+ 1] ||
306 pc
->r_temp
[idx
+ 2] || pc
->r_temp
[idx
+ 3])
307 return alloc_temp4(pc
, dst
, idx
+ 4);
309 for (i
= 0; i
< 4; i
++) {
310 dst
[i
] = MALLOC_STRUCT(nv50_reg
);
311 ctor_reg(dst
[i
], P_TEMP
, -1, idx
+ i
);
312 pc
->r_temp
[idx
+ i
] = dst
[i
];
319 free_temp4(struct nv50_pc
*pc
, struct nv50_reg
*reg
[4])
323 for (i
= 0; i
< 4; i
++)
324 free_temp(pc
, reg
[i
]);
327 static struct nv50_reg
*
328 temp_temp(struct nv50_pc
*pc
)
330 if (pc
->temp_temp_nr
>= 16)
333 pc
->temp_temp
[pc
->temp_temp_nr
] = alloc_temp(pc
, NULL
);
334 return pc
->temp_temp
[pc
->temp_temp_nr
++];
338 kill_temp_temp(struct nv50_pc
*pc
)
342 for (i
= 0; i
< pc
->temp_temp_nr
; i
++)
343 free_temp(pc
, pc
->temp_temp
[i
]);
344 pc
->temp_temp_nr
= 0;
348 ctor_immd(struct nv50_pc
*pc
, float x
, float y
, float z
, float w
)
350 pc
->immd_buf
= REALLOC(pc
->immd_buf
, (pc
->immd_nr
* 4 * sizeof(float)),
351 (pc
->immd_nr
+ 1) * 4 * sizeof(float));
352 pc
->immd_buf
[(pc
->immd_nr
* 4) + 0] = x
;
353 pc
->immd_buf
[(pc
->immd_nr
* 4) + 1] = y
;
354 pc
->immd_buf
[(pc
->immd_nr
* 4) + 2] = z
;
355 pc
->immd_buf
[(pc
->immd_nr
* 4) + 3] = w
;
357 return pc
->immd_nr
++;
360 static struct nv50_reg
*
361 alloc_immd(struct nv50_pc
*pc
, float f
)
363 struct nv50_reg
*r
= MALLOC_STRUCT(nv50_reg
);
366 for (hw
= 0; hw
< pc
->immd_nr
* 4; hw
++)
367 if (pc
->immd_buf
[hw
] == f
)
370 if (hw
== pc
->immd_nr
* 4)
371 hw
= ctor_immd(pc
, f
, -f
, 0.5 * f
, 0) * 4;
373 ctor_reg(r
, P_IMMD
, -1, hw
);
377 static struct nv50_program_exec
*
378 exec(struct nv50_pc
*pc
)
380 struct nv50_program_exec
*e
= CALLOC_STRUCT(nv50_program_exec
);
387 emit(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
389 struct nv50_program
*p
= pc
->p
;
392 p
->exec_tail
->next
= e
;
396 p
->exec_size
+= (e
->inst
[0] & 1) ? 2 : 1;
399 static INLINE
void set_long(struct nv50_pc
*, struct nv50_program_exec
*);
402 is_long(struct nv50_program_exec
*e
)
410 is_immd(struct nv50_program_exec
*e
)
412 if (is_long(e
) && (e
->inst
[1] & 3) == 3)
418 set_pred(struct nv50_pc
*pc
, unsigned pred
, unsigned idx
,
419 struct nv50_program_exec
*e
)
422 e
->inst
[1] &= ~((0x1f << 7) | (0x3 << 12));
423 e
->inst
[1] |= (pred
<< 7) | (idx
<< 12);
427 set_pred_wr(struct nv50_pc
*pc
, unsigned on
, unsigned idx
,
428 struct nv50_program_exec
*e
)
431 e
->inst
[1] &= ~((0x3 << 4) | (1 << 6));
432 e
->inst
[1] |= (idx
<< 4) | (on
<< 6);
436 set_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
442 set_pred(pc
, 0xf, 0, e
);
443 set_pred_wr(pc
, 0, 0, e
);
447 set_dst(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_program_exec
*e
)
449 if (dst
->type
== P_RESULT
) {
451 e
->inst
[1] |= 0x00000008;
457 e
->inst
[0] |= (dst
->hw
<< 2);
461 set_immd(struct nv50_pc
*pc
, struct nv50_reg
*imm
, struct nv50_program_exec
*e
)
463 float f
= pc
->immd_buf
[imm
->hw
];
464 unsigned val
= fui(imm
->neg
? -f
: f
);
467 /*XXX: can't be predicated - bits overlap.. catch cases where both
468 * are required and avoid them. */
469 set_pred(pc
, 0, 0, e
);
470 set_pred_wr(pc
, 0, 0, e
);
472 e
->inst
[1] |= 0x00000002 | 0x00000001;
473 e
->inst
[0] |= (val
& 0x3f) << 16;
474 e
->inst
[1] |= (val
>> 6) << 2;
478 set_addr(struct nv50_program_exec
*e
, struct nv50_reg
*a
)
480 assert(!(e
->inst
[0] & 0x0c000000));
481 assert(!(e
->inst
[1] & 0x00000004));
483 e
->inst
[0] |= (a
->hw
& 3) << 26;
484 e
->inst
[1] |= (a
->hw
>> 2) << 2;
488 emit_add_addr_imm(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
489 struct nv50_reg
*src0
, uint16_t src1_val
)
491 struct nv50_program_exec
*e
= exec(pc
);
493 e
->inst
[0] = 0xd0000000 | (src1_val
<< 9);
494 e
->inst
[1] = 0x20000000;
496 e
->inst
[0] |= dst
->hw
<< 2;
497 if (src0
) /* otherwise will add to $a0, which is always 0 */
503 static struct nv50_reg
*
504 alloc_addr(struct nv50_pc
*pc
, struct nv50_reg
*ref
)
507 struct nv50_reg
*a_tgsi
= NULL
, *a
= NULL
;
510 /* allocate for TGSI address reg */
511 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
) {
512 if (pc
->r_addr
[i
].index
>= 0)
514 if (pc
->r_addr
[i
].rhw
>= 0 &&
515 pc
->r_addr
[i
].acc
== pc
->insn_cur
)
518 pc
->r_addr
[i
].rhw
= -1;
519 pc
->r_addr
[i
].index
= i
;
520 return &pc
->r_addr
[i
];
526 /* Allocate and set an address reg so we can access 'ref'.
528 * If and r_addr has index < 0, it is not reserved for TGSI,
529 * and index will be the negative of the TGSI addr index the
530 * value in rhw is relative to, or -256 if rhw is an offset
531 * from 0. If rhw < 0, the reg has not been initialized.
533 for (i
= NV50_SU_MAX_ADDR
- 1; i
>= 0; --i
) {
534 if (pc
->r_addr
[i
].index
>= 0) /* occupied for TGSI */
536 if (pc
->r_addr
[i
].rhw
< 0) { /* unused */
540 if (!a
&& pc
->r_addr
[i
].acc
!= pc
->insn_cur
)
543 if (ref
->hw
- pc
->r_addr
[i
].rhw
>= 128)
546 if ((ref
->acc
>= 0 && pc
->r_addr
[i
].index
== -256) ||
547 (ref
->acc
< 0 && -pc
->r_addr
[i
].index
== ref
->index
)) {
548 pc
->r_addr
[i
].acc
= pc
->insn_cur
;
549 return &pc
->r_addr
[i
];
555 a_tgsi
= pc
->addr
[ref
->index
];
557 emit_add_addr_imm(pc
, a
, a_tgsi
, (ref
->hw
& ~0x7f) * 4);
559 a
->rhw
= ref
->hw
& ~0x7f;
560 a
->acc
= pc
->insn_cur
;
561 a
->index
= a_tgsi
? -ref
->index
: -256;
565 #define INTERP_LINEAR 0
566 #define INTERP_FLAT 1
567 #define INTERP_PERSPECTIVE 2
568 #define INTERP_CENTROID 4
570 /* interpolant index has been stored in dst->rhw */
572 emit_interp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*iv
,
575 assert(dst
->rhw
!= -1);
576 struct nv50_program_exec
*e
= exec(pc
);
578 e
->inst
[0] |= 0x80000000;
580 e
->inst
[0] |= (dst
->rhw
<< 16);
582 if (mode
& INTERP_FLAT
) {
583 e
->inst
[0] |= (1 << 8);
585 if (mode
& INTERP_PERSPECTIVE
) {
586 e
->inst
[0] |= (1 << 25);
588 e
->inst
[0] |= (iv
->hw
<< 9);
591 if (mode
& INTERP_CENTROID
)
592 e
->inst
[0] |= (1 << 24);
599 set_data(struct nv50_pc
*pc
, struct nv50_reg
*src
, unsigned m
, unsigned s
,
600 struct nv50_program_exec
*e
)
604 e
->param
.index
= src
->hw
& 127;
606 e
->param
.mask
= m
<< (s
% 32);
609 set_addr(e
, alloc_addr(pc
, src
));
612 assert(src
->type
== P_CONST
);
613 set_addr(e
, pc
->addr
[src
->index
]);
616 e
->inst
[1] |= (((src
->type
== P_IMMD
) ? 0 : 1) << 22);
620 emit_mov(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
622 struct nv50_program_exec
*e
= exec(pc
);
624 e
->inst
[0] = 0x10000000;
630 if (!is_long(e
) && src
->type
== P_IMMD
) {
631 set_immd(pc
, src
, e
);
632 /*XXX: 32-bit, but steals part of "half" reg space - need to
633 * catch and handle this case if/when we do half-regs
636 if (src
->type
== P_IMMD
|| src
->type
== P_CONST
) {
638 set_data(pc
, src
, 0x7f, 9, e
);
639 e
->inst
[1] |= 0x20000000; /* src0 const? */
641 if (src
->type
== P_ATTR
) {
643 e
->inst
[1] |= 0x00200000;
649 e
->inst
[0] |= (src
->hw
<< 9);
652 if (is_long(e
) && !is_immd(e
)) {
653 e
->inst
[1] |= 0x04000000; /* 32-bit */
654 e
->inst
[1] |= 0x0000c000; /* "subsubop" 0x3 */
655 if (!(e
->inst
[1] & 0x20000000))
656 e
->inst
[1] |= 0x00030000; /* "subsubop" 0xf */
658 e
->inst
[0] |= 0x00008000;
664 emit_mov_immdval(struct nv50_pc
*pc
, struct nv50_reg
*dst
, float f
)
666 struct nv50_reg
*imm
= alloc_immd(pc
, f
);
667 emit_mov(pc
, dst
, imm
);
672 check_swap_src_0_1(struct nv50_pc
*pc
,
673 struct nv50_reg
**s0
, struct nv50_reg
**s1
)
675 struct nv50_reg
*src0
= *s0
, *src1
= *s1
;
677 if (src0
->type
== P_CONST
) {
678 if (src1
->type
!= P_CONST
) {
684 if (src1
->type
== P_ATTR
) {
685 if (src0
->type
!= P_ATTR
) {
696 set_src_0_restricted(struct nv50_pc
*pc
, struct nv50_reg
*src
,
697 struct nv50_program_exec
*e
)
699 struct nv50_reg
*temp
;
701 if (src
->type
!= P_TEMP
) {
702 temp
= temp_temp(pc
);
703 emit_mov(pc
, temp
, src
);
710 e
->inst
[0] |= (src
->hw
<< 9);
714 set_src_0(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
716 if (src
->type
== P_ATTR
) {
718 e
->inst
[1] |= 0x00200000;
720 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
721 struct nv50_reg
*temp
= temp_temp(pc
);
723 emit_mov(pc
, temp
, src
);
730 e
->inst
[0] |= (src
->hw
<< 9);
734 set_src_1(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
736 if (src
->type
== P_ATTR
) {
737 struct nv50_reg
*temp
= temp_temp(pc
);
739 emit_mov(pc
, temp
, src
);
742 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
743 assert(!(e
->inst
[0] & 0x00800000));
744 if (e
->inst
[0] & 0x01000000) {
745 struct nv50_reg
*temp
= temp_temp(pc
);
747 emit_mov(pc
, temp
, src
);
750 set_data(pc
, src
, 0x7f, 16, e
);
751 e
->inst
[0] |= 0x00800000;
758 e
->inst
[0] |= ((src
->hw
& 127) << 16);
762 set_src_2(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
766 if (src
->type
== P_ATTR
) {
767 struct nv50_reg
*temp
= temp_temp(pc
);
769 emit_mov(pc
, temp
, src
);
772 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
773 assert(!(e
->inst
[0] & 0x01000000));
774 if (e
->inst
[0] & 0x00800000) {
775 struct nv50_reg
*temp
= temp_temp(pc
);
777 emit_mov(pc
, temp
, src
);
780 set_data(pc
, src
, 0x7f, 32+14, e
);
781 e
->inst
[0] |= 0x01000000;
786 e
->inst
[1] |= ((src
->hw
& 127) << 14);
790 emit_mul(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
791 struct nv50_reg
*src1
)
793 struct nv50_program_exec
*e
= exec(pc
);
795 e
->inst
[0] |= 0xc0000000;
800 check_swap_src_0_1(pc
, &src0
, &src1
);
802 set_src_0(pc
, src0
, e
);
803 if (src1
->type
== P_IMMD
&& !is_long(e
)) {
805 e
->inst
[0] |= 0x00008000;
806 set_immd(pc
, src1
, e
);
808 set_src_1(pc
, src1
, e
);
809 if (src0
->neg
^ src1
->neg
) {
811 e
->inst
[1] |= 0x08000000;
813 e
->inst
[0] |= 0x00008000;
821 emit_add(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
822 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
824 struct nv50_program_exec
*e
= exec(pc
);
826 e
->inst
[0] = 0xb0000000;
829 check_swap_src_0_1(pc
, &src0
, &src1
);
831 if (!pc
->allow32
|| (src0
->neg
| src1
->neg
) || src1
->hw
> 63) {
833 e
->inst
[1] |= (src0
->neg
<< 26) | (src1
->neg
<< 27);
837 set_src_0(pc
, src0
, e
);
838 if (src1
->type
== P_CONST
|| src1
->type
== P_ATTR
|| is_long(e
))
839 set_src_2(pc
, src1
, e
);
841 if (src1
->type
== P_IMMD
)
842 set_immd(pc
, src1
, e
);
844 set_src_1(pc
, src1
, e
);
850 emit_arl(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
853 struct nv50_program_exec
*e
= exec(pc
);
856 e
->inst
[1] |= 0xc0000000;
858 e
->inst
[0] |= dst
->hw
<< 2;
859 e
->inst
[0] |= s
<< 16; /* shift left */
860 set_src_0_restricted(pc
, src
, e
);
866 emit_minmax(struct nv50_pc
*pc
, unsigned sub
, struct nv50_reg
*dst
,
867 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
869 struct nv50_program_exec
*e
= exec(pc
);
872 e
->inst
[0] |= 0xb0000000;
873 e
->inst
[1] |= (sub
<< 29);
875 check_swap_src_0_1(pc
, &src0
, &src1
);
877 set_src_0(pc
, src0
, e
);
878 set_src_1(pc
, src1
, e
);
884 emit_sub(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
885 struct nv50_reg
*src1
)
887 assert(src0
!= src1
);
889 emit_add(pc
, dst
, src0
, src1
);
894 emit_bitop2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
895 struct nv50_reg
*src1
, unsigned op
)
897 struct nv50_program_exec
*e
= exec(pc
);
899 e
->inst
[0] = 0xd0000000;
902 check_swap_src_0_1(pc
, &src0
, &src1
);
904 set_src_0(pc
, src0
, e
);
906 if (op
!= TGSI_OPCODE_AND
&& op
!= TGSI_OPCODE_OR
&&
907 op
!= TGSI_OPCODE_XOR
)
908 assert(!"invalid bit op");
910 if (src1
->type
== P_IMMD
&& src0
->type
== P_TEMP
&& pc
->allow32
) {
911 set_immd(pc
, src1
, e
);
912 if (op
== TGSI_OPCODE_OR
)
913 e
->inst
[0] |= 0x0100;
915 if (op
== TGSI_OPCODE_XOR
)
916 e
->inst
[0] |= 0x8000;
918 set_src_1(pc
, src1
, e
);
919 e
->inst
[1] |= 0x04000000; /* 32 bit */
920 if (op
== TGSI_OPCODE_OR
)
921 e
->inst
[1] |= 0x4000;
923 if (op
== TGSI_OPCODE_XOR
)
924 e
->inst
[1] |= 0x8000;
931 emit_mad(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
932 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
934 struct nv50_program_exec
*e
= exec(pc
);
936 e
->inst
[0] |= 0xe0000000;
938 check_swap_src_0_1(pc
, &src0
, &src1
);
940 set_src_0(pc
, src0
, e
);
941 set_src_1(pc
, src1
, e
);
942 set_src_2(pc
, src2
, e
);
944 if (src0
->neg
^ src1
->neg
)
945 e
->inst
[1] |= 0x04000000;
947 e
->inst
[1] |= 0x08000000;
953 emit_msb(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
954 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
956 assert(src2
!= src0
&& src2
!= src1
);
958 emit_mad(pc
, dst
, src0
, src1
, src2
);
963 emit_flop(struct nv50_pc
*pc
, unsigned sub
,
964 struct nv50_reg
*dst
, struct nv50_reg
*src
)
966 struct nv50_program_exec
*e
= exec(pc
);
968 e
->inst
[0] |= 0x90000000;
971 e
->inst
[1] |= (sub
<< 29);
976 if (sub
== 0 || sub
== 2)
977 set_src_0_restricted(pc
, src
, e
);
979 set_src_0(pc
, src
, e
);
985 emit_preex2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
987 struct nv50_program_exec
*e
= exec(pc
);
989 e
->inst
[0] |= 0xb0000000;
992 set_src_0(pc
, src
, e
);
994 e
->inst
[1] |= (6 << 29) | 0x00004000;
1000 emit_precossin(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1002 struct nv50_program_exec
*e
= exec(pc
);
1004 e
->inst
[0] |= 0xb0000000;
1006 set_dst(pc
, dst
, e
);
1007 set_src_0(pc
, src
, e
);
1009 e
->inst
[1] |= (6 << 29);
1014 #define CVTOP_RN 0x01
1015 #define CVTOP_FLOOR 0x03
1016 #define CVTOP_CEIL 0x05
1017 #define CVTOP_TRUNC 0x07
1018 #define CVTOP_SAT 0x08
1019 #define CVTOP_ABS 0x10
1021 /* 0x04 == 32 bit dst */
1022 /* 0x40 == dst is float */
1023 /* 0x80 == src is float */
1024 #define CVT_F32_F32 0xc4
1025 #define CVT_F32_S32 0x44
1026 #define CVT_S32_F32 0x8c
1027 #define CVT_S32_S32 0x0c
1028 #define CVT_NEG 0x20
1032 emit_cvt(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
1033 int wp
, unsigned cvn
, unsigned fmt
)
1035 struct nv50_program_exec
*e
;
1040 e
->inst
[0] |= 0xa0000000;
1041 e
->inst
[1] |= 0x00004000; /* 32 bit src */
1042 e
->inst
[1] |= (cvn
<< 16);
1043 e
->inst
[1] |= (fmt
<< 24);
1044 set_src_0(pc
, src
, e
);
1047 set_pred_wr(pc
, 1, wp
, e
);
1050 set_dst(pc
, dst
, e
);
1052 e
->inst
[0] |= 0x000001fc;
1053 e
->inst
[1] |= 0x00000008;
1059 /* nv50 Condition codes:
1066 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1067 * 0x8 = unordered bit (allows NaN)
1070 emit_set(struct nv50_pc
*pc
, unsigned ccode
, struct nv50_reg
*dst
, int wp
,
1071 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
1073 static const unsigned cc_swapped
[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1075 struct nv50_program_exec
*e
= exec(pc
);
1076 struct nv50_reg
*rdst
;
1079 if (check_swap_src_0_1(pc
, &src0
, &src1
))
1080 ccode
= cc_swapped
[ccode
& 7] | (ccode
& 8);
1083 if (dst
&& dst
->type
!= P_TEMP
)
1084 dst
= alloc_temp(pc
, NULL
);
1088 e
->inst
[0] |= 0xb0000000;
1089 e
->inst
[1] |= 0x60000000 | (ccode
<< 14);
1091 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1092 * that doesn't seem to match what the hw actually does
1093 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1097 set_pred_wr(pc
, 1, wp
, e
);
1099 set_dst(pc
, dst
, e
);
1101 e
->inst
[0] |= 0x000001fc;
1102 e
->inst
[1] |= 0x00000008;
1105 set_src_0(pc
, src0
, e
);
1106 set_src_1(pc
, src1
, e
);
1109 pc
->if_cond
= pc
->p
->exec_tail
; /* record for OPCODE_IF */
1111 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1113 emit_cvt(pc
, rdst
, dst
, -1, CVTOP_ABS
| CVTOP_RN
, CVT_F32_S32
);
1114 if (rdst
&& rdst
!= dst
)
1118 static INLINE
unsigned
1119 map_tgsi_setop_cc(unsigned op
)
1122 case TGSI_OPCODE_SLT
: return 0x1;
1123 case TGSI_OPCODE_SGE
: return 0x6;
1124 case TGSI_OPCODE_SEQ
: return 0x2;
1125 case TGSI_OPCODE_SGT
: return 0x4;
1126 case TGSI_OPCODE_SLE
: return 0x3;
1127 case TGSI_OPCODE_SNE
: return 0xd;
1135 emit_flr(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1137 emit_cvt(pc
, dst
, src
, -1, CVTOP_FLOOR
, CVT_F32_F32
| CVT_RI
);
1141 emit_pow(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1142 struct nv50_reg
*v
, struct nv50_reg
*e
)
1144 struct nv50_reg
*temp
= alloc_temp(pc
, NULL
);
1146 emit_flop(pc
, 3, temp
, v
);
1147 emit_mul(pc
, temp
, temp
, e
);
1148 emit_preex2(pc
, temp
, temp
);
1149 emit_flop(pc
, 6, dst
, temp
);
1151 free_temp(pc
, temp
);
1155 emit_abs(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1157 emit_cvt(pc
, dst
, src
, -1, CVTOP_ABS
, CVT_F32_F32
);
1161 emit_sat(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1163 emit_cvt(pc
, dst
, src
, -1, CVTOP_SAT
, CVT_F32_F32
);
1167 emit_lit(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1168 struct nv50_reg
**src
)
1170 struct nv50_reg
*one
= alloc_immd(pc
, 1.0);
1171 struct nv50_reg
*zero
= alloc_immd(pc
, 0.0);
1172 struct nv50_reg
*neg128
= alloc_immd(pc
, -127.999999);
1173 struct nv50_reg
*pos128
= alloc_immd(pc
, 127.999999);
1174 struct nv50_reg
*tmp
[4];
1175 boolean allow32
= pc
->allow32
;
1177 pc
->allow32
= FALSE
;
1179 if (mask
& (3 << 1)) {
1180 tmp
[0] = alloc_temp(pc
, NULL
);
1181 emit_minmax(pc
, 4, tmp
[0], src
[0], zero
);
1184 if (mask
& (1 << 2)) {
1185 set_pred_wr(pc
, 1, 0, pc
->p
->exec_tail
);
1187 tmp
[1] = temp_temp(pc
);
1188 emit_minmax(pc
, 4, tmp
[1], src
[1], zero
);
1190 tmp
[3] = temp_temp(pc
);
1191 emit_minmax(pc
, 4, tmp
[3], src
[3], neg128
);
1192 emit_minmax(pc
, 5, tmp
[3], tmp
[3], pos128
);
1194 emit_pow(pc
, dst
[2], tmp
[1], tmp
[3]);
1195 emit_mov(pc
, dst
[2], zero
);
1196 set_pred(pc
, 3, 0, pc
->p
->exec_tail
);
1199 if (mask
& (1 << 1))
1200 assimilate_temp(pc
, dst
[1], tmp
[0]);
1202 if (mask
& (1 << 2))
1203 free_temp(pc
, tmp
[0]);
1205 pc
->allow32
= allow32
;
1207 /* do this last, in case src[i,j] == dst[0,3] */
1208 if (mask
& (1 << 0))
1209 emit_mov(pc
, dst
[0], one
);
1211 if (mask
& (1 << 3))
1212 emit_mov(pc
, dst
[3], one
);
1221 emit_neg(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1223 emit_cvt(pc
, dst
, src
, -1, CVTOP_RN
, CVT_F32_F32
| CVT_NEG
);
1227 emit_kil(struct nv50_pc
*pc
, struct nv50_reg
*src
)
1229 struct nv50_program_exec
*e
;
1230 const int r_pred
= 1;
1231 unsigned cvn
= CVT_F32_F32
;
1235 /* write predicate reg */
1236 emit_cvt(pc
, NULL
, src
, r_pred
, CVTOP_RN
, cvn
);
1238 /* conditional discard */
1240 e
->inst
[0] = 0x00000002;
1242 set_pred(pc
, 0x1 /* LT */, r_pred
, e
);
1247 emit_tex(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1248 struct nv50_reg
**src
, unsigned unit
, unsigned type
, boolean proj
)
1250 struct nv50_reg
*temp
, *t
[4];
1251 struct nv50_program_exec
*e
;
1253 unsigned c
, mode
, dim
;
1256 case TGSI_TEXTURE_1D
:
1259 case TGSI_TEXTURE_UNKNOWN
:
1260 case TGSI_TEXTURE_2D
:
1261 case TGSI_TEXTURE_SHADOW1D
: /* XXX: x, z */
1262 case TGSI_TEXTURE_RECT
:
1265 case TGSI_TEXTURE_3D
:
1266 case TGSI_TEXTURE_CUBE
:
1267 case TGSI_TEXTURE_SHADOW2D
:
1268 case TGSI_TEXTURE_SHADOWRECT
: /* XXX */
1276 /* some cards need t[0]'s hw index to be a multiple of 4 */
1277 alloc_temp4(pc
, t
, 0);
1280 if (src
[0]->type
== P_TEMP
&& src
[0]->rhw
!= -1) {
1281 mode
= pc
->interp_mode
[src
[0]->index
];
1283 t
[3]->rhw
= src
[3]->rhw
;
1284 emit_interp(pc
, t
[3], NULL
, (mode
& INTERP_CENTROID
));
1285 emit_flop(pc
, 0, t
[3], t
[3]);
1287 for (c
= 0; c
< dim
; c
++) {
1288 t
[c
]->rhw
= src
[c
]->rhw
;
1289 emit_interp(pc
, t
[c
], t
[3],
1290 (mode
| INTERP_PERSPECTIVE
));
1293 emit_flop(pc
, 0, t
[3], src
[3]);
1294 for (c
= 0; c
< dim
; c
++)
1295 emit_mul(pc
, t
[c
], src
[c
], t
[3]);
1297 /* XXX: for some reason the blob sometimes uses MAD:
1298 * emit_mad(pc, t[c], src[0][c], t[3], t[3])
1299 * pc->p->exec_tail->inst[1] |= 0x080fc000;
1303 if (type
== TGSI_TEXTURE_CUBE
) {
1304 temp
= temp_temp(pc
);
1305 emit_minmax(pc
, 4, temp
, src
[0], src
[1]);
1306 emit_minmax(pc
, 4, temp
, temp
, src
[2]);
1307 emit_flop(pc
, 0, temp
, temp
);
1308 for (c
= 0; c
< 3; c
++)
1309 emit_mul(pc
, t
[c
], src
[c
], temp
);
1311 for (c
= 0; c
< dim
; c
++)
1312 emit_mov(pc
, t
[c
], src
[c
]);
1318 e
->inst
[0] |= 0xf0000000;
1319 e
->inst
[1] |= 0x00000004;
1320 set_dst(pc
, t
[0], e
);
1321 e
->inst
[0] |= (unit
<< 9);
1324 e
->inst
[0] |= 0x00400000;
1327 e
->inst
[0] |= 0x00800000;
1329 e
->inst
[0] |= (mask
& 0x3) << 25;
1330 e
->inst
[1] |= (mask
& 0xc) << 12;
1336 if (mask
& 1) emit_mov(pc
, dst
[0], t
[c
++]);
1337 if (mask
& 2) emit_mov(pc
, dst
[1], t
[c
++]);
1338 if (mask
& 4) emit_mov(pc
, dst
[2], t
[c
++]);
1339 if (mask
& 8) emit_mov(pc
, dst
[3], t
[c
]);
1343 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1344 * the texture coordinates, not the fetched values: latency ? */
1346 for (c
= 0; c
< 4; c
++) {
1347 if (mask
& (1 << c
))
1348 assimilate_temp(pc
, dst
[c
], t
[c
]);
1350 free_temp(pc
, t
[c
]);
1356 emit_branch(struct nv50_pc
*pc
, int pred
, unsigned cc
,
1357 struct nv50_program_exec
**join
)
1359 struct nv50_program_exec
*e
= exec(pc
);
1363 e
->inst
[0] |= 0xa0000002;
1370 e
->inst
[0] |= 0x10000002;
1372 set_pred(pc
, cc
, pred
, e
);
1377 emit_nop(struct nv50_pc
*pc
)
1379 struct nv50_program_exec
*e
= exec(pc
);
1381 e
->inst
[0] = 0xf0000000;
1383 e
->inst
[1] = 0xe0000000;
1388 emit_ddx(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1390 struct nv50_program_exec
*e
= exec(pc
);
1392 assert(src
->type
== P_TEMP
);
1394 e
->inst
[0] = 0xc0140000;
1395 e
->inst
[1] = 0x89800000;
1397 set_dst(pc
, dst
, e
);
1398 set_src_0(pc
, src
, e
);
1399 set_src_2(pc
, src
, e
);
1405 emit_ddy(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1407 struct nv50_program_exec
*e
= exec(pc
);
1409 assert(src
->type
== P_TEMP
);
1411 if (!src
->neg
) /* ! double negation */
1412 emit_neg(pc
, src
, src
);
1414 e
->inst
[0] = 0xc0150000;
1415 e
->inst
[1] = 0x8a400000;
1417 set_dst(pc
, dst
, e
);
1418 set_src_0(pc
, src
, e
);
1419 set_src_2(pc
, src
, e
);
1425 convert_to_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
1427 unsigned q
= 0, m
= ~0;
1429 assert(!is_long(e
));
1431 switch (e
->inst
[0] >> 28) {
1438 /* INTERP (move centroid, perspective and flat bits) */
1440 q
= (e
->inst
[0] & (3 << 24)) >> (24 - 16);
1441 q
|= (e
->inst
[0] & (1 << 8)) << (18 - 8);
1449 q
= ((e
->inst
[0] & (~m
)) >> 2);
1454 q
= ((e
->inst
[0] & (~m
)) << 12);
1457 /* MAD (if src2 == dst) */
1458 q
= ((e
->inst
[0] & 0x1fc) << 12);
1472 /* Some operations support an optional negation flag. */
1474 negate_supported(const struct tgsi_full_instruction
*insn
, int i
)
1478 switch (insn
->Instruction
.Opcode
) {
1479 case TGSI_OPCODE_DDY
:
1480 case TGSI_OPCODE_DP3
:
1481 case TGSI_OPCODE_DP4
:
1482 case TGSI_OPCODE_MUL
:
1483 case TGSI_OPCODE_KIL
:
1484 case TGSI_OPCODE_ADD
:
1485 case TGSI_OPCODE_SUB
:
1486 case TGSI_OPCODE_MAD
:
1488 case TGSI_OPCODE_POW
:
1496 /* Watch out for possible multiple uses of an nv50_reg, we
1497 * can't use nv50_reg::neg in these cases.
1499 for (s
= 0; s
< insn
->Instruction
.NumSrcRegs
; ++s
) {
1502 if ((insn
->FullSrcRegisters
[s
].SrcRegister
.Index
==
1503 insn
->FullSrcRegisters
[i
].SrcRegister
.Index
) &&
1504 (insn
->FullSrcRegisters
[s
].SrcRegister
.File
==
1505 insn
->FullSrcRegisters
[i
].SrcRegister
.File
))
1512 /* Return a read mask for source registers deduced from opcode & write mask. */
1514 nv50_tgsi_src_mask(const struct tgsi_full_instruction
*insn
, int c
)
1516 unsigned x
, mask
= insn
->FullDstRegisters
[0].DstRegister
.WriteMask
;
1518 switch (insn
->Instruction
.Opcode
) {
1519 case TGSI_OPCODE_COS
:
1520 case TGSI_OPCODE_SIN
:
1521 return (mask
& 0x8) | ((mask
& 0x7) ? 0x1 : 0x0);
1522 case TGSI_OPCODE_DP3
:
1524 case TGSI_OPCODE_DP4
:
1525 case TGSI_OPCODE_DPH
:
1526 case TGSI_OPCODE_KIL
: /* WriteMask ignored */
1528 case TGSI_OPCODE_DST
:
1529 return mask
& (c
? 0xa : 0x6);
1530 case TGSI_OPCODE_EX2
:
1531 case TGSI_OPCODE_LG2
:
1532 case TGSI_OPCODE_POW
:
1533 case TGSI_OPCODE_RCP
:
1534 case TGSI_OPCODE_RSQ
:
1535 case TGSI_OPCODE_SCS
:
1537 case TGSI_OPCODE_LIT
:
1539 case TGSI_OPCODE_TEX
:
1540 case TGSI_OPCODE_TXP
:
1542 const struct tgsi_instruction_ext_texture
*tex
;
1544 assert(insn
->Instruction
.Extended
);
1545 tex
= &insn
->InstructionExtTexture
;
1548 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_TXP
)
1551 switch (tex
->Texture
) {
1552 case TGSI_TEXTURE_1D
:
1555 case TGSI_TEXTURE_2D
:
1563 case TGSI_OPCODE_XPD
:
1565 if (mask
& 1) x
|= 0x6;
1566 if (mask
& 2) x
|= 0x5;
1567 if (mask
& 4) x
|= 0x3;
1576 static struct nv50_reg
*
1577 tgsi_dst(struct nv50_pc
*pc
, int c
, const struct tgsi_full_dst_register
*dst
)
1579 switch (dst
->DstRegister
.File
) {
1580 case TGSI_FILE_TEMPORARY
:
1581 return &pc
->temp
[dst
->DstRegister
.Index
* 4 + c
];
1582 case TGSI_FILE_OUTPUT
:
1583 return &pc
->result
[dst
->DstRegister
.Index
* 4 + c
];
1584 case TGSI_FILE_ADDRESS
:
1586 struct nv50_reg
*r
= pc
->addr
[dst
->DstRegister
.Index
* 4 + c
];
1588 r
= alloc_addr(pc
, NULL
);
1589 pc
->addr
[dst
->DstRegister
.Index
* 4 + c
] = r
;
1594 case TGSI_FILE_NULL
:
1603 static struct nv50_reg
*
1604 tgsi_src(struct nv50_pc
*pc
, int chan
, const struct tgsi_full_src_register
*src
,
1607 struct nv50_reg
*r
= NULL
;
1608 struct nv50_reg
*temp
;
1609 unsigned sgn
, c
, swz
;
1611 if (src
->SrcRegister
.File
!= TGSI_FILE_CONSTANT
)
1612 assert(!src
->SrcRegister
.Indirect
);
1614 sgn
= tgsi_util_get_full_src_register_sign_mode(src
, chan
);
1616 c
= tgsi_util_get_full_src_register_swizzle(src
, chan
);
1618 case TGSI_SWIZZLE_X
:
1619 case TGSI_SWIZZLE_Y
:
1620 case TGSI_SWIZZLE_Z
:
1621 case TGSI_SWIZZLE_W
:
1622 switch (src
->SrcRegister
.File
) {
1623 case TGSI_FILE_INPUT
:
1624 r
= &pc
->attr
[src
->SrcRegister
.Index
* 4 + c
];
1626 case TGSI_FILE_TEMPORARY
:
1627 r
= &pc
->temp
[src
->SrcRegister
.Index
* 4 + c
];
1629 case TGSI_FILE_CONSTANT
:
1630 if (!src
->SrcRegister
.Indirect
) {
1631 r
= &pc
->param
[src
->SrcRegister
.Index
* 4 + c
];
1634 /* Indicate indirection by setting r->acc < 0 and
1635 * use the index field to select the address reg.
1637 r
= MALLOC_STRUCT(nv50_reg
);
1638 swz
= tgsi_util_get_src_register_swizzle(
1639 &src
->SrcRegisterInd
, 0);
1640 ctor_reg(r
, P_CONST
,
1641 src
->SrcRegisterInd
.Index
* 4 + swz
,
1642 src
->SrcRegister
.Index
* 4 + c
);
1645 case TGSI_FILE_IMMEDIATE
:
1646 r
= &pc
->immd
[src
->SrcRegister
.Index
* 4 + c
];
1648 case TGSI_FILE_SAMPLER
:
1650 case TGSI_FILE_ADDRESS
:
1651 r
= pc
->addr
[src
->SrcRegister
.Index
* 4 + c
];
1665 case TGSI_UTIL_SIGN_KEEP
:
1667 case TGSI_UTIL_SIGN_CLEAR
:
1668 temp
= temp_temp(pc
);
1669 emit_abs(pc
, temp
, r
);
1672 case TGSI_UTIL_SIGN_TOGGLE
:
1676 temp
= temp_temp(pc
);
1677 emit_neg(pc
, temp
, r
);
1681 case TGSI_UTIL_SIGN_SET
:
1682 temp
= temp_temp(pc
);
1683 emit_cvt(pc
, temp
, r
, -1, CVTOP_ABS
, CVT_F32_F32
| CVT_NEG
);
1694 /* return TRUE for ops that produce only a single result */
1696 is_scalar_op(unsigned op
)
1699 case TGSI_OPCODE_COS
:
1700 case TGSI_OPCODE_DP2
:
1701 case TGSI_OPCODE_DP3
:
1702 case TGSI_OPCODE_DP4
:
1703 case TGSI_OPCODE_DPH
:
1704 case TGSI_OPCODE_EX2
:
1705 case TGSI_OPCODE_LG2
:
1706 case TGSI_OPCODE_POW
:
1707 case TGSI_OPCODE_RCP
:
1708 case TGSI_OPCODE_RSQ
:
1709 case TGSI_OPCODE_SIN
:
1711 case TGSI_OPCODE_KIL:
1712 case TGSI_OPCODE_LIT:
1713 case TGSI_OPCODE_SCS:
1721 /* Returns a bitmask indicating which dst components depend
1722 * on source s, component c (reverse of nv50_tgsi_src_mask).
1725 nv50_tgsi_dst_revdep(unsigned op
, int s
, int c
)
1727 if (is_scalar_op(op
))
1731 case TGSI_OPCODE_DST
:
1732 return (1 << c
) & (s
? 0xa : 0x6);
1733 case TGSI_OPCODE_XPD
:
1743 case TGSI_OPCODE_LIT
:
1744 case TGSI_OPCODE_SCS
:
1745 case TGSI_OPCODE_TEX
:
1746 case TGSI_OPCODE_TXP
:
1747 /* these take care of dangerous swizzles themselves */
1749 case TGSI_OPCODE_IF
:
1750 case TGSI_OPCODE_KIL
:
1751 /* don't call this function for these ops */
1755 /* linear vector instruction */
1760 static INLINE boolean
1761 has_pred(struct nv50_program_exec
*e
, unsigned cc
)
1763 if (!is_long(e
) || is_immd(e
))
1765 return ((e
->inst
[1] & 0x780) == (cc
<< 7));
1768 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
1775 nv50_kill_branch(struct nv50_pc
*pc
)
1777 int lvl
= pc
->if_lvl
;
1779 if (pc
->if_insn
[lvl
]->next
!= pc
->p
->exec_tail
)
1782 /* if ccode == 'true', the BRA is from an ELSE and the predicate
1783 * reg may no longer be valid, since we currently always use $p0
1785 if (has_pred(pc
->if_insn
[lvl
], 0xf))
1787 assert(pc
->if_insn
[lvl
] && pc
->br_join
[lvl
]);
1789 /* We'll use the exec allocated for JOIN_AT (as we can't easily
1790 * update prev's next); if exec_tail is BRK, update the pointer.
1792 if (pc
->loop_lvl
&& pc
->br_loop
[pc
->loop_lvl
- 1] == pc
->p
->exec_tail
)
1793 pc
->br_loop
[pc
->loop_lvl
- 1] = pc
->br_join
[lvl
];
1795 pc
->p
->exec_size
-= 4; /* remove JOIN_AT and BRA */
1797 *pc
->br_join
[lvl
] = *pc
->p
->exec_tail
;
1799 FREE(pc
->if_insn
[lvl
]);
1800 FREE(pc
->p
->exec_tail
);
1802 pc
->p
->exec_tail
= pc
->br_join
[lvl
];
1803 pc
->p
->exec_tail
->next
= NULL
;
1804 set_pred(pc
, 0xd, 0, pc
->p
->exec_tail
);
1810 nv50_program_tx_insn(struct nv50_pc
*pc
,
1811 const struct tgsi_full_instruction
*inst
)
1813 struct nv50_reg
*rdst
[4], *dst
[4], *brdc
, *src
[3][4], *temp
;
1814 unsigned mask
, sat
, unit
;
1817 mask
= inst
->FullDstRegisters
[0].DstRegister
.WriteMask
;
1818 sat
= inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
;
1820 memset(src
, 0, sizeof(src
));
1822 for (c
= 0; c
< 4; c
++) {
1823 if ((mask
& (1 << c
)) && !pc
->r_dst
[c
])
1824 dst
[c
] = tgsi_dst(pc
, c
, &inst
->FullDstRegisters
[0]);
1826 dst
[c
] = pc
->r_dst
[c
];
1830 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1831 const struct tgsi_full_src_register
*fs
= &inst
->FullSrcRegisters
[i
];
1835 src_mask
= nv50_tgsi_src_mask(inst
, i
);
1836 neg_supp
= negate_supported(inst
, i
);
1838 if (fs
->SrcRegister
.File
== TGSI_FILE_SAMPLER
)
1839 unit
= fs
->SrcRegister
.Index
;
1841 for (c
= 0; c
< 4; c
++)
1842 if (src_mask
& (1 << c
))
1843 src
[i
][c
] = tgsi_src(pc
, c
, fs
, neg_supp
);
1846 brdc
= temp
= pc
->r_brdc
;
1847 if (brdc
&& brdc
->type
!= P_TEMP
) {
1848 temp
= temp_temp(pc
);
1853 for (c
= 0; c
< 4; c
++) {
1854 if (!(mask
& (1 << c
)) || dst
[c
]->type
== P_TEMP
)
1856 /* rdst[c] = dst[c]; */ /* done above */
1857 dst
[c
] = temp_temp(pc
);
1861 assert(brdc
|| !is_scalar_op(inst
->Instruction
.Opcode
));
1863 switch (inst
->Instruction
.Opcode
) {
1864 case TGSI_OPCODE_ABS
:
1865 for (c
= 0; c
< 4; c
++) {
1866 if (!(mask
& (1 << c
)))
1868 emit_abs(pc
, dst
[c
], src
[0][c
]);
1871 case TGSI_OPCODE_ADD
:
1872 for (c
= 0; c
< 4; c
++) {
1873 if (!(mask
& (1 << c
)))
1875 emit_add(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
1878 case TGSI_OPCODE_AND
:
1879 case TGSI_OPCODE_XOR
:
1880 case TGSI_OPCODE_OR
:
1881 for (c
= 0; c
< 4; c
++) {
1882 if (!(mask
& (1 << c
)))
1884 emit_bitop2(pc
, dst
[c
], src
[0][c
], src
[1][c
],
1885 inst
->Instruction
.Opcode
);
1888 case TGSI_OPCODE_ARL
:
1890 temp
= temp_temp(pc
);
1891 emit_cvt(pc
, temp
, src
[0][0], -1, CVTOP_FLOOR
, CVT_S32_F32
);
1892 emit_arl(pc
, dst
[0], temp
, 4);
1894 case TGSI_OPCODE_BGNLOOP
:
1895 pc
->loop_pos
[pc
->loop_lvl
++] = pc
->p
->exec_size
;
1898 case TGSI_OPCODE_BRK
:
1899 emit_branch(pc
, -1, 0, NULL
);
1900 assert(pc
->loop_lvl
> 0);
1901 pc
->br_loop
[pc
->loop_lvl
- 1] = pc
->p
->exec_tail
;
1903 case TGSI_OPCODE_CEIL
:
1904 for (c
= 0; c
< 4; c
++) {
1905 if (!(mask
& (1 << c
)))
1907 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
1908 CVTOP_CEIL
, CVT_F32_F32
| CVT_RI
);
1911 case TGSI_OPCODE_CMP
:
1912 pc
->allow32
= FALSE
;
1913 for (c
= 0; c
< 4; c
++) {
1914 if (!(mask
& (1 << c
)))
1916 emit_cvt(pc
, NULL
, src
[0][c
], 1, CVTOP_RN
, CVT_F32_F32
);
1917 emit_mov(pc
, dst
[c
], src
[1][c
]);
1918 set_pred(pc
, 0x1, 1, pc
->p
->exec_tail
); /* @SF */
1919 emit_mov(pc
, dst
[c
], src
[2][c
]);
1920 set_pred(pc
, 0x6, 1, pc
->p
->exec_tail
); /* @NSF */
1923 case TGSI_OPCODE_COS
:
1925 emit_precossin(pc
, temp
, src
[0][3]);
1926 emit_flop(pc
, 5, dst
[3], temp
);
1930 temp
= brdc
= temp_temp(pc
);
1932 emit_precossin(pc
, temp
, src
[0][0]);
1933 emit_flop(pc
, 5, brdc
, temp
);
1935 case TGSI_OPCODE_DDX
:
1936 for (c
= 0; c
< 4; c
++) {
1937 if (!(mask
& (1 << c
)))
1939 emit_ddx(pc
, dst
[c
], src
[0][c
]);
1942 case TGSI_OPCODE_DDY
:
1943 for (c
= 0; c
< 4; c
++) {
1944 if (!(mask
& (1 << c
)))
1946 emit_ddy(pc
, dst
[c
], src
[0][c
]);
1949 case TGSI_OPCODE_DP3
:
1950 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1951 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1952 emit_mad(pc
, brdc
, src
[0][2], src
[1][2], temp
);
1954 case TGSI_OPCODE_DP4
:
1955 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1956 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1957 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
1958 emit_mad(pc
, brdc
, src
[0][3], src
[1][3], temp
);
1960 case TGSI_OPCODE_DPH
:
1961 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
1962 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
1963 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
1964 emit_add(pc
, brdc
, src
[1][3], temp
);
1966 case TGSI_OPCODE_DST
:
1967 if (mask
& (1 << 1))
1968 emit_mul(pc
, dst
[1], src
[0][1], src
[1][1]);
1969 if (mask
& (1 << 2))
1970 emit_mov(pc
, dst
[2], src
[0][2]);
1971 if (mask
& (1 << 3))
1972 emit_mov(pc
, dst
[3], src
[1][3]);
1973 if (mask
& (1 << 0))
1974 emit_mov_immdval(pc
, dst
[0], 1.0f
);
1976 case TGSI_OPCODE_ELSE
:
1977 emit_branch(pc
, -1, 0, NULL
);
1978 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
1979 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
1982 case TGSI_OPCODE_ENDIF
:
1983 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
1985 /* try to replace branch over 1 insn with a predicated insn */
1986 if (nv50_kill_branch(pc
) == TRUE
)
1989 if (pc
->br_join
[pc
->if_lvl
]) {
1990 pc
->br_join
[pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
1991 pc
->br_join
[pc
->if_lvl
] = NULL
;
1994 /* emit a NOP as join point, we could set it on the next
1995 * one, but would have to make sure it is long and !immd
1998 pc
->p
->exec_tail
->inst
[1] |= 2;
2000 case TGSI_OPCODE_ENDLOOP
:
2001 emit_branch(pc
, -1, 0, NULL
);
2002 pc
->p
->exec_tail
->param
.index
= pc
->loop_pos
[--pc
->loop_lvl
];
2003 pc
->br_loop
[pc
->loop_lvl
]->param
.index
= pc
->p
->exec_size
;
2006 case TGSI_OPCODE_EX2
:
2007 emit_preex2(pc
, temp
, src
[0][0]);
2008 emit_flop(pc
, 6, brdc
, temp
);
2010 case TGSI_OPCODE_FLR
:
2011 for (c
= 0; c
< 4; c
++) {
2012 if (!(mask
& (1 << c
)))
2014 emit_flr(pc
, dst
[c
], src
[0][c
]);
2017 case TGSI_OPCODE_FRC
:
2018 temp
= temp_temp(pc
);
2019 for (c
= 0; c
< 4; c
++) {
2020 if (!(mask
& (1 << c
)))
2022 emit_flr(pc
, temp
, src
[0][c
]);
2023 emit_sub(pc
, dst
[c
], src
[0][c
], temp
);
2026 case TGSI_OPCODE_IF
:
2027 /* emitting a join_at may not be necessary */
2028 assert(pc
->if_lvl
< MAX_IF_DEPTH
);
2029 /* set_pred_wr(pc, 1, 0, pc->if_cond); */
2030 emit_cvt(pc
, NULL
, src
[0][0], 0, CVTOP_ABS
| CVTOP_RN
,
2032 emit_branch(pc
, 0, 2, &pc
->br_join
[pc
->if_lvl
]);
2033 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
2036 case TGSI_OPCODE_KIL
:
2037 emit_kil(pc
, src
[0][0]);
2038 emit_kil(pc
, src
[0][1]);
2039 emit_kil(pc
, src
[0][2]);
2040 emit_kil(pc
, src
[0][3]);
2042 case TGSI_OPCODE_LIT
:
2043 emit_lit(pc
, &dst
[0], mask
, &src
[0][0]);
2045 case TGSI_OPCODE_LG2
:
2046 emit_flop(pc
, 3, brdc
, src
[0][0]);
2048 case TGSI_OPCODE_LRP
:
2049 temp
= temp_temp(pc
);
2050 for (c
= 0; c
< 4; c
++) {
2051 if (!(mask
& (1 << c
)))
2053 emit_sub(pc
, temp
, src
[1][c
], src
[2][c
]);
2054 emit_mad(pc
, dst
[c
], temp
, src
[0][c
], src
[2][c
]);
2057 case TGSI_OPCODE_MAD
:
2058 for (c
= 0; c
< 4; c
++) {
2059 if (!(mask
& (1 << c
)))
2061 emit_mad(pc
, dst
[c
], src
[0][c
], src
[1][c
], src
[2][c
]);
2064 case TGSI_OPCODE_MAX
:
2065 for (c
= 0; c
< 4; c
++) {
2066 if (!(mask
& (1 << c
)))
2068 emit_minmax(pc
, 4, dst
[c
], src
[0][c
], src
[1][c
]);
2071 case TGSI_OPCODE_MIN
:
2072 for (c
= 0; c
< 4; c
++) {
2073 if (!(mask
& (1 << c
)))
2075 emit_minmax(pc
, 5, dst
[c
], src
[0][c
], src
[1][c
]);
2078 case TGSI_OPCODE_MOV
:
2079 for (c
= 0; c
< 4; c
++) {
2080 if (!(mask
& (1 << c
)))
2082 emit_mov(pc
, dst
[c
], src
[0][c
]);
2085 case TGSI_OPCODE_MUL
:
2086 for (c
= 0; c
< 4; c
++) {
2087 if (!(mask
& (1 << c
)))
2089 emit_mul(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2092 case TGSI_OPCODE_POW
:
2093 emit_pow(pc
, brdc
, src
[0][0], src
[1][0]);
2095 case TGSI_OPCODE_RCP
:
2096 emit_flop(pc
, 0, brdc
, src
[0][0]);
2098 case TGSI_OPCODE_RSQ
:
2099 emit_flop(pc
, 2, brdc
, src
[0][0]);
2101 case TGSI_OPCODE_SCS
:
2102 temp
= temp_temp(pc
);
2104 emit_precossin(pc
, temp
, src
[0][0]);
2105 if (mask
& (1 << 0))
2106 emit_flop(pc
, 5, dst
[0], temp
);
2107 if (mask
& (1 << 1))
2108 emit_flop(pc
, 4, dst
[1], temp
);
2109 if (mask
& (1 << 2))
2110 emit_mov_immdval(pc
, dst
[2], 0.0);
2111 if (mask
& (1 << 3))
2112 emit_mov_immdval(pc
, dst
[3], 1.0);
2114 case TGSI_OPCODE_SIN
:
2116 emit_precossin(pc
, temp
, src
[0][3]);
2117 emit_flop(pc
, 4, dst
[3], temp
);
2121 temp
= brdc
= temp_temp(pc
);
2123 emit_precossin(pc
, temp
, src
[0][0]);
2124 emit_flop(pc
, 4, brdc
, temp
);
2126 case TGSI_OPCODE_SLT
:
2127 case TGSI_OPCODE_SGE
:
2128 case TGSI_OPCODE_SEQ
:
2129 case TGSI_OPCODE_SGT
:
2130 case TGSI_OPCODE_SLE
:
2131 case TGSI_OPCODE_SNE
:
2132 i
= map_tgsi_setop_cc(inst
->Instruction
.Opcode
);
2133 for (c
= 0; c
< 4; c
++) {
2134 if (!(mask
& (1 << c
)))
2136 emit_set(pc
, i
, dst
[c
], -1, src
[0][c
], src
[1][c
]);
2139 case TGSI_OPCODE_SUB
:
2140 for (c
= 0; c
< 4; c
++) {
2141 if (!(mask
& (1 << c
)))
2143 emit_sub(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2146 case TGSI_OPCODE_TEX
:
2147 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2148 inst
->InstructionExtTexture
.Texture
, FALSE
);
2150 case TGSI_OPCODE_TXP
:
2151 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2152 inst
->InstructionExtTexture
.Texture
, TRUE
);
2154 case TGSI_OPCODE_TRUNC
:
2155 for (c
= 0; c
< 4; c
++) {
2156 if (!(mask
& (1 << c
)))
2158 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2159 CVTOP_TRUNC
, CVT_F32_F32
| CVT_RI
);
2162 case TGSI_OPCODE_XPD
:
2163 temp
= temp_temp(pc
);
2164 if (mask
& (1 << 0)) {
2165 emit_mul(pc
, temp
, src
[0][2], src
[1][1]);
2166 emit_msb(pc
, dst
[0], src
[0][1], src
[1][2], temp
);
2168 if (mask
& (1 << 1)) {
2169 emit_mul(pc
, temp
, src
[0][0], src
[1][2]);
2170 emit_msb(pc
, dst
[1], src
[0][2], src
[1][0], temp
);
2172 if (mask
& (1 << 2)) {
2173 emit_mul(pc
, temp
, src
[0][1], src
[1][0]);
2174 emit_msb(pc
, dst
[2], src
[0][0], src
[1][1], temp
);
2176 if (mask
& (1 << 3))
2177 emit_mov_immdval(pc
, dst
[3], 1.0);
2179 case TGSI_OPCODE_END
:
2182 NOUVEAU_ERR("invalid opcode %d\n", inst
->Instruction
.Opcode
);
2188 emit_sat(pc
, brdc
, brdc
);
2189 for (c
= 0; c
< 4; c
++)
2190 if ((mask
& (1 << c
)) && dst
[c
] != brdc
)
2191 emit_mov(pc
, dst
[c
], brdc
);
2194 for (c
= 0; c
< 4; c
++) {
2195 if (!(mask
& (1 << c
)))
2197 /* In this case we saturate later, and dst[c] won't
2198 * be another temp_temp (and thus lost), since rdst
2199 * already is TEMP (see above). */
2200 if (rdst
[c
]->type
== P_TEMP
&& rdst
[c
]->index
< 0)
2202 emit_sat(pc
, rdst
[c
], dst
[c
]);
2206 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2207 for (c
= 0; c
< 4; c
++) {
2211 if (src
[i
][c
]->index
== -1 && src
[i
][c
]->type
== P_IMMD
)
2214 if (src
[i
][c
]->acc
< 0 && src
[i
][c
]->type
== P_CONST
)
2215 FREE(src
[i
][c
]); /* indirect constant */
2224 prep_inspect_insn(struct nv50_pc
*pc
, const struct tgsi_full_instruction
*insn
)
2226 struct nv50_reg
*reg
= NULL
;
2227 const struct tgsi_full_src_register
*src
;
2228 const struct tgsi_dst_register
*dst
;
2229 unsigned i
, c
, k
, mask
;
2231 dst
= &insn
->FullDstRegisters
[0].DstRegister
;
2232 mask
= dst
->WriteMask
;
2234 if (dst
->File
== TGSI_FILE_TEMPORARY
)
2237 if (dst
->File
== TGSI_FILE_OUTPUT
)
2241 for (c
= 0; c
< 4; c
++) {
2242 if (!(mask
& (1 << c
)))
2244 reg
[dst
->Index
* 4 + c
].acc
= pc
->insn_nr
;
2248 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
2249 src
= &insn
->FullSrcRegisters
[i
];
2251 if (src
->SrcRegister
.File
== TGSI_FILE_TEMPORARY
)
2254 if (src
->SrcRegister
.File
== TGSI_FILE_INPUT
)
2259 mask
= nv50_tgsi_src_mask(insn
, i
);
2261 for (c
= 0; c
< 4; c
++) {
2262 if (!(mask
& (1 << c
)))
2264 k
= tgsi_util_get_full_src_register_swizzle(src
, c
);
2266 reg
[src
->SrcRegister
.Index
* 4 + k
].acc
= pc
->insn_nr
;
2271 /* Returns a bitmask indicating which dst components need to be
2272 * written to temporaries first to avoid 'corrupting' sources.
2274 * m[i] (out) indicate component to write in the i-th position
2275 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2278 nv50_revdep_reorder(unsigned m
[4], unsigned rdep
[4])
2280 unsigned i
, c
, x
, unsafe
;
2282 for (c
= 0; c
< 4; c
++)
2285 /* Swap as long as a dst component written earlier is depended on
2286 * by one written later, but the next one isn't depended on by it.
2288 for (c
= 0; c
< 3; c
++) {
2289 if (rdep
[m
[c
+ 1]] & (1 << m
[c
]))
2290 continue; /* if next one is depended on by us */
2291 for (i
= c
+ 1; i
< 4; i
++)
2292 /* if we are depended on by a later one */
2293 if (rdep
[m
[c
]] & (1 << m
[i
]))
2306 /* mark dependencies that could not be resolved by reordering */
2307 for (i
= 0; i
< 3; ++i
)
2308 for (c
= i
+ 1; c
< 4; ++c
)
2309 if (rdep
[m
[i
]] & (1 << m
[c
]))
2312 /* NOTE: $unsafe is with respect to order, not component */
2316 /* Select a suitable dst register for broadcasting scalar results,
2317 * or return NULL if we have to allocate an extra TEMP.
2319 * If e.g. only 1 component is written, we may also emit the final
2320 * result to a write-only register.
2322 static struct nv50_reg
*
2323 tgsi_broadcast_dst(struct nv50_pc
*pc
,
2324 const struct tgsi_full_dst_register
*fd
, unsigned mask
)
2326 if (fd
->DstRegister
.File
== TGSI_FILE_TEMPORARY
) {
2327 int c
= ffs(~mask
& fd
->DstRegister
.WriteMask
);
2329 return tgsi_dst(pc
, c
- 1, fd
);
2331 int c
= ffs(fd
->DstRegister
.WriteMask
) - 1;
2332 if ((1 << c
) == fd
->DstRegister
.WriteMask
)
2333 return tgsi_dst(pc
, c
, fd
);
2339 /* Scan source swizzles and return a bitmask indicating dst regs that
2340 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2343 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction
*insn
,
2346 const struct tgsi_full_dst_register
*fd
= &insn
->FullDstRegisters
[0];
2347 const struct tgsi_full_src_register
*fs
;
2348 unsigned i
, deqs
= 0;
2350 for (i
= 0; i
< 4; ++i
)
2353 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
2354 unsigned chn
, mask
= nv50_tgsi_src_mask(insn
, i
);
2355 boolean neg_supp
= negate_supported(insn
, i
);
2357 fs
= &insn
->FullSrcRegisters
[i
];
2358 if (fs
->SrcRegister
.File
!= fd
->DstRegister
.File
||
2359 fs
->SrcRegister
.Index
!= fd
->DstRegister
.Index
)
2362 for (chn
= 0; chn
< 4; ++chn
) {
2365 if (!(mask
& (1 << chn
))) /* src is not read */
2367 c
= tgsi_util_get_full_src_register_swizzle(fs
, chn
);
2368 s
= tgsi_util_get_full_src_register_sign_mode(fs
, chn
);
2370 if (!(fd
->DstRegister
.WriteMask
& (1 << c
)))
2373 /* no danger if src is copied to TEMP first */
2374 if ((s
!= TGSI_UTIL_SIGN_KEEP
) &&
2375 (s
!= TGSI_UTIL_SIGN_TOGGLE
|| !neg_supp
))
2378 rdep
[c
] |= nv50_tgsi_dst_revdep(
2379 insn
->Instruction
.Opcode
, i
, chn
);
2388 nv50_tgsi_insn(struct nv50_pc
*pc
, const union tgsi_full_token
*tok
)
2390 struct tgsi_full_instruction insn
= tok
->FullInstruction
;
2391 const struct tgsi_full_dst_register
*fd
;
2392 unsigned i
, deqs
, rdep
[4], m
[4];
2394 fd
= &tok
->FullInstruction
.FullDstRegisters
[0];
2395 deqs
= nv50_tgsi_scan_swizzle(&insn
, rdep
);
2397 if (is_scalar_op(insn
.Instruction
.Opcode
)) {
2398 pc
->r_brdc
= tgsi_broadcast_dst(pc
, fd
, deqs
);
2400 pc
->r_brdc
= temp_temp(pc
);
2401 return nv50_program_tx_insn(pc
, &insn
);
2406 return nv50_program_tx_insn(pc
, &insn
);
2408 deqs
= nv50_revdep_reorder(m
, rdep
);
2410 for (i
= 0; i
< 4; ++i
) {
2411 assert(pc
->r_dst
[m
[i
]] == NULL
);
2413 insn
.FullDstRegisters
[0].DstRegister
.WriteMask
=
2414 fd
->DstRegister
.WriteMask
& (1 << m
[i
]);
2416 if (!insn
.FullDstRegisters
[0].DstRegister
.WriteMask
)
2419 if (deqs
& (1 << i
))
2420 pc
->r_dst
[m
[i
]] = alloc_temp(pc
, NULL
);
2422 if (!nv50_program_tx_insn(pc
, &insn
))
2426 for (i
= 0; i
< 4; i
++) {
2427 struct nv50_reg
*reg
= pc
->r_dst
[i
];
2430 pc
->r_dst
[i
] = NULL
;
2432 if (insn
.Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
)
2433 emit_sat(pc
, tgsi_dst(pc
, i
, fd
), reg
);
2435 emit_mov(pc
, tgsi_dst(pc
, i
, fd
), reg
);
2443 load_interpolant(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
2445 struct nv50_reg
*iv
, **ppiv
;
2446 unsigned mode
= pc
->interp_mode
[reg
->index
];
2448 ppiv
= (mode
& INTERP_CENTROID
) ? &pc
->iv_c
: &pc
->iv_p
;
2451 if ((mode
& INTERP_PERSPECTIVE
) && !iv
) {
2452 iv
= *ppiv
= alloc_temp(pc
, NULL
);
2453 iv
->rhw
= popcnt4(pc
->p
->cfg
.regs
[1] >> 24) - 1;
2455 emit_interp(pc
, iv
, NULL
, mode
& INTERP_CENTROID
);
2456 emit_flop(pc
, 0, iv
, iv
);
2458 /* XXX: when loading interpolants dynamically, move these
2459 * to the program head, or make sure it can't be skipped.
2463 emit_interp(pc
, reg
, iv
, mode
);
2466 /* The face input is always at v[255] (varying space), with a
2467 * value of 0 for back-facing, and 0xffffffff for front-facing.
2470 load_frontfacing(struct nv50_pc
*pc
, struct nv50_reg
*a
)
2472 struct nv50_reg
*one
= alloc_immd(pc
, 1.0f
);
2474 assert(a
->rhw
== -1);
2475 alloc_reg(pc
, a
); /* do this before rhw is set */
2477 load_interpolant(pc
, a
);
2478 emit_bitop2(pc
, a
, a
, one
, TGSI_OPCODE_AND
);
2484 nv50_program_tx_prep(struct nv50_pc
*pc
)
2486 struct tgsi_parse_context tp
;
2487 struct nv50_program
*p
= pc
->p
;
2488 boolean ret
= FALSE
;
2489 unsigned i
, c
, flat_nr
= 0;
2491 tgsi_parse_init(&tp
, pc
->p
->pipe
.tokens
);
2492 while (!tgsi_parse_end_of_tokens(&tp
)) {
2493 const union tgsi_full_token
*tok
= &tp
.FullToken
;
2495 tgsi_parse_token(&tp
);
2496 switch (tok
->Token
.Type
) {
2497 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2499 const struct tgsi_full_immediate
*imm
=
2500 &tp
.FullToken
.FullImmediate
;
2502 ctor_immd(pc
, imm
->u
[0].Float
,
2508 case TGSI_TOKEN_TYPE_DECLARATION
:
2510 const struct tgsi_full_declaration
*d
;
2511 unsigned si
, last
, first
, mode
;
2513 d
= &tp
.FullToken
.FullDeclaration
;
2514 first
= d
->DeclarationRange
.First
;
2515 last
= d
->DeclarationRange
.Last
;
2517 switch (d
->Declaration
.File
) {
2518 case TGSI_FILE_TEMPORARY
:
2520 case TGSI_FILE_OUTPUT
:
2521 if (!d
->Declaration
.Semantic
||
2522 p
->type
== PIPE_SHADER_FRAGMENT
)
2525 si
= d
->Semantic
.SemanticIndex
;
2526 switch (d
->Semantic
.SemanticName
) {
2527 case TGSI_SEMANTIC_BCOLOR
:
2528 p
->cfg
.two_side
[si
].hw
= first
;
2529 if (p
->cfg
.io_nr
> first
)
2530 p
->cfg
.io_nr
= first
;
2532 case TGSI_SEMANTIC_PSIZE
:
2533 p
->cfg
.psiz
= first
;
2534 if (p
->cfg
.io_nr
> first
)
2535 p
->cfg
.io_nr
= first
;
2538 case TGSI_SEMANTIC_CLIP_DISTANCE:
2539 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2546 case TGSI_FILE_INPUT
:
2548 if (p
->type
!= PIPE_SHADER_FRAGMENT
)
2551 switch (d
->Declaration
.Interpolate
) {
2552 case TGSI_INTERPOLATE_CONSTANT
:
2556 case TGSI_INTERPOLATE_PERSPECTIVE
:
2557 mode
= INTERP_PERSPECTIVE
;
2558 p
->cfg
.regs
[1] |= 0x08 << 24;
2561 mode
= INTERP_LINEAR
;
2564 if (d
->Declaration
.Centroid
)
2565 mode
|= INTERP_CENTROID
;
2568 for (i
= first
; i
<= last
; i
++)
2569 pc
->interp_mode
[i
] = mode
;
2572 case TGSI_FILE_ADDRESS
:
2573 case TGSI_FILE_CONSTANT
:
2574 case TGSI_FILE_SAMPLER
:
2577 NOUVEAU_ERR("bad decl file %d\n",
2578 d
->Declaration
.File
);
2583 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2585 prep_inspect_insn(pc
, &tok
->FullInstruction
);
2592 if (p
->type
== PIPE_SHADER_VERTEX
) {
2595 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
) {
2596 if (pc
->attr
[i
].acc
) {
2597 pc
->attr
[i
].hw
= rid
++;
2598 p
->cfg
.attr
[i
/ 32] |= 1 << (i
% 32);
2602 for (i
= 0, rid
= 0; i
< pc
->result_nr
; ++i
) {
2603 p
->cfg
.io
[i
].hw
= rid
;
2604 p
->cfg
.io
[i
].id_vp
= i
;
2606 for (c
= 0; c
< 4; ++c
) {
2608 if (!pc
->result
[n
].acc
)
2610 pc
->result
[n
].hw
= rid
++;
2611 p
->cfg
.io
[i
].mask
|= 1 << c
;
2615 for (c
= 0; c
< 2; ++c
)
2616 if (p
->cfg
.two_side
[c
].hw
< 0x40)
2617 p
->cfg
.two_side
[c
] = p
->cfg
.io
[
2618 p
->cfg
.two_side
[c
].hw
];
2620 if (p
->cfg
.psiz
< 0x40)
2621 p
->cfg
.psiz
= p
->cfg
.io
[p
->cfg
.psiz
].hw
;
2623 if (p
->type
== PIPE_SHADER_FRAGMENT
) {
2625 unsigned n
= 0, m
= pc
->attr_nr
- flat_nr
;
2629 int base
= (TGSI_SEMANTIC_POSITION
==
2630 p
->info
.input_semantic_name
[0]) ? 0 : 1;
2632 /* non-flat interpolants have to be mapped to
2633 * the lower hardware IDs, so sort them:
2635 for (i
= 0; i
< pc
->attr_nr
; i
++) {
2636 if (pc
->interp_mode
[i
] == INTERP_FLAT
) {
2637 p
->cfg
.io
[m
].id_vp
= i
+ base
;
2638 p
->cfg
.io
[m
++].id_fp
= i
;
2640 if (!(pc
->interp_mode
[i
] & INTERP_PERSPECTIVE
))
2641 p
->cfg
.io
[n
].linear
= TRUE
;
2642 p
->cfg
.io
[n
].id_vp
= i
+ base
;
2643 p
->cfg
.io
[n
++].id_fp
= i
;
2647 if (!base
) /* set w-coordinate mask from perspective interp */
2648 p
->cfg
.io
[0].mask
|= p
->cfg
.regs
[1] >> 24;
2650 aid
= popcnt4( /* if fcrd isn't contained in cfg.io */
2651 base
? (p
->cfg
.regs
[1] >> 24) : p
->cfg
.io
[0].mask
);
2653 for (n
= 0; n
< pc
->attr_nr
; ++n
) {
2654 p
->cfg
.io
[n
].hw
= rid
= aid
;
2655 i
= p
->cfg
.io
[n
].id_fp
;
2657 if (p
->info
.input_semantic_name
[n
] ==
2658 TGSI_SEMANTIC_FACE
) {
2659 load_frontfacing(pc
, &pc
->attr
[i
* 4]);
2663 for (c
= 0; c
< 4; ++c
) {
2664 if (!pc
->attr
[i
* 4 + c
].acc
)
2666 pc
->attr
[i
* 4 + c
].rhw
= rid
++;
2667 p
->cfg
.io
[n
].mask
|= 1 << c
;
2669 load_interpolant(pc
, &pc
->attr
[i
* 4 + c
]);
2671 aid
+= popcnt4(p
->cfg
.io
[n
].mask
);
2675 p
->cfg
.regs
[1] |= p
->cfg
.io
[0].mask
<< 24;
2677 m
= popcnt4(p
->cfg
.regs
[1] >> 24);
2679 /* set count of non-position inputs and of non-flat
2680 * non-position inputs for FP_INTERPOLANT_CTRL
2682 p
->cfg
.regs
[1] |= aid
- m
;
2685 i
= p
->cfg
.io
[pc
->attr_nr
- flat_nr
].hw
;
2686 p
->cfg
.regs
[1] |= (i
- m
) << 16;
2688 p
->cfg
.regs
[1] |= p
->cfg
.regs
[1] << 16;
2690 /* mark color semantic for light-twoside */
2692 for (i
= 0; i
< pc
->attr_nr
; i
++) {
2695 sn
= p
->info
.input_semantic_name
[p
->cfg
.io
[i
].id_fp
];
2696 si
= p
->info
.input_semantic_index
[p
->cfg
.io
[i
].id_fp
];
2698 if (sn
== TGSI_SEMANTIC_COLOR
) {
2699 p
->cfg
.two_side
[si
] = p
->cfg
.io
[i
];
2701 /* increase colour count */
2702 p
->cfg
.regs
[0] += popcnt4(
2703 p
->cfg
.two_side
[si
].mask
) << 16;
2705 n
= MIN2(n
, p
->cfg
.io
[i
].hw
- m
);
2709 p
->cfg
.regs
[0] += n
;
2711 /* Initialize FP results:
2712 * FragDepth is always first TGSI and last hw output
2714 i
= p
->info
.writes_z
? 4 : 0;
2715 for (rid
= 0; i
< pc
->result_nr
* 4; i
++)
2716 pc
->result
[i
].rhw
= rid
++;
2717 if (p
->info
.writes_z
)
2718 pc
->result
[2].rhw
= rid
;
2720 p
->cfg
.high_result
= rid
;
2722 /* separate/different colour results for MRTs ? */
2723 if (pc
->result_nr
- (p
->info
.writes_z
? 1 : 0) > 1)
2724 p
->cfg
.regs
[2] |= 1;
2730 pc
->immd
= MALLOC(pc
->immd_nr
* 4 * sizeof(struct nv50_reg
));
2734 for (i
= 0; i
< pc
->immd_nr
; i
++) {
2735 for (c
= 0; c
< 4; c
++, rid
++)
2736 ctor_reg(&pc
->immd
[rid
], P_IMMD
, i
, rid
);
2743 free_temp(pc
, pc
->iv_p
);
2745 free_temp(pc
, pc
->iv_c
);
2747 tgsi_parse_free(&tp
);
2752 free_nv50_pc(struct nv50_pc
*pc
)
2769 ctor_nv50_pc(struct nv50_pc
*pc
, struct nv50_program
*p
)
2772 unsigned rtype
[2] = { P_ATTR
, P_RESULT
};
2775 pc
->temp_nr
= p
->info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
2776 pc
->attr_nr
= p
->info
.file_max
[TGSI_FILE_INPUT
] + 1;
2777 pc
->result_nr
= p
->info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
2778 pc
->param_nr
= p
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
2779 pc
->addr_nr
= p
->info
.file_max
[TGSI_FILE_ADDRESS
] + 1;
2780 assert(pc
->addr_nr
<= 2);
2782 p
->cfg
.high_temp
= 4;
2784 p
->cfg
.two_side
[0].hw
= 0x40;
2785 p
->cfg
.two_side
[1].hw
= 0x40;
2788 case PIPE_SHADER_VERTEX
:
2791 p
->cfg
.io_nr
= pc
->result_nr
;
2793 case PIPE_SHADER_FRAGMENT
:
2794 rtype
[0] = rtype
[1] = P_TEMP
;
2796 p
->cfg
.regs
[0] = 0x01000004;
2797 p
->cfg
.io_nr
= pc
->attr_nr
;
2799 if (p
->info
.writes_z
) {
2800 p
->cfg
.regs
[2] |= 0x00000100;
2801 p
->cfg
.regs
[3] |= 0x00000011;
2803 if (p
->info
.uses_kill
)
2804 p
->cfg
.regs
[2] |= 0x00100000;
2809 pc
->temp
= MALLOC(pc
->temp_nr
* 4 * sizeof(struct nv50_reg
));
2813 for (i
= 0; i
< pc
->temp_nr
* 4; ++i
)
2814 ctor_reg(&pc
->temp
[i
], P_TEMP
, i
/ 4, -1);
2818 pc
->attr
= MALLOC(pc
->attr_nr
* 4 * sizeof(struct nv50_reg
));
2822 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
)
2823 ctor_reg(&pc
->attr
[i
], rtype
[0], i
/ 4, -1);
2826 if (pc
->result_nr
) {
2827 unsigned nr
= pc
->result_nr
* 4;
2829 pc
->result
= MALLOC(nr
* sizeof(struct nv50_reg
));
2833 for (i
= 0; i
< nr
; ++i
)
2834 ctor_reg(&pc
->result
[i
], rtype
[1], i
/ 4, -1);
2840 pc
->param
= MALLOC(pc
->param_nr
* 4 * sizeof(struct nv50_reg
));
2844 for (i
= 0; i
< pc
->param_nr
; ++i
)
2845 for (c
= 0; c
< 4; ++c
, ++rid
)
2846 ctor_reg(&pc
->param
[rid
], P_CONST
, i
, rid
);
2850 pc
->addr
= CALLOC(pc
->addr_nr
* 4, sizeof(struct nv50_reg
*));
2854 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
2855 ctor_reg(&pc
->r_addr
[i
], P_ADDR
, -256, i
+ 1);
2861 nv50_fp_move_results(struct nv50_pc
*pc
)
2863 struct nv50_reg reg
;
2866 ctor_reg(®
, P_TEMP
, -1, -1);
2868 for (i
= 0; i
< pc
->result_nr
* 4; ++i
) {
2869 if (pc
->result
[i
].rhw
< 0 || pc
->result
[i
].hw
< 0)
2871 if (pc
->result
[i
].rhw
!= pc
->result
[i
].hw
) {
2872 reg
.hw
= pc
->result
[i
].rhw
;
2873 emit_mov(pc
, ®
, &pc
->result
[i
]);
2879 nv50_program_fixup_insns(struct nv50_pc
*pc
)
2881 struct nv50_program_exec
*e
, *prev
= NULL
, **bra_list
;
2884 bra_list
= CALLOC(pc
->p
->exec_size
, sizeof(struct nv50_program_exec
*));
2886 /* Collect branch instructions, we need to adjust their offsets
2887 * when converting 32 bit instructions to 64 bit ones
2889 for (n
= 0, e
= pc
->p
->exec_head
; e
; e
= e
->next
)
2890 if (e
->param
.index
>= 0 && !e
->param
.mask
)
2893 /* Make sure we don't have any single 32 bit instructions. */
2894 for (e
= pc
->p
->exec_head
, pos
= 0; e
; e
= e
->next
) {
2895 pos
+= is_long(e
) ? 2 : 1;
2897 if ((pos
& 1) && (!e
->next
|| is_long(e
->next
))) {
2898 for (i
= 0; i
< n
; ++i
)
2899 if (bra_list
[i
]->param
.index
>= pos
)
2900 bra_list
[i
]->param
.index
+= 1;
2901 convert_to_long(pc
, e
);
2908 assert(!is_immd(pc
->p
->exec_head
));
2909 assert(!is_immd(pc
->p
->exec_tail
));
2911 /* last instruction must be long so it can have the end bit set */
2912 if (!is_long(pc
->p
->exec_tail
)) {
2913 convert_to_long(pc
, pc
->p
->exec_tail
);
2915 convert_to_long(pc
, prev
);
2917 assert(!(pc
->p
->exec_tail
->inst
[1] & 2));
2918 /* set the end-bit */
2919 pc
->p
->exec_tail
->inst
[1] |= 1;
2925 nv50_program_tx(struct nv50_program
*p
)
2927 struct tgsi_parse_context parse
;
2931 pc
= CALLOC_STRUCT(nv50_pc
);
2935 ret
= ctor_nv50_pc(pc
, p
);
2939 ret
= nv50_program_tx_prep(pc
);
2943 tgsi_parse_init(&parse
, pc
->p
->pipe
.tokens
);
2944 while (!tgsi_parse_end_of_tokens(&parse
)) {
2945 const union tgsi_full_token
*tok
= &parse
.FullToken
;
2947 /* don't allow half insn/immd on first and last instruction */
2949 if (pc
->insn_cur
== 0 || pc
->insn_cur
+ 2 == pc
->insn_nr
)
2950 pc
->allow32
= FALSE
;
2952 tgsi_parse_token(&parse
);
2954 switch (tok
->Token
.Type
) {
2955 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2957 ret
= nv50_tgsi_insn(pc
, tok
);
2966 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
)
2967 nv50_fp_move_results(pc
);
2969 nv50_program_fixup_insns(pc
);
2971 p
->param_nr
= pc
->param_nr
* 4;
2972 p
->immd_nr
= pc
->immd_nr
* 4;
2973 p
->immd
= pc
->immd_buf
;
2976 tgsi_parse_free(&parse
);
2984 nv50_program_validate(struct nv50_context
*nv50
, struct nv50_program
*p
)
2986 if (nv50_program_tx(p
) == FALSE
)
2988 p
->translated
= TRUE
;
2992 nv50_program_upload_data(struct nv50_context
*nv50
, float *map
,
2993 unsigned start
, unsigned count
, unsigned cbuf
)
2995 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
2996 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
2999 unsigned nr
= count
> 2047 ? 2047 : count
;
3001 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 1);
3002 OUT_RING (chan
, (cbuf
<< 0) | (start
<< 8));
3003 BEGIN_RING(chan
, tesla
, NV50TCL_CB_DATA(0) | 0x40000000, nr
);
3004 OUT_RINGp (chan
, map
, nr
);
3013 nv50_program_validate_data(struct nv50_context
*nv50
, struct nv50_program
*p
)
3015 struct pipe_screen
*pscreen
= nv50
->pipe
.screen
;
3017 if (!p
->data
[0] && p
->immd_nr
) {
3018 struct nouveau_resource
*heap
= nv50
->screen
->immd_heap
[0];
3020 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
, &p
->data
[0])) {
3021 while (heap
->next
&& heap
->size
< p
->immd_nr
) {
3022 struct nv50_program
*evict
= heap
->next
->priv
;
3023 nouveau_resource_free(&evict
->data
[0]);
3026 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
,
3031 /* immediates only need to be uploaded again when freed */
3032 nv50_program_upload_data(nv50
, p
->immd
, p
->data
[0]->start
,
3033 p
->immd_nr
, NV50_CB_PMISC
);
3036 assert(p
->param_nr
<= 512);
3040 float *map
= pipe_buffer_map(pscreen
, nv50
->constbuf
[p
->type
],
3041 PIPE_BUFFER_USAGE_CPU_READ
);
3043 if (p
->type
== PIPE_SHADER_VERTEX
)
3048 nv50_program_upload_data(nv50
, map
, 0, p
->param_nr
, cb
);
3049 pipe_buffer_unmap(pscreen
, nv50
->constbuf
[p
->type
]);
3054 nv50_program_validate_code(struct nv50_context
*nv50
, struct nv50_program
*p
)
3056 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
3057 struct nv50_program_exec
*e
;
3059 boolean upload
= FALSE
;
3062 nouveau_bo_new(chan
->device
, NOUVEAU_BO_VRAM
, 0x100,
3063 p
->exec_size
* 4, &p
->bo
);
3067 if (p
->data
[0] && p
->data
[0]->start
!= p
->data_start
[0])
3073 up
= MALLOC(p
->exec_size
* 4);
3075 for (i
= 0, e
= p
->exec_head
; e
; e
= e
->next
) {
3076 unsigned ei
, ci
, bs
;
3078 if (e
->param
.index
>= 0 && e
->param
.mask
) {
3079 bs
= (e
->inst
[1] >> 22) & 0x07;
3081 ei
= e
->param
.shift
>> 5;
3082 ci
= e
->param
.index
;
3084 ci
+= p
->data
[bs
]->start
;
3086 e
->inst
[ei
] &= ~e
->param
.mask
;
3087 e
->inst
[ei
] |= (ci
<< e
->param
.shift
);
3089 if (e
->param
.index
>= 0) {
3090 /* zero mask means param is a jump/branch offset */
3091 assert(!(e
->param
.index
& 1));
3092 /* seem to be 8 byte steps */
3093 ei
= (e
->param
.index
>> 1) + 0 /* START_ID */;
3095 e
->inst
[0] &= 0xf0000fff;
3096 e
->inst
[0] |= ei
<< 12;
3099 up
[i
++] = e
->inst
[0];
3101 up
[i
++] = e
->inst
[1];
3103 assert(i
== p
->exec_size
);
3106 p
->data_start
[0] = p
->data
[0]->start
;
3108 #ifdef NV50_PROGRAM_DUMP
3109 NOUVEAU_ERR("-------\n");
3110 for (e
= p
->exec_head
; e
; e
= e
->next
) {
3111 NOUVEAU_ERR("0x%08x\n", e
->inst
[0]);
3113 NOUVEAU_ERR("0x%08x\n", e
->inst
[1]);
3116 nv50_upload_sifc(nv50
, p
->bo
, 0, NOUVEAU_BO_VRAM
,
3117 NV50_2D_DST_FORMAT_R8_UNORM
, 65536, 1, 262144,
3118 up
, NV50_2D_SIFC_FORMAT_R8_UNORM
, 0,
3119 0, 0, p
->exec_size
* 4, 1, 1);
3125 nv50_vertprog_validate(struct nv50_context
*nv50
)
3127 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3128 struct nv50_program
*p
= nv50
->vertprog
;
3129 struct nouveau_stateobj
*so
;
3131 if (!p
->translated
) {
3132 nv50_program_validate(nv50
, p
);
3137 nv50_program_validate_data(nv50
, p
);
3138 nv50_program_validate_code(nv50
, p
);
3141 so_method(so
, tesla
, NV50TCL_VP_ADDRESS_HIGH
, 2);
3142 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3143 NOUVEAU_BO_HIGH
, 0, 0);
3144 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3145 NOUVEAU_BO_LOW
, 0, 0);
3146 so_method(so
, tesla
, NV50TCL_VP_ATTR_EN_0
, 2);
3147 so_data (so
, p
->cfg
.attr
[0]);
3148 so_data (so
, p
->cfg
.attr
[1]);
3149 so_method(so
, tesla
, NV50TCL_VP_REG_ALLOC_RESULT
, 1);
3150 so_data (so
, p
->cfg
.high_result
);
3151 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 2);
3152 so_data (so
, p
->cfg
.high_result
); //8);
3153 so_data (so
, p
->cfg
.high_temp
);
3154 so_method(so
, tesla
, NV50TCL_VP_START_ID
, 1);
3155 so_data (so
, 0); /* program start offset */
3156 so_ref(so
, &nv50
->state
.vertprog
);
3161 nv50_fragprog_validate(struct nv50_context
*nv50
)
3163 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3164 struct nv50_program
*p
= nv50
->fragprog
;
3165 struct nouveau_stateobj
*so
;
3167 if (!p
->translated
) {
3168 nv50_program_validate(nv50
, p
);
3173 nv50_program_validate_data(nv50
, p
);
3174 nv50_program_validate_code(nv50
, p
);
3177 so_method(so
, tesla
, NV50TCL_FP_ADDRESS_HIGH
, 2);
3178 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3179 NOUVEAU_BO_HIGH
, 0, 0);
3180 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3181 NOUVEAU_BO_LOW
, 0, 0);
3182 so_method(so
, tesla
, NV50TCL_FP_REG_ALLOC_TEMP
, 1);
3183 so_data (so
, p
->cfg
.high_temp
);
3184 so_method(so
, tesla
, NV50TCL_FP_RESULT_COUNT
, 1);
3185 so_data (so
, p
->cfg
.high_result
);
3186 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK19A8
, 1);
3187 so_data (so
, p
->cfg
.regs
[2]);
3188 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK196C
, 1);
3189 so_data (so
, p
->cfg
.regs
[3]);
3190 so_method(so
, tesla
, NV50TCL_FP_START_ID
, 1);
3191 so_data (so
, 0); /* program start offset */
3192 so_ref(so
, &nv50
->state
.fragprog
);
3197 nv50_pntc_replace(struct nv50_context
*nv50
, uint32_t pntc
[8], unsigned base
)
3199 struct nv50_program
*fp
= nv50
->fragprog
;
3200 struct nv50_program
*vp
= nv50
->vertprog
;
3201 unsigned i
, c
, m
= base
;
3203 /* XXX: This can't work correctly in all cases yet, we either
3204 * have to create TGSI_SEMANTIC_PNTC or sprite_coord_mode has
3205 * to be per FP input instead of per VP output
3207 memset(pntc
, 0, 8 * sizeof(uint32_t));
3209 for (i
= 0; i
< fp
->cfg
.io_nr
; i
++) {
3211 uint8_t j
= fp
->cfg
.io
[i
].id_vp
, k
= fp
->cfg
.io
[i
].id_fp
;
3212 unsigned n
= popcnt4(fp
->cfg
.io
[i
].mask
);
3214 if (fp
->info
.input_semantic_name
[k
] != TGSI_SEMANTIC_GENERIC
) {
3219 sn
= vp
->info
.input_semantic_name
[j
];
3220 si
= vp
->info
.input_semantic_index
[j
];
3222 if (j
< fp
->cfg
.io_nr
&& sn
== TGSI_SEMANTIC_GENERIC
) {
3224 nv50
->rasterizer
->pipe
.sprite_coord_mode
[si
];
3226 if (mode
== PIPE_SPRITE_COORD_NONE
) {
3232 /* this is either PointCoord or replaced by sprite coords */
3233 for (c
= 0; c
< 4; c
++) {
3234 if (!(fp
->cfg
.io
[i
].mask
& (1 << c
)))
3236 pntc
[m
/ 8] |= (c
+ 1) << ((m
% 8) * 4);
3243 nv50_sreg4_map(uint32_t *p_map
, int mid
, uint32_t lin
[4],
3244 struct nv50_sreg4
*fpi
, struct nv50_sreg4
*vpo
)
3247 uint8_t mv
= vpo
->mask
, mf
= fpi
->mask
, oid
= vpo
->hw
;
3248 uint8_t *map
= (uint8_t *)p_map
;
3250 for (c
= 0; c
< 4; ++c
) {
3252 if (fpi
->linear
== TRUE
)
3253 lin
[mid
/ 32] |= 1 << (mid
% 32);
3254 map
[mid
++] = (mv
& 1) ? oid
: ((c
== 3) ? 0x41 : 0x40);
3266 nv50_linkage_validate(struct nv50_context
*nv50
)
3268 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3269 struct nv50_program
*vp
= nv50
->vertprog
;
3270 struct nv50_program
*fp
= nv50
->fragprog
;
3271 struct nouveau_stateobj
*so
;
3272 struct nv50_sreg4 dummy
, *vpo
;
3274 uint32_t map
[16], lin
[4], reg
[5], pcrd
[8];
3276 memset(map
, 0, sizeof(map
));
3277 memset(lin
, 0, sizeof(lin
));
3279 reg
[1] = 0x00000004; /* low and high clip distance map ids */
3280 reg
[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3281 reg
[3] = 0x00000000; /* point size map id & enable */
3282 reg
[0] = fp
->cfg
.regs
[0]; /* colour semantic reg */
3283 reg
[4] = fp
->cfg
.regs
[1]; /* interpolant info */
3285 dummy
.linear
= FALSE
;
3286 dummy
.mask
= 0xf; /* map all components of HPOS */
3287 m
= nv50_sreg4_map(map
, m
, lin
, &dummy
, &vp
->cfg
.io
[0]);
3291 if (vp
->cfg
.clpd
< 0x40) {
3292 for (c
= 0; c
< vp
->cfg
.clpd_nr
; ++c
)
3293 map
[m
++] = vp
->cfg
.clpd
+ c
;
3297 reg
[0] |= m
<< 8; /* adjust BFC0 id */
3299 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3300 if (nv50
->rasterizer
->pipe
.light_twoside
) {
3301 vpo
= &vp
->cfg
.two_side
[0];
3303 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[0], &vpo
[0]);
3304 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[1], &vpo
[1]);
3307 reg
[0] += m
- 4; /* adjust FFC0 id */
3308 reg
[4] |= m
<< 8; /* set mid where 'normal' FP inputs start */
3311 if (fp
->info
.input_semantic_name
[0] == TGSI_SEMANTIC_POSITION
)
3313 for (; i
< fp
->cfg
.io_nr
; i
++) {
3314 ubyte sn
= fp
->info
.input_semantic_name
[fp
->cfg
.io
[i
].id_fp
];
3315 ubyte si
= fp
->info
.input_semantic_index
[fp
->cfg
.io
[i
].id_fp
];
3317 n
= fp
->cfg
.io
[i
].id_vp
;
3318 if (n
>= vp
->cfg
.io_nr
||
3319 vp
->info
.output_semantic_name
[n
] != sn
||
3320 vp
->info
.output_semantic_index
[n
] != si
)
3323 vpo
= &vp
->cfg
.io
[n
];
3325 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.io
[i
], vpo
);
3328 if (nv50
->rasterizer
->pipe
.point_size_per_vertex
) {
3329 map
[m
/ 4] |= vp
->cfg
.psiz
<< ((m
% 4) * 8);
3330 reg
[3] = (m
++ << 4) | 1;
3333 /* now fill the stateobj */
3337 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 1);
3339 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP(0), n
);
3340 so_datap (so
, map
, n
);
3342 so_method(so
, tesla
, NV50TCL_MAP_SEMANTIC_0
, 4);
3343 so_datap (so
, reg
, 4);
3345 so_method(so
, tesla
, NV50TCL_FP_INTERPOLANT_CTRL
, 1);
3346 so_data (so
, reg
[4]);
3348 so_method(so
, tesla
, 0x1540, 4);
3349 so_datap (so
, lin
, 4);
3351 if (nv50
->rasterizer
->pipe
.point_sprite
) {
3352 nv50_pntc_replace(nv50
, pcrd
, (reg
[4] >> 8) & 0xff);
3354 so_method(so
, tesla
, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3355 so_datap (so
, pcrd
, 8);
3358 so_ref(so
, &nv50
->state
.programs
);
3363 nv50_program_destroy(struct nv50_context
*nv50
, struct nv50_program
*p
)
3365 while (p
->exec_head
) {
3366 struct nv50_program_exec
*e
= p
->exec_head
;
3368 p
->exec_head
= e
->next
;
3371 p
->exec_tail
= NULL
;
3374 nouveau_bo_ref(NULL
, &p
->bo
);
3376 nouveau_resource_free(&p
->data
[0]);