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nv50: handle integer SET operations
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
100 #define NV50_MOD_SAT 4
101 #define NV50_MOD_I32 8
102
103 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
104
105 /* STACK: Conditionals and loops have to use the (per warp) stack.
106 * Stack entries consist of an entry type (divergent path, join at),
107 * a mask indicating the active threads of the warp, and an address.
108 * MPs can store 12 stack entries internally, if we need more (and
109 * we probably do), we have to create a stack buffer in VRAM.
110 */
111 /* impose low limits for now */
112 #define NV50_MAX_COND_NESTING 4
113 #define NV50_MAX_LOOP_NESTING 3
114
115 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
116
117 struct nv50_pc {
118 struct nv50_program *p;
119
120 /* hw resources */
121 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
122 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
123
124 /* tgsi resources */
125 struct nv50_reg *temp;
126 int temp_nr;
127 struct nv50_reg *attr;
128 int attr_nr;
129 struct nv50_reg *result;
130 int result_nr;
131 struct nv50_reg *param;
132 int param_nr;
133 struct nv50_reg *immd;
134 uint32_t *immd_buf;
135 int immd_nr;
136 struct nv50_reg **addr;
137 int addr_nr;
138 uint8_t addr_alloc; /* set bit indicates used for TGSI_FILE_ADDRESS */
139
140 struct nv50_reg *temp_temp[16];
141 unsigned temp_temp_nr;
142
143 /* broadcast and destination replacement regs */
144 struct nv50_reg *r_brdc;
145 struct nv50_reg *r_dst[4];
146
147 struct nv50_reg reg_instances[16];
148 unsigned reg_instance_nr;
149
150 unsigned interp_mode[32];
151 /* perspective interpolation registers */
152 struct nv50_reg *iv_p;
153 struct nv50_reg *iv_c;
154
155 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
156 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
157 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
158 int if_lvl, loop_lvl;
159 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
160
161 unsigned *insn_pos; /* actual program offset of each TGSI insn */
162 boolean in_subroutine;
163
164 /* current instruction and total number of insns */
165 unsigned insn_cur;
166 unsigned insn_nr;
167
168 boolean allow32;
169
170 uint8_t edgeflag_out;
171 };
172
173 static INLINE void
174 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
175 {
176 reg->type = type;
177 reg->index = index;
178 reg->hw = hw;
179 reg->mod = 0;
180 reg->rhw = -1;
181 reg->acc = 0;
182 }
183
184 static INLINE unsigned
185 popcnt4(uint32_t val)
186 {
187 static const unsigned cnt[16]
188 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
189 return cnt[val & 0xf];
190 }
191
192 static void
193 terminate_mbb(struct nv50_pc *pc)
194 {
195 int i;
196
197 /* remove records of temporary address register values */
198 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
199 pc->r_addr[i].rhw = -1;
200 }
201
202 static void
203 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
204 {
205 int i = 0;
206
207 if (reg->type == P_RESULT) {
208 if (pc->p->cfg.high_result < (reg->hw + 1))
209 pc->p->cfg.high_result = reg->hw + 1;
210 }
211
212 if (reg->type != P_TEMP)
213 return;
214
215 if (reg->hw >= 0) {
216 /*XXX: do this here too to catch FP temp-as-attr usage..
217 * not clean, but works */
218 if (pc->p->cfg.high_temp < (reg->hw + 1))
219 pc->p->cfg.high_temp = reg->hw + 1;
220 return;
221 }
222
223 if (reg->rhw != -1) {
224 /* try to allocate temporary with index rhw first */
225 if (!(pc->r_temp[reg->rhw])) {
226 pc->r_temp[reg->rhw] = reg;
227 reg->hw = reg->rhw;
228 if (pc->p->cfg.high_temp < (reg->rhw + 1))
229 pc->p->cfg.high_temp = reg->rhw + 1;
230 return;
231 }
232 /* make sure we don't get things like $r0 needs to go
233 * in $r1 and $r1 in $r0
234 */
235 i = pc->result_nr * 4;
236 }
237
238 for (; i < NV50_SU_MAX_TEMP; i++) {
239 if (!(pc->r_temp[i])) {
240 pc->r_temp[i] = reg;
241 reg->hw = i;
242 if (pc->p->cfg.high_temp < (i + 1))
243 pc->p->cfg.high_temp = i + 1;
244 return;
245 }
246 }
247
248 assert(0);
249 }
250
251 static INLINE struct nv50_reg *
252 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
253 {
254 struct nv50_reg *ri;
255
256 assert(pc->reg_instance_nr < 16);
257 ri = &pc->reg_instances[pc->reg_instance_nr++];
258 if (reg) {
259 alloc_reg(pc, reg);
260 *ri = *reg;
261 reg->mod = 0;
262 }
263 return ri;
264 }
265
266 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
267 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
268 * lest we risk temp_temps overwriting regs alloc'd "later".
269 */
270 static struct nv50_reg *
271 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
272 {
273 struct nv50_reg *r;
274 int i;
275
276 if (dst && dst->type == P_TEMP && dst->hw == -1)
277 return dst;
278
279 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
280 if (!pc->r_temp[i]) {
281 r = MALLOC_STRUCT(nv50_reg);
282 ctor_reg(r, P_TEMP, -1, i);
283 pc->r_temp[i] = r;
284 return r;
285 }
286 }
287
288 assert(0);
289 return NULL;
290 }
291
292 /* release the hardware resource held by r */
293 static void
294 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
295 {
296 assert(r->type == P_TEMP);
297 if (r->hw == -1)
298 return;
299
300 assert(pc->r_temp[r->hw] == r);
301 pc->r_temp[r->hw] = NULL;
302
303 r->acc = 0;
304 if (r->index == -1)
305 FREE(r);
306 }
307
308 static void
309 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
310 {
311 if (r->index == -1) {
312 unsigned hw = r->hw;
313
314 FREE(pc->r_temp[hw]);
315 pc->r_temp[hw] = NULL;
316 }
317 }
318
319 static int
320 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
321 {
322 int i;
323
324 if ((idx + 4) >= NV50_SU_MAX_TEMP)
325 return 1;
326
327 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
328 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
329 return alloc_temp4(pc, dst, idx + 4);
330
331 for (i = 0; i < 4; i++) {
332 dst[i] = MALLOC_STRUCT(nv50_reg);
333 ctor_reg(dst[i], P_TEMP, -1, idx + i);
334 pc->r_temp[idx + i] = dst[i];
335 }
336
337 return 0;
338 }
339
340 static void
341 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
342 {
343 int i;
344
345 for (i = 0; i < 4; i++)
346 free_temp(pc, reg[i]);
347 }
348
349 static struct nv50_reg *
350 temp_temp(struct nv50_pc *pc)
351 {
352 if (pc->temp_temp_nr >= 16)
353 assert(0);
354
355 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
356 return pc->temp_temp[pc->temp_temp_nr++];
357 }
358
359 static void
360 kill_temp_temp(struct nv50_pc *pc)
361 {
362 int i;
363
364 for (i = 0; i < pc->temp_temp_nr; i++)
365 free_temp(pc, pc->temp_temp[i]);
366 pc->temp_temp_nr = 0;
367 }
368
369 static int
370 ctor_immd_4u32(struct nv50_pc *pc,
371 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
372 {
373 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
374
375 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
376
377 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
378 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
379 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
380 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
381
382 return pc->immd_nr++;
383 }
384
385 static INLINE int
386 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
387 {
388 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
389 }
390
391 static struct nv50_reg *
392 alloc_immd(struct nv50_pc *pc, float f)
393 {
394 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
395 unsigned hw;
396
397 for (hw = 0; hw < pc->immd_nr * 4; hw++)
398 if (pc->immd_buf[hw] == fui(f))
399 break;
400
401 if (hw == pc->immd_nr * 4)
402 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
403
404 ctor_reg(r, P_IMMD, -1, hw);
405 return r;
406 }
407
408 static struct nv50_program_exec *
409 exec(struct nv50_pc *pc)
410 {
411 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
412
413 e->param.index = -1;
414 return e;
415 }
416
417 static void
418 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
419 {
420 struct nv50_program *p = pc->p;
421
422 if (p->exec_tail)
423 p->exec_tail->next = e;
424 if (!p->exec_head)
425 p->exec_head = e;
426 p->exec_tail = e;
427 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
428 }
429
430 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
431
432 static boolean
433 is_long(struct nv50_program_exec *e)
434 {
435 if (e->inst[0] & 1)
436 return TRUE;
437 return FALSE;
438 }
439
440 static boolean
441 is_immd(struct nv50_program_exec *e)
442 {
443 if (is_long(e) && (e->inst[1] & 3) == 3)
444 return TRUE;
445 return FALSE;
446 }
447
448 static boolean
449 is_join(struct nv50_program_exec *e)
450 {
451 if (is_long(e) && (e->inst[1] & 3) == 2)
452 return TRUE;
453 return FALSE;
454 }
455
456 static INLINE void
457 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
458 struct nv50_program_exec *e)
459 {
460 assert(!is_immd(e));
461 set_long(pc, e);
462 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
463 e->inst[1] |= (pred << 7) | (idx << 12);
464 }
465
466 static INLINE void
467 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
468 struct nv50_program_exec *e)
469 {
470 set_long(pc, e);
471 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
472 e->inst[1] |= (idx << 4) | (on << 6);
473 }
474
475 static INLINE void
476 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
477 {
478 if (is_long(e))
479 return;
480
481 e->inst[0] |= 1;
482 set_pred(pc, 0xf, 0, e);
483 set_pred_wr(pc, 0, 0, e);
484 }
485
486 static INLINE void
487 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
488 {
489 if (dst->type == P_RESULT) {
490 set_long(pc, e);
491 e->inst[1] |= 0x00000008;
492 }
493
494 alloc_reg(pc, dst);
495 if (dst->hw > 63)
496 set_long(pc, e);
497 e->inst[0] |= (dst->hw << 2);
498 }
499
500 static INLINE void
501 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
502 {
503 set_long(pc, e);
504 /* XXX: can't be predicated - bits overlap; cases where both
505 * are required should be avoided by using pc->allow32 */
506 set_pred(pc, 0, 0, e);
507 set_pred_wr(pc, 0, 0, e);
508
509 e->inst[1] |= 0x00000002 | 0x00000001;
510 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
511 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
512 }
513
514 static INLINE void
515 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
516 {
517 assert(!(e->inst[0] & 0x0c000000));
518 assert(!(e->inst[1] & 0x00000004));
519
520 e->inst[0] |= (a->hw & 3) << 26;
521 e->inst[1] |= (a->hw >> 2) << 2;
522 }
523
524 static void
525 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
526 struct nv50_reg *src0, uint16_t src1_val)
527 {
528 struct nv50_program_exec *e = exec(pc);
529
530 e->inst[0] = 0xd0000000 | (src1_val << 9);
531 e->inst[1] = 0x20000000;
532 set_long(pc, e);
533 e->inst[0] |= dst->hw << 2;
534 if (src0) /* otherwise will add to $a0, which is always 0 */
535 set_addr(e, src0);
536
537 emit(pc, e);
538 }
539
540 static struct nv50_reg *
541 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
542 {
543 struct nv50_reg *a_tgsi = NULL, *a = NULL;
544 int i;
545 uint8_t avail = ~pc->addr_alloc;
546
547 if (!ref) {
548 /* allocate for TGSI_FILE_ADDRESS */
549 while (avail) {
550 i = ffs(avail) - 1;
551
552 if (pc->r_addr[i].rhw < 0 ||
553 pc->r_addr[i].acc != pc->insn_cur) {
554 pc->addr_alloc |= (1 << i);
555
556 pc->r_addr[i].rhw = -1;
557 pc->r_addr[i].index = i;
558 return &pc->r_addr[i];
559 }
560 avail &= ~(1 << i);
561 }
562 assert(0);
563 return NULL;
564 }
565
566 /* Allocate and set an address reg so we can access 'ref'.
567 *
568 * If and r_addr->index will be -1 or the hw index the value
569 * value in rhw is relative to. If rhw < 0, the reg has not
570 * been initialized or is in use for TGSI_FILE_ADDRESS.
571 */
572 while (avail) { /* only consider regs that are not TGSI */
573 i = ffs(avail) - 1;
574 avail &= ~(1 << i);
575
576 if ((!a || a->rhw >= 0) && pc->r_addr[i].rhw < 0) {
577 /* prefer an usused reg with low hw index */
578 a = &pc->r_addr[i];
579 continue;
580 }
581 if (!a && pc->r_addr[i].acc != pc->insn_cur)
582 a = &pc->r_addr[i];
583
584 if (ref->hw - pc->r_addr[i].rhw >= 128)
585 continue;
586
587 if ((ref->acc >= 0 && pc->r_addr[i].index < 0) ||
588 (ref->acc < 0 && pc->r_addr[i].index == ref->index)) {
589 pc->r_addr[i].acc = pc->insn_cur;
590 return &pc->r_addr[i];
591 }
592 }
593 assert(a);
594
595 if (ref->acc < 0)
596 a_tgsi = pc->addr[ref->index];
597
598 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
599
600 a->rhw = ref->hw & ~0x7f;
601 a->acc = pc->insn_cur;
602 a->index = a_tgsi ? ref->index : -1;
603 return a;
604 }
605
606 #define INTERP_LINEAR 0
607 #define INTERP_FLAT 1
608 #define INTERP_PERSPECTIVE 2
609 #define INTERP_CENTROID 4
610
611 /* interpolant index has been stored in dst->rhw */
612 static void
613 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
614 unsigned mode)
615 {
616 assert(dst->rhw != -1);
617 struct nv50_program_exec *e = exec(pc);
618
619 e->inst[0] |= 0x80000000;
620 set_dst(pc, dst, e);
621 e->inst[0] |= (dst->rhw << 16);
622
623 if (mode & INTERP_FLAT) {
624 e->inst[0] |= (1 << 8);
625 } else {
626 if (mode & INTERP_PERSPECTIVE) {
627 e->inst[0] |= (1 << 25);
628 alloc_reg(pc, iv);
629 e->inst[0] |= (iv->hw << 9);
630 }
631
632 if (mode & INTERP_CENTROID)
633 e->inst[0] |= (1 << 24);
634 }
635
636 emit(pc, e);
637 }
638
639 static void
640 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
641 struct nv50_program_exec *e)
642 {
643 set_long(pc, e);
644
645 e->param.index = src->hw & 127;
646 e->param.shift = s;
647 e->param.mask = m << (s % 32);
648
649 if (src->hw > 127)
650 set_addr(e, alloc_addr(pc, src));
651 else
652 if (src->acc < 0) {
653 assert(src->type == P_CONST);
654 set_addr(e, pc->addr[src->index]);
655 }
656
657 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
658 }
659
660 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
661 static void
662 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
663 {
664 struct nv50_program_exec *e = exec(pc);
665
666 e->inst[0] = 0x10000000;
667 if (!pc->allow32)
668 set_long(pc, e);
669
670 set_dst(pc, dst, e);
671
672 if (!is_long(e) && src->type == P_IMMD) {
673 set_immd(pc, src, e);
674 /*XXX: 32-bit, but steals part of "half" reg space - need to
675 * catch and handle this case if/when we do half-regs
676 */
677 } else
678 if (src->type == P_IMMD || src->type == P_CONST) {
679 set_long(pc, e);
680 set_data(pc, src, 0x7f, 9, e);
681 e->inst[1] |= 0x20000000; /* mov from c[] */
682 } else {
683 if (src->type == P_ATTR) {
684 set_long(pc, e);
685 e->inst[1] |= 0x00200000;
686 }
687
688 alloc_reg(pc, src);
689 if (src->hw > 63)
690 set_long(pc, e);
691 e->inst[0] |= (src->hw << 9);
692 }
693
694 if (is_long(e) && !is_immd(e)) {
695 e->inst[1] |= 0x04000000; /* 32-bit */
696 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
697 if (!(e->inst[1] & 0x20000000))
698 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
699 } else
700 e->inst[0] |= 0x00008000;
701
702 emit(pc, e);
703 }
704
705 static INLINE void
706 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
707 {
708 struct nv50_reg *imm = alloc_immd(pc, f);
709 emit_mov(pc, dst, imm);
710 FREE(imm);
711 }
712
713 /* Assign the hw of the discarded temporary register src
714 * to the tgsi register dst and free src.
715 */
716 static void
717 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
718 {
719 assert(src->index == -1 && src->hw != -1);
720
721 if (pc->if_lvl || pc->loop_lvl ||
722 (dst->type != P_TEMP) ||
723 (src->hw < pc->result_nr * 4 &&
724 pc->p->type == PIPE_SHADER_FRAGMENT) ||
725 pc->p->info.opcode_count[TGSI_OPCODE_CAL] ||
726 pc->p->info.opcode_count[TGSI_OPCODE_BRA]) {
727
728 emit_mov(pc, dst, src);
729 free_temp(pc, src);
730 return;
731 }
732
733 if (dst->hw != -1)
734 pc->r_temp[dst->hw] = NULL;
735 pc->r_temp[src->hw] = dst;
736 dst->hw = src->hw;
737
738 FREE(src);
739 }
740
741 static void
742 emit_nop(struct nv50_pc *pc)
743 {
744 struct nv50_program_exec *e = exec(pc);
745
746 e->inst[0] = 0xf0000000;
747 set_long(pc, e);
748 e->inst[1] = 0xe0000000;
749 emit(pc, e);
750 }
751
752 static boolean
753 check_swap_src_0_1(struct nv50_pc *pc,
754 struct nv50_reg **s0, struct nv50_reg **s1)
755 {
756 struct nv50_reg *src0 = *s0, *src1 = *s1;
757
758 if (src0->type == P_CONST) {
759 if (src1->type != P_CONST) {
760 *s0 = src1;
761 *s1 = src0;
762 return TRUE;
763 }
764 } else
765 if (src1->type == P_ATTR) {
766 if (src0->type != P_ATTR) {
767 *s0 = src1;
768 *s1 = src0;
769 return TRUE;
770 }
771 }
772
773 return FALSE;
774 }
775
776 static void
777 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
778 struct nv50_program_exec *e)
779 {
780 struct nv50_reg *temp;
781
782 if (src->type != P_TEMP) {
783 temp = temp_temp(pc);
784 emit_mov(pc, temp, src);
785 src = temp;
786 }
787
788 alloc_reg(pc, src);
789 if (src->hw > 63)
790 set_long(pc, e);
791 e->inst[0] |= (src->hw << 9);
792 }
793
794 static void
795 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
796 {
797 if (src->type == P_ATTR) {
798 set_long(pc, e);
799 e->inst[1] |= 0x00200000;
800 } else
801 if (src->type == P_CONST || src->type == P_IMMD) {
802 struct nv50_reg *temp = temp_temp(pc);
803
804 emit_mov(pc, temp, src);
805 src = temp;
806 }
807
808 alloc_reg(pc, src);
809 if (src->hw > 63)
810 set_long(pc, e);
811 e->inst[0] |= (src->hw << 9);
812 }
813
814 static void
815 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
816 {
817 if (src->type == P_ATTR) {
818 struct nv50_reg *temp = temp_temp(pc);
819
820 emit_mov(pc, temp, src);
821 src = temp;
822 } else
823 if (src->type == P_CONST || src->type == P_IMMD) {
824 assert(!(e->inst[0] & 0x00800000));
825 if (e->inst[0] & 0x01000000) {
826 struct nv50_reg *temp = temp_temp(pc);
827
828 emit_mov(pc, temp, src);
829 src = temp;
830 } else {
831 set_data(pc, src, 0x7f, 16, e);
832 e->inst[0] |= 0x00800000;
833 }
834 }
835
836 alloc_reg(pc, src);
837 if (src->hw > 63)
838 set_long(pc, e);
839 e->inst[0] |= ((src->hw & 127) << 16);
840 }
841
842 static void
843 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
844 {
845 set_long(pc, e);
846
847 if (src->type == P_ATTR) {
848 struct nv50_reg *temp = temp_temp(pc);
849
850 emit_mov(pc, temp, src);
851 src = temp;
852 } else
853 if (src->type == P_CONST || src->type == P_IMMD) {
854 assert(!(e->inst[0] & 0x01000000));
855 if (e->inst[0] & 0x00800000) {
856 struct nv50_reg *temp = temp_temp(pc);
857
858 emit_mov(pc, temp, src);
859 src = temp;
860 } else {
861 set_data(pc, src, 0x7f, 32+14, e);
862 e->inst[0] |= 0x01000000;
863 }
864 }
865
866 alloc_reg(pc, src);
867 e->inst[1] |= ((src->hw & 127) << 14);
868 }
869
870 static void
871 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
872 {
873 struct nv50_program_exec *e = exec(pc);
874
875 assert(dst->type == P_TEMP);
876 e->inst[1] = 0x20000000 | (pred << 12);
877 set_long(pc, e);
878 set_dst(pc, dst, e);
879
880 emit(pc, e);
881 }
882
883 static void
884 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
885 {
886 struct nv50_program_exec *e = exec(pc);
887
888 e->inst[0] = 0x000001fc;
889 e->inst[1] = 0xa0000008;
890 set_long(pc, e);
891 set_pred_wr(pc, 1, pred, e);
892 set_src_0_restricted(pc, src, e);
893
894 emit(pc, e);
895 }
896
897 static void
898 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
899 struct nv50_reg *src1)
900 {
901 struct nv50_program_exec *e = exec(pc);
902
903 e->inst[0] |= 0xc0000000;
904
905 if (!pc->allow32)
906 set_long(pc, e);
907
908 check_swap_src_0_1(pc, &src0, &src1);
909 set_dst(pc, dst, e);
910 set_src_0(pc, src0, e);
911 if (src1->type == P_IMMD && !is_long(e)) {
912 if (src0->mod ^ src1->mod)
913 e->inst[0] |= 0x00008000;
914 set_immd(pc, src1, e);
915 } else {
916 set_src_1(pc, src1, e);
917 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
918 if (is_long(e))
919 e->inst[1] |= 0x08000000;
920 else
921 e->inst[0] |= 0x00008000;
922 }
923 }
924
925 emit(pc, e);
926 }
927
928 static void
929 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
930 struct nv50_reg *src0, struct nv50_reg *src1)
931 {
932 struct nv50_program_exec *e = exec(pc);
933
934 e->inst[0] = 0xb0000000;
935
936 alloc_reg(pc, src1);
937 check_swap_src_0_1(pc, &src0, &src1);
938
939 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
940 set_long(pc, e);
941 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
942 ((src1->mod & NV50_MOD_NEG) << 27);
943 }
944
945 set_dst(pc, dst, e);
946 set_src_0(pc, src0, e);
947 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
948 set_src_2(pc, src1, e);
949 else
950 if (src1->type == P_IMMD)
951 set_immd(pc, src1, e);
952 else
953 set_src_1(pc, src1, e);
954
955 emit(pc, e);
956 }
957
958 static void
959 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
960 uint8_t s)
961 {
962 struct nv50_program_exec *e = exec(pc);
963
964 set_long(pc, e);
965 e->inst[1] |= 0xc0000000;
966
967 e->inst[0] |= dst->hw << 2;
968 e->inst[0] |= s << 16; /* shift left */
969 set_src_0_restricted(pc, src, e);
970
971 emit(pc, e);
972 }
973
974 static void
975 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
976 struct nv50_reg *src0, struct nv50_reg *src1)
977 {
978 struct nv50_program_exec *e = exec(pc);
979
980 set_long(pc, e);
981 e->inst[0] |= 0xb0000000;
982 e->inst[1] |= (sub << 29);
983
984 check_swap_src_0_1(pc, &src0, &src1);
985 set_dst(pc, dst, e);
986 set_src_0(pc, src0, e);
987 set_src_1(pc, src1, e);
988
989 if (src0->mod & NV50_MOD_ABS)
990 e->inst[1] |= 0x00100000;
991 if (src1->mod & NV50_MOD_ABS)
992 e->inst[1] |= 0x00080000;
993
994 emit(pc, e);
995 }
996
997 static INLINE void
998 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
999 struct nv50_reg *src1)
1000 {
1001 src1->mod ^= NV50_MOD_NEG;
1002 emit_add(pc, dst, src0, src1);
1003 src1->mod ^= NV50_MOD_NEG;
1004 }
1005
1006 static void
1007 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1008 struct nv50_reg *src1, unsigned op)
1009 {
1010 struct nv50_program_exec *e = exec(pc);
1011
1012 e->inst[0] = 0xd0000000;
1013 set_long(pc, e);
1014
1015 check_swap_src_0_1(pc, &src0, &src1);
1016 set_dst(pc, dst, e);
1017 set_src_0(pc, src0, e);
1018
1019 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1020 op != TGSI_OPCODE_XOR)
1021 assert(!"invalid bit op");
1022
1023 assert(!(src0->mod | src1->mod));
1024
1025 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1026 set_immd(pc, src1, e);
1027 if (op == TGSI_OPCODE_OR)
1028 e->inst[0] |= 0x0100;
1029 else
1030 if (op == TGSI_OPCODE_XOR)
1031 e->inst[0] |= 0x8000;
1032 } else {
1033 set_src_1(pc, src1, e);
1034 e->inst[1] |= 0x04000000; /* 32 bit */
1035 if (op == TGSI_OPCODE_OR)
1036 e->inst[1] |= 0x4000;
1037 else
1038 if (op == TGSI_OPCODE_XOR)
1039 e->inst[1] |= 0x8000;
1040 }
1041
1042 emit(pc, e);
1043 }
1044
1045 static void
1046 emit_shift(struct nv50_pc *pc, struct nv50_reg *dst,
1047 struct nv50_reg *src0, struct nv50_reg *src1, unsigned dir)
1048 {
1049 struct nv50_program_exec *e = exec(pc);
1050
1051 e->inst[0] = 0x30000000;
1052 e->inst[1] = 0xc4000000;
1053
1054 set_long(pc, e);
1055 set_dst(pc, dst, e);
1056 set_src_0(pc, src0, e);
1057
1058 if (src1->type == P_IMMD) {
1059 e->inst[1] |= (1 << 20);
1060 e->inst[0] |= (pc->immd_buf[src1->hw] & 0x7f) << 16;
1061 } else
1062 set_src_1(pc, src1, e);
1063
1064 if (dir != TGSI_OPCODE_SHL)
1065 e->inst[1] |= (1 << 29);
1066
1067 if (dir == TGSI_OPCODE_ISHR)
1068 e->inst[1] |= (1 << 27);
1069
1070 emit(pc, e);
1071 }
1072
1073 static void
1074 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1075 struct nv50_reg *src1, struct nv50_reg *src2)
1076 {
1077 struct nv50_program_exec *e = exec(pc);
1078
1079 e->inst[0] |= 0xe0000000;
1080
1081 check_swap_src_0_1(pc, &src0, &src1);
1082 set_dst(pc, dst, e);
1083 set_src_0(pc, src0, e);
1084 set_src_1(pc, src1, e);
1085 set_src_2(pc, src2, e);
1086
1087 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1088 e->inst[1] |= 0x04000000;
1089 if (src2->mod & NV50_MOD_NEG)
1090 e->inst[1] |= 0x08000000;
1091
1092 emit(pc, e);
1093 }
1094
1095 static INLINE void
1096 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1097 struct nv50_reg *src1, struct nv50_reg *src2)
1098 {
1099 src2->mod ^= NV50_MOD_NEG;
1100 emit_mad(pc, dst, src0, src1, src2);
1101 src2->mod ^= NV50_MOD_NEG;
1102 }
1103
1104 #define NV50_FLOP_RCP 0
1105 #define NV50_FLOP_RSQ 2
1106 #define NV50_FLOP_LG2 3
1107 #define NV50_FLOP_SIN 4
1108 #define NV50_FLOP_COS 5
1109 #define NV50_FLOP_EX2 6
1110
1111 /* rcp, rsqrt, lg2 support neg and abs */
1112 static void
1113 emit_flop(struct nv50_pc *pc, unsigned sub,
1114 struct nv50_reg *dst, struct nv50_reg *src)
1115 {
1116 struct nv50_program_exec *e = exec(pc);
1117
1118 e->inst[0] |= 0x90000000;
1119 if (sub || src->mod) {
1120 set_long(pc, e);
1121 e->inst[1] |= (sub << 29);
1122 }
1123
1124 set_dst(pc, dst, e);
1125 set_src_0_restricted(pc, src, e);
1126
1127 assert(!src->mod || sub < 4);
1128
1129 if (src->mod & NV50_MOD_NEG)
1130 e->inst[1] |= 0x04000000;
1131 if (src->mod & NV50_MOD_ABS)
1132 e->inst[1] |= 0x00100000;
1133
1134 emit(pc, e);
1135 }
1136
1137 static void
1138 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1139 {
1140 struct nv50_program_exec *e = exec(pc);
1141
1142 e->inst[0] |= 0xb0000000;
1143
1144 set_dst(pc, dst, e);
1145 set_src_0(pc, src, e);
1146 set_long(pc, e);
1147 e->inst[1] |= (6 << 29) | 0x00004000;
1148
1149 if (src->mod & NV50_MOD_NEG)
1150 e->inst[1] |= 0x04000000;
1151 if (src->mod & NV50_MOD_ABS)
1152 e->inst[1] |= 0x00100000;
1153
1154 emit(pc, e);
1155 }
1156
1157 static void
1158 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1159 {
1160 struct nv50_program_exec *e = exec(pc);
1161
1162 e->inst[0] |= 0xb0000000;
1163
1164 set_dst(pc, dst, e);
1165 set_src_0(pc, src, e);
1166 set_long(pc, e);
1167 e->inst[1] |= (6 << 29);
1168
1169 if (src->mod & NV50_MOD_NEG)
1170 e->inst[1] |= 0x04000000;
1171 if (src->mod & NV50_MOD_ABS)
1172 e->inst[1] |= 0x00100000;
1173
1174 emit(pc, e);
1175 }
1176
1177 #define CVT_RN (0x00 << 16)
1178 #define CVT_FLOOR (0x02 << 16)
1179 #define CVT_CEIL (0x04 << 16)
1180 #define CVT_TRUNC (0x06 << 16)
1181 #define CVT_SAT (0x08 << 16)
1182 #define CVT_ABS (0x10 << 16)
1183
1184 #define CVT_X32_X32 0x04004000
1185 #define CVT_X32_S32 0x04014000
1186 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1187 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1188 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1189 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1190 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1191 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1192 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1193 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1194
1195 #define CVT_NEG 0x20000000
1196 #define CVT_RI 0x08000000
1197
1198 static void
1199 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1200 int wp, uint32_t cvn)
1201 {
1202 struct nv50_program_exec *e;
1203
1204 e = exec(pc);
1205
1206 if (src->mod & NV50_MOD_NEG) cvn |= CVT_NEG;
1207 if (src->mod & NV50_MOD_ABS) cvn |= CVT_ABS;
1208
1209 e->inst[0] = 0xa0000000;
1210 e->inst[1] = cvn;
1211 set_long(pc, e);
1212 set_src_0(pc, src, e);
1213
1214 if (wp >= 0)
1215 set_pred_wr(pc, 1, wp, e);
1216
1217 if (dst)
1218 set_dst(pc, dst, e);
1219 else {
1220 e->inst[0] |= 0x000001fc;
1221 e->inst[1] |= 0x00000008;
1222 }
1223
1224 emit(pc, e);
1225 }
1226
1227 /* nv50 Condition codes:
1228 * 0x1 = LT
1229 * 0x2 = EQ
1230 * 0x3 = LE
1231 * 0x4 = GT
1232 * 0x5 = NE
1233 * 0x6 = GE
1234 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1235 * 0x8 = unordered bit (allows NaN)
1236 *
1237 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1238 */
1239 static void
1240 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1241 struct nv50_reg *src0, struct nv50_reg *src1, uint8_t mode)
1242 {
1243 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1244
1245 struct nv50_program_exec *e = exec(pc);
1246 struct nv50_reg *rdst;
1247
1248 assert(ccode < 16);
1249 if (check_swap_src_0_1(pc, &src0, &src1))
1250 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1251
1252 rdst = dst;
1253 if (dst && dst->type != P_TEMP)
1254 dst = alloc_temp(pc, NULL);
1255
1256 set_long(pc, e);
1257 e->inst[0] |= 0x30000000 | (mode << 24);
1258 e->inst[1] |= 0x60000000 | (ccode << 14);
1259
1260 if (wp >= 0)
1261 set_pred_wr(pc, 1, wp, e);
1262 if (dst)
1263 set_dst(pc, dst, e);
1264 else {
1265 e->inst[0] |= 0x000001fc;
1266 e->inst[1] |= 0x00000008;
1267 }
1268
1269 set_src_0(pc, src0, e);
1270 set_src_1(pc, src1, e);
1271
1272 emit(pc, e);
1273
1274 if (rdst && mode == 0x80) /* convert to float ? */
1275 emit_cvt(pc, rdst, dst, -1, CVT_ABS | CVT_F32_S32);
1276 if (rdst && rdst != dst)
1277 free_temp(pc, dst);
1278 }
1279
1280 static INLINE void
1281 map_tgsi_setop_hw(unsigned op, uint8_t *cc, uint8_t *ty)
1282 {
1283 switch (op) {
1284 case TGSI_OPCODE_SLT: *cc = 0x1; *ty = 0x80; break;
1285 case TGSI_OPCODE_SGE: *cc = 0x6; *ty = 0x80; break;
1286 case TGSI_OPCODE_SEQ: *cc = 0x2; *ty = 0x80; break;
1287 case TGSI_OPCODE_SGT: *cc = 0x4; *ty = 0x80; break;
1288 case TGSI_OPCODE_SLE: *cc = 0x3; *ty = 0x80; break;
1289 case TGSI_OPCODE_SNE: *cc = 0xd; *ty = 0x80; break;
1290
1291 case TGSI_OPCODE_ISLT: *cc = 0x1; *ty = 0x0c; break;
1292 case TGSI_OPCODE_ISGE: *cc = 0x6; *ty = 0x0c; break;
1293 case TGSI_OPCODE_USEQ: *cc = 0x2; *ty = 0x04; break;
1294 case TGSI_OPCODE_USGE: *cc = 0x6; *ty = 0x04; break;
1295 case TGSI_OPCODE_USLT: *cc = 0x1; *ty = 0x04; break;
1296 case TGSI_OPCODE_USNE: *cc = 0x5; *ty = 0x04; break;
1297 default:
1298 assert(0);
1299 return;
1300 }
1301 }
1302
1303 static INLINE void
1304 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1305 {
1306 emit_cvt(pc, dst, src, -1, CVT_FLOOR | CVT_F32_F32 | CVT_RI);
1307 }
1308
1309 static void
1310 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1311 struct nv50_reg *v, struct nv50_reg *e)
1312 {
1313 struct nv50_reg *temp = alloc_temp(pc, NULL);
1314
1315 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1316 emit_mul(pc, temp, temp, e);
1317 emit_preex2(pc, temp, temp);
1318 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1319
1320 free_temp(pc, temp);
1321 }
1322
1323 static INLINE void
1324 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1325 {
1326 emit_cvt(pc, dst, src, -1, CVT_SAT | CVT_F32_F32);
1327 }
1328
1329 static void
1330 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1331 struct nv50_reg **src)
1332 {
1333 struct nv50_reg *one = alloc_immd(pc, 1.0);
1334 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1335 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1336 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1337 struct nv50_reg *tmp[4];
1338 boolean allow32 = pc->allow32;
1339
1340 pc->allow32 = FALSE;
1341
1342 if (mask & (3 << 1)) {
1343 tmp[0] = alloc_temp(pc, NULL);
1344 emit_minmax(pc, 4, tmp[0], src[0], zero);
1345 }
1346
1347 if (mask & (1 << 2)) {
1348 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1349
1350 tmp[1] = temp_temp(pc);
1351 emit_minmax(pc, 4, tmp[1], src[1], zero);
1352
1353 tmp[3] = temp_temp(pc);
1354 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1355 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1356
1357 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1358 emit_mov(pc, dst[2], zero);
1359 set_pred(pc, 3, 0, pc->p->exec_tail);
1360 }
1361
1362 if (mask & (1 << 1))
1363 assimilate_temp(pc, dst[1], tmp[0]);
1364 else
1365 if (mask & (1 << 2))
1366 free_temp(pc, tmp[0]);
1367
1368 pc->allow32 = allow32;
1369
1370 /* do this last, in case src[i,j] == dst[0,3] */
1371 if (mask & (1 << 0))
1372 emit_mov(pc, dst[0], one);
1373
1374 if (mask & (1 << 3))
1375 emit_mov(pc, dst[3], one);
1376
1377 FREE(pos128);
1378 FREE(neg128);
1379 FREE(zero);
1380 FREE(one);
1381 }
1382
1383 static void
1384 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1385 {
1386 struct nv50_program_exec *e;
1387 const int r_pred = 1;
1388
1389 e = exec(pc);
1390 e->inst[0] = 0x00000002; /* discard */
1391 set_long(pc, e); /* sets cond code to ALWAYS */
1392
1393 if (src) {
1394 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1395 /* write to predicate reg */
1396 emit_cvt(pc, NULL, src, r_pred, CVT_F32_F32);
1397 }
1398
1399 emit(pc, e);
1400 }
1401
1402 static struct nv50_program_exec *
1403 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1404 {
1405 struct nv50_program_exec *e = exec(pc);
1406
1407 e->inst[0] = (op << 28) | 2;
1408 set_long(pc, e);
1409 if (pred >= 0)
1410 set_pred(pc, cc, pred, e);
1411
1412 emit(pc, e);
1413 return e;
1414 }
1415
1416 static INLINE struct nv50_program_exec *
1417 emit_breakaddr(struct nv50_pc *pc)
1418 {
1419 return emit_control_flow(pc, 0x4, -1, 0);
1420 }
1421
1422 static INLINE void
1423 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1424 {
1425 emit_control_flow(pc, 0x5, pred, cc);
1426 }
1427
1428 static INLINE struct nv50_program_exec *
1429 emit_joinat(struct nv50_pc *pc)
1430 {
1431 return emit_control_flow(pc, 0xa, -1, 0);
1432 }
1433
1434 static INLINE struct nv50_program_exec *
1435 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1436 {
1437 return emit_control_flow(pc, 0x1, pred, cc);
1438 }
1439
1440 static INLINE struct nv50_program_exec *
1441 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1442 {
1443 return emit_control_flow(pc, 0x2, pred, cc);
1444 }
1445
1446 static INLINE void
1447 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1448 {
1449 emit_control_flow(pc, 0x3, pred, cc);
1450 }
1451
1452 #define QOP_ADD 0
1453 #define QOP_SUBR 1
1454 #define QOP_SUB 2
1455 #define QOP_MOV_SRC1 3
1456
1457 /* For a quad of threads / top left, top right, bottom left, bottom right
1458 * pixels, do a different operation, and take src0 from a specific thread.
1459 */
1460 static void
1461 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1462 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1463 {
1464 struct nv50_program_exec *e = exec(pc);
1465
1466 e->inst[0] = 0xc0000000;
1467 e->inst[1] = 0x80000000;
1468 set_long(pc, e);
1469 e->inst[0] |= lane_src0 << 16;
1470 set_src_0(pc, src0, e);
1471 set_src_2(pc, src1, e);
1472
1473 if (wp >= 0)
1474 set_pred_wr(pc, 1, wp, e);
1475
1476 if (dst)
1477 set_dst(pc, dst, e);
1478 else {
1479 e->inst[0] |= 0x000001fc;
1480 e->inst[1] |= 0x00000008;
1481 }
1482
1483 e->inst[0] |= (qop & 3) << 20;
1484 e->inst[1] |= (qop >> 2) << 22;
1485
1486 emit(pc, e);
1487 }
1488
1489 static void
1490 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1491 struct nv50_reg **src, unsigned arg, boolean proj)
1492 {
1493 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1494
1495 src[0]->mod |= NV50_MOD_ABS;
1496 src[1]->mod |= NV50_MOD_ABS;
1497 src[2]->mod |= NV50_MOD_ABS;
1498
1499 emit_minmax(pc, 4, t[2], src[0], src[1]);
1500 emit_minmax(pc, 4, t[2], src[2], t[2]);
1501
1502 src[0]->mod = mod[0];
1503 src[1]->mod = mod[1];
1504 src[2]->mod = mod[2];
1505
1506 if (proj && 0 /* looks more correct without this */)
1507 emit_mul(pc, t[2], t[2], src[3]);
1508 else
1509 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1510 emit_mov(pc, t[3], src[3]);
1511
1512 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1513
1514 emit_mul(pc, t[0], src[0], t[2]);
1515 emit_mul(pc, t[1], src[1], t[2]);
1516 emit_mul(pc, t[2], src[2], t[2]);
1517 }
1518
1519 static void
1520 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1521 struct nv50_reg **src, unsigned dim, unsigned arg)
1522 {
1523 unsigned c, mode;
1524
1525 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1526 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1527
1528 t[3]->rhw = src[3]->rhw;
1529 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1530 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1531
1532 for (c = 0; c < dim; ++c) {
1533 t[c]->rhw = src[c]->rhw;
1534 emit_interp(pc, t[c], t[3], mode);
1535 }
1536 if (arg != dim) { /* depth reference value */
1537 t[dim]->rhw = src[2]->rhw;
1538 emit_interp(pc, t[dim], t[3], mode);
1539 }
1540 } else {
1541 /* XXX: for some reason the blob sometimes uses MAD
1542 * (mad f32 $rX $rY $rZ neg $r63)
1543 */
1544 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1545 for (c = 0; c < dim; ++c)
1546 emit_mul(pc, t[c], src[c], t[3]);
1547 if (arg != dim) /* depth reference value */
1548 emit_mul(pc, t[dim], src[2], t[3]);
1549 }
1550 }
1551
1552 static INLINE void
1553 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1554 {
1555 switch (type) {
1556 case TGSI_TEXTURE_1D:
1557 *arg = *dim = 1;
1558 break;
1559 case TGSI_TEXTURE_SHADOW1D:
1560 *dim = 1;
1561 *arg = 2;
1562 break;
1563 case TGSI_TEXTURE_UNKNOWN:
1564 case TGSI_TEXTURE_2D:
1565 case TGSI_TEXTURE_RECT:
1566 *arg = *dim = 2;
1567 break;
1568 case TGSI_TEXTURE_SHADOW2D:
1569 case TGSI_TEXTURE_SHADOWRECT:
1570 *dim = 2;
1571 *arg = 3;
1572 break;
1573 case TGSI_TEXTURE_3D:
1574 case TGSI_TEXTURE_CUBE:
1575 *dim = *arg = 3;
1576 break;
1577 default:
1578 assert(0);
1579 break;
1580 }
1581 }
1582
1583 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1584 * different LOD values, so branch off groups of equal LOD.
1585 */
1586 static void
1587 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1588 struct nv50_reg *src, struct nv50_program_exec *tex)
1589 {
1590 struct nv50_program_exec *join_at;
1591 unsigned i, target = pc->p->exec_size + 9 * 2;
1592
1593 if (pc->p->type != PIPE_SHADER_FRAGMENT) {
1594 emit(pc, tex);
1595 return;
1596 }
1597 pc->allow32 = FALSE;
1598
1599 /* Subtract lod of each pixel from lod of top left pixel, jump
1600 * texlod insn if result is 0, then repeat for 2 other pixels.
1601 */
1602 join_at = emit_joinat(pc);
1603 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1604 emit_branch(pc, 0, 2)->param.index = target;
1605
1606 for (i = 1; i < 4; ++i) {
1607 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1608 emit_branch(pc, 0, 2)->param.index = target;
1609 }
1610
1611 emit_mov(pc, tlod, src); /* target */
1612 emit(pc, tex); /* texlod */
1613
1614 join_at->param.index = target + 2 * 2;
1615 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1616 }
1617
1618 static void
1619 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1620 struct nv50_program_exec *tex)
1621 {
1622 struct nv50_program_exec *e;
1623 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1624 int r_pred = 0;
1625 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1626
1627 pc->allow32 = FALSE;
1628 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1629
1630 /* Subtract bias value of thread i from bias values of each thread,
1631 * store result in r_pred, and set bit i in r_bits if result was 0.
1632 */
1633 assert(arg < 4);
1634 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1635 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1636 emit_mov(pc, r_bits, &imm_1248);
1637 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1638 }
1639 emit_mov_to_pred(pc, r_pred, r_bits);
1640
1641 /* The lanes of a quad are now grouped by the bit in r_pred they have
1642 * set. Put the input values for TEX into a new register set for each
1643 * group and execute TEX only for a specific group.
1644 * We cannot use the same register set for each group because we need
1645 * the derivatives, which are implicitly calculated, to be correct.
1646 */
1647 for (i = 1; i < 4; ++i) {
1648 alloc_temp4(pc, t123[i], 0);
1649
1650 for (c = 0; c <= arg; ++c)
1651 emit_mov(pc, t123[i][c], t[c]);
1652
1653 *(e = exec(pc)) = *(tex);
1654 e->inst[0] &= ~0x01fc;
1655 set_dst(pc, t123[i][0], e);
1656 set_pred(pc, cc[i], r_pred, e);
1657 emit(pc, e);
1658 }
1659 /* finally TEX on the original regs (where we kept the input) */
1660 set_pred(pc, cc[0], r_pred, tex);
1661 emit(pc, tex);
1662
1663 /* put the 3 * n other results into regs for lane 0 */
1664 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1665 for (i = 1; i < 4; ++i) {
1666 for (c = 0; c < n; ++c) {
1667 emit_mov(pc, t[c], t123[i][c]);
1668 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1669 }
1670 free_temp4(pc, t123[i]);
1671 }
1672
1673 emit_nop(pc);
1674 free_temp(pc, r_bits);
1675 }
1676
1677 static void
1678 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1679 struct nv50_reg **src, unsigned unit, unsigned type,
1680 boolean proj, int bias_lod)
1681 {
1682 struct nv50_reg *t[4];
1683 struct nv50_program_exec *e;
1684 unsigned c, dim, arg;
1685
1686 /* t[i] must be within a single 128 bit super-reg */
1687 alloc_temp4(pc, t, 0);
1688
1689 e = exec(pc);
1690 e->inst[0] = 0xf0000000;
1691 set_long(pc, e);
1692 set_dst(pc, t[0], e);
1693
1694 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1695 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1696
1697 /* live flag (don't set if TEX results affect input to another TEX): */
1698 /* e->inst[0] |= 0x00000004; */
1699
1700 get_tex_dim(type, &dim, &arg);
1701
1702 if (type == TGSI_TEXTURE_CUBE) {
1703 e->inst[0] |= 0x08000000;
1704 load_cube_tex_coords(pc, t, src, arg, proj);
1705 } else
1706 if (proj)
1707 load_proj_tex_coords(pc, t, src, dim, arg);
1708 else {
1709 for (c = 0; c < dim; c++)
1710 emit_mov(pc, t[c], src[c]);
1711 if (arg != dim) /* depth reference value (always src.z here) */
1712 emit_mov(pc, t[dim], src[2]);
1713 }
1714
1715 e->inst[0] |= (mask & 0x3) << 25;
1716 e->inst[1] |= (mask & 0xc) << 12;
1717
1718 if (!bias_lod) {
1719 e->inst[0] |= (arg - 1) << 22;
1720 emit(pc, e);
1721 } else
1722 if (bias_lod < 0) {
1723 assert(pc->p->type == PIPE_SHADER_FRAGMENT);
1724 e->inst[0] |= arg << 22;
1725 e->inst[1] |= 0x20000000; /* texbias */
1726 emit_mov(pc, t[arg], src[3]);
1727 emit_texbias_sequence(pc, t, arg, e);
1728 } else {
1729 e->inst[0] |= arg << 22;
1730 e->inst[1] |= 0x40000000; /* texlod */
1731 emit_mov(pc, t[arg], src[3]);
1732 emit_texlod_sequence(pc, t[arg], src[3], e);
1733 }
1734
1735 #if 1
1736 c = 0;
1737 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1738 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1739 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1740 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1741
1742 free_temp4(pc, t);
1743 #else
1744 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1745 * the texture coordinates, not the fetched values: latency ? */
1746
1747 for (c = 0; c < 4; c++) {
1748 if (mask & (1 << c))
1749 assimilate_temp(pc, dst[c], t[c]);
1750 else
1751 free_temp(pc, t[c]);
1752 }
1753 #endif
1754 }
1755
1756 static void
1757 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1758 {
1759 struct nv50_program_exec *e = exec(pc);
1760
1761 assert(src->type == P_TEMP);
1762
1763 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
1764 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
1765 set_long(pc, e);
1766 set_dst(pc, dst, e);
1767 set_src_0(pc, src, e);
1768 set_src_2(pc, src, e);
1769
1770 emit(pc, e);
1771 }
1772
1773 static void
1774 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1775 {
1776 struct nv50_program_exec *e = exec(pc);
1777
1778 assert(src->type == P_TEMP);
1779
1780 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
1781 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
1782 set_long(pc, e);
1783 set_dst(pc, dst, e);
1784 set_src_0(pc, src, e);
1785 set_src_2(pc, src, e);
1786
1787 emit(pc, e);
1788 }
1789
1790 static void
1791 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1792 {
1793 unsigned q = 0, m = ~0;
1794
1795 assert(!is_long(e));
1796
1797 switch (e->inst[0] >> 28) {
1798 case 0x1:
1799 /* MOV */
1800 q = 0x0403c000;
1801 m = 0xffff7fff;
1802 break;
1803 case 0x8:
1804 /* INTERP (move centroid, perspective and flat bits) */
1805 m = ~0x03000100;
1806 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1807 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1808 break;
1809 case 0x9:
1810 /* RCP */
1811 break;
1812 case 0xB:
1813 /* ADD */
1814 m = ~(127 << 16);
1815 q = ((e->inst[0] & (~m)) >> 2);
1816 break;
1817 case 0xC:
1818 /* MUL */
1819 m = ~0x00008000;
1820 q = ((e->inst[0] & (~m)) << 12);
1821 break;
1822 case 0xE:
1823 /* MAD (if src2 == dst) */
1824 q = ((e->inst[0] & 0x1fc) << 12);
1825 break;
1826 default:
1827 assert(0);
1828 break;
1829 }
1830
1831 set_long(pc, e);
1832 pc->p->exec_size++;
1833
1834 e->inst[0] &= m;
1835 e->inst[1] |= q;
1836 }
1837
1838 /* Some operations support an optional negation flag. */
1839 static int
1840 get_supported_mods(const struct tgsi_full_instruction *insn, int i)
1841 {
1842 switch (insn->Instruction.Opcode) {
1843 case TGSI_OPCODE_ADD:
1844 case TGSI_OPCODE_COS:
1845 case TGSI_OPCODE_DDX:
1846 case TGSI_OPCODE_DDY:
1847 case TGSI_OPCODE_DP3:
1848 case TGSI_OPCODE_DP4:
1849 case TGSI_OPCODE_EX2:
1850 case TGSI_OPCODE_KIL:
1851 case TGSI_OPCODE_LG2:
1852 case TGSI_OPCODE_MAD:
1853 case TGSI_OPCODE_MUL:
1854 case TGSI_OPCODE_POW:
1855 case TGSI_OPCODE_RCP:
1856 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
1857 case TGSI_OPCODE_SCS:
1858 case TGSI_OPCODE_SIN:
1859 case TGSI_OPCODE_SUB:
1860 return NV50_MOD_NEG;
1861 case TGSI_OPCODE_MAX:
1862 case TGSI_OPCODE_MIN:
1863 case TGSI_OPCODE_INEG: /* tgsi src sign toggle/set would be stupid */
1864 return NV50_MOD_ABS;
1865 case TGSI_OPCODE_CEIL:
1866 case TGSI_OPCODE_FLR:
1867 case TGSI_OPCODE_TRUNC:
1868 return NV50_MOD_NEG | NV50_MOD_ABS;
1869 case TGSI_OPCODE_F2I:
1870 case TGSI_OPCODE_F2U:
1871 case TGSI_OPCODE_I2F:
1872 case TGSI_OPCODE_U2F:
1873 return NV50_MOD_NEG | NV50_MOD_ABS | NV50_MOD_I32;
1874 case TGSI_OPCODE_SHL:
1875 case TGSI_OPCODE_ISHR:
1876 case TGSI_OPCODE_USHR:
1877 return NV50_MOD_I32;
1878 default:
1879 return 0;
1880 }
1881 }
1882
1883 /* Return a read mask for source registers deduced from opcode & write mask. */
1884 static unsigned
1885 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1886 {
1887 unsigned x, mask = insn->Dst[0].Register.WriteMask;
1888
1889 switch (insn->Instruction.Opcode) {
1890 case TGSI_OPCODE_COS:
1891 case TGSI_OPCODE_SIN:
1892 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1893 case TGSI_OPCODE_DP3:
1894 return 0x7;
1895 case TGSI_OPCODE_DP4:
1896 case TGSI_OPCODE_DPH:
1897 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1898 return 0xf;
1899 case TGSI_OPCODE_DST:
1900 return mask & (c ? 0xa : 0x6);
1901 case TGSI_OPCODE_EX2:
1902 case TGSI_OPCODE_EXP:
1903 case TGSI_OPCODE_LG2:
1904 case TGSI_OPCODE_LOG:
1905 case TGSI_OPCODE_POW:
1906 case TGSI_OPCODE_RCP:
1907 case TGSI_OPCODE_RSQ:
1908 case TGSI_OPCODE_SCS:
1909 return 0x1;
1910 case TGSI_OPCODE_IF:
1911 return 0x1;
1912 case TGSI_OPCODE_LIT:
1913 return 0xb;
1914 case TGSI_OPCODE_TEX:
1915 case TGSI_OPCODE_TXB:
1916 case TGSI_OPCODE_TXL:
1917 case TGSI_OPCODE_TXP:
1918 {
1919 const struct tgsi_instruction_texture *tex;
1920
1921 assert(insn->Instruction.Texture);
1922 tex = &insn->Texture;
1923
1924 mask = 0x7;
1925 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
1926 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
1927 mask |= 0x8; /* bias, lod or proj */
1928
1929 switch (tex->Texture) {
1930 case TGSI_TEXTURE_1D:
1931 mask &= 0x9;
1932 break;
1933 case TGSI_TEXTURE_SHADOW1D:
1934 mask &= 0x5;
1935 break;
1936 case TGSI_TEXTURE_2D:
1937 mask &= 0xb;
1938 break;
1939 default:
1940 break;
1941 }
1942 }
1943 return mask;
1944 case TGSI_OPCODE_XPD:
1945 x = 0;
1946 if (mask & 1) x |= 0x6;
1947 if (mask & 2) x |= 0x5;
1948 if (mask & 4) x |= 0x3;
1949 return x;
1950 default:
1951 break;
1952 }
1953
1954 return mask;
1955 }
1956
1957 static struct nv50_reg *
1958 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1959 {
1960 switch (dst->Register.File) {
1961 case TGSI_FILE_TEMPORARY:
1962 return &pc->temp[dst->Register.Index * 4 + c];
1963 case TGSI_FILE_OUTPUT:
1964 return &pc->result[dst->Register.Index * 4 + c];
1965 case TGSI_FILE_ADDRESS:
1966 {
1967 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
1968 if (!r) {
1969 r = alloc_addr(pc, NULL);
1970 pc->addr[dst->Register.Index * 4 + c] = r;
1971 }
1972 assert(r);
1973 return r;
1974 }
1975 case TGSI_FILE_NULL:
1976 return NULL;
1977 default:
1978 break;
1979 }
1980
1981 return NULL;
1982 }
1983
1984 static struct nv50_reg *
1985 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1986 int mod)
1987 {
1988 struct nv50_reg *r = NULL;
1989 struct nv50_reg *temp = NULL;
1990 unsigned sgn, c, swz, cvn;
1991
1992 if (src->Register.File != TGSI_FILE_CONSTANT)
1993 assert(!src->Register.Indirect);
1994
1995 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1996
1997 c = tgsi_util_get_full_src_register_swizzle(src, chan);
1998 switch (c) {
1999 case TGSI_SWIZZLE_X:
2000 case TGSI_SWIZZLE_Y:
2001 case TGSI_SWIZZLE_Z:
2002 case TGSI_SWIZZLE_W:
2003 switch (src->Register.File) {
2004 case TGSI_FILE_INPUT:
2005 r = &pc->attr[src->Register.Index * 4 + c];
2006 break;
2007 case TGSI_FILE_TEMPORARY:
2008 r = &pc->temp[src->Register.Index * 4 + c];
2009 break;
2010 case TGSI_FILE_CONSTANT:
2011 if (!src->Register.Indirect) {
2012 r = &pc->param[src->Register.Index * 4 + c];
2013 break;
2014 }
2015 /* Indicate indirection by setting r->acc < 0 and
2016 * use the index field to select the address reg.
2017 */
2018 r = reg_instance(pc, NULL);
2019 swz = tgsi_util_get_src_register_swizzle(
2020 &src->Indirect, 0);
2021 ctor_reg(r, P_CONST,
2022 src->Indirect.Index * 4 + swz,
2023 src->Register.Index * 4 + c);
2024 r->acc = -1;
2025 break;
2026 case TGSI_FILE_IMMEDIATE:
2027 r = &pc->immd[src->Register.Index * 4 + c];
2028 break;
2029 case TGSI_FILE_SAMPLER:
2030 return NULL;
2031 case TGSI_FILE_ADDRESS:
2032 r = pc->addr[src->Register.Index * 4 + c];
2033 assert(r);
2034 break;
2035 default:
2036 assert(0);
2037 break;
2038 }
2039 break;
2040 default:
2041 assert(0);
2042 break;
2043 }
2044
2045 cvn = (mod & NV50_MOD_I32) ? CVT_S32_S32 : CVT_F32_F32;
2046
2047 switch (sgn) {
2048 case TGSI_UTIL_SIGN_CLEAR:
2049 r->mod = NV50_MOD_ABS;
2050 break;
2051 case TGSI_UTIL_SIGN_SET:
2052 r->mod = NV50_MOD_NEG_ABS;
2053 break;
2054 case TGSI_UTIL_SIGN_TOGGLE:
2055 r->mod = NV50_MOD_NEG;
2056 break;
2057 default:
2058 assert(!r->mod && sgn == TGSI_UTIL_SIGN_KEEP);
2059 break;
2060 }
2061
2062 if ((r->mod & mod) != r->mod) {
2063 temp = temp_temp(pc);
2064 emit_cvt(pc, temp, r, -1, cvn);
2065 r->mod = 0;
2066 r = temp;
2067 } else
2068 r->mod |= mod & NV50_MOD_I32;
2069
2070 assert(r);
2071 if (r->acc >= 0 && r != temp)
2072 return reg_instance(pc, r); /* will clear r->mod */
2073 return r;
2074 }
2075
2076 /* return TRUE for ops that produce only a single result */
2077 static boolean
2078 is_scalar_op(unsigned op)
2079 {
2080 switch (op) {
2081 case TGSI_OPCODE_COS:
2082 case TGSI_OPCODE_DP2:
2083 case TGSI_OPCODE_DP3:
2084 case TGSI_OPCODE_DP4:
2085 case TGSI_OPCODE_DPH:
2086 case TGSI_OPCODE_EX2:
2087 case TGSI_OPCODE_LG2:
2088 case TGSI_OPCODE_POW:
2089 case TGSI_OPCODE_RCP:
2090 case TGSI_OPCODE_RSQ:
2091 case TGSI_OPCODE_SIN:
2092 /*
2093 case TGSI_OPCODE_KIL:
2094 case TGSI_OPCODE_LIT:
2095 case TGSI_OPCODE_SCS:
2096 */
2097 return TRUE;
2098 default:
2099 return FALSE;
2100 }
2101 }
2102
2103 /* Returns a bitmask indicating which dst components depend
2104 * on source s, component c (reverse of nv50_tgsi_src_mask).
2105 */
2106 static unsigned
2107 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2108 {
2109 if (is_scalar_op(op))
2110 return 0x1;
2111
2112 switch (op) {
2113 case TGSI_OPCODE_DST:
2114 return (1 << c) & (s ? 0xa : 0x6);
2115 case TGSI_OPCODE_XPD:
2116 switch (c) {
2117 case 0: return 0x6;
2118 case 1: return 0x5;
2119 case 2: return 0x3;
2120 case 3: return 0x0;
2121 default:
2122 assert(0);
2123 return 0x0;
2124 }
2125 case TGSI_OPCODE_EXP:
2126 case TGSI_OPCODE_LOG:
2127 case TGSI_OPCODE_LIT:
2128 case TGSI_OPCODE_SCS:
2129 case TGSI_OPCODE_TEX:
2130 case TGSI_OPCODE_TXB:
2131 case TGSI_OPCODE_TXL:
2132 case TGSI_OPCODE_TXP:
2133 /* these take care of dangerous swizzles themselves */
2134 return 0x0;
2135 case TGSI_OPCODE_IF:
2136 case TGSI_OPCODE_KIL:
2137 /* don't call this function for these ops */
2138 assert(0);
2139 return 0;
2140 default:
2141 /* linear vector instruction */
2142 return (1 << c);
2143 }
2144 }
2145
2146 static INLINE boolean
2147 has_pred(struct nv50_program_exec *e, unsigned cc)
2148 {
2149 if (!is_long(e) || is_immd(e))
2150 return FALSE;
2151 return ((e->inst[1] & 0x780) == (cc << 7));
2152 }
2153
2154 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2155 * join_at ENDIF
2156 * @p0.eq bra ENDIF
2157 * single_op
2158 * ENDIF: nop.join
2159 */
2160 static boolean
2161 nv50_kill_branch(struct nv50_pc *pc)
2162 {
2163 int lvl = pc->if_lvl;
2164
2165 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2166 return FALSE;
2167 if (is_immd(pc->p->exec_tail))
2168 return FALSE;
2169
2170 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2171 * reg may no longer be valid, since we currently always use $p0
2172 */
2173 if (has_pred(pc->if_insn[lvl], 0xf))
2174 return FALSE;
2175 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2176
2177 /* We'll use the exec allocated for JOIN_AT (we can't easily
2178 * access nv50_program_exec's prev).
2179 */
2180 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2181
2182 *pc->if_join[lvl] = *pc->p->exec_tail;
2183
2184 FREE(pc->if_insn[lvl]);
2185 FREE(pc->p->exec_tail);
2186
2187 pc->p->exec_tail = pc->if_join[lvl];
2188 pc->p->exec_tail->next = NULL;
2189 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2190
2191 return TRUE;
2192 }
2193
2194 static void
2195 nv50_fp_move_results(struct nv50_pc *pc)
2196 {
2197 struct nv50_reg reg;
2198 unsigned i;
2199
2200 ctor_reg(&reg, P_TEMP, -1, -1);
2201
2202 for (i = 0; i < pc->result_nr * 4; ++i) {
2203 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2204 continue;
2205 if (pc->result[i].rhw != pc->result[i].hw) {
2206 reg.hw = pc->result[i].rhw;
2207 emit_mov(pc, &reg, &pc->result[i]);
2208 }
2209 }
2210 }
2211
2212 static boolean
2213 nv50_program_tx_insn(struct nv50_pc *pc,
2214 const struct tgsi_full_instruction *inst)
2215 {
2216 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2217 unsigned mask, sat, unit;
2218 int i, c;
2219
2220 mask = inst->Dst[0].Register.WriteMask;
2221 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2222
2223 memset(src, 0, sizeof(src));
2224
2225 for (c = 0; c < 4; c++) {
2226 if ((mask & (1 << c)) && !pc->r_dst[c])
2227 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2228 else
2229 dst[c] = pc->r_dst[c];
2230 rdst[c] = dst[c];
2231 }
2232
2233 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2234 const struct tgsi_full_src_register *fs = &inst->Src[i];
2235 unsigned src_mask;
2236 int mod_supp;
2237
2238 src_mask = nv50_tgsi_src_mask(inst, i);
2239 mod_supp = get_supported_mods(inst, i);
2240
2241 if (fs->Register.File == TGSI_FILE_SAMPLER)
2242 unit = fs->Register.Index;
2243
2244 for (c = 0; c < 4; c++)
2245 if (src_mask & (1 << c))
2246 src[i][c] = tgsi_src(pc, c, fs, mod_supp);
2247 }
2248
2249 brdc = temp = pc->r_brdc;
2250 if (brdc && brdc->type != P_TEMP) {
2251 temp = temp_temp(pc);
2252 if (sat)
2253 brdc = temp;
2254 } else
2255 if (sat) {
2256 for (c = 0; c < 4; c++) {
2257 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2258 continue;
2259 /* rdst[c] = dst[c]; */ /* done above */
2260 dst[c] = temp_temp(pc);
2261 }
2262 }
2263
2264 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2265
2266 switch (inst->Instruction.Opcode) {
2267 case TGSI_OPCODE_ABS:
2268 for (c = 0; c < 4; c++) {
2269 if (!(mask & (1 << c)))
2270 continue;
2271 emit_cvt(pc, dst[c], src[0][c], -1,
2272 CVT_ABS | CVT_F32_F32);
2273 }
2274 break;
2275 case TGSI_OPCODE_ADD:
2276 for (c = 0; c < 4; c++) {
2277 if (!(mask & (1 << c)))
2278 continue;
2279 emit_add(pc, dst[c], src[0][c], src[1][c]);
2280 }
2281 break;
2282 case TGSI_OPCODE_AND:
2283 case TGSI_OPCODE_XOR:
2284 case TGSI_OPCODE_OR:
2285 for (c = 0; c < 4; c++) {
2286 if (!(mask & (1 << c)))
2287 continue;
2288 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2289 inst->Instruction.Opcode);
2290 }
2291 break;
2292 case TGSI_OPCODE_ARL:
2293 assert(src[0][0]);
2294 temp = temp_temp(pc);
2295 emit_cvt(pc, temp, src[0][0], -1, CVT_FLOOR | CVT_S32_F32);
2296 emit_arl(pc, dst[0], temp, 4);
2297 break;
2298 case TGSI_OPCODE_BGNLOOP:
2299 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2300 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2301 terminate_mbb(pc);
2302 break;
2303 case TGSI_OPCODE_BGNSUB:
2304 assert(!pc->in_subroutine);
2305 pc->in_subroutine = TRUE;
2306 /* probably not necessary, but align to 8 byte boundary */
2307 if (!is_long(pc->p->exec_tail))
2308 convert_to_long(pc, pc->p->exec_tail);
2309 break;
2310 case TGSI_OPCODE_BRK:
2311 assert(pc->loop_lvl > 0);
2312 emit_break(pc, -1, 0);
2313 break;
2314 case TGSI_OPCODE_CAL:
2315 assert(inst->Label.Label < pc->insn_nr);
2316 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2317 /* replaced by actual offset in nv50_program_fixup_insns */
2318 break;
2319 case TGSI_OPCODE_CEIL:
2320 for (c = 0; c < 4; c++) {
2321 if (!(mask & (1 << c)))
2322 continue;
2323 emit_cvt(pc, dst[c], src[0][c], -1,
2324 CVT_CEIL | CVT_F32_F32 | CVT_RI);
2325 }
2326 break;
2327 case TGSI_OPCODE_CMP:
2328 pc->allow32 = FALSE;
2329 for (c = 0; c < 4; c++) {
2330 if (!(mask & (1 << c)))
2331 continue;
2332 emit_cvt(pc, NULL, src[0][c], 1, CVT_F32_F32);
2333 emit_mov(pc, dst[c], src[1][c]);
2334 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2335 emit_mov(pc, dst[c], src[2][c]);
2336 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2337 }
2338 break;
2339 case TGSI_OPCODE_CONT:
2340 assert(pc->loop_lvl > 0);
2341 emit_branch(pc, -1, 0)->param.index =
2342 pc->loop_pos[pc->loop_lvl - 1];
2343 break;
2344 case TGSI_OPCODE_COS:
2345 if (mask & 8) {
2346 emit_precossin(pc, temp, src[0][3]);
2347 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2348 if (!(mask &= 7))
2349 break;
2350 if (temp == dst[3])
2351 temp = brdc = temp_temp(pc);
2352 }
2353 emit_precossin(pc, temp, src[0][0]);
2354 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2355 break;
2356 case TGSI_OPCODE_DDX:
2357 for (c = 0; c < 4; c++) {
2358 if (!(mask & (1 << c)))
2359 continue;
2360 emit_ddx(pc, dst[c], src[0][c]);
2361 }
2362 break;
2363 case TGSI_OPCODE_DDY:
2364 for (c = 0; c < 4; c++) {
2365 if (!(mask & (1 << c)))
2366 continue;
2367 emit_ddy(pc, dst[c], src[0][c]);
2368 }
2369 break;
2370 case TGSI_OPCODE_DP3:
2371 emit_mul(pc, temp, src[0][0], src[1][0]);
2372 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2373 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2374 break;
2375 case TGSI_OPCODE_DP4:
2376 emit_mul(pc, temp, src[0][0], src[1][0]);
2377 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2378 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2379 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2380 break;
2381 case TGSI_OPCODE_DPH:
2382 emit_mul(pc, temp, src[0][0], src[1][0]);
2383 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2384 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2385 emit_add(pc, brdc, src[1][3], temp);
2386 break;
2387 case TGSI_OPCODE_DST:
2388 if (mask & (1 << 1))
2389 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2390 if (mask & (1 << 2))
2391 emit_mov(pc, dst[2], src[0][2]);
2392 if (mask & (1 << 3))
2393 emit_mov(pc, dst[3], src[1][3]);
2394 if (mask & (1 << 0))
2395 emit_mov_immdval(pc, dst[0], 1.0f);
2396 break;
2397 case TGSI_OPCODE_ELSE:
2398 emit_branch(pc, -1, 0);
2399 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2400 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2401 terminate_mbb(pc);
2402 break;
2403 case TGSI_OPCODE_ENDIF:
2404 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2405
2406 /* try to replace branch over 1 insn with a predicated insn */
2407 if (nv50_kill_branch(pc) == TRUE)
2408 break;
2409
2410 if (pc->if_join[pc->if_lvl]) {
2411 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2412 pc->if_join[pc->if_lvl] = NULL;
2413 }
2414 terminate_mbb(pc);
2415 /* emit a NOP as join point, we could set it on the next
2416 * one, but would have to make sure it is long and !immd
2417 */
2418 JOIN_ON(emit_nop(pc));
2419 break;
2420 case TGSI_OPCODE_ENDLOOP:
2421 emit_branch(pc, -1, 0)->param.index =
2422 pc->loop_pos[--pc->loop_lvl];
2423 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2424 terminate_mbb(pc);
2425 break;
2426 case TGSI_OPCODE_ENDSUB:
2427 assert(pc->in_subroutine);
2428 pc->in_subroutine = FALSE;
2429 break;
2430 case TGSI_OPCODE_EX2:
2431 emit_preex2(pc, temp, src[0][0]);
2432 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2433 break;
2434 case TGSI_OPCODE_EXP:
2435 {
2436 struct nv50_reg *t[2];
2437
2438 assert(!temp);
2439 t[0] = temp_temp(pc);
2440 t[1] = temp_temp(pc);
2441
2442 if (mask & 0x6)
2443 emit_mov(pc, t[0], src[0][0]);
2444 if (mask & 0x3)
2445 emit_flr(pc, t[1], src[0][0]);
2446
2447 if (mask & (1 << 1))
2448 emit_sub(pc, dst[1], t[0], t[1]);
2449 if (mask & (1 << 0)) {
2450 emit_preex2(pc, t[1], t[1]);
2451 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2452 }
2453 if (mask & (1 << 2)) {
2454 emit_preex2(pc, t[0], t[0]);
2455 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2456 }
2457 if (mask & (1 << 3))
2458 emit_mov_immdval(pc, dst[3], 1.0f);
2459 }
2460 break;
2461 case TGSI_OPCODE_F2I:
2462 for (c = 0; c < 4; c++) {
2463 if (!(mask & (1 << c)))
2464 continue;
2465 emit_cvt(pc, dst[c], src[0][c], -1,
2466 CVT_TRUNC | CVT_S32_F32);
2467 }
2468 break;
2469 case TGSI_OPCODE_F2U:
2470 for (c = 0; c < 4; c++) {
2471 if (!(mask & (1 << c)))
2472 continue;
2473 emit_cvt(pc, dst[c], src[0][c], -1,
2474 CVT_TRUNC | CVT_U32_F32);
2475 }
2476 break;
2477 case TGSI_OPCODE_FLR:
2478 for (c = 0; c < 4; c++) {
2479 if (!(mask & (1 << c)))
2480 continue;
2481 emit_flr(pc, dst[c], src[0][c]);
2482 }
2483 break;
2484 case TGSI_OPCODE_FRC:
2485 temp = temp_temp(pc);
2486 for (c = 0; c < 4; c++) {
2487 if (!(mask & (1 << c)))
2488 continue;
2489 emit_flr(pc, temp, src[0][c]);
2490 emit_sub(pc, dst[c], src[0][c], temp);
2491 }
2492 break;
2493 case TGSI_OPCODE_I2F:
2494 for (c = 0; c < 4; c++) {
2495 if (!(mask & (1 << c)))
2496 continue;
2497 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_S32);
2498 }
2499 break;
2500 case TGSI_OPCODE_IF:
2501 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2502 emit_cvt(pc, NULL, src[0][0], 0, CVT_ABS | CVT_F32_F32);
2503 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2504 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2505 terminate_mbb(pc);
2506 break;
2507 case TGSI_OPCODE_INEG:
2508 for (c = 0; c < 4; c++) {
2509 if (!(mask & (1 << c)))
2510 continue;
2511 emit_cvt(pc, dst[c], src[0][c], -1,
2512 CVT_S32_S32 | CVT_NEG);
2513 }
2514 break;
2515 case TGSI_OPCODE_KIL:
2516 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2517 emit_kil(pc, src[0][0]);
2518 emit_kil(pc, src[0][1]);
2519 emit_kil(pc, src[0][2]);
2520 emit_kil(pc, src[0][3]);
2521 break;
2522 case TGSI_OPCODE_KILP:
2523 emit_kil(pc, NULL);
2524 break;
2525 case TGSI_OPCODE_LIT:
2526 emit_lit(pc, &dst[0], mask, &src[0][0]);
2527 break;
2528 case TGSI_OPCODE_LG2:
2529 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2530 break;
2531 case TGSI_OPCODE_LOG:
2532 {
2533 struct nv50_reg *t[2];
2534
2535 t[0] = temp_temp(pc);
2536 if (mask & (1 << 1))
2537 t[1] = temp_temp(pc);
2538 else
2539 t[1] = t[0];
2540
2541 emit_cvt(pc, t[0], src[0][0], -1, CVT_ABS | CVT_F32_F32);
2542 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2543 if (mask & (1 << 2))
2544 emit_mov(pc, dst[2], t[1]);
2545 emit_flr(pc, t[1], t[1]);
2546 if (mask & (1 << 0))
2547 emit_mov(pc, dst[0], t[1]);
2548 if (mask & (1 << 1)) {
2549 t[1]->mod = NV50_MOD_NEG;
2550 emit_preex2(pc, t[1], t[1]);
2551 t[1]->mod = 0;
2552 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2553 emit_mul(pc, dst[1], t[0], t[1]);
2554 }
2555 if (mask & (1 << 3))
2556 emit_mov_immdval(pc, dst[3], 1.0f);
2557 }
2558 break;
2559 case TGSI_OPCODE_LRP:
2560 temp = temp_temp(pc);
2561 for (c = 0; c < 4; c++) {
2562 if (!(mask & (1 << c)))
2563 continue;
2564 emit_sub(pc, temp, src[1][c], src[2][c]);
2565 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2566 }
2567 break;
2568 case TGSI_OPCODE_MAD:
2569 for (c = 0; c < 4; c++) {
2570 if (!(mask & (1 << c)))
2571 continue;
2572 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2573 }
2574 break;
2575 case TGSI_OPCODE_MAX:
2576 for (c = 0; c < 4; c++) {
2577 if (!(mask & (1 << c)))
2578 continue;
2579 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
2580 }
2581 break;
2582 case TGSI_OPCODE_MIN:
2583 for (c = 0; c < 4; c++) {
2584 if (!(mask & (1 << c)))
2585 continue;
2586 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
2587 }
2588 break;
2589 case TGSI_OPCODE_MOV:
2590 for (c = 0; c < 4; c++) {
2591 if (!(mask & (1 << c)))
2592 continue;
2593 emit_mov(pc, dst[c], src[0][c]);
2594 }
2595 break;
2596 case TGSI_OPCODE_MUL:
2597 for (c = 0; c < 4; c++) {
2598 if (!(mask & (1 << c)))
2599 continue;
2600 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2601 }
2602 break;
2603 case TGSI_OPCODE_POW:
2604 emit_pow(pc, brdc, src[0][0], src[1][0]);
2605 break;
2606 case TGSI_OPCODE_RCP:
2607 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2608 break;
2609 case TGSI_OPCODE_RET:
2610 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2611 nv50_fp_move_results(pc);
2612 emit_ret(pc, -1, 0);
2613 break;
2614 case TGSI_OPCODE_RSQ:
2615 src[0][0]->mod |= NV50_MOD_ABS;
2616 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2617 break;
2618 case TGSI_OPCODE_SCS:
2619 temp = temp_temp(pc);
2620 if (mask & 3)
2621 emit_precossin(pc, temp, src[0][0]);
2622 if (mask & (1 << 0))
2623 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
2624 if (mask & (1 << 1))
2625 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
2626 if (mask & (1 << 2))
2627 emit_mov_immdval(pc, dst[2], 0.0);
2628 if (mask & (1 << 3))
2629 emit_mov_immdval(pc, dst[3], 1.0);
2630 break;
2631 case TGSI_OPCODE_SHL:
2632 case TGSI_OPCODE_ISHR:
2633 case TGSI_OPCODE_USHR:
2634 for (c = 0; c < 4; c++) {
2635 if (!(mask & (1 << c)))
2636 continue;
2637 emit_shift(pc, dst[c], src[0][c], src[1][c],
2638 inst->Instruction.Opcode);
2639 }
2640 break;
2641 case TGSI_OPCODE_SIN:
2642 if (mask & 8) {
2643 emit_precossin(pc, temp, src[0][3]);
2644 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
2645 if (!(mask &= 7))
2646 break;
2647 if (temp == dst[3])
2648 temp = brdc = temp_temp(pc);
2649 }
2650 emit_precossin(pc, temp, src[0][0]);
2651 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
2652 break;
2653 case TGSI_OPCODE_SLT:
2654 case TGSI_OPCODE_SGE:
2655 case TGSI_OPCODE_SEQ:
2656 case TGSI_OPCODE_SGT:
2657 case TGSI_OPCODE_SLE:
2658 case TGSI_OPCODE_SNE:
2659 case TGSI_OPCODE_ISLT:
2660 case TGSI_OPCODE_ISGE:
2661 case TGSI_OPCODE_USEQ:
2662 case TGSI_OPCODE_USGE:
2663 case TGSI_OPCODE_USLT:
2664 case TGSI_OPCODE_USNE:
2665 {
2666 uint8_t cc, ty;
2667
2668 map_tgsi_setop_hw(inst->Instruction.Opcode, &cc, &ty);
2669
2670 for (c = 0; c < 4; c++) {
2671 if (!(mask & (1 << c)))
2672 continue;
2673 emit_set(pc, cc, dst[c], -1, src[0][c], src[1][c], ty);
2674 }
2675 }
2676 break;
2677 case TGSI_OPCODE_SUB:
2678 for (c = 0; c < 4; c++) {
2679 if (!(mask & (1 << c)))
2680 continue;
2681 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2682 }
2683 break;
2684 case TGSI_OPCODE_TEX:
2685 emit_tex(pc, dst, mask, src[0], unit,
2686 inst->Texture.Texture, FALSE, 0);
2687 break;
2688 case TGSI_OPCODE_TXB:
2689 emit_tex(pc, dst, mask, src[0], unit,
2690 inst->Texture.Texture, FALSE, -1);
2691 break;
2692 case TGSI_OPCODE_TXL:
2693 emit_tex(pc, dst, mask, src[0], unit,
2694 inst->Texture.Texture, FALSE, 1);
2695 break;
2696 case TGSI_OPCODE_TXP:
2697 emit_tex(pc, dst, mask, src[0], unit,
2698 inst->Texture.Texture, TRUE, 0);
2699 break;
2700 case TGSI_OPCODE_TRUNC:
2701 for (c = 0; c < 4; c++) {
2702 if (!(mask & (1 << c)))
2703 continue;
2704 emit_cvt(pc, dst[c], src[0][c], -1,
2705 CVT_TRUNC | CVT_F32_F32 | CVT_RI);
2706 }
2707 break;
2708 case TGSI_OPCODE_U2F:
2709 for (c = 0; c < 4; c++) {
2710 if (!(mask & (1 << c)))
2711 continue;
2712 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_U32);
2713 }
2714 break;
2715 case TGSI_OPCODE_XPD:
2716 temp = temp_temp(pc);
2717 if (mask & (1 << 0)) {
2718 emit_mul(pc, temp, src[0][2], src[1][1]);
2719 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2720 }
2721 if (mask & (1 << 1)) {
2722 emit_mul(pc, temp, src[0][0], src[1][2]);
2723 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2724 }
2725 if (mask & (1 << 2)) {
2726 emit_mul(pc, temp, src[0][1], src[1][0]);
2727 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2728 }
2729 if (mask & (1 << 3))
2730 emit_mov_immdval(pc, dst[3], 1.0);
2731 break;
2732 case TGSI_OPCODE_END:
2733 if (pc->p->type == PIPE_SHADER_FRAGMENT)
2734 nv50_fp_move_results(pc);
2735
2736 /* last insn must be long so it can have the exit bit set */
2737 if (!is_long(pc->p->exec_tail))
2738 convert_to_long(pc, pc->p->exec_tail);
2739 else
2740 if (is_immd(pc->p->exec_tail) || is_join(pc->p->exec_tail))
2741 emit_nop(pc);
2742
2743 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
2744 break;
2745 default:
2746 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2747 return FALSE;
2748 }
2749
2750 if (brdc) {
2751 if (sat)
2752 emit_sat(pc, brdc, brdc);
2753 for (c = 0; c < 4; c++)
2754 if ((mask & (1 << c)) && dst[c] != brdc)
2755 emit_mov(pc, dst[c], brdc);
2756 } else
2757 if (sat) {
2758 for (c = 0; c < 4; c++) {
2759 if (!(mask & (1 << c)))
2760 continue;
2761 /* In this case we saturate later, and dst[c] won't
2762 * be another temp_temp (and thus lost), since rdst
2763 * already is TEMP (see above). */
2764 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2765 continue;
2766 emit_sat(pc, rdst[c], dst[c]);
2767 }
2768 }
2769
2770 kill_temp_temp(pc);
2771 pc->reg_instance_nr = 0;
2772
2773 return TRUE;
2774 }
2775
2776 static void
2777 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2778 {
2779 struct nv50_reg *reg = NULL;
2780 const struct tgsi_full_src_register *src;
2781 const struct tgsi_dst_register *dst;
2782 unsigned i, c, k, mask;
2783
2784 dst = &insn->Dst[0].Register;
2785 mask = dst->WriteMask;
2786
2787 if (dst->File == TGSI_FILE_TEMPORARY)
2788 reg = pc->temp;
2789 else
2790 if (dst->File == TGSI_FILE_OUTPUT) {
2791 reg = pc->result;
2792
2793 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
2794 dst->Index == pc->edgeflag_out &&
2795 insn->Src[0].Register.File == TGSI_FILE_INPUT)
2796 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
2797 }
2798
2799 if (reg) {
2800 for (c = 0; c < 4; c++) {
2801 if (!(mask & (1 << c)))
2802 continue;
2803 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2804 }
2805 }
2806
2807 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2808 src = &insn->Src[i];
2809
2810 if (src->Register.File == TGSI_FILE_TEMPORARY)
2811 reg = pc->temp;
2812 else
2813 if (src->Register.File == TGSI_FILE_INPUT)
2814 reg = pc->attr;
2815 else
2816 continue;
2817
2818 mask = nv50_tgsi_src_mask(insn, i);
2819
2820 for (c = 0; c < 4; c++) {
2821 if (!(mask & (1 << c)))
2822 continue;
2823 k = tgsi_util_get_full_src_register_swizzle(src, c);
2824
2825 reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
2826 }
2827 }
2828 }
2829
2830 /* Returns a bitmask indicating which dst components need to be
2831 * written to temporaries first to avoid 'corrupting' sources.
2832 *
2833 * m[i] (out) indicate component to write in the i-th position
2834 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2835 */
2836 static unsigned
2837 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2838 {
2839 unsigned i, c, x, unsafe;
2840
2841 for (c = 0; c < 4; c++)
2842 m[c] = c;
2843
2844 /* Swap as long as a dst component written earlier is depended on
2845 * by one written later, but the next one isn't depended on by it.
2846 */
2847 for (c = 0; c < 3; c++) {
2848 if (rdep[m[c + 1]] & (1 << m[c]))
2849 continue; /* if next one is depended on by us */
2850 for (i = c + 1; i < 4; i++)
2851 /* if we are depended on by a later one */
2852 if (rdep[m[c]] & (1 << m[i]))
2853 break;
2854 if (i == 4)
2855 continue;
2856 /* now, swap */
2857 x = m[c];
2858 m[c] = m[c + 1];
2859 m[c + 1] = x;
2860
2861 /* restart */
2862 c = 0;
2863 }
2864
2865 /* mark dependencies that could not be resolved by reordering */
2866 for (i = 0; i < 3; ++i)
2867 for (c = i + 1; c < 4; ++c)
2868 if (rdep[m[i]] & (1 << m[c]))
2869 unsafe |= (1 << i);
2870
2871 /* NOTE: $unsafe is with respect to order, not component */
2872 return unsafe;
2873 }
2874
2875 /* Select a suitable dst register for broadcasting scalar results,
2876 * or return NULL if we have to allocate an extra TEMP.
2877 *
2878 * If e.g. only 1 component is written, we may also emit the final
2879 * result to a write-only register.
2880 */
2881 static struct nv50_reg *
2882 tgsi_broadcast_dst(struct nv50_pc *pc,
2883 const struct tgsi_full_dst_register *fd, unsigned mask)
2884 {
2885 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
2886 int c = ffs(~mask & fd->Register.WriteMask);
2887 if (c)
2888 return tgsi_dst(pc, c - 1, fd);
2889 } else {
2890 int c = ffs(fd->Register.WriteMask) - 1;
2891 if ((1 << c) == fd->Register.WriteMask)
2892 return tgsi_dst(pc, c, fd);
2893 }
2894
2895 return NULL;
2896 }
2897
2898 /* Scan source swizzles and return a bitmask indicating dst regs that
2899 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2900 */
2901 static unsigned
2902 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2903 unsigned rdep[4])
2904 {
2905 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
2906 const struct tgsi_full_src_register *fs;
2907 unsigned i, deqs = 0;
2908
2909 for (i = 0; i < 4; ++i)
2910 rdep[i] = 0;
2911
2912 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2913 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2914 int ms = get_supported_mods(insn, i);
2915
2916 fs = &insn->Src[i];
2917 if (fs->Register.File != fd->Register.File ||
2918 fs->Register.Index != fd->Register.Index)
2919 continue;
2920
2921 for (chn = 0; chn < 4; ++chn) {
2922 unsigned s, c;
2923
2924 if (!(mask & (1 << chn))) /* src is not read */
2925 continue;
2926 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2927 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2928
2929 if (!(fd->Register.WriteMask & (1 << c)))
2930 continue;
2931
2932 if (s == TGSI_UTIL_SIGN_TOGGLE && !(ms & NV50_MOD_NEG))
2933 continue;
2934 if (s == TGSI_UTIL_SIGN_CLEAR && !(ms & NV50_MOD_ABS))
2935 continue;
2936 if ((s == TGSI_UTIL_SIGN_SET) && ((ms & 3) != 3))
2937 continue;
2938
2939 rdep[c] |= nv50_tgsi_dst_revdep(
2940 insn->Instruction.Opcode, i, chn);
2941 deqs |= (1 << c);
2942 }
2943 }
2944
2945 return deqs;
2946 }
2947
2948 static boolean
2949 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2950 {
2951 struct tgsi_full_instruction insn = tok->FullInstruction;
2952 const struct tgsi_full_dst_register *fd;
2953 unsigned i, deqs, rdep[4], m[4];
2954
2955 fd = &tok->FullInstruction.Dst[0];
2956 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2957
2958 if (is_scalar_op(insn.Instruction.Opcode)) {
2959 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2960 if (!pc->r_brdc)
2961 pc->r_brdc = temp_temp(pc);
2962 return nv50_program_tx_insn(pc, &insn);
2963 }
2964 pc->r_brdc = NULL;
2965
2966 if (!deqs || (!rdep[0] && !rdep[1] && !rdep[2] && !rdep[3]))
2967 return nv50_program_tx_insn(pc, &insn);
2968
2969 deqs = nv50_revdep_reorder(m, rdep);
2970
2971 for (i = 0; i < 4; ++i) {
2972 assert(pc->r_dst[m[i]] == NULL);
2973
2974 insn.Dst[0].Register.WriteMask =
2975 fd->Register.WriteMask & (1 << m[i]);
2976
2977 if (!insn.Dst[0].Register.WriteMask)
2978 continue;
2979
2980 if (deqs & (1 << i))
2981 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2982
2983 if (!nv50_program_tx_insn(pc, &insn))
2984 return FALSE;
2985 }
2986
2987 for (i = 0; i < 4; i++) {
2988 struct nv50_reg *reg = pc->r_dst[i];
2989 if (!reg)
2990 continue;
2991 pc->r_dst[i] = NULL;
2992
2993 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2994 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2995 else
2996 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2997 free_temp(pc, reg);
2998 }
2999
3000 return TRUE;
3001 }
3002
3003 static void
3004 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
3005 {
3006 struct nv50_reg *iv, **ppiv;
3007 unsigned mode = pc->interp_mode[reg->index];
3008
3009 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
3010 iv = *ppiv;
3011
3012 if ((mode & INTERP_PERSPECTIVE) && !iv) {
3013 iv = *ppiv = alloc_temp(pc, NULL);
3014 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
3015
3016 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
3017 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
3018
3019 /* XXX: when loading interpolants dynamically, move these
3020 * to the program head, or make sure it can't be skipped.
3021 */
3022 }
3023
3024 emit_interp(pc, reg, iv, mode);
3025 }
3026
3027 /* The face input is always at v[255] (varying space), with a
3028 * value of 0 for back-facing, and 0xffffffff for front-facing.
3029 */
3030 static void
3031 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
3032 {
3033 struct nv50_reg *one = alloc_immd(pc, 1.0f);
3034
3035 assert(a->rhw == -1);
3036 alloc_reg(pc, a); /* do this before rhw is set */
3037 a->rhw = 255;
3038 load_interpolant(pc, a);
3039 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
3040
3041 FREE(one);
3042 }
3043
3044 static boolean
3045 nv50_program_tx_prep(struct nv50_pc *pc)
3046 {
3047 struct tgsi_parse_context tp;
3048 struct nv50_program *p = pc->p;
3049 boolean ret = FALSE;
3050 unsigned i, c, flat_nr = 0;
3051
3052 tgsi_parse_init(&tp, pc->p->pipe.tokens);
3053 while (!tgsi_parse_end_of_tokens(&tp)) {
3054 const union tgsi_full_token *tok = &tp.FullToken;
3055
3056 tgsi_parse_token(&tp);
3057 switch (tok->Token.Type) {
3058 case TGSI_TOKEN_TYPE_IMMEDIATE:
3059 {
3060 const struct tgsi_full_immediate *imm =
3061 &tp.FullToken.FullImmediate;
3062
3063 ctor_immd_4f32(pc, imm->u[0].Float,
3064 imm->u[1].Float,
3065 imm->u[2].Float,
3066 imm->u[3].Float);
3067 }
3068 break;
3069 case TGSI_TOKEN_TYPE_DECLARATION:
3070 {
3071 const struct tgsi_full_declaration *d;
3072 unsigned si, last, first, mode;
3073
3074 d = &tp.FullToken.FullDeclaration;
3075 first = d->Range.First;
3076 last = d->Range.Last;
3077
3078 switch (d->Declaration.File) {
3079 case TGSI_FILE_TEMPORARY:
3080 break;
3081 case TGSI_FILE_OUTPUT:
3082 if (!d->Declaration.Semantic ||
3083 p->type == PIPE_SHADER_FRAGMENT)
3084 break;
3085
3086 si = d->Semantic.Index;
3087 switch (d->Semantic.Name) {
3088 case TGSI_SEMANTIC_BCOLOR:
3089 p->cfg.two_side[si].hw = first;
3090 if (p->cfg.io_nr > first)
3091 p->cfg.io_nr = first;
3092 break;
3093 case TGSI_SEMANTIC_PSIZE:
3094 p->cfg.psiz = first;
3095 if (p->cfg.io_nr > first)
3096 p->cfg.io_nr = first;
3097 break;
3098 case TGSI_SEMANTIC_EDGEFLAG:
3099 pc->edgeflag_out = first;
3100 break;
3101 /*
3102 case TGSI_SEMANTIC_CLIP_DISTANCE:
3103 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3104 break;
3105 */
3106 default:
3107 break;
3108 }
3109 break;
3110 case TGSI_FILE_INPUT:
3111 {
3112 if (p->type != PIPE_SHADER_FRAGMENT)
3113 break;
3114
3115 switch (d->Declaration.Interpolate) {
3116 case TGSI_INTERPOLATE_CONSTANT:
3117 mode = INTERP_FLAT;
3118 flat_nr++;
3119 break;
3120 case TGSI_INTERPOLATE_PERSPECTIVE:
3121 mode = INTERP_PERSPECTIVE;
3122 p->cfg.regs[1] |= 0x08 << 24;
3123 break;
3124 default:
3125 mode = INTERP_LINEAR;
3126 break;
3127 }
3128 if (d->Declaration.Centroid)
3129 mode |= INTERP_CENTROID;
3130
3131 assert(last < 32);
3132 for (i = first; i <= last; i++)
3133 pc->interp_mode[i] = mode;
3134 }
3135 break;
3136 case TGSI_FILE_ADDRESS:
3137 case TGSI_FILE_CONSTANT:
3138 case TGSI_FILE_SAMPLER:
3139 break;
3140 default:
3141 NOUVEAU_ERR("bad decl file %d\n",
3142 d->Declaration.File);
3143 goto out_err;
3144 }
3145 }
3146 break;
3147 case TGSI_TOKEN_TYPE_INSTRUCTION:
3148 pc->insn_nr++;
3149 prep_inspect_insn(pc, &tok->FullInstruction);
3150 break;
3151 default:
3152 break;
3153 }
3154 }
3155
3156 if (p->type == PIPE_SHADER_VERTEX) {
3157 int rid = 0;
3158
3159 for (i = 0; i < pc->attr_nr * 4; ++i) {
3160 if (pc->attr[i].acc) {
3161 pc->attr[i].hw = rid++;
3162 p->cfg.attr[i / 32] |= 1 << (i % 32);
3163 }
3164 }
3165
3166 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3167 p->cfg.io[i].hw = rid;
3168 p->cfg.io[i].id = i;
3169
3170 for (c = 0; c < 4; ++c) {
3171 int n = i * 4 + c;
3172 if (!pc->result[n].acc)
3173 continue;
3174 pc->result[n].hw = rid++;
3175 p->cfg.io[i].mask |= 1 << c;
3176 }
3177 }
3178
3179 for (c = 0; c < 2; ++c)
3180 if (p->cfg.two_side[c].hw < 0x40)
3181 p->cfg.two_side[c] = p->cfg.io[
3182 p->cfg.two_side[c].hw];
3183
3184 if (p->cfg.psiz < 0x40)
3185 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
3186 } else
3187 if (p->type == PIPE_SHADER_FRAGMENT) {
3188 int rid, aid;
3189 unsigned n = 0, m = pc->attr_nr - flat_nr;
3190
3191 pc->allow32 = TRUE;
3192
3193 int base = (TGSI_SEMANTIC_POSITION ==
3194 p->info.input_semantic_name[0]) ? 0 : 1;
3195
3196 /* non-flat interpolants have to be mapped to
3197 * the lower hardware IDs, so sort them:
3198 */
3199 for (i = 0; i < pc->attr_nr; i++) {
3200 if (pc->interp_mode[i] == INTERP_FLAT)
3201 p->cfg.io[m++].id = i;
3202 else {
3203 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3204 p->cfg.io[n].linear = TRUE;
3205 p->cfg.io[n++].id = i;
3206 }
3207 }
3208
3209 if (!base) /* set w-coordinate mask from perspective interp */
3210 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
3211
3212 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
3213 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
3214
3215 for (n = 0; n < pc->attr_nr; ++n) {
3216 p->cfg.io[n].hw = rid = aid;
3217 i = p->cfg.io[n].id;
3218
3219 if (p->info.input_semantic_name[n] ==
3220 TGSI_SEMANTIC_FACE) {
3221 load_frontfacing(pc, &pc->attr[i * 4]);
3222 continue;
3223 }
3224
3225 for (c = 0; c < 4; ++c) {
3226 if (!pc->attr[i * 4 + c].acc)
3227 continue;
3228 pc->attr[i * 4 + c].rhw = rid++;
3229 p->cfg.io[n].mask |= 1 << c;
3230
3231 load_interpolant(pc, &pc->attr[i * 4 + c]);
3232 }
3233 aid += popcnt4(p->cfg.io[n].mask);
3234 }
3235
3236 if (!base)
3237 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
3238
3239 m = popcnt4(p->cfg.regs[1] >> 24);
3240
3241 /* set count of non-position inputs and of non-flat
3242 * non-position inputs for FP_INTERPOLANT_CTRL
3243 */
3244 p->cfg.regs[1] |= aid - m;
3245
3246 if (flat_nr) {
3247 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
3248 p->cfg.regs[1] |= (i - m) << 16;
3249 } else
3250 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3251
3252 /* mark color semantic for light-twoside */
3253 n = 0x40;
3254 for (i = 0; i < pc->attr_nr; i++) {
3255 ubyte si, sn;
3256
3257 sn = p->info.input_semantic_name[p->cfg.io[i].id];
3258 si = p->info.input_semantic_index[p->cfg.io[i].id];
3259
3260 if (sn == TGSI_SEMANTIC_COLOR) {
3261 p->cfg.two_side[si] = p->cfg.io[i];
3262
3263 /* increase colour count */
3264 p->cfg.regs[0] += popcnt4(
3265 p->cfg.two_side[si].mask) << 16;
3266
3267 n = MIN2(n, p->cfg.io[i].hw - m);
3268 }
3269 }
3270 if (n < 0x40)
3271 p->cfg.regs[0] += n;
3272
3273 /* Initialize FP results:
3274 * FragDepth is always first TGSI and last hw output
3275 */
3276 i = p->info.writes_z ? 4 : 0;
3277 for (rid = 0; i < pc->result_nr * 4; i++)
3278 pc->result[i].rhw = rid++;
3279 if (p->info.writes_z)
3280 pc->result[2].rhw = rid;
3281
3282 p->cfg.high_result = rid;
3283
3284 /* separate/different colour results for MRTs ? */
3285 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3286 p->cfg.regs[2] |= 1;
3287 }
3288
3289 if (pc->immd_nr) {
3290 int rid = 0;
3291
3292 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3293 if (!pc->immd)
3294 goto out_err;
3295
3296 for (i = 0; i < pc->immd_nr; i++) {
3297 for (c = 0; c < 4; c++, rid++)
3298 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3299 }
3300 }
3301
3302 ret = TRUE;
3303 out_err:
3304 if (pc->iv_p)
3305 free_temp(pc, pc->iv_p);
3306 if (pc->iv_c)
3307 free_temp(pc, pc->iv_c);
3308
3309 tgsi_parse_free(&tp);
3310 return ret;
3311 }
3312
3313 static void
3314 free_nv50_pc(struct nv50_pc *pc)
3315 {
3316 if (pc->immd)
3317 FREE(pc->immd);
3318 if (pc->param)
3319 FREE(pc->param);
3320 if (pc->result)
3321 FREE(pc->result);
3322 if (pc->attr)
3323 FREE(pc->attr);
3324 if (pc->temp)
3325 FREE(pc->temp);
3326
3327 FREE(pc);
3328 }
3329
3330 static boolean
3331 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3332 {
3333 int i, c;
3334 unsigned rtype[2] = { P_ATTR, P_RESULT };
3335
3336 pc->p = p;
3337 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3338 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3339 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3340 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3341 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3342 assert(pc->addr_nr <= 2);
3343
3344 p->cfg.high_temp = 4;
3345
3346 p->cfg.two_side[0].hw = 0x40;
3347 p->cfg.two_side[1].hw = 0x40;
3348
3349 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3350
3351 switch (p->type) {
3352 case PIPE_SHADER_VERTEX:
3353 p->cfg.psiz = 0x40;
3354 p->cfg.clpd = 0x40;
3355 p->cfg.io_nr = pc->result_nr;
3356 break;
3357 case PIPE_SHADER_FRAGMENT:
3358 rtype[0] = rtype[1] = P_TEMP;
3359
3360 p->cfg.regs[0] = 0x01000004;
3361 p->cfg.io_nr = pc->attr_nr;
3362
3363 if (p->info.writes_z) {
3364 p->cfg.regs[2] |= 0x00000100;
3365 p->cfg.regs[3] |= 0x00000011;
3366 }
3367 if (p->info.uses_kill)
3368 p->cfg.regs[2] |= 0x00100000;
3369 break;
3370 }
3371
3372 if (pc->temp_nr) {
3373 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3374 if (!pc->temp)
3375 return FALSE;
3376
3377 for (i = 0; i < pc->temp_nr * 4; ++i)
3378 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3379 }
3380
3381 if (pc->attr_nr) {
3382 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3383 if (!pc->attr)
3384 return FALSE;
3385
3386 for (i = 0; i < pc->attr_nr * 4; ++i)
3387 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3388 }
3389
3390 if (pc->result_nr) {
3391 unsigned nr = pc->result_nr * 4;
3392
3393 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3394 if (!pc->result)
3395 return FALSE;
3396
3397 for (i = 0; i < nr; ++i)
3398 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3399 }
3400
3401 if (pc->param_nr) {
3402 int rid = 0;
3403
3404 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3405 if (!pc->param)
3406 return FALSE;
3407
3408 for (i = 0; i < pc->param_nr; ++i)
3409 for (c = 0; c < 4; ++c, ++rid)
3410 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3411 }
3412
3413 if (pc->addr_nr) {
3414 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3415 if (!pc->addr)
3416 return FALSE;
3417 }
3418 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3419 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
3420
3421 return TRUE;
3422 }
3423
3424 static void
3425 nv50_program_fixup_insns(struct nv50_pc *pc)
3426 {
3427 struct nv50_program_exec *e, **bra_list;
3428 unsigned i, n, pos;
3429
3430 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3431
3432 /* Collect branch instructions, we need to adjust their offsets
3433 * when converting 32 bit instructions to 64 bit ones
3434 */
3435 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3436 if (e->param.index >= 0 && !e->param.mask)
3437 bra_list[n++] = e;
3438
3439 /* Make sure we don't have any single 32 bit instructions. */
3440 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3441 pos += is_long(e) ? 2 : 1;
3442
3443 if ((pos & 1) && (!e->next || is_long(e->next))) {
3444 for (i = 0; i < n; ++i)
3445 if (bra_list[i]->param.index >= pos)
3446 bra_list[i]->param.index += 1;
3447 for (i = 0; i < pc->insn_nr; ++i)
3448 if (pc->insn_pos[i] >= pos)
3449 pc->insn_pos[i] += 1;
3450 convert_to_long(pc, e);
3451 ++pos;
3452 }
3453 }
3454
3455 FREE(bra_list);
3456
3457 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
3458 return;
3459
3460 /* fill in CALL offsets */
3461 for (e = pc->p->exec_head; e; e = e->next) {
3462 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
3463 e->param.index = pc->insn_pos[e->param.index];
3464 }
3465 }
3466
3467 static boolean
3468 nv50_program_tx(struct nv50_program *p)
3469 {
3470 struct tgsi_parse_context parse;
3471 struct nv50_pc *pc;
3472 boolean ret;
3473
3474 pc = CALLOC_STRUCT(nv50_pc);
3475 if (!pc)
3476 return FALSE;
3477
3478 ret = ctor_nv50_pc(pc, p);
3479 if (ret == FALSE)
3480 goto out_cleanup;
3481
3482 ret = nv50_program_tx_prep(pc);
3483 if (ret == FALSE)
3484 goto out_cleanup;
3485
3486 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
3487
3488 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3489 while (!tgsi_parse_end_of_tokens(&parse)) {
3490 const union tgsi_full_token *tok = &parse.FullToken;
3491
3492 /* previously allow32 was FALSE for first & last instruction */
3493 pc->allow32 = TRUE;
3494
3495 tgsi_parse_token(&parse);
3496
3497 switch (tok->Token.Type) {
3498 case TGSI_TOKEN_TYPE_INSTRUCTION:
3499 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
3500 ++pc->insn_cur;
3501 ret = nv50_tgsi_insn(pc, tok);
3502 if (ret == FALSE)
3503 goto out_err;
3504 break;
3505 default:
3506 break;
3507 }
3508 }
3509
3510 nv50_program_fixup_insns(pc);
3511
3512 p->param_nr = pc->param_nr * 4;
3513 p->immd_nr = pc->immd_nr * 4;
3514 p->immd = pc->immd_buf;
3515
3516 out_err:
3517 tgsi_parse_free(&parse);
3518
3519 out_cleanup:
3520 free_nv50_pc(pc);
3521 return ret;
3522 }
3523
3524 static void
3525 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3526 {
3527 if (nv50_program_tx(p) == FALSE)
3528 assert(0);
3529 p->translated = TRUE;
3530 }
3531
3532 static void
3533 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
3534 unsigned start, unsigned count, unsigned cbuf)
3535 {
3536 struct nouveau_channel *chan = nv50->screen->base.channel;
3537 struct nouveau_grobj *tesla = nv50->screen->tesla;
3538
3539 while (count) {
3540 unsigned nr = count > 2047 ? 2047 : count;
3541
3542 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3543 OUT_RING (chan, (cbuf << 0) | (start << 8));
3544 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3545 OUT_RINGp (chan, map, nr);
3546
3547 map += nr;
3548 start += nr;
3549 count -= nr;
3550 }
3551 }
3552
3553 static void
3554 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3555 {
3556 struct pipe_screen *pscreen = nv50->pipe.screen;
3557
3558 if (!p->data[0] && p->immd_nr) {
3559 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3560
3561 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3562 while (heap->next && heap->size < p->immd_nr) {
3563 struct nv50_program *evict = heap->next->priv;
3564 nouveau_resource_free(&evict->data[0]);
3565 }
3566
3567 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3568 &p->data[0]))
3569 assert(0);
3570 }
3571
3572 /* immediates only need to be uploaded again when freed */
3573 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3574 p->immd_nr, NV50_CB_PMISC);
3575 }
3576
3577 assert(p->param_nr <= 512);
3578
3579 if (p->param_nr) {
3580 unsigned cb;
3581 uint32_t *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3582 PIPE_BUFFER_USAGE_CPU_READ);
3583
3584 if (p->type == PIPE_SHADER_VERTEX)
3585 cb = NV50_CB_PVP;
3586 else
3587 cb = NV50_CB_PFP;
3588
3589 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3590 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3591 }
3592 }
3593
3594 static void
3595 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3596 {
3597 struct nouveau_channel *chan = nv50->screen->base.channel;
3598 struct nv50_program_exec *e;
3599 uint32_t *up, i;
3600 boolean upload = FALSE;
3601
3602 if (!p->bo) {
3603 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3604 p->exec_size * 4, &p->bo);
3605 upload = TRUE;
3606 }
3607
3608 if (p->data[0] && p->data[0]->start != p->data_start[0])
3609 upload = TRUE;
3610
3611 if (!upload)
3612 return;
3613
3614 up = MALLOC(p->exec_size * 4);
3615
3616 for (i = 0, e = p->exec_head; e; e = e->next) {
3617 unsigned ei, ci, bs;
3618
3619 if (e->param.index >= 0 && e->param.mask) {
3620 bs = (e->inst[1] >> 22) & 0x07;
3621 assert(bs < 2);
3622 ei = e->param.shift >> 5;
3623 ci = e->param.index;
3624 if (bs == 0)
3625 ci += p->data[bs]->start;
3626
3627 e->inst[ei] &= ~e->param.mask;
3628 e->inst[ei] |= (ci << e->param.shift);
3629 } else
3630 if (e->param.index >= 0) {
3631 /* zero mask means param is a jump/branch offset */
3632 assert(!(e->param.index & 1));
3633 /* seem to be 8 byte steps */
3634 ei = (e->param.index >> 1) + 0 /* START_ID */;
3635
3636 e->inst[0] &= 0xf0000fff;
3637 e->inst[0] |= ei << 12;
3638 }
3639
3640 up[i++] = e->inst[0];
3641 if (is_long(e))
3642 up[i++] = e->inst[1];
3643 }
3644 assert(i == p->exec_size);
3645
3646 if (p->data[0])
3647 p->data_start[0] = p->data[0]->start;
3648
3649 #ifdef NV50_PROGRAM_DUMP
3650 NOUVEAU_ERR("-------\n");
3651 for (e = p->exec_head; e; e = e->next) {
3652 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3653 if (is_long(e))
3654 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3655 }
3656 #endif
3657 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3658 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3659 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3660 0, 0, p->exec_size * 4, 1, 1);
3661
3662 FREE(up);
3663 }
3664
3665 void
3666 nv50_vertprog_validate(struct nv50_context *nv50)
3667 {
3668 struct nouveau_grobj *tesla = nv50->screen->tesla;
3669 struct nv50_program *p = nv50->vertprog;
3670 struct nouveau_stateobj *so;
3671
3672 if (!p->translated) {
3673 nv50_program_validate(nv50, p);
3674 if (!p->translated)
3675 assert(0);
3676 }
3677
3678 nv50_program_validate_data(nv50, p);
3679 nv50_program_validate_code(nv50, p);
3680
3681 so = so_new(5, 8, 2);
3682 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3683 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3684 NOUVEAU_BO_HIGH, 0, 0);
3685 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3686 NOUVEAU_BO_LOW, 0, 0);
3687 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3688 so_data (so, p->cfg.attr[0]);
3689 so_data (so, p->cfg.attr[1]);
3690 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3691 so_data (so, p->cfg.high_result);
3692 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3693 so_data (so, p->cfg.high_result); //8);
3694 so_data (so, p->cfg.high_temp);
3695 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3696 so_data (so, 0); /* program start offset */
3697 so_ref(so, &nv50->state.vertprog);
3698 so_ref(NULL, &so);
3699 }
3700
3701 void
3702 nv50_fragprog_validate(struct nv50_context *nv50)
3703 {
3704 struct nouveau_grobj *tesla = nv50->screen->tesla;
3705 struct nv50_program *p = nv50->fragprog;
3706 struct nouveau_stateobj *so;
3707
3708 if (!p->translated) {
3709 nv50_program_validate(nv50, p);
3710 if (!p->translated)
3711 assert(0);
3712 }
3713
3714 nv50_program_validate_data(nv50, p);
3715 nv50_program_validate_code(nv50, p);
3716
3717 so = so_new(6, 7, 2);
3718 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3719 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3720 NOUVEAU_BO_HIGH, 0, 0);
3721 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3722 NOUVEAU_BO_LOW, 0, 0);
3723 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3724 so_data (so, p->cfg.high_temp);
3725 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3726 so_data (so, p->cfg.high_result);
3727 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
3728 so_data (so, p->cfg.regs[2]);
3729 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3730 so_data (so, p->cfg.regs[3]);
3731 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3732 so_data (so, 0); /* program start offset */
3733 so_ref(so, &nv50->state.fragprog);
3734 so_ref(NULL, &so);
3735 }
3736
3737 static void
3738 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3739 {
3740 struct nv50_program *fp = nv50->fragprog;
3741 struct nv50_program *vp = nv50->vertprog;
3742 unsigned i, c, m = base;
3743
3744 /* XXX: this might not work correctly in all cases yet - we'll
3745 * just assume that an FP generic input that is not written in
3746 * the VP is PointCoord.
3747 */
3748 memset(pntc, 0, 8 * sizeof(uint32_t));
3749
3750 for (i = 0; i < fp->cfg.io_nr; i++) {
3751 uint8_t sn, si;
3752 uint8_t j, k = fp->cfg.io[i].id;
3753 unsigned n = popcnt4(fp->cfg.io[i].mask);
3754
3755 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3756 m += n;
3757 continue;
3758 }
3759
3760 for (j = 0; j < vp->info.num_outputs; ++j) {
3761 sn = vp->info.output_semantic_name[j];
3762 si = vp->info.output_semantic_index[j];
3763
3764 if (sn == fp->info.input_semantic_name[k] &&
3765 si == fp->info.input_semantic_index[k])
3766 break;
3767 }
3768
3769 if (j < vp->info.num_outputs) {
3770 ubyte mode =
3771 nv50->rasterizer->pipe.sprite_coord_mode[si];
3772
3773 if (mode == PIPE_SPRITE_COORD_NONE) {
3774 m += n;
3775 continue;
3776 }
3777 }
3778
3779 /* this is either PointCoord or replaced by sprite coords */
3780 for (c = 0; c < 4; c++) {
3781 if (!(fp->cfg.io[i].mask & (1 << c)))
3782 continue;
3783 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3784 ++m;
3785 }
3786 }
3787 }
3788
3789 static int
3790 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3791 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3792 {
3793 int c;
3794 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3795 uint8_t *map = (uint8_t *)p_map;
3796
3797 for (c = 0; c < 4; ++c) {
3798 if (mf & 1) {
3799 if (fpi->linear == TRUE)
3800 lin[mid / 32] |= 1 << (mid % 32);
3801 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3802 }
3803
3804 oid += mv & 1;
3805 mf >>= 1;
3806 mv >>= 1;
3807 }
3808
3809 return mid;
3810 }
3811
3812 void
3813 nv50_linkage_validate(struct nv50_context *nv50)
3814 {
3815 struct nouveau_grobj *tesla = nv50->screen->tesla;
3816 struct nv50_program *vp = nv50->vertprog;
3817 struct nv50_program *fp = nv50->fragprog;
3818 struct nouveau_stateobj *so;
3819 struct nv50_sreg4 dummy, *vpo;
3820 int i, n, c, m = 0;
3821 uint32_t map[16], lin[4], reg[5], pcrd[8];
3822
3823 memset(map, 0, sizeof(map));
3824 memset(lin, 0, sizeof(lin));
3825
3826 reg[1] = 0x00000004; /* low and high clip distance map ids */
3827 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3828 reg[3] = 0x00000000; /* point size map id & enable */
3829 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3830 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3831
3832 dummy.linear = FALSE;
3833 dummy.mask = 0xf; /* map all components of HPOS */
3834 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3835
3836 dummy.mask = 0x0;
3837
3838 if (vp->cfg.clpd < 0x40) {
3839 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3840 map[m++] = vp->cfg.clpd + c;
3841 reg[1] = (m << 8);
3842 }
3843
3844 reg[0] |= m << 8; /* adjust BFC0 id */
3845
3846 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3847 if (nv50->rasterizer->pipe.light_twoside) {
3848 vpo = &vp->cfg.two_side[0];
3849
3850 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3851 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3852 }
3853
3854 reg[0] += m - 4; /* adjust FFC0 id */
3855 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3856
3857 for (i = 0; i < fp->cfg.io_nr; i++) {
3858 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
3859 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
3860
3861 /* position must be mapped first */
3862 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
3863
3864 /* maybe even remove these from cfg.io */
3865 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
3866 continue;
3867
3868 /* VP outputs and vp->cfg.io are in the same order */
3869 for (n = 0; n < vp->info.num_outputs; ++n) {
3870 if (vp->info.output_semantic_name[n] == sn &&
3871 vp->info.output_semantic_index[n] == si)
3872 break;
3873 }
3874 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
3875
3876 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3877 }
3878
3879 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3880 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3881 reg[3] = (m++ << 4) | 1;
3882 }
3883
3884 /* now fill the stateobj */
3885 so = so_new(6, 58, 0);
3886
3887 n = (m + 3) / 4;
3888 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3889 so_data (so, m);
3890 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3891 so_datap (so, map, n);
3892
3893 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3894 so_datap (so, reg, 4);
3895
3896 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3897 so_data (so, reg[4]);
3898
3899 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
3900 so_datap (so, lin, 4);
3901
3902 if (nv50->rasterizer->pipe.point_sprite) {
3903 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3904
3905 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3906 so_datap (so, pcrd, 8);
3907 }
3908
3909 so_ref(so, &nv50->state.programs);
3910 so_ref(NULL, &so);
3911 }
3912
3913 void
3914 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3915 {
3916 while (p->exec_head) {
3917 struct nv50_program_exec *e = p->exec_head;
3918
3919 p->exec_head = e->next;
3920 FREE(e);
3921 }
3922 p->exec_tail = NULL;
3923 p->exec_size = 0;
3924
3925 nouveau_bo_ref(NULL, &p->bo);
3926
3927 nouveau_resource_free(&p->data[0]);
3928
3929 p->translated = 0;
3930 }