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nv50: add src_mask case for IF opcode
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_SAT 4
100
101 /* arbitrary limits */
102 #define MAX_IF_DEPTH 4
103 #define MAX_LOOP_DEPTH 4
104
105 struct nv50_pc {
106 struct nv50_program *p;
107
108 /* hw resources */
109 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
110 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
111
112 /* tgsi resources */
113 struct nv50_reg *temp;
114 int temp_nr;
115 struct nv50_reg *attr;
116 int attr_nr;
117 struct nv50_reg *result;
118 int result_nr;
119 struct nv50_reg *param;
120 int param_nr;
121 struct nv50_reg *immd;
122 float *immd_buf;
123 int immd_nr;
124 struct nv50_reg **addr;
125 int addr_nr;
126
127 struct nv50_reg *temp_temp[16];
128 unsigned temp_temp_nr;
129
130 /* broadcast and destination replacement regs */
131 struct nv50_reg *r_brdc;
132 struct nv50_reg *r_dst[4];
133
134 struct nv50_reg reg_instances[16];
135 unsigned reg_instance_nr;
136
137 unsigned interp_mode[32];
138 /* perspective interpolation registers */
139 struct nv50_reg *iv_p;
140 struct nv50_reg *iv_c;
141
142 struct nv50_program_exec *if_cond;
143 struct nv50_program_exec *if_insn[MAX_IF_DEPTH];
144 struct nv50_program_exec *br_join[MAX_IF_DEPTH];
145 struct nv50_program_exec *br_loop[MAX_LOOP_DEPTH]; /* for BRK branch */
146 int if_lvl, loop_lvl;
147 unsigned loop_pos[MAX_LOOP_DEPTH];
148
149 /* current instruction and total number of insns */
150 unsigned insn_cur;
151 unsigned insn_nr;
152
153 boolean allow32;
154 };
155
156 static INLINE struct nv50_reg *
157 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
158 {
159 struct nv50_reg *dup = NULL;
160 if (reg) {
161 assert(pc->reg_instance_nr < 16);
162 dup = &pc->reg_instances[pc->reg_instance_nr++];
163 *dup = *reg;
164 reg->mod = 0;
165 }
166 return dup;
167 }
168
169 static INLINE void
170 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
171 {
172 reg->type = type;
173 reg->index = index;
174 reg->hw = hw;
175 reg->mod = 0;
176 reg->rhw = -1;
177 reg->acc = 0;
178 }
179
180 static INLINE unsigned
181 popcnt4(uint32_t val)
182 {
183 static const unsigned cnt[16]
184 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
185 return cnt[val & 0xf];
186 }
187
188 static void
189 terminate_mbb(struct nv50_pc *pc)
190 {
191 int i;
192
193 /* remove records of temporary address register values */
194 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
195 if (pc->r_addr[i].index < 0)
196 pc->r_addr[i].rhw = -1;
197 }
198
199 static void
200 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
201 {
202 int i = 0;
203
204 if (reg->type == P_RESULT) {
205 if (pc->p->cfg.high_result < (reg->hw + 1))
206 pc->p->cfg.high_result = reg->hw + 1;
207 }
208
209 if (reg->type != P_TEMP)
210 return;
211
212 if (reg->hw >= 0) {
213 /*XXX: do this here too to catch FP temp-as-attr usage..
214 * not clean, but works */
215 if (pc->p->cfg.high_temp < (reg->hw + 1))
216 pc->p->cfg.high_temp = reg->hw + 1;
217 return;
218 }
219
220 if (reg->rhw != -1) {
221 /* try to allocate temporary with index rhw first */
222 if (!(pc->r_temp[reg->rhw])) {
223 pc->r_temp[reg->rhw] = reg;
224 reg->hw = reg->rhw;
225 if (pc->p->cfg.high_temp < (reg->rhw + 1))
226 pc->p->cfg.high_temp = reg->rhw + 1;
227 return;
228 }
229 /* make sure we don't get things like $r0 needs to go
230 * in $r1 and $r1 in $r0
231 */
232 i = pc->result_nr * 4;
233 }
234
235 for (; i < NV50_SU_MAX_TEMP; i++) {
236 if (!(pc->r_temp[i])) {
237 pc->r_temp[i] = reg;
238 reg->hw = i;
239 if (pc->p->cfg.high_temp < (i + 1))
240 pc->p->cfg.high_temp = i + 1;
241 return;
242 }
243 }
244
245 assert(0);
246 }
247
248 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
249 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
250 * lest we risk temp_temps overwriting regs alloc'd "later".
251 */
252 static struct nv50_reg *
253 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
254 {
255 struct nv50_reg *r;
256 int i;
257
258 if (dst && dst->type == P_TEMP && dst->hw == -1)
259 return dst;
260
261 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
262 if (!pc->r_temp[i]) {
263 r = MALLOC_STRUCT(nv50_reg);
264 ctor_reg(r, P_TEMP, -1, i);
265 pc->r_temp[i] = r;
266 return r;
267 }
268 }
269
270 assert(0);
271 return NULL;
272 }
273
274 /* Assign the hw of the discarded temporary register src
275 * to the tgsi register dst and free src.
276 */
277 static void
278 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
279 {
280 assert(src->index == -1 && src->hw != -1);
281
282 if (dst->hw != -1)
283 pc->r_temp[dst->hw] = NULL;
284 pc->r_temp[src->hw] = dst;
285 dst->hw = src->hw;
286
287 FREE(src);
288 }
289
290 /* release the hardware resource held by r */
291 static void
292 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
293 {
294 assert(r->type == P_TEMP);
295 if (r->hw == -1)
296 return;
297
298 assert(pc->r_temp[r->hw] == r);
299 pc->r_temp[r->hw] = NULL;
300
301 r->acc = 0;
302 if (r->index == -1)
303 FREE(r);
304 }
305
306 static void
307 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
308 {
309 if (r->index == -1) {
310 unsigned hw = r->hw;
311
312 FREE(pc->r_temp[hw]);
313 pc->r_temp[hw] = NULL;
314 }
315 }
316
317 static int
318 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
319 {
320 int i;
321
322 if ((idx + 4) >= NV50_SU_MAX_TEMP)
323 return 1;
324
325 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
326 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
327 return alloc_temp4(pc, dst, idx + 4);
328
329 for (i = 0; i < 4; i++) {
330 dst[i] = MALLOC_STRUCT(nv50_reg);
331 ctor_reg(dst[i], P_TEMP, -1, idx + i);
332 pc->r_temp[idx + i] = dst[i];
333 }
334
335 return 0;
336 }
337
338 static void
339 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
340 {
341 int i;
342
343 for (i = 0; i < 4; i++)
344 free_temp(pc, reg[i]);
345 }
346
347 static struct nv50_reg *
348 temp_temp(struct nv50_pc *pc)
349 {
350 if (pc->temp_temp_nr >= 16)
351 assert(0);
352
353 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
354 return pc->temp_temp[pc->temp_temp_nr++];
355 }
356
357 static void
358 kill_temp_temp(struct nv50_pc *pc)
359 {
360 int i;
361
362 for (i = 0; i < pc->temp_temp_nr; i++)
363 free_temp(pc, pc->temp_temp[i]);
364 pc->temp_temp_nr = 0;
365 }
366
367 static int
368 ctor_immd(struct nv50_pc *pc, float x, float y, float z, float w)
369 {
370 pc->immd_buf = REALLOC(pc->immd_buf, (pc->immd_nr * 4 * sizeof(float)),
371 (pc->immd_nr + 1) * 4 * sizeof(float));
372 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
373 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
374 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
375 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
376
377 return pc->immd_nr++;
378 }
379
380 static struct nv50_reg *
381 alloc_immd(struct nv50_pc *pc, float f)
382 {
383 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
384 unsigned hw;
385
386 for (hw = 0; hw < pc->immd_nr * 4; hw++)
387 if (pc->immd_buf[hw] == f)
388 break;
389
390 if (hw == pc->immd_nr * 4)
391 hw = ctor_immd(pc, f, -f, 0.5 * f, 0) * 4;
392
393 ctor_reg(r, P_IMMD, -1, hw);
394 return r;
395 }
396
397 static struct nv50_program_exec *
398 exec(struct nv50_pc *pc)
399 {
400 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
401
402 e->param.index = -1;
403 return e;
404 }
405
406 static void
407 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
408 {
409 struct nv50_program *p = pc->p;
410
411 if (p->exec_tail)
412 p->exec_tail->next = e;
413 if (!p->exec_head)
414 p->exec_head = e;
415 p->exec_tail = e;
416 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
417 }
418
419 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
420
421 static boolean
422 is_long(struct nv50_program_exec *e)
423 {
424 if (e->inst[0] & 1)
425 return TRUE;
426 return FALSE;
427 }
428
429 static boolean
430 is_immd(struct nv50_program_exec *e)
431 {
432 if (is_long(e) && (e->inst[1] & 3) == 3)
433 return TRUE;
434 return FALSE;
435 }
436
437 static INLINE void
438 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
439 struct nv50_program_exec *e)
440 {
441 set_long(pc, e);
442 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
443 e->inst[1] |= (pred << 7) | (idx << 12);
444 }
445
446 static INLINE void
447 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
448 struct nv50_program_exec *e)
449 {
450 set_long(pc, e);
451 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
452 e->inst[1] |= (idx << 4) | (on << 6);
453 }
454
455 static INLINE void
456 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
457 {
458 if (is_long(e))
459 return;
460
461 e->inst[0] |= 1;
462 set_pred(pc, 0xf, 0, e);
463 set_pred_wr(pc, 0, 0, e);
464 }
465
466 static INLINE void
467 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
468 {
469 if (dst->type == P_RESULT) {
470 set_long(pc, e);
471 e->inst[1] |= 0x00000008;
472 }
473
474 alloc_reg(pc, dst);
475 if (dst->hw > 63)
476 set_long(pc, e);
477 e->inst[0] |= (dst->hw << 2);
478 }
479
480 static INLINE void
481 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
482 {
483 unsigned val;
484 float f = pc->immd_buf[imm->hw];
485
486 if (imm->mod & NV50_MOD_ABS)
487 f = fabsf(f);
488 val = fui((imm->mod & NV50_MOD_NEG) ? -f : f);
489
490 set_long(pc, e);
491 /*XXX: can't be predicated - bits overlap.. catch cases where both
492 * are required and avoid them. */
493 set_pred(pc, 0, 0, e);
494 set_pred_wr(pc, 0, 0, e);
495
496 e->inst[1] |= 0x00000002 | 0x00000001;
497 e->inst[0] |= (val & 0x3f) << 16;
498 e->inst[1] |= (val >> 6) << 2;
499 }
500
501 static INLINE void
502 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
503 {
504 assert(!(e->inst[0] & 0x0c000000));
505 assert(!(e->inst[1] & 0x00000004));
506
507 e->inst[0] |= (a->hw & 3) << 26;
508 e->inst[1] |= (a->hw >> 2) << 2;
509 }
510
511 static void
512 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
513 struct nv50_reg *src0, uint16_t src1_val)
514 {
515 struct nv50_program_exec *e = exec(pc);
516
517 e->inst[0] = 0xd0000000 | (src1_val << 9);
518 e->inst[1] = 0x20000000;
519 set_long(pc, e);
520 e->inst[0] |= dst->hw << 2;
521 if (src0) /* otherwise will add to $a0, which is always 0 */
522 set_addr(e, src0);
523
524 emit(pc, e);
525 }
526
527 static struct nv50_reg *
528 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
529 {
530 int i;
531 struct nv50_reg *a_tgsi = NULL, *a = NULL;
532
533 if (!ref) {
534 /* allocate for TGSI address reg */
535 for (i = 0; i < NV50_SU_MAX_ADDR; ++i) {
536 if (pc->r_addr[i].index >= 0)
537 continue;
538 if (pc->r_addr[i].rhw >= 0 &&
539 pc->r_addr[i].acc == pc->insn_cur)
540 continue;
541
542 pc->r_addr[i].rhw = -1;
543 pc->r_addr[i].index = i;
544 return &pc->r_addr[i];
545 }
546 assert(0);
547 return NULL;
548 }
549
550 /* Allocate and set an address reg so we can access 'ref'.
551 *
552 * If and r_addr has index < 0, it is not reserved for TGSI,
553 * and index will be the negative of the TGSI addr index the
554 * value in rhw is relative to, or -256 if rhw is an offset
555 * from 0. If rhw < 0, the reg has not been initialized.
556 */
557 for (i = NV50_SU_MAX_ADDR - 1; i >= 0; --i) {
558 if (pc->r_addr[i].index >= 0) /* occupied for TGSI */
559 continue;
560 if (pc->r_addr[i].rhw < 0) { /* unused */
561 a = &pc->r_addr[i];
562 continue;
563 }
564 if (!a && pc->r_addr[i].acc != pc->insn_cur)
565 a = &pc->r_addr[i];
566
567 if (ref->hw - pc->r_addr[i].rhw >= 128)
568 continue;
569
570 if ((ref->acc >= 0 && pc->r_addr[i].index == -256) ||
571 (ref->acc < 0 && -pc->r_addr[i].index == ref->index)) {
572 pc->r_addr[i].acc = pc->insn_cur;
573 return &pc->r_addr[i];
574 }
575 }
576 assert(a);
577
578 if (ref->acc < 0)
579 a_tgsi = pc->addr[ref->index];
580
581 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
582
583 a->rhw = ref->hw & ~0x7f;
584 a->acc = pc->insn_cur;
585 a->index = a_tgsi ? -ref->index : -256;
586 return a;
587 }
588
589 #define INTERP_LINEAR 0
590 #define INTERP_FLAT 1
591 #define INTERP_PERSPECTIVE 2
592 #define INTERP_CENTROID 4
593
594 /* interpolant index has been stored in dst->rhw */
595 static void
596 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
597 unsigned mode)
598 {
599 assert(dst->rhw != -1);
600 struct nv50_program_exec *e = exec(pc);
601
602 e->inst[0] |= 0x80000000;
603 set_dst(pc, dst, e);
604 e->inst[0] |= (dst->rhw << 16);
605
606 if (mode & INTERP_FLAT) {
607 e->inst[0] |= (1 << 8);
608 } else {
609 if (mode & INTERP_PERSPECTIVE) {
610 e->inst[0] |= (1 << 25);
611 alloc_reg(pc, iv);
612 e->inst[0] |= (iv->hw << 9);
613 }
614
615 if (mode & INTERP_CENTROID)
616 e->inst[0] |= (1 << 24);
617 }
618
619 emit(pc, e);
620 }
621
622 static void
623 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
624 struct nv50_program_exec *e)
625 {
626 set_long(pc, e);
627
628 e->param.index = src->hw & 127;
629 e->param.shift = s;
630 e->param.mask = m << (s % 32);
631
632 if (src->hw > 127)
633 set_addr(e, alloc_addr(pc, src));
634 else
635 if (src->acc < 0) {
636 assert(src->type == P_CONST);
637 set_addr(e, pc->addr[src->index]);
638 }
639
640 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
641 }
642
643 static void
644 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
645 {
646 struct nv50_program_exec *e = exec(pc);
647
648 e->inst[0] = 0x10000000;
649 if (!pc->allow32)
650 set_long(pc, e);
651
652 set_dst(pc, dst, e);
653
654 if (!is_long(e) && src->type == P_IMMD) {
655 set_immd(pc, src, e);
656 /*XXX: 32-bit, but steals part of "half" reg space - need to
657 * catch and handle this case if/when we do half-regs
658 */
659 } else
660 if (src->type == P_IMMD || src->type == P_CONST) {
661 set_long(pc, e);
662 set_data(pc, src, 0x7f, 9, e);
663 e->inst[1] |= 0x20000000; /* src0 const? */
664 } else {
665 if (src->type == P_ATTR) {
666 set_long(pc, e);
667 e->inst[1] |= 0x00200000;
668 }
669
670 alloc_reg(pc, src);
671 if (src->hw > 63)
672 set_long(pc, e);
673 e->inst[0] |= (src->hw << 9);
674 }
675
676 if (is_long(e) && !is_immd(e)) {
677 e->inst[1] |= 0x04000000; /* 32-bit */
678 e->inst[1] |= 0x0000c000; /* "subsubop" 0x3 */
679 if (!(e->inst[1] & 0x20000000))
680 e->inst[1] |= 0x00030000; /* "subsubop" 0xf */
681 } else
682 e->inst[0] |= 0x00008000;
683
684 emit(pc, e);
685 }
686
687 static INLINE void
688 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
689 {
690 struct nv50_reg *imm = alloc_immd(pc, f);
691 emit_mov(pc, dst, imm);
692 FREE(imm);
693 }
694
695 static boolean
696 check_swap_src_0_1(struct nv50_pc *pc,
697 struct nv50_reg **s0, struct nv50_reg **s1)
698 {
699 struct nv50_reg *src0 = *s0, *src1 = *s1;
700
701 if (src0->type == P_CONST) {
702 if (src1->type != P_CONST) {
703 *s0 = src1;
704 *s1 = src0;
705 return TRUE;
706 }
707 } else
708 if (src1->type == P_ATTR) {
709 if (src0->type != P_ATTR) {
710 *s0 = src1;
711 *s1 = src0;
712 return TRUE;
713 }
714 }
715
716 return FALSE;
717 }
718
719 static void
720 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
721 struct nv50_program_exec *e)
722 {
723 struct nv50_reg *temp;
724
725 if (src->type != P_TEMP) {
726 temp = temp_temp(pc);
727 emit_mov(pc, temp, src);
728 src = temp;
729 }
730
731 alloc_reg(pc, src);
732 if (src->hw > 63)
733 set_long(pc, e);
734 e->inst[0] |= (src->hw << 9);
735 }
736
737 static void
738 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
739 {
740 if (src->type == P_ATTR) {
741 set_long(pc, e);
742 e->inst[1] |= 0x00200000;
743 } else
744 if (src->type == P_CONST || src->type == P_IMMD) {
745 struct nv50_reg *temp = temp_temp(pc);
746
747 emit_mov(pc, temp, src);
748 src = temp;
749 }
750
751 alloc_reg(pc, src);
752 if (src->hw > 63)
753 set_long(pc, e);
754 e->inst[0] |= (src->hw << 9);
755 }
756
757 static void
758 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
759 {
760 if (src->type == P_ATTR) {
761 struct nv50_reg *temp = temp_temp(pc);
762
763 emit_mov(pc, temp, src);
764 src = temp;
765 } else
766 if (src->type == P_CONST || src->type == P_IMMD) {
767 assert(!(e->inst[0] & 0x00800000));
768 if (e->inst[0] & 0x01000000) {
769 struct nv50_reg *temp = temp_temp(pc);
770
771 emit_mov(pc, temp, src);
772 src = temp;
773 } else {
774 set_data(pc, src, 0x7f, 16, e);
775 e->inst[0] |= 0x00800000;
776 }
777 }
778
779 alloc_reg(pc, src);
780 if (src->hw > 63)
781 set_long(pc, e);
782 e->inst[0] |= ((src->hw & 127) << 16);
783 }
784
785 static void
786 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
787 {
788 set_long(pc, e);
789
790 if (src->type == P_ATTR) {
791 struct nv50_reg *temp = temp_temp(pc);
792
793 emit_mov(pc, temp, src);
794 src = temp;
795 } else
796 if (src->type == P_CONST || src->type == P_IMMD) {
797 assert(!(e->inst[0] & 0x01000000));
798 if (e->inst[0] & 0x00800000) {
799 struct nv50_reg *temp = temp_temp(pc);
800
801 emit_mov(pc, temp, src);
802 src = temp;
803 } else {
804 set_data(pc, src, 0x7f, 32+14, e);
805 e->inst[0] |= 0x01000000;
806 }
807 }
808
809 alloc_reg(pc, src);
810 e->inst[1] |= ((src->hw & 127) << 14);
811 }
812
813 static void
814 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
815 struct nv50_reg *src1)
816 {
817 struct nv50_program_exec *e = exec(pc);
818
819 e->inst[0] |= 0xc0000000;
820
821 if (!pc->allow32)
822 set_long(pc, e);
823
824 check_swap_src_0_1(pc, &src0, &src1);
825 set_dst(pc, dst, e);
826 set_src_0(pc, src0, e);
827 if (src1->type == P_IMMD && !is_long(e)) {
828 if (src0->mod & NV50_MOD_NEG)
829 e->inst[0] |= 0x00008000;
830 set_immd(pc, src1, e);
831 } else {
832 set_src_1(pc, src1, e);
833 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
834 if (is_long(e))
835 e->inst[1] |= 0x08000000;
836 else
837 e->inst[0] |= 0x00008000;
838 }
839 }
840
841 emit(pc, e);
842 }
843
844 static void
845 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
846 struct nv50_reg *src0, struct nv50_reg *src1)
847 {
848 struct nv50_program_exec *e = exec(pc);
849
850 e->inst[0] = 0xb0000000;
851
852 alloc_reg(pc, src1);
853 check_swap_src_0_1(pc, &src0, &src1);
854
855 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
856 set_long(pc, e);
857 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
858 ((src1->mod & NV50_MOD_NEG) << 27);
859 }
860
861 set_dst(pc, dst, e);
862 set_src_0(pc, src0, e);
863 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
864 set_src_2(pc, src1, e);
865 else
866 if (src1->type == P_IMMD)
867 set_immd(pc, src1, e);
868 else
869 set_src_1(pc, src1, e);
870
871 emit(pc, e);
872 }
873
874 static void
875 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
876 uint8_t s)
877 {
878 struct nv50_program_exec *e = exec(pc);
879
880 set_long(pc, e);
881 e->inst[1] |= 0xc0000000;
882
883 e->inst[0] |= dst->hw << 2;
884 e->inst[0] |= s << 16; /* shift left */
885 set_src_0_restricted(pc, src, e);
886
887 emit(pc, e);
888 }
889
890 static void
891 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
892 struct nv50_reg *src0, struct nv50_reg *src1)
893 {
894 struct nv50_program_exec *e = exec(pc);
895
896 set_long(pc, e);
897 e->inst[0] |= 0xb0000000;
898 e->inst[1] |= (sub << 29);
899
900 check_swap_src_0_1(pc, &src0, &src1);
901 set_dst(pc, dst, e);
902 set_src_0(pc, src0, e);
903 set_src_1(pc, src1, e);
904
905 if (src0->mod & NV50_MOD_ABS)
906 e->inst[1] |= 0x00100000;
907 if (src1->mod & NV50_MOD_ABS)
908 e->inst[1] |= 0x00080000;
909
910 emit(pc, e);
911 }
912
913 static INLINE void
914 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
915 struct nv50_reg *src1)
916 {
917 src1->mod ^= NV50_MOD_NEG;
918 emit_add(pc, dst, src0, src1);
919 src1->mod ^= NV50_MOD_NEG;
920 }
921
922 static void
923 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
924 struct nv50_reg *src1, unsigned op)
925 {
926 struct nv50_program_exec *e = exec(pc);
927
928 e->inst[0] = 0xd0000000;
929 set_long(pc, e);
930
931 check_swap_src_0_1(pc, &src0, &src1);
932 set_dst(pc, dst, e);
933 set_src_0(pc, src0, e);
934
935 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
936 op != TGSI_OPCODE_XOR)
937 assert(!"invalid bit op");
938
939 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
940 set_immd(pc, src1, e);
941 if (op == TGSI_OPCODE_OR)
942 e->inst[0] |= 0x0100;
943 else
944 if (op == TGSI_OPCODE_XOR)
945 e->inst[0] |= 0x8000;
946 } else {
947 set_src_1(pc, src1, e);
948 e->inst[1] |= 0x04000000; /* 32 bit */
949 if (op == TGSI_OPCODE_OR)
950 e->inst[1] |= 0x4000;
951 else
952 if (op == TGSI_OPCODE_XOR)
953 e->inst[1] |= 0x8000;
954 }
955
956 emit(pc, e);
957 }
958
959 static void
960 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
961 struct nv50_reg *src1, struct nv50_reg *src2)
962 {
963 struct nv50_program_exec *e = exec(pc);
964
965 e->inst[0] |= 0xe0000000;
966
967 check_swap_src_0_1(pc, &src0, &src1);
968 set_dst(pc, dst, e);
969 set_src_0(pc, src0, e);
970 set_src_1(pc, src1, e);
971 set_src_2(pc, src2, e);
972
973 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
974 e->inst[1] |= 0x04000000;
975 if (src2->mod & NV50_MOD_NEG)
976 e->inst[1] |= 0x08000000;
977
978 emit(pc, e);
979 }
980
981 static INLINE void
982 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
983 struct nv50_reg *src1, struct nv50_reg *src2)
984 {
985 src2->mod ^= NV50_MOD_NEG;
986 emit_mad(pc, dst, src0, src1, src2);
987 src2->mod ^= NV50_MOD_NEG;
988 }
989
990 static void
991 emit_flop(struct nv50_pc *pc, unsigned sub,
992 struct nv50_reg *dst, struct nv50_reg *src)
993 {
994 struct nv50_program_exec *e = exec(pc);
995
996 e->inst[0] |= 0x90000000;
997 if (sub) {
998 set_long(pc, e);
999 e->inst[1] |= (sub << 29);
1000 }
1001
1002 set_dst(pc, dst, e);
1003
1004 if (sub == 0 || sub == 2)
1005 set_src_0_restricted(pc, src, e);
1006 else
1007 set_src_0(pc, src, e);
1008
1009 emit(pc, e);
1010 }
1011
1012 static void
1013 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1014 {
1015 struct nv50_program_exec *e = exec(pc);
1016
1017 e->inst[0] |= 0xb0000000;
1018
1019 set_dst(pc, dst, e);
1020 set_src_0(pc, src, e);
1021 set_long(pc, e);
1022 e->inst[1] |= (6 << 29) | 0x00004000;
1023
1024 emit(pc, e);
1025 }
1026
1027 static void
1028 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1029 {
1030 struct nv50_program_exec *e = exec(pc);
1031
1032 e->inst[0] |= 0xb0000000;
1033
1034 set_dst(pc, dst, e);
1035 set_src_0(pc, src, e);
1036 set_long(pc, e);
1037 e->inst[1] |= (6 << 29);
1038
1039 emit(pc, e);
1040 }
1041
1042 #define CVTOP_RN 0x01
1043 #define CVTOP_FLOOR 0x03
1044 #define CVTOP_CEIL 0x05
1045 #define CVTOP_TRUNC 0x07
1046 #define CVTOP_SAT 0x08
1047 #define CVTOP_ABS 0x10
1048
1049 /* 0x04 == 32 bit dst */
1050 /* 0x40 == dst is float */
1051 /* 0x80 == src is float */
1052 #define CVT_F32_F32 0xc4
1053 #define CVT_F32_S32 0x44
1054 #define CVT_S32_F32 0x8c
1055 #define CVT_S32_S32 0x0c
1056 #define CVT_NEG 0x20
1057 #define CVT_RI 0x08
1058
1059 static void
1060 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1061 int wp, unsigned cvn, unsigned fmt)
1062 {
1063 struct nv50_program_exec *e;
1064
1065 e = exec(pc);
1066 set_long(pc, e);
1067
1068 e->inst[0] |= 0xa0000000;
1069 e->inst[1] |= 0x00004000; /* 32 bit src */
1070 e->inst[1] |= (cvn << 16);
1071 e->inst[1] |= (fmt << 24);
1072 set_src_0(pc, src, e);
1073
1074 if (wp >= 0)
1075 set_pred_wr(pc, 1, wp, e);
1076
1077 if (dst)
1078 set_dst(pc, dst, e);
1079 else {
1080 e->inst[0] |= 0x000001fc;
1081 e->inst[1] |= 0x00000008;
1082 }
1083
1084 emit(pc, e);
1085 }
1086
1087 /* nv50 Condition codes:
1088 * 0x1 = LT
1089 * 0x2 = EQ
1090 * 0x3 = LE
1091 * 0x4 = GT
1092 * 0x5 = NE
1093 * 0x6 = GE
1094 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1095 * 0x8 = unordered bit (allows NaN)
1096 */
1097 static void
1098 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1099 struct nv50_reg *src0, struct nv50_reg *src1)
1100 {
1101 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1102
1103 struct nv50_program_exec *e = exec(pc);
1104 struct nv50_reg *rdst;
1105
1106 assert(ccode < 16);
1107 if (check_swap_src_0_1(pc, &src0, &src1))
1108 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1109
1110 rdst = dst;
1111 if (dst && dst->type != P_TEMP)
1112 dst = alloc_temp(pc, NULL);
1113
1114 /* set.u32 */
1115 set_long(pc, e);
1116 e->inst[0] |= 0xb0000000;
1117 e->inst[1] |= 0x60000000 | (ccode << 14);
1118
1119 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1120 * that doesn't seem to match what the hw actually does
1121 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1122 */
1123
1124 if (wp >= 0)
1125 set_pred_wr(pc, 1, wp, e);
1126 if (dst)
1127 set_dst(pc, dst, e);
1128 else {
1129 e->inst[0] |= 0x000001fc;
1130 e->inst[1] |= 0x00000008;
1131 }
1132
1133 set_src_0(pc, src0, e);
1134 set_src_1(pc, src1, e);
1135
1136 emit(pc, e);
1137 pc->if_cond = pc->p->exec_tail; /* record for OPCODE_IF */
1138
1139 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1140 if (rdst)
1141 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
1142 if (rdst && rdst != dst)
1143 free_temp(pc, dst);
1144 }
1145
1146 static INLINE unsigned
1147 map_tgsi_setop_cc(unsigned op)
1148 {
1149 switch (op) {
1150 case TGSI_OPCODE_SLT: return 0x1;
1151 case TGSI_OPCODE_SGE: return 0x6;
1152 case TGSI_OPCODE_SEQ: return 0x2;
1153 case TGSI_OPCODE_SGT: return 0x4;
1154 case TGSI_OPCODE_SLE: return 0x3;
1155 case TGSI_OPCODE_SNE: return 0xd;
1156 default:
1157 assert(0);
1158 return 0;
1159 }
1160 }
1161
1162 static INLINE void
1163 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1164 {
1165 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
1166 }
1167
1168 static void
1169 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1170 struct nv50_reg *v, struct nv50_reg *e)
1171 {
1172 struct nv50_reg *temp = alloc_temp(pc, NULL);
1173
1174 emit_flop(pc, 3, temp, v);
1175 emit_mul(pc, temp, temp, e);
1176 emit_preex2(pc, temp, temp);
1177 emit_flop(pc, 6, dst, temp);
1178
1179 free_temp(pc, temp);
1180 }
1181
1182 static INLINE void
1183 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1184 {
1185 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
1186 }
1187
1188 static INLINE void
1189 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1190 {
1191 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
1192 }
1193
1194 static void
1195 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1196 struct nv50_reg **src)
1197 {
1198 struct nv50_reg *one = alloc_immd(pc, 1.0);
1199 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1200 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1201 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1202 struct nv50_reg *tmp[4];
1203 boolean allow32 = pc->allow32;
1204
1205 pc->allow32 = FALSE;
1206
1207 if (mask & (3 << 1)) {
1208 tmp[0] = alloc_temp(pc, NULL);
1209 emit_minmax(pc, 4, tmp[0], src[0], zero);
1210 }
1211
1212 if (mask & (1 << 2)) {
1213 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1214
1215 tmp[1] = temp_temp(pc);
1216 emit_minmax(pc, 4, tmp[1], src[1], zero);
1217
1218 tmp[3] = temp_temp(pc);
1219 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1220 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1221
1222 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1223 emit_mov(pc, dst[2], zero);
1224 set_pred(pc, 3, 0, pc->p->exec_tail);
1225 }
1226
1227 if (mask & (1 << 1))
1228 assimilate_temp(pc, dst[1], tmp[0]);
1229 else
1230 if (mask & (1 << 2))
1231 free_temp(pc, tmp[0]);
1232
1233 pc->allow32 = allow32;
1234
1235 /* do this last, in case src[i,j] == dst[0,3] */
1236 if (mask & (1 << 0))
1237 emit_mov(pc, dst[0], one);
1238
1239 if (mask & (1 << 3))
1240 emit_mov(pc, dst[3], one);
1241
1242 FREE(pos128);
1243 FREE(neg128);
1244 FREE(zero);
1245 FREE(one);
1246 }
1247
1248 static INLINE void
1249 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1250 {
1251 emit_cvt(pc, dst, src, -1, CVTOP_RN, CVT_F32_F32 | CVT_NEG);
1252 }
1253
1254 static void
1255 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1256 {
1257 struct nv50_program_exec *e;
1258 const int r_pred = 1;
1259 unsigned cvn = CVT_F32_F32;
1260
1261 if (src->mod & NV50_MOD_NEG)
1262 cvn |= CVT_NEG;
1263 /* write predicate reg */
1264 emit_cvt(pc, NULL, src, r_pred, CVTOP_RN, cvn);
1265
1266 /* conditional discard */
1267 e = exec(pc);
1268 e->inst[0] = 0x00000002;
1269 set_long(pc, e);
1270 set_pred(pc, 0x1 /* LT */, r_pred, e);
1271 emit(pc, e);
1272 }
1273
1274 static void
1275 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1276 struct nv50_reg **src, boolean proj)
1277 {
1278 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1279
1280 src[0]->mod |= NV50_MOD_ABS;
1281 src[1]->mod |= NV50_MOD_ABS;
1282 src[2]->mod |= NV50_MOD_ABS;
1283
1284 emit_minmax(pc, 4, t[2], src[0], src[1]);
1285 emit_minmax(pc, 4, t[2], src[2], t[2]);
1286
1287 src[0]->mod = mod[0];
1288 src[1]->mod = mod[1];
1289 src[2]->mod = mod[2];
1290
1291 if (proj && 0 /* looks more correct without this */)
1292 emit_mul(pc, t[2], t[2], src[3]);
1293 emit_flop(pc, 0, t[2], t[2]);
1294
1295 emit_mul(pc, t[0], src[0], t[2]);
1296 emit_mul(pc, t[1], src[1], t[2]);
1297 emit_mul(pc, t[2], src[2], t[2]);
1298 }
1299
1300 static void
1301 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1302 struct nv50_reg **src, unsigned unit, unsigned type, boolean proj)
1303 {
1304 struct nv50_reg *t[4];
1305 struct nv50_program_exec *e;
1306
1307 unsigned c, mode, dim;
1308
1309 switch (type) {
1310 case TGSI_TEXTURE_1D:
1311 dim = 1;
1312 break;
1313 case TGSI_TEXTURE_UNKNOWN:
1314 case TGSI_TEXTURE_2D:
1315 case TGSI_TEXTURE_SHADOW1D: /* XXX: x, z */
1316 case TGSI_TEXTURE_RECT:
1317 dim = 2;
1318 break;
1319 case TGSI_TEXTURE_3D:
1320 case TGSI_TEXTURE_CUBE:
1321 case TGSI_TEXTURE_SHADOW2D:
1322 case TGSI_TEXTURE_SHADOWRECT: /* XXX */
1323 dim = 3;
1324 break;
1325 default:
1326 assert(0);
1327 break;
1328 }
1329
1330 /* some cards need t[0]'s hw index to be a multiple of 4 */
1331 alloc_temp4(pc, t, 0);
1332
1333 if (type == TGSI_TEXTURE_CUBE) {
1334 load_cube_tex_coords(pc, t, src, proj);
1335 } else
1336 if (proj) {
1337 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1338 mode = pc->interp_mode[src[0]->index];
1339
1340 t[3]->rhw = src[3]->rhw;
1341 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1342 emit_flop(pc, 0, t[3], t[3]);
1343
1344 for (c = 0; c < dim; c++) {
1345 t[c]->rhw = src[c]->rhw;
1346 emit_interp(pc, t[c], t[3],
1347 (mode | INTERP_PERSPECTIVE));
1348 }
1349 } else {
1350 emit_flop(pc, 0, t[3], src[3]);
1351 for (c = 0; c < dim; c++)
1352 emit_mul(pc, t[c], src[c], t[3]);
1353
1354 /* XXX: for some reason the blob sometimes uses MAD:
1355 * emit_mad(pc, t[c], src[0][c], t[3], t[3])
1356 * pc->p->exec_tail->inst[1] |= 0x080fc000;
1357 */
1358 }
1359 } else {
1360 for (c = 0; c < dim; c++)
1361 emit_mov(pc, t[c], src[c]);
1362 }
1363
1364 e = exec(pc);
1365 set_long(pc, e);
1366 e->inst[0] |= 0xf0000000;
1367 e->inst[1] |= 0x00000004;
1368 set_dst(pc, t[0], e);
1369 e->inst[0] |= (unit << 9);
1370
1371 if (dim == 2)
1372 e->inst[0] |= 0x00400000;
1373 else
1374 if (dim == 3) {
1375 e->inst[0] |= 0x00800000;
1376 if (type == TGSI_TEXTURE_CUBE)
1377 e->inst[0] |= 0x08000000;
1378 }
1379
1380 e->inst[0] |= (mask & 0x3) << 25;
1381 e->inst[1] |= (mask & 0xc) << 12;
1382
1383 emit(pc, e);
1384 #if 1
1385 c = 0;
1386 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1387 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1388 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1389 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1390
1391 free_temp4(pc, t);
1392 #else
1393 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1394 * the texture coordinates, not the fetched values: latency ? */
1395
1396 for (c = 0; c < 4; c++) {
1397 if (mask & (1 << c))
1398 assimilate_temp(pc, dst[c], t[c]);
1399 else
1400 free_temp(pc, t[c]);
1401 }
1402 #endif
1403 }
1404
1405 static void
1406 emit_branch(struct nv50_pc *pc, int pred, unsigned cc,
1407 struct nv50_program_exec **join)
1408 {
1409 struct nv50_program_exec *e = exec(pc);
1410
1411 if (join) {
1412 set_long(pc, e);
1413 e->inst[0] |= 0xa0000002;
1414 emit(pc, e);
1415 *join = e;
1416 e = exec(pc);
1417 }
1418
1419 set_long(pc, e);
1420 e->inst[0] |= 0x10000002;
1421 if (pred >= 0)
1422 set_pred(pc, cc, pred, e);
1423 emit(pc, e);
1424 }
1425
1426 static void
1427 emit_nop(struct nv50_pc *pc)
1428 {
1429 struct nv50_program_exec *e = exec(pc);
1430
1431 e->inst[0] = 0xf0000000;
1432 set_long(pc, e);
1433 e->inst[1] = 0xe0000000;
1434 emit(pc, e);
1435 }
1436
1437 static void
1438 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1439 {
1440 struct nv50_program_exec *e = exec(pc);
1441
1442 assert(src->type == P_TEMP);
1443
1444 e->inst[0] = 0xc0140000;
1445 e->inst[1] = 0x89800000;
1446 set_long(pc, e);
1447 set_dst(pc, dst, e);
1448 set_src_0(pc, src, e);
1449 set_src_2(pc, src, e);
1450
1451 emit(pc, e);
1452 }
1453
1454 static void
1455 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1456 {
1457 struct nv50_reg *r = src;
1458 struct nv50_program_exec *e = exec(pc);
1459
1460 assert(src->type == P_TEMP);
1461
1462 if (!(src->mod & NV50_MOD_NEG)) { /* ! double negation */
1463 r = alloc_temp(pc, NULL);
1464 emit_neg(pc, r, src);
1465 }
1466
1467 e->inst[0] = 0xc0150000;
1468 e->inst[1] = 0x8a400000;
1469 set_long(pc, e);
1470 set_dst(pc, dst, e);
1471 set_src_0(pc, r, e);
1472 set_src_2(pc, r, e);
1473
1474 if (r != src)
1475 free_temp(pc, r);
1476
1477 emit(pc, e);
1478 }
1479
1480 static void
1481 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1482 {
1483 unsigned q = 0, m = ~0;
1484
1485 assert(!is_long(e));
1486
1487 switch (e->inst[0] >> 28) {
1488 case 0x1:
1489 /* MOV */
1490 q = 0x0403c000;
1491 m = 0xffff7fff;
1492 break;
1493 case 0x8:
1494 /* INTERP (move centroid, perspective and flat bits) */
1495 m = ~0x03000100;
1496 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1497 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1498 break;
1499 case 0x9:
1500 /* RCP */
1501 break;
1502 case 0xB:
1503 /* ADD */
1504 m = ~(127 << 16);
1505 q = ((e->inst[0] & (~m)) >> 2);
1506 break;
1507 case 0xC:
1508 /* MUL */
1509 m = ~0x00008000;
1510 q = ((e->inst[0] & (~m)) << 12);
1511 break;
1512 case 0xE:
1513 /* MAD (if src2 == dst) */
1514 q = ((e->inst[0] & 0x1fc) << 12);
1515 break;
1516 default:
1517 assert(0);
1518 break;
1519 }
1520
1521 set_long(pc, e);
1522 pc->p->exec_size++;
1523
1524 e->inst[0] &= m;
1525 e->inst[1] |= q;
1526 }
1527
1528 /* Some operations support an optional negation flag. */
1529 static boolean
1530 negate_supported(const struct tgsi_full_instruction *insn, int i)
1531 {
1532 switch (insn->Instruction.Opcode) {
1533 case TGSI_OPCODE_DDY:
1534 case TGSI_OPCODE_DP3:
1535 case TGSI_OPCODE_DP4:
1536 case TGSI_OPCODE_MUL:
1537 case TGSI_OPCODE_KIL:
1538 case TGSI_OPCODE_ADD:
1539 case TGSI_OPCODE_SUB:
1540 case TGSI_OPCODE_MAD:
1541 return TRUE;
1542 case TGSI_OPCODE_POW:
1543 if (i == 1)
1544 return TRUE;
1545 return FALSE;
1546 default:
1547 return FALSE;
1548 }
1549 }
1550
1551 /* Return a read mask for source registers deduced from opcode & write mask. */
1552 static unsigned
1553 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1554 {
1555 unsigned x, mask = insn->Dst[0].Register.WriteMask;
1556
1557 switch (insn->Instruction.Opcode) {
1558 case TGSI_OPCODE_COS:
1559 case TGSI_OPCODE_SIN:
1560 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1561 case TGSI_OPCODE_DP3:
1562 return 0x7;
1563 case TGSI_OPCODE_DP4:
1564 case TGSI_OPCODE_DPH:
1565 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1566 return 0xf;
1567 case TGSI_OPCODE_DST:
1568 return mask & (c ? 0xa : 0x6);
1569 case TGSI_OPCODE_EX2:
1570 case TGSI_OPCODE_LG2:
1571 case TGSI_OPCODE_POW:
1572 case TGSI_OPCODE_RCP:
1573 case TGSI_OPCODE_RSQ:
1574 case TGSI_OPCODE_SCS:
1575 return 0x1;
1576 case TGSI_OPCODE_IF:
1577 return 0x1;
1578 case TGSI_OPCODE_LIT:
1579 return 0xb;
1580 case TGSI_OPCODE_TEX:
1581 case TGSI_OPCODE_TXP:
1582 {
1583 const struct tgsi_instruction_texture *tex;
1584
1585 assert(insn->Instruction.Texture);
1586 tex = &insn->Texture;
1587
1588 mask = 0x7;
1589 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP)
1590 mask |= 0x8;
1591
1592 switch (tex->Texture) {
1593 case TGSI_TEXTURE_1D:
1594 mask &= 0x9;
1595 break;
1596 case TGSI_TEXTURE_2D:
1597 mask &= 0xb;
1598 break;
1599 default:
1600 break;
1601 }
1602 }
1603 return mask;
1604 case TGSI_OPCODE_XPD:
1605 x = 0;
1606 if (mask & 1) x |= 0x6;
1607 if (mask & 2) x |= 0x5;
1608 if (mask & 4) x |= 0x3;
1609 return x;
1610 default:
1611 break;
1612 }
1613
1614 return mask;
1615 }
1616
1617 static struct nv50_reg *
1618 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1619 {
1620 switch (dst->Register.File) {
1621 case TGSI_FILE_TEMPORARY:
1622 return &pc->temp[dst->Register.Index * 4 + c];
1623 case TGSI_FILE_OUTPUT:
1624 return &pc->result[dst->Register.Index * 4 + c];
1625 case TGSI_FILE_ADDRESS:
1626 {
1627 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
1628 if (!r) {
1629 r = alloc_addr(pc, NULL);
1630 pc->addr[dst->Register.Index * 4 + c] = r;
1631 }
1632 assert(r);
1633 return r;
1634 }
1635 case TGSI_FILE_NULL:
1636 return NULL;
1637 default:
1638 break;
1639 }
1640
1641 return NULL;
1642 }
1643
1644 static struct nv50_reg *
1645 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1646 boolean neg)
1647 {
1648 struct nv50_reg *r = NULL;
1649 struct nv50_reg *temp;
1650 unsigned sgn, c, swz;
1651
1652 if (src->Register.File != TGSI_FILE_CONSTANT)
1653 assert(!src->Register.Indirect);
1654
1655 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1656
1657 c = tgsi_util_get_full_src_register_swizzle(src, chan);
1658 switch (c) {
1659 case TGSI_SWIZZLE_X:
1660 case TGSI_SWIZZLE_Y:
1661 case TGSI_SWIZZLE_Z:
1662 case TGSI_SWIZZLE_W:
1663 switch (src->Register.File) {
1664 case TGSI_FILE_INPUT:
1665 r = &pc->attr[src->Register.Index * 4 + c];
1666 break;
1667 case TGSI_FILE_TEMPORARY:
1668 r = &pc->temp[src->Register.Index * 4 + c];
1669 break;
1670 case TGSI_FILE_CONSTANT:
1671 if (!src->Register.Indirect) {
1672 r = &pc->param[src->Register.Index * 4 + c];
1673 break;
1674 }
1675 /* Indicate indirection by setting r->acc < 0 and
1676 * use the index field to select the address reg.
1677 */
1678 r = MALLOC_STRUCT(nv50_reg);
1679 swz = tgsi_util_get_src_register_swizzle(
1680 &src->Indirect, 0);
1681 ctor_reg(r, P_CONST,
1682 src->Indirect.Index * 4 + swz,
1683 src->Register.Index * 4 + c);
1684 r->acc = -1;
1685 break;
1686 case TGSI_FILE_IMMEDIATE:
1687 r = &pc->immd[src->Register.Index * 4 + c];
1688 break;
1689 case TGSI_FILE_SAMPLER:
1690 break;
1691 case TGSI_FILE_ADDRESS:
1692 r = pc->addr[src->Register.Index * 4 + c];
1693 assert(r);
1694 break;
1695 default:
1696 assert(0);
1697 break;
1698 }
1699 break;
1700 default:
1701 assert(0);
1702 break;
1703 }
1704
1705 switch (sgn) {
1706 case TGSI_UTIL_SIGN_KEEP:
1707 break;
1708 case TGSI_UTIL_SIGN_CLEAR:
1709 temp = temp_temp(pc);
1710 emit_abs(pc, temp, r);
1711 r = temp;
1712 break;
1713 case TGSI_UTIL_SIGN_TOGGLE:
1714 if (neg)
1715 r->mod = NV50_MOD_NEG;
1716 else {
1717 temp = temp_temp(pc);
1718 emit_neg(pc, temp, r);
1719 r = temp;
1720 }
1721 break;
1722 case TGSI_UTIL_SIGN_SET:
1723 temp = temp_temp(pc);
1724 emit_cvt(pc, temp, r, -1, CVTOP_ABS, CVT_F32_F32 | CVT_NEG);
1725 r = temp;
1726 break;
1727 default:
1728 assert(0);
1729 break;
1730 }
1731
1732 return r;
1733 }
1734
1735 /* return TRUE for ops that produce only a single result */
1736 static boolean
1737 is_scalar_op(unsigned op)
1738 {
1739 switch (op) {
1740 case TGSI_OPCODE_COS:
1741 case TGSI_OPCODE_DP2:
1742 case TGSI_OPCODE_DP3:
1743 case TGSI_OPCODE_DP4:
1744 case TGSI_OPCODE_DPH:
1745 case TGSI_OPCODE_EX2:
1746 case TGSI_OPCODE_LG2:
1747 case TGSI_OPCODE_POW:
1748 case TGSI_OPCODE_RCP:
1749 case TGSI_OPCODE_RSQ:
1750 case TGSI_OPCODE_SIN:
1751 /*
1752 case TGSI_OPCODE_KIL:
1753 case TGSI_OPCODE_LIT:
1754 case TGSI_OPCODE_SCS:
1755 */
1756 return TRUE;
1757 default:
1758 return FALSE;
1759 }
1760 }
1761
1762 /* Returns a bitmask indicating which dst components depend
1763 * on source s, component c (reverse of nv50_tgsi_src_mask).
1764 */
1765 static unsigned
1766 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
1767 {
1768 if (is_scalar_op(op))
1769 return 0x1;
1770
1771 switch (op) {
1772 case TGSI_OPCODE_DST:
1773 return (1 << c) & (s ? 0xa : 0x6);
1774 case TGSI_OPCODE_XPD:
1775 switch (c) {
1776 case 0: return 0x6;
1777 case 1: return 0x5;
1778 case 2: return 0x3;
1779 case 3: return 0x0;
1780 default:
1781 assert(0);
1782 return 0x0;
1783 }
1784 case TGSI_OPCODE_LIT:
1785 case TGSI_OPCODE_SCS:
1786 case TGSI_OPCODE_TEX:
1787 case TGSI_OPCODE_TXP:
1788 /* these take care of dangerous swizzles themselves */
1789 return 0x0;
1790 case TGSI_OPCODE_IF:
1791 case TGSI_OPCODE_KIL:
1792 /* don't call this function for these ops */
1793 assert(0);
1794 return 0;
1795 default:
1796 /* linear vector instruction */
1797 return (1 << c);
1798 }
1799 }
1800
1801 static INLINE boolean
1802 has_pred(struct nv50_program_exec *e, unsigned cc)
1803 {
1804 if (!is_long(e) || is_immd(e))
1805 return FALSE;
1806 return ((e->inst[1] & 0x780) == (cc << 7));
1807 }
1808
1809 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
1810 * join_at ENDIF
1811 * @p0.eq bra ENDIF
1812 * single_op
1813 * ENDIF: nop.join
1814 */
1815 static boolean
1816 nv50_kill_branch(struct nv50_pc *pc)
1817 {
1818 int lvl = pc->if_lvl;
1819
1820 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
1821 return FALSE;
1822
1823 /* if ccode == 'true', the BRA is from an ELSE and the predicate
1824 * reg may no longer be valid, since we currently always use $p0
1825 */
1826 if (has_pred(pc->if_insn[lvl], 0xf))
1827 return FALSE;
1828 assert(pc->if_insn[lvl] && pc->br_join[lvl]);
1829
1830 /* We'll use the exec allocated for JOIN_AT (as we can't easily
1831 * update prev's next); if exec_tail is BRK, update the pointer.
1832 */
1833 if (pc->loop_lvl && pc->br_loop[pc->loop_lvl - 1] == pc->p->exec_tail)
1834 pc->br_loop[pc->loop_lvl - 1] = pc->br_join[lvl];
1835
1836 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
1837
1838 *pc->br_join[lvl] = *pc->p->exec_tail;
1839
1840 FREE(pc->if_insn[lvl]);
1841 FREE(pc->p->exec_tail);
1842
1843 pc->p->exec_tail = pc->br_join[lvl];
1844 pc->p->exec_tail->next = NULL;
1845 set_pred(pc, 0xd, 0, pc->p->exec_tail);
1846
1847 return TRUE;
1848 }
1849
1850 static boolean
1851 nv50_program_tx_insn(struct nv50_pc *pc,
1852 const struct tgsi_full_instruction *inst)
1853 {
1854 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
1855 unsigned mask, sat, unit;
1856 int i, c;
1857
1858 mask = inst->Dst[0].Register.WriteMask;
1859 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
1860
1861 memset(src, 0, sizeof(src));
1862
1863 for (c = 0; c < 4; c++) {
1864 if ((mask & (1 << c)) && !pc->r_dst[c])
1865 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
1866 else
1867 dst[c] = pc->r_dst[c];
1868 rdst[c] = dst[c];
1869 }
1870
1871 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1872 const struct tgsi_full_src_register *fs = &inst->Src[i];
1873 unsigned src_mask;
1874 boolean neg_supp;
1875
1876 src_mask = nv50_tgsi_src_mask(inst, i);
1877 neg_supp = negate_supported(inst, i);
1878
1879 if (fs->Register.File == TGSI_FILE_SAMPLER)
1880 unit = fs->Register.Index;
1881
1882 for (c = 0; c < 4; c++)
1883 if (src_mask & (1 << c))
1884 src[i][c] = reg_instance(pc,
1885 tgsi_src(pc, c, fs, neg_supp));
1886 }
1887
1888 brdc = temp = pc->r_brdc;
1889 if (brdc && brdc->type != P_TEMP) {
1890 temp = temp_temp(pc);
1891 if (sat)
1892 brdc = temp;
1893 } else
1894 if (sat) {
1895 for (c = 0; c < 4; c++) {
1896 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
1897 continue;
1898 /* rdst[c] = dst[c]; */ /* done above */
1899 dst[c] = temp_temp(pc);
1900 }
1901 }
1902
1903 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
1904
1905 switch (inst->Instruction.Opcode) {
1906 case TGSI_OPCODE_ABS:
1907 for (c = 0; c < 4; c++) {
1908 if (!(mask & (1 << c)))
1909 continue;
1910 emit_abs(pc, dst[c], src[0][c]);
1911 }
1912 break;
1913 case TGSI_OPCODE_ADD:
1914 for (c = 0; c < 4; c++) {
1915 if (!(mask & (1 << c)))
1916 continue;
1917 emit_add(pc, dst[c], src[0][c], src[1][c]);
1918 }
1919 break;
1920 case TGSI_OPCODE_AND:
1921 case TGSI_OPCODE_XOR:
1922 case TGSI_OPCODE_OR:
1923 for (c = 0; c < 4; c++) {
1924 if (!(mask & (1 << c)))
1925 continue;
1926 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
1927 inst->Instruction.Opcode);
1928 }
1929 break;
1930 case TGSI_OPCODE_ARL:
1931 assert(src[0][0]);
1932 temp = temp_temp(pc);
1933 emit_cvt(pc, temp, src[0][0], -1, CVTOP_FLOOR, CVT_S32_F32);
1934 emit_arl(pc, dst[0], temp, 4);
1935 break;
1936 case TGSI_OPCODE_BGNLOOP:
1937 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
1938 terminate_mbb(pc);
1939 break;
1940 case TGSI_OPCODE_BRK:
1941 emit_branch(pc, -1, 0, NULL);
1942 assert(pc->loop_lvl > 0);
1943 pc->br_loop[pc->loop_lvl - 1] = pc->p->exec_tail;
1944 break;
1945 case TGSI_OPCODE_CEIL:
1946 for (c = 0; c < 4; c++) {
1947 if (!(mask & (1 << c)))
1948 continue;
1949 emit_cvt(pc, dst[c], src[0][c], -1,
1950 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
1951 }
1952 break;
1953 case TGSI_OPCODE_CMP:
1954 pc->allow32 = FALSE;
1955 for (c = 0; c < 4; c++) {
1956 if (!(mask & (1 << c)))
1957 continue;
1958 emit_cvt(pc, NULL, src[0][c], 1, CVTOP_RN, CVT_F32_F32);
1959 emit_mov(pc, dst[c], src[1][c]);
1960 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
1961 emit_mov(pc, dst[c], src[2][c]);
1962 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
1963 }
1964 break;
1965 case TGSI_OPCODE_COS:
1966 if (mask & 8) {
1967 emit_precossin(pc, temp, src[0][3]);
1968 emit_flop(pc, 5, dst[3], temp);
1969 if (!(mask &= 7))
1970 break;
1971 if (temp == dst[3])
1972 temp = brdc = temp_temp(pc);
1973 }
1974 emit_precossin(pc, temp, src[0][0]);
1975 emit_flop(pc, 5, brdc, temp);
1976 break;
1977 case TGSI_OPCODE_DDX:
1978 for (c = 0; c < 4; c++) {
1979 if (!(mask & (1 << c)))
1980 continue;
1981 emit_ddx(pc, dst[c], src[0][c]);
1982 }
1983 break;
1984 case TGSI_OPCODE_DDY:
1985 for (c = 0; c < 4; c++) {
1986 if (!(mask & (1 << c)))
1987 continue;
1988 emit_ddy(pc, dst[c], src[0][c]);
1989 }
1990 break;
1991 case TGSI_OPCODE_DP3:
1992 emit_mul(pc, temp, src[0][0], src[1][0]);
1993 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1994 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
1995 break;
1996 case TGSI_OPCODE_DP4:
1997 emit_mul(pc, temp, src[0][0], src[1][0]);
1998 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1999 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2000 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2001 break;
2002 case TGSI_OPCODE_DPH:
2003 emit_mul(pc, temp, src[0][0], src[1][0]);
2004 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2005 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2006 emit_add(pc, brdc, src[1][3], temp);
2007 break;
2008 case TGSI_OPCODE_DST:
2009 if (mask & (1 << 1))
2010 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2011 if (mask & (1 << 2))
2012 emit_mov(pc, dst[2], src[0][2]);
2013 if (mask & (1 << 3))
2014 emit_mov(pc, dst[3], src[1][3]);
2015 if (mask & (1 << 0))
2016 emit_mov_immdval(pc, dst[0], 1.0f);
2017 break;
2018 case TGSI_OPCODE_ELSE:
2019 emit_branch(pc, -1, 0, NULL);
2020 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2021 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2022 terminate_mbb(pc);
2023 break;
2024 case TGSI_OPCODE_ENDIF:
2025 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2026
2027 /* try to replace branch over 1 insn with a predicated insn */
2028 if (nv50_kill_branch(pc) == TRUE)
2029 break;
2030
2031 if (pc->br_join[pc->if_lvl]) {
2032 pc->br_join[pc->if_lvl]->param.index = pc->p->exec_size;
2033 pc->br_join[pc->if_lvl] = NULL;
2034 }
2035 terminate_mbb(pc);
2036 /* emit a NOP as join point, we could set it on the next
2037 * one, but would have to make sure it is long and !immd
2038 */
2039 emit_nop(pc);
2040 pc->p->exec_tail->inst[1] |= 2;
2041 break;
2042 case TGSI_OPCODE_ENDLOOP:
2043 emit_branch(pc, -1, 0, NULL);
2044 pc->p->exec_tail->param.index = pc->loop_pos[--pc->loop_lvl];
2045 pc->br_loop[pc->loop_lvl]->param.index = pc->p->exec_size;
2046 terminate_mbb(pc);
2047 break;
2048 case TGSI_OPCODE_EX2:
2049 emit_preex2(pc, temp, src[0][0]);
2050 emit_flop(pc, 6, brdc, temp);
2051 break;
2052 case TGSI_OPCODE_FLR:
2053 for (c = 0; c < 4; c++) {
2054 if (!(mask & (1 << c)))
2055 continue;
2056 emit_flr(pc, dst[c], src[0][c]);
2057 }
2058 break;
2059 case TGSI_OPCODE_FRC:
2060 temp = temp_temp(pc);
2061 for (c = 0; c < 4; c++) {
2062 if (!(mask & (1 << c)))
2063 continue;
2064 emit_flr(pc, temp, src[0][c]);
2065 emit_sub(pc, dst[c], src[0][c], temp);
2066 }
2067 break;
2068 case TGSI_OPCODE_IF:
2069 /* emitting a join_at may not be necessary */
2070 assert(pc->if_lvl < MAX_IF_DEPTH);
2071 /* set_pred_wr(pc, 1, 0, pc->if_cond); */
2072 emit_cvt(pc, NULL, src[0][0], 0, CVTOP_ABS | CVTOP_RN,
2073 CVT_F32_F32);
2074 emit_branch(pc, 0, 2, &pc->br_join[pc->if_lvl]);
2075 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2076 terminate_mbb(pc);
2077 break;
2078 case TGSI_OPCODE_KIL:
2079 emit_kil(pc, src[0][0]);
2080 emit_kil(pc, src[0][1]);
2081 emit_kil(pc, src[0][2]);
2082 emit_kil(pc, src[0][3]);
2083 break;
2084 case TGSI_OPCODE_LIT:
2085 emit_lit(pc, &dst[0], mask, &src[0][0]);
2086 break;
2087 case TGSI_OPCODE_LG2:
2088 emit_flop(pc, 3, brdc, src[0][0]);
2089 break;
2090 case TGSI_OPCODE_LRP:
2091 temp = temp_temp(pc);
2092 for (c = 0; c < 4; c++) {
2093 if (!(mask & (1 << c)))
2094 continue;
2095 emit_sub(pc, temp, src[1][c], src[2][c]);
2096 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2097 }
2098 break;
2099 case TGSI_OPCODE_MAD:
2100 for (c = 0; c < 4; c++) {
2101 if (!(mask & (1 << c)))
2102 continue;
2103 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2104 }
2105 break;
2106 case TGSI_OPCODE_MAX:
2107 for (c = 0; c < 4; c++) {
2108 if (!(mask & (1 << c)))
2109 continue;
2110 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
2111 }
2112 break;
2113 case TGSI_OPCODE_MIN:
2114 for (c = 0; c < 4; c++) {
2115 if (!(mask & (1 << c)))
2116 continue;
2117 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
2118 }
2119 break;
2120 case TGSI_OPCODE_MOV:
2121 for (c = 0; c < 4; c++) {
2122 if (!(mask & (1 << c)))
2123 continue;
2124 emit_mov(pc, dst[c], src[0][c]);
2125 }
2126 break;
2127 case TGSI_OPCODE_MUL:
2128 for (c = 0; c < 4; c++) {
2129 if (!(mask & (1 << c)))
2130 continue;
2131 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2132 }
2133 break;
2134 case TGSI_OPCODE_POW:
2135 emit_pow(pc, brdc, src[0][0], src[1][0]);
2136 break;
2137 case TGSI_OPCODE_RCP:
2138 emit_flop(pc, 0, brdc, src[0][0]);
2139 break;
2140 case TGSI_OPCODE_RSQ:
2141 emit_flop(pc, 2, brdc, src[0][0]);
2142 break;
2143 case TGSI_OPCODE_SCS:
2144 temp = temp_temp(pc);
2145 if (mask & 3)
2146 emit_precossin(pc, temp, src[0][0]);
2147 if (mask & (1 << 0))
2148 emit_flop(pc, 5, dst[0], temp);
2149 if (mask & (1 << 1))
2150 emit_flop(pc, 4, dst[1], temp);
2151 if (mask & (1 << 2))
2152 emit_mov_immdval(pc, dst[2], 0.0);
2153 if (mask & (1 << 3))
2154 emit_mov_immdval(pc, dst[3], 1.0);
2155 break;
2156 case TGSI_OPCODE_SIN:
2157 if (mask & 8) {
2158 emit_precossin(pc, temp, src[0][3]);
2159 emit_flop(pc, 4, dst[3], temp);
2160 if (!(mask &= 7))
2161 break;
2162 if (temp == dst[3])
2163 temp = brdc = temp_temp(pc);
2164 }
2165 emit_precossin(pc, temp, src[0][0]);
2166 emit_flop(pc, 4, brdc, temp);
2167 break;
2168 case TGSI_OPCODE_SLT:
2169 case TGSI_OPCODE_SGE:
2170 case TGSI_OPCODE_SEQ:
2171 case TGSI_OPCODE_SGT:
2172 case TGSI_OPCODE_SLE:
2173 case TGSI_OPCODE_SNE:
2174 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
2175 for (c = 0; c < 4; c++) {
2176 if (!(mask & (1 << c)))
2177 continue;
2178 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
2179 }
2180 break;
2181 case TGSI_OPCODE_SUB:
2182 for (c = 0; c < 4; c++) {
2183 if (!(mask & (1 << c)))
2184 continue;
2185 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2186 }
2187 break;
2188 case TGSI_OPCODE_TEX:
2189 emit_tex(pc, dst, mask, src[0], unit,
2190 inst->Texture.Texture, FALSE);
2191 break;
2192 case TGSI_OPCODE_TXP:
2193 emit_tex(pc, dst, mask, src[0], unit,
2194 inst->Texture.Texture, TRUE);
2195 break;
2196 case TGSI_OPCODE_TRUNC:
2197 for (c = 0; c < 4; c++) {
2198 if (!(mask & (1 << c)))
2199 continue;
2200 emit_cvt(pc, dst[c], src[0][c], -1,
2201 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
2202 }
2203 break;
2204 case TGSI_OPCODE_XPD:
2205 temp = temp_temp(pc);
2206 if (mask & (1 << 0)) {
2207 emit_mul(pc, temp, src[0][2], src[1][1]);
2208 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2209 }
2210 if (mask & (1 << 1)) {
2211 emit_mul(pc, temp, src[0][0], src[1][2]);
2212 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2213 }
2214 if (mask & (1 << 2)) {
2215 emit_mul(pc, temp, src[0][1], src[1][0]);
2216 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2217 }
2218 if (mask & (1 << 3))
2219 emit_mov_immdval(pc, dst[3], 1.0);
2220 break;
2221 case TGSI_OPCODE_END:
2222 break;
2223 default:
2224 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2225 return FALSE;
2226 }
2227
2228 if (brdc) {
2229 if (sat)
2230 emit_sat(pc, brdc, brdc);
2231 for (c = 0; c < 4; c++)
2232 if ((mask & (1 << c)) && dst[c] != brdc)
2233 emit_mov(pc, dst[c], brdc);
2234 } else
2235 if (sat) {
2236 for (c = 0; c < 4; c++) {
2237 if (!(mask & (1 << c)))
2238 continue;
2239 /* In this case we saturate later, and dst[c] won't
2240 * be another temp_temp (and thus lost), since rdst
2241 * already is TEMP (see above). */
2242 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2243 continue;
2244 emit_sat(pc, rdst[c], dst[c]);
2245 }
2246 }
2247
2248 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2249 for (c = 0; c < 4; c++) {
2250 if (!src[i][c])
2251 continue;
2252 if (src[i][c]->acc < 0 && src[i][c]->type == P_CONST)
2253 FREE(src[i][c]); /* indirect constant */
2254 }
2255 }
2256
2257 kill_temp_temp(pc);
2258 pc->reg_instance_nr = 0;
2259
2260 return TRUE;
2261 }
2262
2263 static void
2264 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2265 {
2266 struct nv50_reg *reg = NULL;
2267 const struct tgsi_full_src_register *src;
2268 const struct tgsi_dst_register *dst;
2269 unsigned i, c, k, mask;
2270
2271 dst = &insn->Dst[0].Register;
2272 mask = dst->WriteMask;
2273
2274 if (dst->File == TGSI_FILE_TEMPORARY)
2275 reg = pc->temp;
2276 else
2277 if (dst->File == TGSI_FILE_OUTPUT)
2278 reg = pc->result;
2279
2280 if (reg) {
2281 for (c = 0; c < 4; c++) {
2282 if (!(mask & (1 << c)))
2283 continue;
2284 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2285 }
2286 }
2287
2288 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2289 src = &insn->Src[i];
2290
2291 if (src->Register.File == TGSI_FILE_TEMPORARY)
2292 reg = pc->temp;
2293 else
2294 if (src->Register.File == TGSI_FILE_INPUT)
2295 reg = pc->attr;
2296 else
2297 continue;
2298
2299 mask = nv50_tgsi_src_mask(insn, i);
2300
2301 for (c = 0; c < 4; c++) {
2302 if (!(mask & (1 << c)))
2303 continue;
2304 k = tgsi_util_get_full_src_register_swizzle(src, c);
2305
2306 reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
2307 }
2308 }
2309 }
2310
2311 /* Returns a bitmask indicating which dst components need to be
2312 * written to temporaries first to avoid 'corrupting' sources.
2313 *
2314 * m[i] (out) indicate component to write in the i-th position
2315 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2316 */
2317 static unsigned
2318 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2319 {
2320 unsigned i, c, x, unsafe;
2321
2322 for (c = 0; c < 4; c++)
2323 m[c] = c;
2324
2325 /* Swap as long as a dst component written earlier is depended on
2326 * by one written later, but the next one isn't depended on by it.
2327 */
2328 for (c = 0; c < 3; c++) {
2329 if (rdep[m[c + 1]] & (1 << m[c]))
2330 continue; /* if next one is depended on by us */
2331 for (i = c + 1; i < 4; i++)
2332 /* if we are depended on by a later one */
2333 if (rdep[m[c]] & (1 << m[i]))
2334 break;
2335 if (i == 4)
2336 continue;
2337 /* now, swap */
2338 x = m[c];
2339 m[c] = m[c + 1];
2340 m[c + 1] = x;
2341
2342 /* restart */
2343 c = 0;
2344 }
2345
2346 /* mark dependencies that could not be resolved by reordering */
2347 for (i = 0; i < 3; ++i)
2348 for (c = i + 1; c < 4; ++c)
2349 if (rdep[m[i]] & (1 << m[c]))
2350 unsafe |= (1 << i);
2351
2352 /* NOTE: $unsafe is with respect to order, not component */
2353 return unsafe;
2354 }
2355
2356 /* Select a suitable dst register for broadcasting scalar results,
2357 * or return NULL if we have to allocate an extra TEMP.
2358 *
2359 * If e.g. only 1 component is written, we may also emit the final
2360 * result to a write-only register.
2361 */
2362 static struct nv50_reg *
2363 tgsi_broadcast_dst(struct nv50_pc *pc,
2364 const struct tgsi_full_dst_register *fd, unsigned mask)
2365 {
2366 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
2367 int c = ffs(~mask & fd->Register.WriteMask);
2368 if (c)
2369 return tgsi_dst(pc, c - 1, fd);
2370 } else {
2371 int c = ffs(fd->Register.WriteMask) - 1;
2372 if ((1 << c) == fd->Register.WriteMask)
2373 return tgsi_dst(pc, c, fd);
2374 }
2375
2376 return NULL;
2377 }
2378
2379 /* Scan source swizzles and return a bitmask indicating dst regs that
2380 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2381 */
2382 static unsigned
2383 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2384 unsigned rdep[4])
2385 {
2386 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
2387 const struct tgsi_full_src_register *fs;
2388 unsigned i, deqs = 0;
2389
2390 for (i = 0; i < 4; ++i)
2391 rdep[i] = 0;
2392
2393 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2394 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2395 boolean neg_supp = negate_supported(insn, i);
2396
2397 fs = &insn->Src[i];
2398 if (fs->Register.File != fd->Register.File ||
2399 fs->Register.Index != fd->Register.Index)
2400 continue;
2401
2402 for (chn = 0; chn < 4; ++chn) {
2403 unsigned s, c;
2404
2405 if (!(mask & (1 << chn))) /* src is not read */
2406 continue;
2407 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2408 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2409
2410 if (!(fd->Register.WriteMask & (1 << c)))
2411 continue;
2412
2413 /* no danger if src is copied to TEMP first */
2414 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2415 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2416 continue;
2417
2418 rdep[c] |= nv50_tgsi_dst_revdep(
2419 insn->Instruction.Opcode, i, chn);
2420 deqs |= (1 << c);
2421 }
2422 }
2423
2424 return deqs;
2425 }
2426
2427 static boolean
2428 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2429 {
2430 struct tgsi_full_instruction insn = tok->FullInstruction;
2431 const struct tgsi_full_dst_register *fd;
2432 unsigned i, deqs, rdep[4], m[4];
2433
2434 fd = &tok->FullInstruction.Dst[0];
2435 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2436
2437 if (is_scalar_op(insn.Instruction.Opcode)) {
2438 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2439 if (!pc->r_brdc)
2440 pc->r_brdc = temp_temp(pc);
2441 return nv50_program_tx_insn(pc, &insn);
2442 }
2443 pc->r_brdc = NULL;
2444
2445 if (!deqs)
2446 return nv50_program_tx_insn(pc, &insn);
2447
2448 deqs = nv50_revdep_reorder(m, rdep);
2449
2450 for (i = 0; i < 4; ++i) {
2451 assert(pc->r_dst[m[i]] == NULL);
2452
2453 insn.Dst[0].Register.WriteMask =
2454 fd->Register.WriteMask & (1 << m[i]);
2455
2456 if (!insn.Dst[0].Register.WriteMask)
2457 continue;
2458
2459 if (deqs & (1 << i))
2460 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2461
2462 if (!nv50_program_tx_insn(pc, &insn))
2463 return FALSE;
2464 }
2465
2466 for (i = 0; i < 4; i++) {
2467 struct nv50_reg *reg = pc->r_dst[i];
2468 if (!reg)
2469 continue;
2470 pc->r_dst[i] = NULL;
2471
2472 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2473 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2474 else
2475 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2476 free_temp(pc, reg);
2477 }
2478
2479 return TRUE;
2480 }
2481
2482 static void
2483 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2484 {
2485 struct nv50_reg *iv, **ppiv;
2486 unsigned mode = pc->interp_mode[reg->index];
2487
2488 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2489 iv = *ppiv;
2490
2491 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2492 iv = *ppiv = alloc_temp(pc, NULL);
2493 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2494
2495 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2496 emit_flop(pc, 0, iv, iv);
2497
2498 /* XXX: when loading interpolants dynamically, move these
2499 * to the program head, or make sure it can't be skipped.
2500 */
2501 }
2502
2503 emit_interp(pc, reg, iv, mode);
2504 }
2505
2506 /* The face input is always at v[255] (varying space), with a
2507 * value of 0 for back-facing, and 0xffffffff for front-facing.
2508 */
2509 static void
2510 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
2511 {
2512 struct nv50_reg *one = alloc_immd(pc, 1.0f);
2513
2514 assert(a->rhw == -1);
2515 alloc_reg(pc, a); /* do this before rhw is set */
2516 a->rhw = 255;
2517 load_interpolant(pc, a);
2518 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
2519
2520 FREE(one);
2521 }
2522
2523 static boolean
2524 nv50_program_tx_prep(struct nv50_pc *pc)
2525 {
2526 struct tgsi_parse_context tp;
2527 struct nv50_program *p = pc->p;
2528 boolean ret = FALSE;
2529 unsigned i, c, flat_nr = 0;
2530
2531 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2532 while (!tgsi_parse_end_of_tokens(&tp)) {
2533 const union tgsi_full_token *tok = &tp.FullToken;
2534
2535 tgsi_parse_token(&tp);
2536 switch (tok->Token.Type) {
2537 case TGSI_TOKEN_TYPE_IMMEDIATE:
2538 {
2539 const struct tgsi_full_immediate *imm =
2540 &tp.FullToken.FullImmediate;
2541
2542 ctor_immd(pc, imm->u[0].Float,
2543 imm->u[1].Float,
2544 imm->u[2].Float,
2545 imm->u[3].Float);
2546 }
2547 break;
2548 case TGSI_TOKEN_TYPE_DECLARATION:
2549 {
2550 const struct tgsi_full_declaration *d;
2551 unsigned si, last, first, mode;
2552
2553 d = &tp.FullToken.FullDeclaration;
2554 first = d->Range.First;
2555 last = d->Range.Last;
2556
2557 switch (d->Declaration.File) {
2558 case TGSI_FILE_TEMPORARY:
2559 break;
2560 case TGSI_FILE_OUTPUT:
2561 if (!d->Declaration.Semantic ||
2562 p->type == PIPE_SHADER_FRAGMENT)
2563 break;
2564
2565 si = d->Semantic.Index;
2566 switch (d->Semantic.Name) {
2567 case TGSI_SEMANTIC_BCOLOR:
2568 p->cfg.two_side[si].hw = first;
2569 if (p->cfg.io_nr > first)
2570 p->cfg.io_nr = first;
2571 break;
2572 case TGSI_SEMANTIC_PSIZE:
2573 p->cfg.psiz = first;
2574 if (p->cfg.io_nr > first)
2575 p->cfg.io_nr = first;
2576 break;
2577 /*
2578 case TGSI_SEMANTIC_CLIP_DISTANCE:
2579 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2580 break;
2581 */
2582 default:
2583 break;
2584 }
2585 break;
2586 case TGSI_FILE_INPUT:
2587 {
2588 if (p->type != PIPE_SHADER_FRAGMENT)
2589 break;
2590
2591 switch (d->Declaration.Interpolate) {
2592 case TGSI_INTERPOLATE_CONSTANT:
2593 mode = INTERP_FLAT;
2594 flat_nr++;
2595 break;
2596 case TGSI_INTERPOLATE_PERSPECTIVE:
2597 mode = INTERP_PERSPECTIVE;
2598 p->cfg.regs[1] |= 0x08 << 24;
2599 break;
2600 default:
2601 mode = INTERP_LINEAR;
2602 break;
2603 }
2604 if (d->Declaration.Centroid)
2605 mode |= INTERP_CENTROID;
2606
2607 assert(last < 32);
2608 for (i = first; i <= last; i++)
2609 pc->interp_mode[i] = mode;
2610 }
2611 break;
2612 case TGSI_FILE_ADDRESS:
2613 case TGSI_FILE_CONSTANT:
2614 case TGSI_FILE_SAMPLER:
2615 break;
2616 default:
2617 NOUVEAU_ERR("bad decl file %d\n",
2618 d->Declaration.File);
2619 goto out_err;
2620 }
2621 }
2622 break;
2623 case TGSI_TOKEN_TYPE_INSTRUCTION:
2624 pc->insn_nr++;
2625 prep_inspect_insn(pc, &tok->FullInstruction);
2626 break;
2627 default:
2628 break;
2629 }
2630 }
2631
2632 if (p->type == PIPE_SHADER_VERTEX) {
2633 int rid = 0;
2634
2635 for (i = 0; i < pc->attr_nr * 4; ++i) {
2636 if (pc->attr[i].acc) {
2637 pc->attr[i].hw = rid++;
2638 p->cfg.attr[i / 32] |= 1 << (i % 32);
2639 }
2640 }
2641
2642 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
2643 p->cfg.io[i].hw = rid;
2644 p->cfg.io[i].id = i;
2645
2646 for (c = 0; c < 4; ++c) {
2647 int n = i * 4 + c;
2648 if (!pc->result[n].acc)
2649 continue;
2650 pc->result[n].hw = rid++;
2651 p->cfg.io[i].mask |= 1 << c;
2652 }
2653 }
2654
2655 for (c = 0; c < 2; ++c)
2656 if (p->cfg.two_side[c].hw < 0x40)
2657 p->cfg.two_side[c] = p->cfg.io[
2658 p->cfg.two_side[c].hw];
2659
2660 if (p->cfg.psiz < 0x40)
2661 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
2662 } else
2663 if (p->type == PIPE_SHADER_FRAGMENT) {
2664 int rid, aid;
2665 unsigned n = 0, m = pc->attr_nr - flat_nr;
2666
2667 pc->allow32 = TRUE;
2668
2669 int base = (TGSI_SEMANTIC_POSITION ==
2670 p->info.input_semantic_name[0]) ? 0 : 1;
2671
2672 /* non-flat interpolants have to be mapped to
2673 * the lower hardware IDs, so sort them:
2674 */
2675 for (i = 0; i < pc->attr_nr; i++) {
2676 if (pc->interp_mode[i] == INTERP_FLAT)
2677 p->cfg.io[m++].id = i;
2678 else {
2679 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
2680 p->cfg.io[n].linear = TRUE;
2681 p->cfg.io[n++].id = i;
2682 }
2683 }
2684
2685 if (!base) /* set w-coordinate mask from perspective interp */
2686 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
2687
2688 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
2689 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
2690
2691 for (n = 0; n < pc->attr_nr; ++n) {
2692 p->cfg.io[n].hw = rid = aid;
2693 i = p->cfg.io[n].id;
2694
2695 if (p->info.input_semantic_name[n] ==
2696 TGSI_SEMANTIC_FACE) {
2697 load_frontfacing(pc, &pc->attr[i * 4]);
2698 continue;
2699 }
2700
2701 for (c = 0; c < 4; ++c) {
2702 if (!pc->attr[i * 4 + c].acc)
2703 continue;
2704 pc->attr[i * 4 + c].rhw = rid++;
2705 p->cfg.io[n].mask |= 1 << c;
2706
2707 load_interpolant(pc, &pc->attr[i * 4 + c]);
2708 }
2709 aid += popcnt4(p->cfg.io[n].mask);
2710 }
2711
2712 if (!base)
2713 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
2714
2715 m = popcnt4(p->cfg.regs[1] >> 24);
2716
2717 /* set count of non-position inputs and of non-flat
2718 * non-position inputs for FP_INTERPOLANT_CTRL
2719 */
2720 p->cfg.regs[1] |= aid - m;
2721
2722 if (flat_nr) {
2723 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
2724 p->cfg.regs[1] |= (i - m) << 16;
2725 } else
2726 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
2727
2728 /* mark color semantic for light-twoside */
2729 n = 0x40;
2730 for (i = 0; i < pc->attr_nr; i++) {
2731 ubyte si, sn;
2732
2733 sn = p->info.input_semantic_name[p->cfg.io[i].id];
2734 si = p->info.input_semantic_index[p->cfg.io[i].id];
2735
2736 if (sn == TGSI_SEMANTIC_COLOR) {
2737 p->cfg.two_side[si] = p->cfg.io[i];
2738
2739 /* increase colour count */
2740 p->cfg.regs[0] += popcnt4(
2741 p->cfg.two_side[si].mask) << 16;
2742
2743 n = MIN2(n, p->cfg.io[i].hw - m);
2744 }
2745 }
2746 if (n < 0x40)
2747 p->cfg.regs[0] += n;
2748
2749 /* Initialize FP results:
2750 * FragDepth is always first TGSI and last hw output
2751 */
2752 i = p->info.writes_z ? 4 : 0;
2753 for (rid = 0; i < pc->result_nr * 4; i++)
2754 pc->result[i].rhw = rid++;
2755 if (p->info.writes_z)
2756 pc->result[2].rhw = rid;
2757
2758 p->cfg.high_result = rid;
2759
2760 /* separate/different colour results for MRTs ? */
2761 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
2762 p->cfg.regs[2] |= 1;
2763 }
2764
2765 if (pc->immd_nr) {
2766 int rid = 0;
2767
2768 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
2769 if (!pc->immd)
2770 goto out_err;
2771
2772 for (i = 0; i < pc->immd_nr; i++) {
2773 for (c = 0; c < 4; c++, rid++)
2774 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
2775 }
2776 }
2777
2778 ret = TRUE;
2779 out_err:
2780 if (pc->iv_p)
2781 free_temp(pc, pc->iv_p);
2782 if (pc->iv_c)
2783 free_temp(pc, pc->iv_c);
2784
2785 tgsi_parse_free(&tp);
2786 return ret;
2787 }
2788
2789 static void
2790 free_nv50_pc(struct nv50_pc *pc)
2791 {
2792 if (pc->immd)
2793 FREE(pc->immd);
2794 if (pc->param)
2795 FREE(pc->param);
2796 if (pc->result)
2797 FREE(pc->result);
2798 if (pc->attr)
2799 FREE(pc->attr);
2800 if (pc->temp)
2801 FREE(pc->temp);
2802
2803 FREE(pc);
2804 }
2805
2806 static boolean
2807 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
2808 {
2809 int i, c;
2810 unsigned rtype[2] = { P_ATTR, P_RESULT };
2811
2812 pc->p = p;
2813 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
2814 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
2815 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
2816 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
2817 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
2818 assert(pc->addr_nr <= 2);
2819
2820 p->cfg.high_temp = 4;
2821
2822 p->cfg.two_side[0].hw = 0x40;
2823 p->cfg.two_side[1].hw = 0x40;
2824
2825 switch (p->type) {
2826 case PIPE_SHADER_VERTEX:
2827 p->cfg.psiz = 0x40;
2828 p->cfg.clpd = 0x40;
2829 p->cfg.io_nr = pc->result_nr;
2830 break;
2831 case PIPE_SHADER_FRAGMENT:
2832 rtype[0] = rtype[1] = P_TEMP;
2833
2834 p->cfg.regs[0] = 0x01000004;
2835 p->cfg.io_nr = pc->attr_nr;
2836
2837 if (p->info.writes_z) {
2838 p->cfg.regs[2] |= 0x00000100;
2839 p->cfg.regs[3] |= 0x00000011;
2840 }
2841 if (p->info.uses_kill)
2842 p->cfg.regs[2] |= 0x00100000;
2843 break;
2844 }
2845
2846 if (pc->temp_nr) {
2847 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
2848 if (!pc->temp)
2849 return FALSE;
2850
2851 for (i = 0; i < pc->temp_nr * 4; ++i)
2852 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
2853 }
2854
2855 if (pc->attr_nr) {
2856 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
2857 if (!pc->attr)
2858 return FALSE;
2859
2860 for (i = 0; i < pc->attr_nr * 4; ++i)
2861 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
2862 }
2863
2864 if (pc->result_nr) {
2865 unsigned nr = pc->result_nr * 4;
2866
2867 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
2868 if (!pc->result)
2869 return FALSE;
2870
2871 for (i = 0; i < nr; ++i)
2872 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
2873 }
2874
2875 if (pc->param_nr) {
2876 int rid = 0;
2877
2878 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
2879 if (!pc->param)
2880 return FALSE;
2881
2882 for (i = 0; i < pc->param_nr; ++i)
2883 for (c = 0; c < 4; ++c, ++rid)
2884 ctor_reg(&pc->param[rid], P_CONST, i, rid);
2885 }
2886
2887 if (pc->addr_nr) {
2888 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
2889 if (!pc->addr)
2890 return FALSE;
2891 }
2892 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
2893 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
2894
2895 return TRUE;
2896 }
2897
2898 static void
2899 nv50_fp_move_results(struct nv50_pc *pc)
2900 {
2901 struct nv50_reg reg;
2902 unsigned i;
2903
2904 ctor_reg(&reg, P_TEMP, -1, -1);
2905
2906 for (i = 0; i < pc->result_nr * 4; ++i) {
2907 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2908 continue;
2909 if (pc->result[i].rhw != pc->result[i].hw) {
2910 reg.hw = pc->result[i].rhw;
2911 emit_mov(pc, &reg, &pc->result[i]);
2912 }
2913 }
2914 }
2915
2916 static void
2917 nv50_program_fixup_insns(struct nv50_pc *pc)
2918 {
2919 struct nv50_program_exec *e, **bra_list;
2920 unsigned i, n, pos;
2921
2922 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
2923
2924 /* Collect branch instructions, we need to adjust their offsets
2925 * when converting 32 bit instructions to 64 bit ones
2926 */
2927 for (n = 0, e = pc->p->exec_head; e; e = e->next)
2928 if (e->param.index >= 0 && !e->param.mask)
2929 bra_list[n++] = e;
2930
2931 /* last instruction must be long so it can have the exit bit set */
2932 if (!is_long(pc->p->exec_tail))
2933 convert_to_long(pc, pc->p->exec_tail);
2934 /* set exit bit */
2935 pc->p->exec_tail->inst[1] |= 1;
2936
2937 /* !immd on exit insn simultaneously means !join */
2938 assert(!is_immd(pc->p->exec_head));
2939 assert(!is_immd(pc->p->exec_tail));
2940
2941 /* Make sure we don't have any single 32 bit instructions. */
2942 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
2943 pos += is_long(e) ? 2 : 1;
2944
2945 if ((pos & 1) && (!e->next || is_long(e->next))) {
2946 for (i = 0; i < n; ++i)
2947 if (bra_list[i]->param.index >= pos)
2948 bra_list[i]->param.index += 1;
2949 convert_to_long(pc, e);
2950 ++pos;
2951 }
2952 }
2953
2954 FREE(bra_list);
2955 }
2956
2957 static boolean
2958 nv50_program_tx(struct nv50_program *p)
2959 {
2960 struct tgsi_parse_context parse;
2961 struct nv50_pc *pc;
2962 boolean ret;
2963
2964 pc = CALLOC_STRUCT(nv50_pc);
2965 if (!pc)
2966 return FALSE;
2967
2968 ret = ctor_nv50_pc(pc, p);
2969 if (ret == FALSE)
2970 goto out_cleanup;
2971
2972 ret = nv50_program_tx_prep(pc);
2973 if (ret == FALSE)
2974 goto out_cleanup;
2975
2976 tgsi_parse_init(&parse, pc->p->pipe.tokens);
2977 while (!tgsi_parse_end_of_tokens(&parse)) {
2978 const union tgsi_full_token *tok = &parse.FullToken;
2979
2980 /* don't allow half insn/immd on first and last instruction */
2981 pc->allow32 = TRUE;
2982 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr)
2983 pc->allow32 = FALSE;
2984
2985 tgsi_parse_token(&parse);
2986
2987 switch (tok->Token.Type) {
2988 case TGSI_TOKEN_TYPE_INSTRUCTION:
2989 ++pc->insn_cur;
2990 ret = nv50_tgsi_insn(pc, tok);
2991 if (ret == FALSE)
2992 goto out_err;
2993 break;
2994 default:
2995 break;
2996 }
2997 }
2998
2999 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3000 nv50_fp_move_results(pc);
3001
3002 nv50_program_fixup_insns(pc);
3003
3004 p->param_nr = pc->param_nr * 4;
3005 p->immd_nr = pc->immd_nr * 4;
3006 p->immd = pc->immd_buf;
3007
3008 out_err:
3009 tgsi_parse_free(&parse);
3010
3011 out_cleanup:
3012 free_nv50_pc(pc);
3013 return ret;
3014 }
3015
3016 static void
3017 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3018 {
3019 if (nv50_program_tx(p) == FALSE)
3020 assert(0);
3021 p->translated = TRUE;
3022 }
3023
3024 static void
3025 nv50_program_upload_data(struct nv50_context *nv50, float *map,
3026 unsigned start, unsigned count, unsigned cbuf)
3027 {
3028 struct nouveau_channel *chan = nv50->screen->base.channel;
3029 struct nouveau_grobj *tesla = nv50->screen->tesla;
3030
3031 while (count) {
3032 unsigned nr = count > 2047 ? 2047 : count;
3033
3034 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3035 OUT_RING (chan, (cbuf << 0) | (start << 8));
3036 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3037 OUT_RINGp (chan, map, nr);
3038
3039 map += nr;
3040 start += nr;
3041 count -= nr;
3042 }
3043 }
3044
3045 static void
3046 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3047 {
3048 struct pipe_screen *pscreen = nv50->pipe.screen;
3049
3050 if (!p->data[0] && p->immd_nr) {
3051 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3052
3053 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3054 while (heap->next && heap->size < p->immd_nr) {
3055 struct nv50_program *evict = heap->next->priv;
3056 nouveau_resource_free(&evict->data[0]);
3057 }
3058
3059 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3060 &p->data[0]))
3061 assert(0);
3062 }
3063
3064 /* immediates only need to be uploaded again when freed */
3065 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3066 p->immd_nr, NV50_CB_PMISC);
3067 }
3068
3069 assert(p->param_nr <= 512);
3070
3071 if (p->param_nr) {
3072 unsigned cb;
3073 float *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3074 PIPE_BUFFER_USAGE_CPU_READ);
3075
3076 if (p->type == PIPE_SHADER_VERTEX)
3077 cb = NV50_CB_PVP;
3078 else
3079 cb = NV50_CB_PFP;
3080
3081 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3082 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3083 }
3084 }
3085
3086 static void
3087 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3088 {
3089 struct nouveau_channel *chan = nv50->screen->base.channel;
3090 struct nv50_program_exec *e;
3091 uint32_t *up, i;
3092 boolean upload = FALSE;
3093
3094 if (!p->bo) {
3095 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3096 p->exec_size * 4, &p->bo);
3097 upload = TRUE;
3098 }
3099
3100 if (p->data[0] && p->data[0]->start != p->data_start[0])
3101 upload = TRUE;
3102
3103 if (!upload)
3104 return;
3105
3106 up = MALLOC(p->exec_size * 4);
3107
3108 for (i = 0, e = p->exec_head; e; e = e->next) {
3109 unsigned ei, ci, bs;
3110
3111 if (e->param.index >= 0 && e->param.mask) {
3112 bs = (e->inst[1] >> 22) & 0x07;
3113 assert(bs < 2);
3114 ei = e->param.shift >> 5;
3115 ci = e->param.index;
3116 if (bs == 0)
3117 ci += p->data[bs]->start;
3118
3119 e->inst[ei] &= ~e->param.mask;
3120 e->inst[ei] |= (ci << e->param.shift);
3121 } else
3122 if (e->param.index >= 0) {
3123 /* zero mask means param is a jump/branch offset */
3124 assert(!(e->param.index & 1));
3125 /* seem to be 8 byte steps */
3126 ei = (e->param.index >> 1) + 0 /* START_ID */;
3127
3128 e->inst[0] &= 0xf0000fff;
3129 e->inst[0] |= ei << 12;
3130 }
3131
3132 up[i++] = e->inst[0];
3133 if (is_long(e))
3134 up[i++] = e->inst[1];
3135 }
3136 assert(i == p->exec_size);
3137
3138 if (p->data[0])
3139 p->data_start[0] = p->data[0]->start;
3140
3141 #ifdef NV50_PROGRAM_DUMP
3142 NOUVEAU_ERR("-------\n");
3143 for (e = p->exec_head; e; e = e->next) {
3144 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3145 if (is_long(e))
3146 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3147 }
3148 #endif
3149 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3150 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3151 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3152 0, 0, p->exec_size * 4, 1, 1);
3153
3154 FREE(up);
3155 }
3156
3157 void
3158 nv50_vertprog_validate(struct nv50_context *nv50)
3159 {
3160 struct nouveau_grobj *tesla = nv50->screen->tesla;
3161 struct nv50_program *p = nv50->vertprog;
3162 struct nouveau_stateobj *so;
3163
3164 if (!p->translated) {
3165 nv50_program_validate(nv50, p);
3166 if (!p->translated)
3167 assert(0);
3168 }
3169
3170 nv50_program_validate_data(nv50, p);
3171 nv50_program_validate_code(nv50, p);
3172
3173 so = so_new(13, 2);
3174 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3175 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3176 NOUVEAU_BO_HIGH, 0, 0);
3177 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3178 NOUVEAU_BO_LOW, 0, 0);
3179 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3180 so_data (so, p->cfg.attr[0]);
3181 so_data (so, p->cfg.attr[1]);
3182 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3183 so_data (so, p->cfg.high_result);
3184 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3185 so_data (so, p->cfg.high_result); //8);
3186 so_data (so, p->cfg.high_temp);
3187 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3188 so_data (so, 0); /* program start offset */
3189 so_ref(so, &nv50->state.vertprog);
3190 so_ref(NULL, &so);
3191 }
3192
3193 void
3194 nv50_fragprog_validate(struct nv50_context *nv50)
3195 {
3196 struct nouveau_grobj *tesla = nv50->screen->tesla;
3197 struct nv50_program *p = nv50->fragprog;
3198 struct nouveau_stateobj *so;
3199
3200 if (!p->translated) {
3201 nv50_program_validate(nv50, p);
3202 if (!p->translated)
3203 assert(0);
3204 }
3205
3206 nv50_program_validate_data(nv50, p);
3207 nv50_program_validate_code(nv50, p);
3208
3209 so = so_new(64, 2);
3210 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3211 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3212 NOUVEAU_BO_HIGH, 0, 0);
3213 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3214 NOUVEAU_BO_LOW, 0, 0);
3215 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3216 so_data (so, p->cfg.high_temp);
3217 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3218 so_data (so, p->cfg.high_result);
3219 so_method(so, tesla, NV50TCL_FP_CTRL_UNK19A8, 1);
3220 so_data (so, p->cfg.regs[2]);
3221 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3222 so_data (so, p->cfg.regs[3]);
3223 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3224 so_data (so, 0); /* program start offset */
3225 so_ref(so, &nv50->state.fragprog);
3226 so_ref(NULL, &so);
3227 }
3228
3229 static void
3230 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3231 {
3232 struct nv50_program *fp = nv50->fragprog;
3233 struct nv50_program *vp = nv50->vertprog;
3234 unsigned i, c, m = base;
3235
3236 /* XXX: this might not work correctly in all cases yet - we'll
3237 * just assume that an FP generic input that is not written in
3238 * the VP is PointCoord.
3239 */
3240 memset(pntc, 0, 8 * sizeof(uint32_t));
3241
3242 for (i = 0; i < fp->cfg.io_nr; i++) {
3243 uint8_t sn, si;
3244 uint8_t j, k = fp->cfg.io[i].id;
3245 unsigned n = popcnt4(fp->cfg.io[i].mask);
3246
3247 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3248 m += n;
3249 continue;
3250 }
3251
3252 for (j = 0; j < vp->info.num_outputs; ++j) {
3253 sn = vp->info.output_semantic_name[j];
3254 si = vp->info.output_semantic_index[j];
3255
3256 if (sn == fp->info.input_semantic_name[k] &&
3257 si == fp->info.input_semantic_index[k])
3258 break;
3259 }
3260
3261 if (j < vp->info.num_outputs) {
3262 ubyte mode =
3263 nv50->rasterizer->pipe.sprite_coord_mode[si];
3264
3265 if (mode == PIPE_SPRITE_COORD_NONE) {
3266 m += n;
3267 continue;
3268 }
3269 }
3270
3271 /* this is either PointCoord or replaced by sprite coords */
3272 for (c = 0; c < 4; c++) {
3273 if (!(fp->cfg.io[i].mask & (1 << c)))
3274 continue;
3275 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3276 ++m;
3277 }
3278 }
3279 }
3280
3281 static int
3282 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3283 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3284 {
3285 int c;
3286 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3287 uint8_t *map = (uint8_t *)p_map;
3288
3289 for (c = 0; c < 4; ++c) {
3290 if (mf & 1) {
3291 if (fpi->linear == TRUE)
3292 lin[mid / 32] |= 1 << (mid % 32);
3293 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3294 }
3295
3296 oid += mv & 1;
3297 mf >>= 1;
3298 mv >>= 1;
3299 }
3300
3301 return mid;
3302 }
3303
3304 void
3305 nv50_linkage_validate(struct nv50_context *nv50)
3306 {
3307 struct nouveau_grobj *tesla = nv50->screen->tesla;
3308 struct nv50_program *vp = nv50->vertprog;
3309 struct nv50_program *fp = nv50->fragprog;
3310 struct nouveau_stateobj *so;
3311 struct nv50_sreg4 dummy, *vpo;
3312 int i, n, c, m = 0;
3313 uint32_t map[16], lin[4], reg[5], pcrd[8];
3314
3315 memset(map, 0, sizeof(map));
3316 memset(lin, 0, sizeof(lin));
3317
3318 reg[1] = 0x00000004; /* low and high clip distance map ids */
3319 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3320 reg[3] = 0x00000000; /* point size map id & enable */
3321 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3322 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3323
3324 dummy.linear = FALSE;
3325 dummy.mask = 0xf; /* map all components of HPOS */
3326 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3327
3328 dummy.mask = 0x0;
3329
3330 if (vp->cfg.clpd < 0x40) {
3331 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3332 map[m++] = vp->cfg.clpd + c;
3333 reg[1] = (m << 8);
3334 }
3335
3336 reg[0] |= m << 8; /* adjust BFC0 id */
3337
3338 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3339 if (nv50->rasterizer->pipe.light_twoside) {
3340 vpo = &vp->cfg.two_side[0];
3341
3342 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3343 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3344 }
3345
3346 reg[0] += m - 4; /* adjust FFC0 id */
3347 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3348
3349 for (i = 0; i < fp->cfg.io_nr; i++) {
3350 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
3351 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
3352
3353 /* position must be mapped first */
3354 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
3355
3356 /* maybe even remove these from cfg.io */
3357 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
3358 continue;
3359
3360 /* VP outputs and vp->cfg.io are in the same order */
3361 for (n = 0; n < vp->info.num_outputs; ++n) {
3362 if (vp->info.output_semantic_name[n] == sn &&
3363 vp->info.output_semantic_index[n] == si)
3364 break;
3365 }
3366 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
3367
3368 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3369 }
3370
3371 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3372 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3373 reg[3] = (m++ << 4) | 1;
3374 }
3375
3376 /* now fill the stateobj */
3377 so = so_new(64, 0);
3378
3379 n = (m + 3) / 4;
3380 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3381 so_data (so, m);
3382 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3383 so_datap (so, map, n);
3384
3385 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3386 so_datap (so, reg, 4);
3387
3388 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3389 so_data (so, reg[4]);
3390
3391 so_method(so, tesla, 0x1540, 4);
3392 so_datap (so, lin, 4);
3393
3394 if (nv50->rasterizer->pipe.point_sprite) {
3395 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3396
3397 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3398 so_datap (so, pcrd, 8);
3399 }
3400
3401 so_ref(so, &nv50->state.programs);
3402 so_ref(NULL, &so);
3403 }
3404
3405 void
3406 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3407 {
3408 while (p->exec_head) {
3409 struct nv50_program_exec *e = p->exec_head;
3410
3411 p->exec_head = e->next;
3412 FREE(e);
3413 }
3414 p->exec_tail = NULL;
3415 p->exec_size = 0;
3416
3417 nouveau_bo_ref(NULL, &p->bo);
3418
3419 nouveau_resource_free(&p->data[0]);
3420
3421 p->translated = 0;
3422 }