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nv50: implement TGSI_OPCODE_AND/OR/XOR
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int neg;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 /* arbitrary limits */
98 #define MAX_IF_DEPTH 4
99 #define MAX_LOOP_DEPTH 4
100
101 struct nv50_pc {
102 struct nv50_program *p;
103
104 /* hw resources */
105 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
106 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
107
108 /* tgsi resources */
109 struct nv50_reg *temp;
110 int temp_nr;
111 struct nv50_reg *attr;
112 int attr_nr;
113 struct nv50_reg *result;
114 int result_nr;
115 struct nv50_reg *param;
116 int param_nr;
117 struct nv50_reg *immd;
118 float *immd_buf;
119 int immd_nr;
120 struct nv50_reg **addr;
121 int addr_nr;
122
123 struct nv50_reg *temp_temp[16];
124 unsigned temp_temp_nr;
125
126 /* broadcast and destination replacement regs */
127 struct nv50_reg *r_brdc;
128 struct nv50_reg *r_dst[4];
129
130 unsigned interp_mode[32];
131 /* perspective interpolation registers */
132 struct nv50_reg *iv_p;
133 struct nv50_reg *iv_c;
134
135 struct nv50_program_exec *if_cond;
136 struct nv50_program_exec *if_insn[MAX_IF_DEPTH];
137 struct nv50_program_exec *br_join[MAX_IF_DEPTH];
138 struct nv50_program_exec *br_loop[MAX_LOOP_DEPTH]; /* for BRK branch */
139 int if_lvl, loop_lvl;
140 unsigned loop_pos[MAX_LOOP_DEPTH];
141
142 /* current instruction and total number of insns */
143 unsigned insn_cur;
144 unsigned insn_nr;
145
146 boolean allow32;
147 };
148
149 static INLINE void
150 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
151 {
152 reg->type = type;
153 reg->index = index;
154 reg->hw = hw;
155 reg->neg = 0;
156 reg->rhw = -1;
157 reg->acc = 0;
158 }
159
160 static INLINE unsigned
161 popcnt4(uint32_t val)
162 {
163 static const unsigned cnt[16]
164 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
165 return cnt[val & 0xf];
166 }
167
168 static void
169 terminate_mbb(struct nv50_pc *pc)
170 {
171 int i;
172
173 /* remove records of temporary address register values */
174 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
175 if (pc->r_addr[i].index < 0)
176 pc->r_addr[i].rhw = -1;
177 }
178
179 static void
180 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
181 {
182 int i = 0;
183
184 if (reg->type == P_RESULT) {
185 if (pc->p->cfg.high_result < (reg->hw + 1))
186 pc->p->cfg.high_result = reg->hw + 1;
187 }
188
189 if (reg->type != P_TEMP)
190 return;
191
192 if (reg->hw >= 0) {
193 /*XXX: do this here too to catch FP temp-as-attr usage..
194 * not clean, but works */
195 if (pc->p->cfg.high_temp < (reg->hw + 1))
196 pc->p->cfg.high_temp = reg->hw + 1;
197 return;
198 }
199
200 if (reg->rhw != -1) {
201 /* try to allocate temporary with index rhw first */
202 if (!(pc->r_temp[reg->rhw])) {
203 pc->r_temp[reg->rhw] = reg;
204 reg->hw = reg->rhw;
205 if (pc->p->cfg.high_temp < (reg->rhw + 1))
206 pc->p->cfg.high_temp = reg->rhw + 1;
207 return;
208 }
209 /* make sure we don't get things like $r0 needs to go
210 * in $r1 and $r1 in $r0
211 */
212 i = pc->result_nr * 4;
213 }
214
215 for (; i < NV50_SU_MAX_TEMP; i++) {
216 if (!(pc->r_temp[i])) {
217 pc->r_temp[i] = reg;
218 reg->hw = i;
219 if (pc->p->cfg.high_temp < (i + 1))
220 pc->p->cfg.high_temp = i + 1;
221 return;
222 }
223 }
224
225 assert(0);
226 }
227
228 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
229 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
230 * lest we risk temp_temps overwriting regs alloc'd "later".
231 */
232 static struct nv50_reg *
233 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
234 {
235 struct nv50_reg *r;
236 int i;
237
238 if (dst && dst->type == P_TEMP && dst->hw == -1)
239 return dst;
240
241 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
242 if (!pc->r_temp[i]) {
243 r = MALLOC_STRUCT(nv50_reg);
244 ctor_reg(r, P_TEMP, -1, i);
245 pc->r_temp[i] = r;
246 return r;
247 }
248 }
249
250 assert(0);
251 return NULL;
252 }
253
254 /* Assign the hw of the discarded temporary register src
255 * to the tgsi register dst and free src.
256 */
257 static void
258 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
259 {
260 assert(src->index == -1 && src->hw != -1);
261
262 if (dst->hw != -1)
263 pc->r_temp[dst->hw] = NULL;
264 pc->r_temp[src->hw] = dst;
265 dst->hw = src->hw;
266
267 FREE(src);
268 }
269
270 /* release the hardware resource held by r */
271 static void
272 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
273 {
274 assert(r->type == P_TEMP);
275 if (r->hw == -1)
276 return;
277
278 assert(pc->r_temp[r->hw] == r);
279 pc->r_temp[r->hw] = NULL;
280
281 r->acc = 0;
282 if (r->index == -1)
283 FREE(r);
284 }
285
286 static void
287 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
288 {
289 if (r->index == -1) {
290 unsigned hw = r->hw;
291
292 FREE(pc->r_temp[hw]);
293 pc->r_temp[hw] = NULL;
294 }
295 }
296
297 static int
298 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
299 {
300 int i;
301
302 if ((idx + 4) >= NV50_SU_MAX_TEMP)
303 return 1;
304
305 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
306 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
307 return alloc_temp4(pc, dst, idx + 4);
308
309 for (i = 0; i < 4; i++) {
310 dst[i] = MALLOC_STRUCT(nv50_reg);
311 ctor_reg(dst[i], P_TEMP, -1, idx + i);
312 pc->r_temp[idx + i] = dst[i];
313 }
314
315 return 0;
316 }
317
318 static void
319 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
320 {
321 int i;
322
323 for (i = 0; i < 4; i++)
324 free_temp(pc, reg[i]);
325 }
326
327 static struct nv50_reg *
328 temp_temp(struct nv50_pc *pc)
329 {
330 if (pc->temp_temp_nr >= 16)
331 assert(0);
332
333 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
334 return pc->temp_temp[pc->temp_temp_nr++];
335 }
336
337 static void
338 kill_temp_temp(struct nv50_pc *pc)
339 {
340 int i;
341
342 for (i = 0; i < pc->temp_temp_nr; i++)
343 free_temp(pc, pc->temp_temp[i]);
344 pc->temp_temp_nr = 0;
345 }
346
347 static int
348 ctor_immd(struct nv50_pc *pc, float x, float y, float z, float w)
349 {
350 pc->immd_buf = REALLOC(pc->immd_buf, (pc->immd_nr * 4 * sizeof(float)),
351 (pc->immd_nr + 1) * 4 * sizeof(float));
352 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
353 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
354 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
355 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
356
357 return pc->immd_nr++;
358 }
359
360 static struct nv50_reg *
361 alloc_immd(struct nv50_pc *pc, float f)
362 {
363 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
364 unsigned hw;
365
366 for (hw = 0; hw < pc->immd_nr * 4; hw++)
367 if (pc->immd_buf[hw] == f)
368 break;
369
370 if (hw == pc->immd_nr * 4)
371 hw = ctor_immd(pc, f, -f, 0.5 * f, 0) * 4;
372
373 ctor_reg(r, P_IMMD, -1, hw);
374 return r;
375 }
376
377 static struct nv50_program_exec *
378 exec(struct nv50_pc *pc)
379 {
380 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
381
382 e->param.index = -1;
383 return e;
384 }
385
386 static void
387 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
388 {
389 struct nv50_program *p = pc->p;
390
391 if (p->exec_tail)
392 p->exec_tail->next = e;
393 if (!p->exec_head)
394 p->exec_head = e;
395 p->exec_tail = e;
396 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
397 }
398
399 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
400
401 static boolean
402 is_long(struct nv50_program_exec *e)
403 {
404 if (e->inst[0] & 1)
405 return TRUE;
406 return FALSE;
407 }
408
409 static boolean
410 is_immd(struct nv50_program_exec *e)
411 {
412 if (is_long(e) && (e->inst[1] & 3) == 3)
413 return TRUE;
414 return FALSE;
415 }
416
417 static INLINE void
418 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
419 struct nv50_program_exec *e)
420 {
421 set_long(pc, e);
422 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
423 e->inst[1] |= (pred << 7) | (idx << 12);
424 }
425
426 static INLINE void
427 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
428 struct nv50_program_exec *e)
429 {
430 set_long(pc, e);
431 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
432 e->inst[1] |= (idx << 4) | (on << 6);
433 }
434
435 static INLINE void
436 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
437 {
438 if (is_long(e))
439 return;
440
441 e->inst[0] |= 1;
442 set_pred(pc, 0xf, 0, e);
443 set_pred_wr(pc, 0, 0, e);
444 }
445
446 static INLINE void
447 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
448 {
449 if (dst->type == P_RESULT) {
450 set_long(pc, e);
451 e->inst[1] |= 0x00000008;
452 }
453
454 alloc_reg(pc, dst);
455 if (dst->hw > 63)
456 set_long(pc, e);
457 e->inst[0] |= (dst->hw << 2);
458 }
459
460 static INLINE void
461 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
462 {
463 float f = pc->immd_buf[imm->hw];
464 unsigned val = fui(imm->neg ? -f : f);
465
466 set_long(pc, e);
467 /*XXX: can't be predicated - bits overlap.. catch cases where both
468 * are required and avoid them. */
469 set_pred(pc, 0, 0, e);
470 set_pred_wr(pc, 0, 0, e);
471
472 e->inst[1] |= 0x00000002 | 0x00000001;
473 e->inst[0] |= (val & 0x3f) << 16;
474 e->inst[1] |= (val >> 6) << 2;
475 }
476
477 static INLINE void
478 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
479 {
480 assert(!(e->inst[0] & 0x0c000000));
481 assert(!(e->inst[1] & 0x00000004));
482
483 e->inst[0] |= (a->hw & 3) << 26;
484 e->inst[1] |= (a->hw >> 2) << 2;
485 }
486
487 static void
488 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
489 struct nv50_reg *src0, uint16_t src1_val)
490 {
491 struct nv50_program_exec *e = exec(pc);
492
493 e->inst[0] = 0xd0000000 | (src1_val << 9);
494 e->inst[1] = 0x20000000;
495 set_long(pc, e);
496 e->inst[0] |= dst->hw << 2;
497 if (src0) /* otherwise will add to $a0, which is always 0 */
498 set_addr(e, src0);
499
500 emit(pc, e);
501 }
502
503 static struct nv50_reg *
504 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
505 {
506 int i;
507 struct nv50_reg *a_tgsi = NULL, *a = NULL;
508
509 if (!ref) {
510 /* allocate for TGSI address reg */
511 for (i = 0; i < NV50_SU_MAX_ADDR; ++i) {
512 if (pc->r_addr[i].index >= 0)
513 continue;
514 if (pc->r_addr[i].rhw >= 0 &&
515 pc->r_addr[i].acc == pc->insn_cur)
516 continue;
517
518 pc->r_addr[i].rhw = -1;
519 pc->r_addr[i].index = i;
520 return &pc->r_addr[i];
521 }
522 assert(0);
523 return NULL;
524 }
525
526 /* Allocate and set an address reg so we can access 'ref'.
527 *
528 * If and r_addr has index < 0, it is not reserved for TGSI,
529 * and index will be the negative of the TGSI addr index the
530 * value in rhw is relative to, or -256 if rhw is an offset
531 * from 0. If rhw < 0, the reg has not been initialized.
532 */
533 for (i = NV50_SU_MAX_ADDR - 1; i >= 0; --i) {
534 if (pc->r_addr[i].index >= 0) /* occupied for TGSI */
535 continue;
536 if (pc->r_addr[i].rhw < 0) { /* unused */
537 a = &pc->r_addr[i];
538 continue;
539 }
540 if (!a && pc->r_addr[i].acc != pc->insn_cur)
541 a = &pc->r_addr[i];
542
543 if (ref->hw - pc->r_addr[i].rhw >= 128)
544 continue;
545
546 if ((ref->acc >= 0 && pc->r_addr[i].index == -256) ||
547 (ref->acc < 0 && -pc->r_addr[i].index == ref->index)) {
548 pc->r_addr[i].acc = pc->insn_cur;
549 return &pc->r_addr[i];
550 }
551 }
552 assert(a);
553
554 if (ref->acc < 0)
555 a_tgsi = pc->addr[ref->index];
556
557 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
558
559 a->rhw = ref->hw & ~0x7f;
560 a->acc = pc->insn_cur;
561 a->index = a_tgsi ? -ref->index : -256;
562 return a;
563 }
564
565 #define INTERP_LINEAR 0
566 #define INTERP_FLAT 1
567 #define INTERP_PERSPECTIVE 2
568 #define INTERP_CENTROID 4
569
570 /* interpolant index has been stored in dst->rhw */
571 static void
572 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
573 unsigned mode)
574 {
575 assert(dst->rhw != -1);
576 struct nv50_program_exec *e = exec(pc);
577
578 e->inst[0] |= 0x80000000;
579 set_dst(pc, dst, e);
580 e->inst[0] |= (dst->rhw << 16);
581
582 if (mode & INTERP_FLAT) {
583 e->inst[0] |= (1 << 8);
584 } else {
585 if (mode & INTERP_PERSPECTIVE) {
586 e->inst[0] |= (1 << 25);
587 alloc_reg(pc, iv);
588 e->inst[0] |= (iv->hw << 9);
589 }
590
591 if (mode & INTERP_CENTROID)
592 e->inst[0] |= (1 << 24);
593 }
594
595 emit(pc, e);
596 }
597
598 static void
599 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
600 struct nv50_program_exec *e)
601 {
602 set_long(pc, e);
603
604 e->param.index = src->hw & 127;
605 e->param.shift = s;
606 e->param.mask = m << (s % 32);
607
608 if (src->hw > 127)
609 set_addr(e, alloc_addr(pc, src));
610 else
611 if (src->acc < 0) {
612 assert(src->type == P_CONST);
613 set_addr(e, pc->addr[src->index]);
614 }
615
616 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
617 }
618
619 static void
620 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
621 {
622 struct nv50_program_exec *e = exec(pc);
623
624 e->inst[0] = 0x10000000;
625 if (!pc->allow32)
626 set_long(pc, e);
627
628 set_dst(pc, dst, e);
629
630 if (!is_long(e) && src->type == P_IMMD) {
631 set_immd(pc, src, e);
632 /*XXX: 32-bit, but steals part of "half" reg space - need to
633 * catch and handle this case if/when we do half-regs
634 */
635 } else
636 if (src->type == P_IMMD || src->type == P_CONST) {
637 set_long(pc, e);
638 set_data(pc, src, 0x7f, 9, e);
639 e->inst[1] |= 0x20000000; /* src0 const? */
640 } else {
641 if (src->type == P_ATTR) {
642 set_long(pc, e);
643 e->inst[1] |= 0x00200000;
644 }
645
646 alloc_reg(pc, src);
647 if (src->hw > 63)
648 set_long(pc, e);
649 e->inst[0] |= (src->hw << 9);
650 }
651
652 if (is_long(e) && !is_immd(e)) {
653 e->inst[1] |= 0x04000000; /* 32-bit */
654 e->inst[1] |= 0x0000c000; /* "subsubop" 0x3 */
655 if (!(e->inst[1] & 0x20000000))
656 e->inst[1] |= 0x00030000; /* "subsubop" 0xf */
657 } else
658 e->inst[0] |= 0x00008000;
659
660 emit(pc, e);
661 }
662
663 static INLINE void
664 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
665 {
666 struct nv50_reg *imm = alloc_immd(pc, f);
667 emit_mov(pc, dst, imm);
668 FREE(imm);
669 }
670
671 static boolean
672 check_swap_src_0_1(struct nv50_pc *pc,
673 struct nv50_reg **s0, struct nv50_reg **s1)
674 {
675 struct nv50_reg *src0 = *s0, *src1 = *s1;
676
677 if (src0->type == P_CONST) {
678 if (src1->type != P_CONST) {
679 *s0 = src1;
680 *s1 = src0;
681 return TRUE;
682 }
683 } else
684 if (src1->type == P_ATTR) {
685 if (src0->type != P_ATTR) {
686 *s0 = src1;
687 *s1 = src0;
688 return TRUE;
689 }
690 }
691
692 return FALSE;
693 }
694
695 static void
696 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
697 struct nv50_program_exec *e)
698 {
699 struct nv50_reg *temp;
700
701 if (src->type != P_TEMP) {
702 temp = temp_temp(pc);
703 emit_mov(pc, temp, src);
704 src = temp;
705 }
706
707 alloc_reg(pc, src);
708 if (src->hw > 63)
709 set_long(pc, e);
710 e->inst[0] |= (src->hw << 9);
711 }
712
713 static void
714 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
715 {
716 if (src->type == P_ATTR) {
717 set_long(pc, e);
718 e->inst[1] |= 0x00200000;
719 } else
720 if (src->type == P_CONST || src->type == P_IMMD) {
721 struct nv50_reg *temp = temp_temp(pc);
722
723 emit_mov(pc, temp, src);
724 src = temp;
725 }
726
727 alloc_reg(pc, src);
728 if (src->hw > 63)
729 set_long(pc, e);
730 e->inst[0] |= (src->hw << 9);
731 }
732
733 static void
734 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
735 {
736 if (src->type == P_ATTR) {
737 struct nv50_reg *temp = temp_temp(pc);
738
739 emit_mov(pc, temp, src);
740 src = temp;
741 } else
742 if (src->type == P_CONST || src->type == P_IMMD) {
743 assert(!(e->inst[0] & 0x00800000));
744 if (e->inst[0] & 0x01000000) {
745 struct nv50_reg *temp = temp_temp(pc);
746
747 emit_mov(pc, temp, src);
748 src = temp;
749 } else {
750 set_data(pc, src, 0x7f, 16, e);
751 e->inst[0] |= 0x00800000;
752 }
753 }
754
755 alloc_reg(pc, src);
756 if (src->hw > 63)
757 set_long(pc, e);
758 e->inst[0] |= ((src->hw & 127) << 16);
759 }
760
761 static void
762 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
763 {
764 set_long(pc, e);
765
766 if (src->type == P_ATTR) {
767 struct nv50_reg *temp = temp_temp(pc);
768
769 emit_mov(pc, temp, src);
770 src = temp;
771 } else
772 if (src->type == P_CONST || src->type == P_IMMD) {
773 assert(!(e->inst[0] & 0x01000000));
774 if (e->inst[0] & 0x00800000) {
775 struct nv50_reg *temp = temp_temp(pc);
776
777 emit_mov(pc, temp, src);
778 src = temp;
779 } else {
780 set_data(pc, src, 0x7f, 32+14, e);
781 e->inst[0] |= 0x01000000;
782 }
783 }
784
785 alloc_reg(pc, src);
786 e->inst[1] |= ((src->hw & 127) << 14);
787 }
788
789 static void
790 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
791 struct nv50_reg *src1)
792 {
793 struct nv50_program_exec *e = exec(pc);
794
795 e->inst[0] |= 0xc0000000;
796
797 if (!pc->allow32)
798 set_long(pc, e);
799
800 check_swap_src_0_1(pc, &src0, &src1);
801 set_dst(pc, dst, e);
802 set_src_0(pc, src0, e);
803 if (src1->type == P_IMMD && !is_long(e)) {
804 if (src0->neg)
805 e->inst[0] |= 0x00008000;
806 set_immd(pc, src1, e);
807 } else {
808 set_src_1(pc, src1, e);
809 if (src0->neg ^ src1->neg) {
810 if (is_long(e))
811 e->inst[1] |= 0x08000000;
812 else
813 e->inst[0] |= 0x00008000;
814 }
815 }
816
817 emit(pc, e);
818 }
819
820 static void
821 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
822 struct nv50_reg *src0, struct nv50_reg *src1)
823 {
824 struct nv50_program_exec *e = exec(pc);
825
826 e->inst[0] = 0xb0000000;
827
828 alloc_reg(pc, src1);
829 check_swap_src_0_1(pc, &src0, &src1);
830
831 if (!pc->allow32 || (src0->neg | src1->neg) || src1->hw > 63) {
832 set_long(pc, e);
833 e->inst[1] |= (src0->neg << 26) | (src1->neg << 27);
834 }
835
836 set_dst(pc, dst, e);
837 set_src_0(pc, src0, e);
838 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
839 set_src_2(pc, src1, e);
840 else
841 if (src1->type == P_IMMD)
842 set_immd(pc, src1, e);
843 else
844 set_src_1(pc, src1, e);
845
846 emit(pc, e);
847 }
848
849 static void
850 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
851 uint8_t s)
852 {
853 struct nv50_program_exec *e = exec(pc);
854
855 set_long(pc, e);
856 e->inst[1] |= 0xc0000000;
857
858 e->inst[0] |= dst->hw << 2;
859 e->inst[0] |= s << 16; /* shift left */
860 set_src_0_restricted(pc, src, e);
861
862 emit(pc, e);
863 }
864
865 static void
866 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
867 struct nv50_reg *src0, struct nv50_reg *src1)
868 {
869 struct nv50_program_exec *e = exec(pc);
870
871 set_long(pc, e);
872 e->inst[0] |= 0xb0000000;
873 e->inst[1] |= (sub << 29);
874
875 check_swap_src_0_1(pc, &src0, &src1);
876 set_dst(pc, dst, e);
877 set_src_0(pc, src0, e);
878 set_src_1(pc, src1, e);
879
880 emit(pc, e);
881 }
882
883 static INLINE void
884 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
885 struct nv50_reg *src1)
886 {
887 assert(src0 != src1);
888 src1->neg ^= 1;
889 emit_add(pc, dst, src0, src1);
890 src1->neg ^= 1;
891 }
892
893 static void
894 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
895 struct nv50_reg *src1, unsigned op)
896 {
897 struct nv50_program_exec *e = exec(pc);
898
899 e->inst[0] = 0xd0000000;
900 set_long(pc, e);
901
902 check_swap_src_0_1(pc, &src0, &src1);
903 set_dst(pc, dst, e);
904 set_src_0(pc, src0, e);
905
906 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
907 op != TGSI_OPCODE_XOR)
908 assert(!"invalid bit op");
909
910 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
911 set_immd(pc, src1, e);
912 if (op == TGSI_OPCODE_OR)
913 e->inst[0] |= 0x0100;
914 else
915 if (op == TGSI_OPCODE_XOR)
916 e->inst[0] |= 0x8000;
917 } else {
918 set_src_1(pc, src1, e);
919 e->inst[1] |= 0x04000000; /* 32 bit */
920 if (op == TGSI_OPCODE_OR)
921 e->inst[1] |= 0x4000;
922 else
923 if (op == TGSI_OPCODE_XOR)
924 e->inst[1] |= 0x8000;
925 }
926
927 emit(pc, e);
928 }
929
930 static void
931 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
932 struct nv50_reg *src1, struct nv50_reg *src2)
933 {
934 struct nv50_program_exec *e = exec(pc);
935
936 e->inst[0] |= 0xe0000000;
937
938 check_swap_src_0_1(pc, &src0, &src1);
939 set_dst(pc, dst, e);
940 set_src_0(pc, src0, e);
941 set_src_1(pc, src1, e);
942 set_src_2(pc, src2, e);
943
944 if (src0->neg ^ src1->neg)
945 e->inst[1] |= 0x04000000;
946 if (src2->neg)
947 e->inst[1] |= 0x08000000;
948
949 emit(pc, e);
950 }
951
952 static INLINE void
953 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
954 struct nv50_reg *src1, struct nv50_reg *src2)
955 {
956 assert(src2 != src0 && src2 != src1);
957 src2->neg ^= 1;
958 emit_mad(pc, dst, src0, src1, src2);
959 src2->neg ^= 1;
960 }
961
962 static void
963 emit_flop(struct nv50_pc *pc, unsigned sub,
964 struct nv50_reg *dst, struct nv50_reg *src)
965 {
966 struct nv50_program_exec *e = exec(pc);
967
968 e->inst[0] |= 0x90000000;
969 if (sub) {
970 set_long(pc, e);
971 e->inst[1] |= (sub << 29);
972 }
973
974 set_dst(pc, dst, e);
975
976 if (sub == 0 || sub == 2)
977 set_src_0_restricted(pc, src, e);
978 else
979 set_src_0(pc, src, e);
980
981 emit(pc, e);
982 }
983
984 static void
985 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
986 {
987 struct nv50_program_exec *e = exec(pc);
988
989 e->inst[0] |= 0xb0000000;
990
991 set_dst(pc, dst, e);
992 set_src_0(pc, src, e);
993 set_long(pc, e);
994 e->inst[1] |= (6 << 29) | 0x00004000;
995
996 emit(pc, e);
997 }
998
999 static void
1000 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1001 {
1002 struct nv50_program_exec *e = exec(pc);
1003
1004 e->inst[0] |= 0xb0000000;
1005
1006 set_dst(pc, dst, e);
1007 set_src_0(pc, src, e);
1008 set_long(pc, e);
1009 e->inst[1] |= (6 << 29);
1010
1011 emit(pc, e);
1012 }
1013
1014 #define CVTOP_RN 0x01
1015 #define CVTOP_FLOOR 0x03
1016 #define CVTOP_CEIL 0x05
1017 #define CVTOP_TRUNC 0x07
1018 #define CVTOP_SAT 0x08
1019 #define CVTOP_ABS 0x10
1020
1021 /* 0x04 == 32 bit dst */
1022 /* 0x40 == dst is float */
1023 /* 0x80 == src is float */
1024 #define CVT_F32_F32 0xc4
1025 #define CVT_F32_S32 0x44
1026 #define CVT_S32_F32 0x8c
1027 #define CVT_S32_S32 0x0c
1028 #define CVT_NEG 0x20
1029 #define CVT_RI 0x08
1030
1031 static void
1032 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1033 int wp, unsigned cvn, unsigned fmt)
1034 {
1035 struct nv50_program_exec *e;
1036
1037 e = exec(pc);
1038 set_long(pc, e);
1039
1040 e->inst[0] |= 0xa0000000;
1041 e->inst[1] |= 0x00004000; /* 32 bit src */
1042 e->inst[1] |= (cvn << 16);
1043 e->inst[1] |= (fmt << 24);
1044 set_src_0(pc, src, e);
1045
1046 if (wp >= 0)
1047 set_pred_wr(pc, 1, wp, e);
1048
1049 if (dst)
1050 set_dst(pc, dst, e);
1051 else {
1052 e->inst[0] |= 0x000001fc;
1053 e->inst[1] |= 0x00000008;
1054 }
1055
1056 emit(pc, e);
1057 }
1058
1059 /* nv50 Condition codes:
1060 * 0x1 = LT
1061 * 0x2 = EQ
1062 * 0x3 = LE
1063 * 0x4 = GT
1064 * 0x5 = NE
1065 * 0x6 = GE
1066 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1067 * 0x8 = unordered bit (allows NaN)
1068 */
1069 static void
1070 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1071 struct nv50_reg *src0, struct nv50_reg *src1)
1072 {
1073 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1074
1075 struct nv50_program_exec *e = exec(pc);
1076 struct nv50_reg *rdst;
1077
1078 assert(ccode < 16);
1079 if (check_swap_src_0_1(pc, &src0, &src1))
1080 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1081
1082 rdst = dst;
1083 if (dst && dst->type != P_TEMP)
1084 dst = alloc_temp(pc, NULL);
1085
1086 /* set.u32 */
1087 set_long(pc, e);
1088 e->inst[0] |= 0xb0000000;
1089 e->inst[1] |= 0x60000000 | (ccode << 14);
1090
1091 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1092 * that doesn't seem to match what the hw actually does
1093 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1094 */
1095
1096 if (wp >= 0)
1097 set_pred_wr(pc, 1, wp, e);
1098 if (dst)
1099 set_dst(pc, dst, e);
1100 else {
1101 e->inst[0] |= 0x000001fc;
1102 e->inst[1] |= 0x00000008;
1103 }
1104
1105 set_src_0(pc, src0, e);
1106 set_src_1(pc, src1, e);
1107
1108 emit(pc, e);
1109 pc->if_cond = pc->p->exec_tail; /* record for OPCODE_IF */
1110
1111 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1112 if (rdst)
1113 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
1114 if (rdst && rdst != dst)
1115 free_temp(pc, dst);
1116 }
1117
1118 static INLINE unsigned
1119 map_tgsi_setop_cc(unsigned op)
1120 {
1121 switch (op) {
1122 case TGSI_OPCODE_SLT: return 0x1;
1123 case TGSI_OPCODE_SGE: return 0x6;
1124 case TGSI_OPCODE_SEQ: return 0x2;
1125 case TGSI_OPCODE_SGT: return 0x4;
1126 case TGSI_OPCODE_SLE: return 0x3;
1127 case TGSI_OPCODE_SNE: return 0xd;
1128 default:
1129 assert(0);
1130 return 0;
1131 }
1132 }
1133
1134 static INLINE void
1135 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1136 {
1137 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
1138 }
1139
1140 static void
1141 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1142 struct nv50_reg *v, struct nv50_reg *e)
1143 {
1144 struct nv50_reg *temp = alloc_temp(pc, NULL);
1145
1146 emit_flop(pc, 3, temp, v);
1147 emit_mul(pc, temp, temp, e);
1148 emit_preex2(pc, temp, temp);
1149 emit_flop(pc, 6, dst, temp);
1150
1151 free_temp(pc, temp);
1152 }
1153
1154 static INLINE void
1155 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1156 {
1157 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
1158 }
1159
1160 static INLINE void
1161 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1162 {
1163 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
1164 }
1165
1166 static void
1167 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1168 struct nv50_reg **src)
1169 {
1170 struct nv50_reg *one = alloc_immd(pc, 1.0);
1171 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1172 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1173 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1174 struct nv50_reg *tmp[4];
1175 boolean allow32 = pc->allow32;
1176
1177 pc->allow32 = FALSE;
1178
1179 if (mask & (3 << 1)) {
1180 tmp[0] = alloc_temp(pc, NULL);
1181 emit_minmax(pc, 4, tmp[0], src[0], zero);
1182 }
1183
1184 if (mask & (1 << 2)) {
1185 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1186
1187 tmp[1] = temp_temp(pc);
1188 emit_minmax(pc, 4, tmp[1], src[1], zero);
1189
1190 tmp[3] = temp_temp(pc);
1191 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1192 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1193
1194 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1195 emit_mov(pc, dst[2], zero);
1196 set_pred(pc, 3, 0, pc->p->exec_tail);
1197 }
1198
1199 if (mask & (1 << 1))
1200 assimilate_temp(pc, dst[1], tmp[0]);
1201 else
1202 if (mask & (1 << 2))
1203 free_temp(pc, tmp[0]);
1204
1205 pc->allow32 = allow32;
1206
1207 /* do this last, in case src[i,j] == dst[0,3] */
1208 if (mask & (1 << 0))
1209 emit_mov(pc, dst[0], one);
1210
1211 if (mask & (1 << 3))
1212 emit_mov(pc, dst[3], one);
1213
1214 FREE(pos128);
1215 FREE(neg128);
1216 FREE(zero);
1217 FREE(one);
1218 }
1219
1220 static INLINE void
1221 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1222 {
1223 emit_cvt(pc, dst, src, -1, CVTOP_RN, CVT_F32_F32 | CVT_NEG);
1224 }
1225
1226 static void
1227 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1228 {
1229 struct nv50_program_exec *e;
1230 const int r_pred = 1;
1231 unsigned cvn = CVT_F32_F32;
1232
1233 if (src->neg)
1234 cvn |= CVT_NEG;
1235 /* write predicate reg */
1236 emit_cvt(pc, NULL, src, r_pred, CVTOP_RN, cvn);
1237
1238 /* conditional discard */
1239 e = exec(pc);
1240 e->inst[0] = 0x00000002;
1241 set_long(pc, e);
1242 set_pred(pc, 0x1 /* LT */, r_pred, e);
1243 emit(pc, e);
1244 }
1245
1246 static void
1247 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1248 struct nv50_reg **src, unsigned unit, unsigned type, boolean proj)
1249 {
1250 struct nv50_reg *temp, *t[4];
1251 struct nv50_program_exec *e;
1252
1253 unsigned c, mode, dim;
1254
1255 switch (type) {
1256 case TGSI_TEXTURE_1D:
1257 dim = 1;
1258 break;
1259 case TGSI_TEXTURE_UNKNOWN:
1260 case TGSI_TEXTURE_2D:
1261 case TGSI_TEXTURE_SHADOW1D: /* XXX: x, z */
1262 case TGSI_TEXTURE_RECT:
1263 dim = 2;
1264 break;
1265 case TGSI_TEXTURE_3D:
1266 case TGSI_TEXTURE_CUBE:
1267 case TGSI_TEXTURE_SHADOW2D:
1268 case TGSI_TEXTURE_SHADOWRECT: /* XXX */
1269 dim = 3;
1270 break;
1271 default:
1272 assert(0);
1273 break;
1274 }
1275
1276 /* some cards need t[0]'s hw index to be a multiple of 4 */
1277 alloc_temp4(pc, t, 0);
1278
1279 if (proj) {
1280 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1281 mode = pc->interp_mode[src[0]->index];
1282
1283 t[3]->rhw = src[3]->rhw;
1284 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1285 emit_flop(pc, 0, t[3], t[3]);
1286
1287 for (c = 0; c < dim; c++) {
1288 t[c]->rhw = src[c]->rhw;
1289 emit_interp(pc, t[c], t[3],
1290 (mode | INTERP_PERSPECTIVE));
1291 }
1292 } else {
1293 emit_flop(pc, 0, t[3], src[3]);
1294 for (c = 0; c < dim; c++)
1295 emit_mul(pc, t[c], src[c], t[3]);
1296
1297 /* XXX: for some reason the blob sometimes uses MAD:
1298 * emit_mad(pc, t[c], src[0][c], t[3], t[3])
1299 * pc->p->exec_tail->inst[1] |= 0x080fc000;
1300 */
1301 }
1302 } else {
1303 if (type == TGSI_TEXTURE_CUBE) {
1304 temp = temp_temp(pc);
1305 emit_minmax(pc, 4, temp, src[0], src[1]);
1306 emit_minmax(pc, 4, temp, temp, src[2]);
1307 emit_flop(pc, 0, temp, temp);
1308 for (c = 0; c < 3; c++)
1309 emit_mul(pc, t[c], src[c], temp);
1310 } else {
1311 for (c = 0; c < dim; c++)
1312 emit_mov(pc, t[c], src[c]);
1313 }
1314 }
1315
1316 e = exec(pc);
1317 set_long(pc, e);
1318 e->inst[0] |= 0xf0000000;
1319 e->inst[1] |= 0x00000004;
1320 set_dst(pc, t[0], e);
1321 e->inst[0] |= (unit << 9);
1322
1323 if (dim == 2)
1324 e->inst[0] |= 0x00400000;
1325 else
1326 if (dim == 3)
1327 e->inst[0] |= 0x00800000;
1328
1329 e->inst[0] |= (mask & 0x3) << 25;
1330 e->inst[1] |= (mask & 0xc) << 12;
1331
1332 emit(pc, e);
1333
1334 #if 1
1335 c = 0;
1336 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1337 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1338 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1339 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1340
1341 free_temp4(pc, t);
1342 #else
1343 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1344 * the texture coordinates, not the fetched values: latency ? */
1345
1346 for (c = 0; c < 4; c++) {
1347 if (mask & (1 << c))
1348 assimilate_temp(pc, dst[c], t[c]);
1349 else
1350 free_temp(pc, t[c]);
1351 }
1352 #endif
1353 }
1354
1355 static void
1356 emit_branch(struct nv50_pc *pc, int pred, unsigned cc,
1357 struct nv50_program_exec **join)
1358 {
1359 struct nv50_program_exec *e = exec(pc);
1360
1361 if (join) {
1362 set_long(pc, e);
1363 e->inst[0] |= 0xa0000002;
1364 emit(pc, e);
1365 *join = e;
1366 e = exec(pc);
1367 }
1368
1369 set_long(pc, e);
1370 e->inst[0] |= 0x10000002;
1371 if (pred >= 0)
1372 set_pred(pc, cc, pred, e);
1373 emit(pc, e);
1374 }
1375
1376 static void
1377 emit_nop(struct nv50_pc *pc)
1378 {
1379 struct nv50_program_exec *e = exec(pc);
1380
1381 e->inst[0] = 0xf0000000;
1382 set_long(pc, e);
1383 e->inst[1] = 0xe0000000;
1384 emit(pc, e);
1385 }
1386
1387 static void
1388 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1389 {
1390 struct nv50_program_exec *e = exec(pc);
1391
1392 assert(src->type == P_TEMP);
1393
1394 e->inst[0] = 0xc0140000;
1395 e->inst[1] = 0x89800000;
1396 set_long(pc, e);
1397 set_dst(pc, dst, e);
1398 set_src_0(pc, src, e);
1399 set_src_2(pc, src, e);
1400
1401 emit(pc, e);
1402 }
1403
1404 static void
1405 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1406 {
1407 struct nv50_program_exec *e = exec(pc);
1408
1409 assert(src->type == P_TEMP);
1410
1411 if (!src->neg) /* ! double negation */
1412 emit_neg(pc, src, src);
1413
1414 e->inst[0] = 0xc0150000;
1415 e->inst[1] = 0x8a400000;
1416 set_long(pc, e);
1417 set_dst(pc, dst, e);
1418 set_src_0(pc, src, e);
1419 set_src_2(pc, src, e);
1420
1421 emit(pc, e);
1422 }
1423
1424 static void
1425 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1426 {
1427 unsigned q = 0, m = ~0;
1428
1429 assert(!is_long(e));
1430
1431 switch (e->inst[0] >> 28) {
1432 case 0x1:
1433 /* MOV */
1434 q = 0x0403c000;
1435 m = 0xffff7fff;
1436 break;
1437 case 0x8:
1438 /* INTERP (move centroid, perspective and flat bits) */
1439 m = ~0x03000100;
1440 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1441 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1442 break;
1443 case 0x9:
1444 /* RCP */
1445 break;
1446 case 0xB:
1447 /* ADD */
1448 m = ~(127 << 16);
1449 q = ((e->inst[0] & (~m)) >> 2);
1450 break;
1451 case 0xC:
1452 /* MUL */
1453 m = ~0x00008000;
1454 q = ((e->inst[0] & (~m)) << 12);
1455 break;
1456 case 0xE:
1457 /* MAD (if src2 == dst) */
1458 q = ((e->inst[0] & 0x1fc) << 12);
1459 break;
1460 default:
1461 assert(0);
1462 break;
1463 }
1464
1465 set_long(pc, e);
1466 pc->p->exec_size++;
1467
1468 e->inst[0] &= m;
1469 e->inst[1] |= q;
1470 }
1471
1472 /* Some operations support an optional negation flag. */
1473 static boolean
1474 negate_supported(const struct tgsi_full_instruction *insn, int i)
1475 {
1476 int s;
1477
1478 switch (insn->Instruction.Opcode) {
1479 case TGSI_OPCODE_DDY:
1480 case TGSI_OPCODE_DP3:
1481 case TGSI_OPCODE_DP4:
1482 case TGSI_OPCODE_MUL:
1483 case TGSI_OPCODE_KIL:
1484 case TGSI_OPCODE_ADD:
1485 case TGSI_OPCODE_SUB:
1486 case TGSI_OPCODE_MAD:
1487 break;
1488 case TGSI_OPCODE_POW:
1489 if (i == 1)
1490 break;
1491 return FALSE;
1492 default:
1493 return FALSE;
1494 }
1495
1496 /* Watch out for possible multiple uses of an nv50_reg, we
1497 * can't use nv50_reg::neg in these cases.
1498 */
1499 for (s = 0; s < insn->Instruction.NumSrcRegs; ++s) {
1500 if (s == i)
1501 continue;
1502 if ((insn->FullSrcRegisters[s].SrcRegister.Index ==
1503 insn->FullSrcRegisters[i].SrcRegister.Index) &&
1504 (insn->FullSrcRegisters[s].SrcRegister.File ==
1505 insn->FullSrcRegisters[i].SrcRegister.File))
1506 return FALSE;
1507 }
1508
1509 return TRUE;
1510 }
1511
1512 /* Return a read mask for source registers deduced from opcode & write mask. */
1513 static unsigned
1514 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1515 {
1516 unsigned x, mask = insn->FullDstRegisters[0].DstRegister.WriteMask;
1517
1518 switch (insn->Instruction.Opcode) {
1519 case TGSI_OPCODE_COS:
1520 case TGSI_OPCODE_SIN:
1521 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1522 case TGSI_OPCODE_DP3:
1523 return 0x7;
1524 case TGSI_OPCODE_DP4:
1525 case TGSI_OPCODE_DPH:
1526 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1527 return 0xf;
1528 case TGSI_OPCODE_DST:
1529 return mask & (c ? 0xa : 0x6);
1530 case TGSI_OPCODE_EX2:
1531 case TGSI_OPCODE_LG2:
1532 case TGSI_OPCODE_POW:
1533 case TGSI_OPCODE_RCP:
1534 case TGSI_OPCODE_RSQ:
1535 case TGSI_OPCODE_SCS:
1536 return 0x1;
1537 case TGSI_OPCODE_LIT:
1538 return 0xb;
1539 case TGSI_OPCODE_TEX:
1540 case TGSI_OPCODE_TXP:
1541 {
1542 const struct tgsi_instruction_ext_texture *tex;
1543
1544 assert(insn->Instruction.Extended);
1545 tex = &insn->InstructionExtTexture;
1546
1547 mask = 0x7;
1548 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP)
1549 mask |= 0x8;
1550
1551 switch (tex->Texture) {
1552 case TGSI_TEXTURE_1D:
1553 mask &= 0x9;
1554 break;
1555 case TGSI_TEXTURE_2D:
1556 mask &= 0xb;
1557 break;
1558 default:
1559 break;
1560 }
1561 }
1562 return mask;
1563 case TGSI_OPCODE_XPD:
1564 x = 0;
1565 if (mask & 1) x |= 0x6;
1566 if (mask & 2) x |= 0x5;
1567 if (mask & 4) x |= 0x3;
1568 return x;
1569 default:
1570 break;
1571 }
1572
1573 return mask;
1574 }
1575
1576 static struct nv50_reg *
1577 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1578 {
1579 switch (dst->DstRegister.File) {
1580 case TGSI_FILE_TEMPORARY:
1581 return &pc->temp[dst->DstRegister.Index * 4 + c];
1582 case TGSI_FILE_OUTPUT:
1583 return &pc->result[dst->DstRegister.Index * 4 + c];
1584 case TGSI_FILE_ADDRESS:
1585 {
1586 struct nv50_reg *r = pc->addr[dst->DstRegister.Index * 4 + c];
1587 if (!r) {
1588 r = alloc_addr(pc, NULL);
1589 pc->addr[dst->DstRegister.Index * 4 + c] = r;
1590 }
1591 assert(r);
1592 return r;
1593 }
1594 case TGSI_FILE_NULL:
1595 return NULL;
1596 default:
1597 break;
1598 }
1599
1600 return NULL;
1601 }
1602
1603 static struct nv50_reg *
1604 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1605 boolean neg)
1606 {
1607 struct nv50_reg *r = NULL;
1608 struct nv50_reg *temp;
1609 unsigned sgn, c, swz;
1610
1611 if (src->SrcRegister.File != TGSI_FILE_CONSTANT)
1612 assert(!src->SrcRegister.Indirect);
1613
1614 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1615
1616 c = tgsi_util_get_full_src_register_swizzle(src, chan);
1617 switch (c) {
1618 case TGSI_SWIZZLE_X:
1619 case TGSI_SWIZZLE_Y:
1620 case TGSI_SWIZZLE_Z:
1621 case TGSI_SWIZZLE_W:
1622 switch (src->SrcRegister.File) {
1623 case TGSI_FILE_INPUT:
1624 r = &pc->attr[src->SrcRegister.Index * 4 + c];
1625 break;
1626 case TGSI_FILE_TEMPORARY:
1627 r = &pc->temp[src->SrcRegister.Index * 4 + c];
1628 break;
1629 case TGSI_FILE_CONSTANT:
1630 if (!src->SrcRegister.Indirect) {
1631 r = &pc->param[src->SrcRegister.Index * 4 + c];
1632 break;
1633 }
1634 /* Indicate indirection by setting r->acc < 0 and
1635 * use the index field to select the address reg.
1636 */
1637 r = MALLOC_STRUCT(nv50_reg);
1638 swz = tgsi_util_get_src_register_swizzle(
1639 &src->SrcRegisterInd, 0);
1640 ctor_reg(r, P_CONST,
1641 src->SrcRegisterInd.Index * 4 + swz,
1642 src->SrcRegister.Index * 4 + c);
1643 r->acc = -1;
1644 break;
1645 case TGSI_FILE_IMMEDIATE:
1646 r = &pc->immd[src->SrcRegister.Index * 4 + c];
1647 break;
1648 case TGSI_FILE_SAMPLER:
1649 break;
1650 case TGSI_FILE_ADDRESS:
1651 r = pc->addr[src->SrcRegister.Index * 4 + c];
1652 assert(r);
1653 break;
1654 default:
1655 assert(0);
1656 break;
1657 }
1658 break;
1659 default:
1660 assert(0);
1661 break;
1662 }
1663
1664 switch (sgn) {
1665 case TGSI_UTIL_SIGN_KEEP:
1666 break;
1667 case TGSI_UTIL_SIGN_CLEAR:
1668 temp = temp_temp(pc);
1669 emit_abs(pc, temp, r);
1670 r = temp;
1671 break;
1672 case TGSI_UTIL_SIGN_TOGGLE:
1673 if (neg)
1674 r->neg = 1;
1675 else {
1676 temp = temp_temp(pc);
1677 emit_neg(pc, temp, r);
1678 r = temp;
1679 }
1680 break;
1681 case TGSI_UTIL_SIGN_SET:
1682 temp = temp_temp(pc);
1683 emit_cvt(pc, temp, r, -1, CVTOP_ABS, CVT_F32_F32 | CVT_NEG);
1684 r = temp;
1685 break;
1686 default:
1687 assert(0);
1688 break;
1689 }
1690
1691 return r;
1692 }
1693
1694 /* return TRUE for ops that produce only a single result */
1695 static boolean
1696 is_scalar_op(unsigned op)
1697 {
1698 switch (op) {
1699 case TGSI_OPCODE_COS:
1700 case TGSI_OPCODE_DP2:
1701 case TGSI_OPCODE_DP3:
1702 case TGSI_OPCODE_DP4:
1703 case TGSI_OPCODE_DPH:
1704 case TGSI_OPCODE_EX2:
1705 case TGSI_OPCODE_LG2:
1706 case TGSI_OPCODE_POW:
1707 case TGSI_OPCODE_RCP:
1708 case TGSI_OPCODE_RSQ:
1709 case TGSI_OPCODE_SIN:
1710 /*
1711 case TGSI_OPCODE_KIL:
1712 case TGSI_OPCODE_LIT:
1713 case TGSI_OPCODE_SCS:
1714 */
1715 return TRUE;
1716 default:
1717 return FALSE;
1718 }
1719 }
1720
1721 /* Returns a bitmask indicating which dst components depend
1722 * on source s, component c (reverse of nv50_tgsi_src_mask).
1723 */
1724 static unsigned
1725 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
1726 {
1727 if (is_scalar_op(op))
1728 return 0x1;
1729
1730 switch (op) {
1731 case TGSI_OPCODE_DST:
1732 return (1 << c) & (s ? 0xa : 0x6);
1733 case TGSI_OPCODE_XPD:
1734 switch (c) {
1735 case 0: return 0x6;
1736 case 1: return 0x5;
1737 case 2: return 0x3;
1738 case 3: return 0x0;
1739 default:
1740 assert(0);
1741 return 0x0;
1742 }
1743 case TGSI_OPCODE_LIT:
1744 case TGSI_OPCODE_SCS:
1745 case TGSI_OPCODE_TEX:
1746 case TGSI_OPCODE_TXP:
1747 /* these take care of dangerous swizzles themselves */
1748 return 0x0;
1749 case TGSI_OPCODE_IF:
1750 case TGSI_OPCODE_KIL:
1751 /* don't call this function for these ops */
1752 assert(0);
1753 return 0;
1754 default:
1755 /* linear vector instruction */
1756 return (1 << c);
1757 }
1758 }
1759
1760 static INLINE boolean
1761 has_pred(struct nv50_program_exec *e, unsigned cc)
1762 {
1763 if (!is_long(e) || is_immd(e))
1764 return FALSE;
1765 return ((e->inst[1] & 0x780) == (cc << 7));
1766 }
1767
1768 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
1769 * join_at ENDIF
1770 * @p0.eq bra ENDIF
1771 * single_op
1772 * ENDIF: nop.join
1773 */
1774 static boolean
1775 nv50_kill_branch(struct nv50_pc *pc)
1776 {
1777 int lvl = pc->if_lvl;
1778
1779 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
1780 return FALSE;
1781
1782 /* if ccode == 'true', the BRA is from an ELSE and the predicate
1783 * reg may no longer be valid, since we currently always use $p0
1784 */
1785 if (has_pred(pc->if_insn[lvl], 0xf))
1786 return FALSE;
1787 assert(pc->if_insn[lvl] && pc->br_join[lvl]);
1788
1789 /* We'll use the exec allocated for JOIN_AT (as we can't easily
1790 * update prev's next); if exec_tail is BRK, update the pointer.
1791 */
1792 if (pc->loop_lvl && pc->br_loop[pc->loop_lvl - 1] == pc->p->exec_tail)
1793 pc->br_loop[pc->loop_lvl - 1] = pc->br_join[lvl];
1794
1795 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
1796
1797 *pc->br_join[lvl] = *pc->p->exec_tail;
1798
1799 FREE(pc->if_insn[lvl]);
1800 FREE(pc->p->exec_tail);
1801
1802 pc->p->exec_tail = pc->br_join[lvl];
1803 pc->p->exec_tail->next = NULL;
1804 set_pred(pc, 0xd, 0, pc->p->exec_tail);
1805
1806 return TRUE;
1807 }
1808
1809 static boolean
1810 nv50_program_tx_insn(struct nv50_pc *pc,
1811 const struct tgsi_full_instruction *inst)
1812 {
1813 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
1814 unsigned mask, sat, unit;
1815 int i, c;
1816
1817 mask = inst->FullDstRegisters[0].DstRegister.WriteMask;
1818 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
1819
1820 memset(src, 0, sizeof(src));
1821
1822 for (c = 0; c < 4; c++) {
1823 if ((mask & (1 << c)) && !pc->r_dst[c])
1824 dst[c] = tgsi_dst(pc, c, &inst->FullDstRegisters[0]);
1825 else
1826 dst[c] = pc->r_dst[c];
1827 rdst[c] = dst[c];
1828 }
1829
1830 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1831 const struct tgsi_full_src_register *fs = &inst->FullSrcRegisters[i];
1832 unsigned src_mask;
1833 boolean neg_supp;
1834
1835 src_mask = nv50_tgsi_src_mask(inst, i);
1836 neg_supp = negate_supported(inst, i);
1837
1838 if (fs->SrcRegister.File == TGSI_FILE_SAMPLER)
1839 unit = fs->SrcRegister.Index;
1840
1841 for (c = 0; c < 4; c++)
1842 if (src_mask & (1 << c))
1843 src[i][c] = tgsi_src(pc, c, fs, neg_supp);
1844 }
1845
1846 brdc = temp = pc->r_brdc;
1847 if (brdc && brdc->type != P_TEMP) {
1848 temp = temp_temp(pc);
1849 if (sat)
1850 brdc = temp;
1851 } else
1852 if (sat) {
1853 for (c = 0; c < 4; c++) {
1854 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
1855 continue;
1856 /* rdst[c] = dst[c]; */ /* done above */
1857 dst[c] = temp_temp(pc);
1858 }
1859 }
1860
1861 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
1862
1863 switch (inst->Instruction.Opcode) {
1864 case TGSI_OPCODE_ABS:
1865 for (c = 0; c < 4; c++) {
1866 if (!(mask & (1 << c)))
1867 continue;
1868 emit_abs(pc, dst[c], src[0][c]);
1869 }
1870 break;
1871 case TGSI_OPCODE_ADD:
1872 for (c = 0; c < 4; c++) {
1873 if (!(mask & (1 << c)))
1874 continue;
1875 emit_add(pc, dst[c], src[0][c], src[1][c]);
1876 }
1877 break;
1878 case TGSI_OPCODE_AND:
1879 case TGSI_OPCODE_XOR:
1880 case TGSI_OPCODE_OR:
1881 for (c = 0; c < 4; c++) {
1882 if (!(mask & (1 << c)))
1883 continue;
1884 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
1885 inst->Instruction.Opcode);
1886 }
1887 break;
1888 case TGSI_OPCODE_ARL:
1889 assert(src[0][0]);
1890 temp = temp_temp(pc);
1891 emit_cvt(pc, temp, src[0][0], -1, CVTOP_FLOOR, CVT_S32_F32);
1892 emit_arl(pc, dst[0], temp, 4);
1893 break;
1894 case TGSI_OPCODE_BGNLOOP:
1895 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
1896 terminate_mbb(pc);
1897 break;
1898 case TGSI_OPCODE_BRK:
1899 emit_branch(pc, -1, 0, NULL);
1900 assert(pc->loop_lvl > 0);
1901 pc->br_loop[pc->loop_lvl - 1] = pc->p->exec_tail;
1902 break;
1903 case TGSI_OPCODE_CEIL:
1904 for (c = 0; c < 4; c++) {
1905 if (!(mask & (1 << c)))
1906 continue;
1907 emit_cvt(pc, dst[c], src[0][c], -1,
1908 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
1909 }
1910 break;
1911 case TGSI_OPCODE_CMP:
1912 pc->allow32 = FALSE;
1913 for (c = 0; c < 4; c++) {
1914 if (!(mask & (1 << c)))
1915 continue;
1916 emit_cvt(pc, NULL, src[0][c], 1, CVTOP_RN, CVT_F32_F32);
1917 emit_mov(pc, dst[c], src[1][c]);
1918 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
1919 emit_mov(pc, dst[c], src[2][c]);
1920 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
1921 }
1922 break;
1923 case TGSI_OPCODE_COS:
1924 if (mask & 8) {
1925 emit_precossin(pc, temp, src[0][3]);
1926 emit_flop(pc, 5, dst[3], temp);
1927 if (!(mask &= 7))
1928 break;
1929 if (temp == dst[3])
1930 temp = brdc = temp_temp(pc);
1931 }
1932 emit_precossin(pc, temp, src[0][0]);
1933 emit_flop(pc, 5, brdc, temp);
1934 break;
1935 case TGSI_OPCODE_DDX:
1936 for (c = 0; c < 4; c++) {
1937 if (!(mask & (1 << c)))
1938 continue;
1939 emit_ddx(pc, dst[c], src[0][c]);
1940 }
1941 break;
1942 case TGSI_OPCODE_DDY:
1943 for (c = 0; c < 4; c++) {
1944 if (!(mask & (1 << c)))
1945 continue;
1946 emit_ddy(pc, dst[c], src[0][c]);
1947 }
1948 break;
1949 case TGSI_OPCODE_DP3:
1950 emit_mul(pc, temp, src[0][0], src[1][0]);
1951 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1952 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
1953 break;
1954 case TGSI_OPCODE_DP4:
1955 emit_mul(pc, temp, src[0][0], src[1][0]);
1956 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1957 emit_mad(pc, temp, src[0][2], src[1][2], temp);
1958 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
1959 break;
1960 case TGSI_OPCODE_DPH:
1961 emit_mul(pc, temp, src[0][0], src[1][0]);
1962 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1963 emit_mad(pc, temp, src[0][2], src[1][2], temp);
1964 emit_add(pc, brdc, src[1][3], temp);
1965 break;
1966 case TGSI_OPCODE_DST:
1967 if (mask & (1 << 1))
1968 emit_mul(pc, dst[1], src[0][1], src[1][1]);
1969 if (mask & (1 << 2))
1970 emit_mov(pc, dst[2], src[0][2]);
1971 if (mask & (1 << 3))
1972 emit_mov(pc, dst[3], src[1][3]);
1973 if (mask & (1 << 0))
1974 emit_mov_immdval(pc, dst[0], 1.0f);
1975 break;
1976 case TGSI_OPCODE_ELSE:
1977 emit_branch(pc, -1, 0, NULL);
1978 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
1979 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
1980 terminate_mbb(pc);
1981 break;
1982 case TGSI_OPCODE_ENDIF:
1983 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
1984
1985 /* try to replace branch over 1 insn with a predicated insn */
1986 if (nv50_kill_branch(pc) == TRUE)
1987 break;
1988
1989 if (pc->br_join[pc->if_lvl]) {
1990 pc->br_join[pc->if_lvl]->param.index = pc->p->exec_size;
1991 pc->br_join[pc->if_lvl] = NULL;
1992 }
1993 terminate_mbb(pc);
1994 /* emit a NOP as join point, we could set it on the next
1995 * one, but would have to make sure it is long and !immd
1996 */
1997 emit_nop(pc);
1998 pc->p->exec_tail->inst[1] |= 2;
1999 break;
2000 case TGSI_OPCODE_ENDLOOP:
2001 emit_branch(pc, -1, 0, NULL);
2002 pc->p->exec_tail->param.index = pc->loop_pos[--pc->loop_lvl];
2003 pc->br_loop[pc->loop_lvl]->param.index = pc->p->exec_size;
2004 terminate_mbb(pc);
2005 break;
2006 case TGSI_OPCODE_EX2:
2007 emit_preex2(pc, temp, src[0][0]);
2008 emit_flop(pc, 6, brdc, temp);
2009 break;
2010 case TGSI_OPCODE_FLR:
2011 for (c = 0; c < 4; c++) {
2012 if (!(mask & (1 << c)))
2013 continue;
2014 emit_flr(pc, dst[c], src[0][c]);
2015 }
2016 break;
2017 case TGSI_OPCODE_FRC:
2018 temp = temp_temp(pc);
2019 for (c = 0; c < 4; c++) {
2020 if (!(mask & (1 << c)))
2021 continue;
2022 emit_flr(pc, temp, src[0][c]);
2023 emit_sub(pc, dst[c], src[0][c], temp);
2024 }
2025 break;
2026 case TGSI_OPCODE_IF:
2027 /* emitting a join_at may not be necessary */
2028 assert(pc->if_lvl < MAX_IF_DEPTH);
2029 set_pred_wr(pc, 1, 0, pc->if_cond);
2030 emit_branch(pc, 0, 2, &pc->br_join[pc->if_lvl]);
2031 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2032 terminate_mbb(pc);
2033 break;
2034 case TGSI_OPCODE_KIL:
2035 emit_kil(pc, src[0][0]);
2036 emit_kil(pc, src[0][1]);
2037 emit_kil(pc, src[0][2]);
2038 emit_kil(pc, src[0][3]);
2039 break;
2040 case TGSI_OPCODE_LIT:
2041 emit_lit(pc, &dst[0], mask, &src[0][0]);
2042 break;
2043 case TGSI_OPCODE_LG2:
2044 emit_flop(pc, 3, brdc, src[0][0]);
2045 break;
2046 case TGSI_OPCODE_LRP:
2047 temp = temp_temp(pc);
2048 for (c = 0; c < 4; c++) {
2049 if (!(mask & (1 << c)))
2050 continue;
2051 emit_sub(pc, temp, src[1][c], src[2][c]);
2052 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2053 }
2054 break;
2055 case TGSI_OPCODE_MAD:
2056 for (c = 0; c < 4; c++) {
2057 if (!(mask & (1 << c)))
2058 continue;
2059 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2060 }
2061 break;
2062 case TGSI_OPCODE_MAX:
2063 for (c = 0; c < 4; c++) {
2064 if (!(mask & (1 << c)))
2065 continue;
2066 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
2067 }
2068 break;
2069 case TGSI_OPCODE_MIN:
2070 for (c = 0; c < 4; c++) {
2071 if (!(mask & (1 << c)))
2072 continue;
2073 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
2074 }
2075 break;
2076 case TGSI_OPCODE_MOV:
2077 for (c = 0; c < 4; c++) {
2078 if (!(mask & (1 << c)))
2079 continue;
2080 emit_mov(pc, dst[c], src[0][c]);
2081 }
2082 break;
2083 case TGSI_OPCODE_MUL:
2084 for (c = 0; c < 4; c++) {
2085 if (!(mask & (1 << c)))
2086 continue;
2087 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2088 }
2089 break;
2090 case TGSI_OPCODE_POW:
2091 emit_pow(pc, brdc, src[0][0], src[1][0]);
2092 break;
2093 case TGSI_OPCODE_RCP:
2094 emit_flop(pc, 0, brdc, src[0][0]);
2095 break;
2096 case TGSI_OPCODE_RSQ:
2097 emit_flop(pc, 2, brdc, src[0][0]);
2098 break;
2099 case TGSI_OPCODE_SCS:
2100 temp = temp_temp(pc);
2101 if (mask & 3)
2102 emit_precossin(pc, temp, src[0][0]);
2103 if (mask & (1 << 0))
2104 emit_flop(pc, 5, dst[0], temp);
2105 if (mask & (1 << 1))
2106 emit_flop(pc, 4, dst[1], temp);
2107 if (mask & (1 << 2))
2108 emit_mov_immdval(pc, dst[2], 0.0);
2109 if (mask & (1 << 3))
2110 emit_mov_immdval(pc, dst[3], 1.0);
2111 break;
2112 case TGSI_OPCODE_SIN:
2113 if (mask & 8) {
2114 emit_precossin(pc, temp, src[0][3]);
2115 emit_flop(pc, 4, dst[3], temp);
2116 if (!(mask &= 7))
2117 break;
2118 if (temp == dst[3])
2119 temp = brdc = temp_temp(pc);
2120 }
2121 emit_precossin(pc, temp, src[0][0]);
2122 emit_flop(pc, 4, brdc, temp);
2123 break;
2124 case TGSI_OPCODE_SLT:
2125 case TGSI_OPCODE_SGE:
2126 case TGSI_OPCODE_SEQ:
2127 case TGSI_OPCODE_SGT:
2128 case TGSI_OPCODE_SLE:
2129 case TGSI_OPCODE_SNE:
2130 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
2131 for (c = 0; c < 4; c++) {
2132 if (!(mask & (1 << c)))
2133 continue;
2134 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
2135 }
2136 break;
2137 case TGSI_OPCODE_SUB:
2138 for (c = 0; c < 4; c++) {
2139 if (!(mask & (1 << c)))
2140 continue;
2141 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2142 }
2143 break;
2144 case TGSI_OPCODE_TEX:
2145 emit_tex(pc, dst, mask, src[0], unit,
2146 inst->InstructionExtTexture.Texture, FALSE);
2147 break;
2148 case TGSI_OPCODE_TXP:
2149 emit_tex(pc, dst, mask, src[0], unit,
2150 inst->InstructionExtTexture.Texture, TRUE);
2151 break;
2152 case TGSI_OPCODE_TRUNC:
2153 for (c = 0; c < 4; c++) {
2154 if (!(mask & (1 << c)))
2155 continue;
2156 emit_cvt(pc, dst[c], src[0][c], -1,
2157 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
2158 }
2159 break;
2160 case TGSI_OPCODE_XPD:
2161 temp = temp_temp(pc);
2162 if (mask & (1 << 0)) {
2163 emit_mul(pc, temp, src[0][2], src[1][1]);
2164 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2165 }
2166 if (mask & (1 << 1)) {
2167 emit_mul(pc, temp, src[0][0], src[1][2]);
2168 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2169 }
2170 if (mask & (1 << 2)) {
2171 emit_mul(pc, temp, src[0][1], src[1][0]);
2172 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2173 }
2174 if (mask & (1 << 3))
2175 emit_mov_immdval(pc, dst[3], 1.0);
2176 break;
2177 case TGSI_OPCODE_END:
2178 break;
2179 default:
2180 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2181 return FALSE;
2182 }
2183
2184 if (brdc) {
2185 if (sat)
2186 emit_sat(pc, brdc, brdc);
2187 for (c = 0; c < 4; c++)
2188 if ((mask & (1 << c)) && dst[c] != brdc)
2189 emit_mov(pc, dst[c], brdc);
2190 } else
2191 if (sat) {
2192 for (c = 0; c < 4; c++) {
2193 if (!(mask & (1 << c)))
2194 continue;
2195 /* In this case we saturate later, and dst[c] won't
2196 * be another temp_temp (and thus lost), since rdst
2197 * already is TEMP (see above). */
2198 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2199 continue;
2200 emit_sat(pc, rdst[c], dst[c]);
2201 }
2202 }
2203
2204 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2205 for (c = 0; c < 4; c++) {
2206 if (!src[i][c])
2207 continue;
2208 src[i][c]->neg = 0;
2209 if (src[i][c]->index == -1 && src[i][c]->type == P_IMMD)
2210 FREE(src[i][c]);
2211 else
2212 if (src[i][c]->acc < 0 && src[i][c]->type == P_CONST)
2213 FREE(src[i][c]); /* indirect constant */
2214 }
2215 }
2216
2217 kill_temp_temp(pc);
2218 return TRUE;
2219 }
2220
2221 static void
2222 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2223 {
2224 struct nv50_reg *reg = NULL;
2225 const struct tgsi_full_src_register *src;
2226 const struct tgsi_dst_register *dst;
2227 unsigned i, c, k, mask;
2228
2229 dst = &insn->FullDstRegisters[0].DstRegister;
2230 mask = dst->WriteMask;
2231
2232 if (dst->File == TGSI_FILE_TEMPORARY)
2233 reg = pc->temp;
2234 else
2235 if (dst->File == TGSI_FILE_OUTPUT)
2236 reg = pc->result;
2237
2238 if (reg) {
2239 for (c = 0; c < 4; c++) {
2240 if (!(mask & (1 << c)))
2241 continue;
2242 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2243 }
2244 }
2245
2246 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2247 src = &insn->FullSrcRegisters[i];
2248
2249 if (src->SrcRegister.File == TGSI_FILE_TEMPORARY)
2250 reg = pc->temp;
2251 else
2252 if (src->SrcRegister.File == TGSI_FILE_INPUT)
2253 reg = pc->attr;
2254 else
2255 continue;
2256
2257 mask = nv50_tgsi_src_mask(insn, i);
2258
2259 for (c = 0; c < 4; c++) {
2260 if (!(mask & (1 << c)))
2261 continue;
2262 k = tgsi_util_get_full_src_register_swizzle(src, c);
2263
2264 reg[src->SrcRegister.Index * 4 + k].acc = pc->insn_nr;
2265 }
2266 }
2267 }
2268
2269 /* Returns a bitmask indicating which dst components need to be
2270 * written to temporaries first to avoid 'corrupting' sources.
2271 *
2272 * m[i] (out) indicate component to write in the i-th position
2273 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2274 */
2275 static unsigned
2276 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2277 {
2278 unsigned i, c, x, unsafe;
2279
2280 for (c = 0; c < 4; c++)
2281 m[c] = c;
2282
2283 /* Swap as long as a dst component written earlier is depended on
2284 * by one written later, but the next one isn't depended on by it.
2285 */
2286 for (c = 0; c < 3; c++) {
2287 if (rdep[m[c + 1]] & (1 << m[c]))
2288 continue; /* if next one is depended on by us */
2289 for (i = c + 1; i < 4; i++)
2290 /* if we are depended on by a later one */
2291 if (rdep[m[c]] & (1 << m[i]))
2292 break;
2293 if (i == 4)
2294 continue;
2295 /* now, swap */
2296 x = m[c];
2297 m[c] = m[c + 1];
2298 m[c + 1] = x;
2299
2300 /* restart */
2301 c = 0;
2302 }
2303
2304 /* mark dependencies that could not be resolved by reordering */
2305 for (i = 0; i < 3; ++i)
2306 for (c = i + 1; c < 4; ++c)
2307 if (rdep[m[i]] & (1 << m[c]))
2308 unsafe |= (1 << i);
2309
2310 /* NOTE: $unsafe is with respect to order, not component */
2311 return unsafe;
2312 }
2313
2314 /* Select a suitable dst register for broadcasting scalar results,
2315 * or return NULL if we have to allocate an extra TEMP.
2316 *
2317 * If e.g. only 1 component is written, we may also emit the final
2318 * result to a write-only register.
2319 */
2320 static struct nv50_reg *
2321 tgsi_broadcast_dst(struct nv50_pc *pc,
2322 const struct tgsi_full_dst_register *fd, unsigned mask)
2323 {
2324 if (fd->DstRegister.File == TGSI_FILE_TEMPORARY) {
2325 int c = ffs(~mask & fd->DstRegister.WriteMask);
2326 if (c)
2327 return tgsi_dst(pc, c - 1, fd);
2328 } else {
2329 int c = ffs(fd->DstRegister.WriteMask) - 1;
2330 if ((1 << c) == fd->DstRegister.WriteMask)
2331 return tgsi_dst(pc, c, fd);
2332 }
2333
2334 return NULL;
2335 }
2336
2337 /* Scan source swizzles and return a bitmask indicating dst regs that
2338 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2339 */
2340 static unsigned
2341 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2342 unsigned rdep[4])
2343 {
2344 const struct tgsi_full_dst_register *fd = &insn->FullDstRegisters[0];
2345 const struct tgsi_full_src_register *fs;
2346 unsigned i, deqs = 0;
2347
2348 for (i = 0; i < 4; ++i)
2349 rdep[i] = 0;
2350
2351 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2352 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2353 boolean neg_supp = negate_supported(insn, i);
2354
2355 fs = &insn->FullSrcRegisters[i];
2356 if (fs->SrcRegister.File != fd->DstRegister.File ||
2357 fs->SrcRegister.Index != fd->DstRegister.Index)
2358 continue;
2359
2360 for (chn = 0; chn < 4; ++chn) {
2361 unsigned s, c;
2362
2363 if (!(mask & (1 << chn))) /* src is not read */
2364 continue;
2365 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2366 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2367
2368 if (!(fd->DstRegister.WriteMask & (1 << c)))
2369 continue;
2370
2371 /* no danger if src is copied to TEMP first */
2372 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2373 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2374 continue;
2375
2376 rdep[c] |= nv50_tgsi_dst_revdep(
2377 insn->Instruction.Opcode, i, chn);
2378 deqs |= (1 << c);
2379 }
2380 }
2381
2382 return deqs;
2383 }
2384
2385 static boolean
2386 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2387 {
2388 struct tgsi_full_instruction insn = tok->FullInstruction;
2389 const struct tgsi_full_dst_register *fd;
2390 unsigned i, deqs, rdep[4], m[4];
2391
2392 fd = &tok->FullInstruction.FullDstRegisters[0];
2393 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2394
2395 if (is_scalar_op(insn.Instruction.Opcode)) {
2396 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2397 if (!pc->r_brdc)
2398 pc->r_brdc = temp_temp(pc);
2399 return nv50_program_tx_insn(pc, &insn);
2400 }
2401 pc->r_brdc = NULL;
2402
2403 if (!deqs)
2404 return nv50_program_tx_insn(pc, &insn);
2405
2406 deqs = nv50_revdep_reorder(m, rdep);
2407
2408 for (i = 0; i < 4; ++i) {
2409 assert(pc->r_dst[m[i]] == NULL);
2410
2411 insn.FullDstRegisters[0].DstRegister.WriteMask =
2412 fd->DstRegister.WriteMask & (1 << m[i]);
2413
2414 if (!insn.FullDstRegisters[0].DstRegister.WriteMask)
2415 continue;
2416
2417 if (deqs & (1 << i))
2418 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2419
2420 if (!nv50_program_tx_insn(pc, &insn))
2421 return FALSE;
2422 }
2423
2424 for (i = 0; i < 4; i++) {
2425 struct nv50_reg *reg = pc->r_dst[i];
2426 if (!reg)
2427 continue;
2428 pc->r_dst[i] = NULL;
2429
2430 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2431 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2432 else
2433 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2434 free_temp(pc, reg);
2435 }
2436
2437 return TRUE;
2438 }
2439
2440 static void
2441 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2442 {
2443 struct nv50_reg *iv, **ppiv;
2444 unsigned mode = pc->interp_mode[reg->index];
2445
2446 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2447 iv = *ppiv;
2448
2449 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2450 iv = *ppiv = alloc_temp(pc, NULL);
2451 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2452
2453 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2454 emit_flop(pc, 0, iv, iv);
2455
2456 /* XXX: when loading interpolants dynamically, move these
2457 * to the program head, or make sure it can't be skipped.
2458 */
2459 }
2460
2461 emit_interp(pc, reg, iv, mode);
2462 }
2463
2464 static boolean
2465 nv50_program_tx_prep(struct nv50_pc *pc)
2466 {
2467 struct tgsi_parse_context tp;
2468 struct nv50_program *p = pc->p;
2469 boolean ret = FALSE;
2470 unsigned i, c, flat_nr = 0;
2471
2472 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2473 while (!tgsi_parse_end_of_tokens(&tp)) {
2474 const union tgsi_full_token *tok = &tp.FullToken;
2475
2476 tgsi_parse_token(&tp);
2477 switch (tok->Token.Type) {
2478 case TGSI_TOKEN_TYPE_IMMEDIATE:
2479 {
2480 const struct tgsi_full_immediate *imm =
2481 &tp.FullToken.FullImmediate;
2482
2483 ctor_immd(pc, imm->u[0].Float,
2484 imm->u[1].Float,
2485 imm->u[2].Float,
2486 imm->u[3].Float);
2487 }
2488 break;
2489 case TGSI_TOKEN_TYPE_DECLARATION:
2490 {
2491 const struct tgsi_full_declaration *d;
2492 unsigned si, last, first, mode;
2493
2494 d = &tp.FullToken.FullDeclaration;
2495 first = d->DeclarationRange.First;
2496 last = d->DeclarationRange.Last;
2497
2498 switch (d->Declaration.File) {
2499 case TGSI_FILE_TEMPORARY:
2500 break;
2501 case TGSI_FILE_OUTPUT:
2502 if (!d->Declaration.Semantic ||
2503 p->type == PIPE_SHADER_FRAGMENT)
2504 break;
2505
2506 si = d->Semantic.SemanticIndex;
2507 switch (d->Semantic.SemanticName) {
2508 case TGSI_SEMANTIC_BCOLOR:
2509 p->cfg.two_side[si].hw = first;
2510 if (p->cfg.io_nr > first)
2511 p->cfg.io_nr = first;
2512 break;
2513 case TGSI_SEMANTIC_PSIZE:
2514 p->cfg.psiz = first;
2515 if (p->cfg.io_nr > first)
2516 p->cfg.io_nr = first;
2517 break;
2518 /*
2519 case TGSI_SEMANTIC_CLIP_DISTANCE:
2520 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2521 break;
2522 */
2523 default:
2524 break;
2525 }
2526 break;
2527 case TGSI_FILE_INPUT:
2528 {
2529 if (p->type != PIPE_SHADER_FRAGMENT)
2530 break;
2531
2532 switch (d->Declaration.Interpolate) {
2533 case TGSI_INTERPOLATE_CONSTANT:
2534 mode = INTERP_FLAT;
2535 flat_nr++;
2536 break;
2537 case TGSI_INTERPOLATE_PERSPECTIVE:
2538 mode = INTERP_PERSPECTIVE;
2539 p->cfg.regs[1] |= 0x08 << 24;
2540 break;
2541 default:
2542 mode = INTERP_LINEAR;
2543 break;
2544 }
2545 if (d->Declaration.Centroid)
2546 mode |= INTERP_CENTROID;
2547
2548 assert(last < 32);
2549 for (i = first; i <= last; i++)
2550 pc->interp_mode[i] = mode;
2551 }
2552 break;
2553 case TGSI_FILE_ADDRESS:
2554 case TGSI_FILE_CONSTANT:
2555 case TGSI_FILE_SAMPLER:
2556 break;
2557 default:
2558 NOUVEAU_ERR("bad decl file %d\n",
2559 d->Declaration.File);
2560 goto out_err;
2561 }
2562 }
2563 break;
2564 case TGSI_TOKEN_TYPE_INSTRUCTION:
2565 pc->insn_nr++;
2566 prep_inspect_insn(pc, &tok->FullInstruction);
2567 break;
2568 default:
2569 break;
2570 }
2571 }
2572
2573 if (p->type == PIPE_SHADER_VERTEX) {
2574 int rid = 0;
2575
2576 for (i = 0; i < pc->attr_nr * 4; ++i) {
2577 if (pc->attr[i].acc) {
2578 pc->attr[i].hw = rid++;
2579 p->cfg.attr[i / 32] |= 1 << (i % 32);
2580 }
2581 }
2582
2583 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
2584 p->cfg.io[i].hw = rid;
2585 p->cfg.io[i].id_vp = i;
2586
2587 for (c = 0; c < 4; ++c) {
2588 int n = i * 4 + c;
2589 if (!pc->result[n].acc)
2590 continue;
2591 pc->result[n].hw = rid++;
2592 p->cfg.io[i].mask |= 1 << c;
2593 }
2594 }
2595
2596 for (c = 0; c < 2; ++c)
2597 if (p->cfg.two_side[c].hw < 0x40)
2598 p->cfg.two_side[c] = p->cfg.io[
2599 p->cfg.two_side[c].hw];
2600
2601 if (p->cfg.psiz < 0x40)
2602 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
2603 } else
2604 if (p->type == PIPE_SHADER_FRAGMENT) {
2605 int rid, aid;
2606 unsigned n = 0, m = pc->attr_nr - flat_nr;
2607
2608 int base = (TGSI_SEMANTIC_POSITION ==
2609 p->info.input_semantic_name[0]) ? 0 : 1;
2610
2611 /* non-flat interpolants have to be mapped to
2612 * the lower hardware IDs, so sort them:
2613 */
2614 for (i = 0; i < pc->attr_nr; i++) {
2615 if (pc->interp_mode[i] == INTERP_FLAT) {
2616 p->cfg.io[m].id_vp = i + base;
2617 p->cfg.io[m++].id_fp = i;
2618 } else {
2619 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
2620 p->cfg.io[n].linear = TRUE;
2621 p->cfg.io[n].id_vp = i + base;
2622 p->cfg.io[n++].id_fp = i;
2623 }
2624 }
2625
2626 if (!base) /* set w-coordinate mask from perspective interp */
2627 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
2628
2629 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
2630 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
2631
2632 for (n = 0; n < pc->attr_nr; ++n) {
2633 p->cfg.io[n].hw = rid = aid;
2634 i = p->cfg.io[n].id_fp;
2635
2636 for (c = 0; c < 4; ++c) {
2637 if (!pc->attr[i * 4 + c].acc)
2638 continue;
2639 pc->attr[i * 4 + c].rhw = rid++;
2640 p->cfg.io[n].mask |= 1 << c;
2641
2642 load_interpolant(pc, &pc->attr[i * 4 + c]);
2643 }
2644 aid += popcnt4(p->cfg.io[n].mask);
2645 }
2646
2647 if (!base)
2648 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
2649
2650 m = popcnt4(p->cfg.regs[1] >> 24);
2651
2652 /* set count of non-position inputs and of non-flat
2653 * non-position inputs for FP_INTERPOLANT_CTRL
2654 */
2655 p->cfg.regs[1] |= aid - m;
2656
2657 if (flat_nr) {
2658 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
2659 p->cfg.regs[1] |= (i - m) << 16;
2660 } else
2661 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
2662
2663 /* mark color semantic for light-twoside */
2664 n = 0x40;
2665 for (i = 0; i < pc->attr_nr; i++) {
2666 ubyte si, sn;
2667
2668 sn = p->info.input_semantic_name[p->cfg.io[i].id_fp];
2669 si = p->info.input_semantic_index[p->cfg.io[i].id_fp];
2670
2671 if (sn == TGSI_SEMANTIC_COLOR) {
2672 p->cfg.two_side[si] = p->cfg.io[i];
2673
2674 /* increase colour count */
2675 p->cfg.regs[0] += popcnt4(
2676 p->cfg.two_side[si].mask) << 16;
2677
2678 n = MIN2(n, p->cfg.io[i].hw - m);
2679 }
2680 }
2681 if (n < 0x40)
2682 p->cfg.regs[0] += n;
2683
2684 /* Initialize FP results:
2685 * FragDepth is always first TGSI and last hw output
2686 */
2687 i = p->info.writes_z ? 4 : 0;
2688 for (rid = 0; i < pc->result_nr * 4; i++)
2689 pc->result[i].rhw = rid++;
2690 if (p->info.writes_z)
2691 pc->result[2].rhw = rid;
2692
2693 p->cfg.high_result = rid;
2694
2695 /* separate/different colour results for MRTs ? */
2696 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
2697 p->cfg.regs[2] |= 1;
2698 }
2699
2700 if (pc->immd_nr) {
2701 int rid = 0;
2702
2703 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
2704 if (!pc->immd)
2705 goto out_err;
2706
2707 for (i = 0; i < pc->immd_nr; i++) {
2708 for (c = 0; c < 4; c++, rid++)
2709 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
2710 }
2711 }
2712
2713 ret = TRUE;
2714 out_err:
2715 if (pc->iv_p)
2716 free_temp(pc, pc->iv_p);
2717 if (pc->iv_c)
2718 free_temp(pc, pc->iv_c);
2719
2720 tgsi_parse_free(&tp);
2721 return ret;
2722 }
2723
2724 static void
2725 free_nv50_pc(struct nv50_pc *pc)
2726 {
2727 if (pc->immd)
2728 FREE(pc->immd);
2729 if (pc->param)
2730 FREE(pc->param);
2731 if (pc->result)
2732 FREE(pc->result);
2733 if (pc->attr)
2734 FREE(pc->attr);
2735 if (pc->temp)
2736 FREE(pc->temp);
2737
2738 FREE(pc);
2739 }
2740
2741 static boolean
2742 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
2743 {
2744 int i, c;
2745 unsigned rtype[2] = { P_ATTR, P_RESULT };
2746
2747 pc->p = p;
2748 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
2749 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
2750 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
2751 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
2752 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
2753 assert(pc->addr_nr <= 2);
2754
2755 p->cfg.high_temp = 4;
2756
2757 p->cfg.two_side[0].hw = 0x40;
2758 p->cfg.two_side[1].hw = 0x40;
2759
2760 switch (p->type) {
2761 case PIPE_SHADER_VERTEX:
2762 p->cfg.psiz = 0x40;
2763 p->cfg.clpd = 0x40;
2764 p->cfg.io_nr = pc->result_nr;
2765 break;
2766 case PIPE_SHADER_FRAGMENT:
2767 rtype[0] = rtype[1] = P_TEMP;
2768
2769 p->cfg.regs[0] = 0x01000004;
2770 p->cfg.io_nr = pc->attr_nr;
2771
2772 if (p->info.writes_z) {
2773 p->cfg.regs[2] |= 0x00000100;
2774 p->cfg.regs[3] |= 0x00000011;
2775 }
2776 if (p->info.uses_kill)
2777 p->cfg.regs[2] |= 0x00100000;
2778 break;
2779 }
2780
2781 if (pc->temp_nr) {
2782 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
2783 if (!pc->temp)
2784 return FALSE;
2785
2786 for (i = 0; i < pc->temp_nr * 4; ++i)
2787 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
2788 }
2789
2790 if (pc->attr_nr) {
2791 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
2792 if (!pc->attr)
2793 return FALSE;
2794
2795 for (i = 0; i < pc->attr_nr * 4; ++i)
2796 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
2797 }
2798
2799 if (pc->result_nr) {
2800 unsigned nr = pc->result_nr * 4;
2801
2802 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
2803 if (!pc->result)
2804 return FALSE;
2805
2806 for (i = 0; i < nr; ++i)
2807 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
2808 }
2809
2810 if (pc->param_nr) {
2811 int rid = 0;
2812
2813 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
2814 if (!pc->param)
2815 return FALSE;
2816
2817 for (i = 0; i < pc->param_nr; ++i)
2818 for (c = 0; c < 4; ++c, ++rid)
2819 ctor_reg(&pc->param[rid], P_CONST, i, rid);
2820 }
2821
2822 if (pc->addr_nr) {
2823 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
2824 if (!pc->addr)
2825 return FALSE;
2826 }
2827 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
2828 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
2829
2830 return TRUE;
2831 }
2832
2833 static void
2834 nv50_fp_move_results(struct nv50_pc *pc)
2835 {
2836 struct nv50_reg reg;
2837 unsigned i;
2838
2839 ctor_reg(&reg, P_TEMP, -1, -1);
2840
2841 for (i = 0; i < pc->result_nr * 4; ++i) {
2842 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2843 continue;
2844 if (pc->result[i].rhw != pc->result[i].hw) {
2845 reg.hw = pc->result[i].rhw;
2846 emit_mov(pc, &reg, &pc->result[i]);
2847 }
2848 }
2849 }
2850
2851 static void
2852 nv50_program_fixup_insns(struct nv50_pc *pc)
2853 {
2854 struct nv50_program_exec *e, *prev = NULL, **bra_list;
2855 unsigned i, n, pos;
2856
2857 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
2858
2859 /* Collect branch instructions, we need to adjust their offsets
2860 * when converting 32 bit instructions to 64 bit ones
2861 */
2862 for (n = 0, e = pc->p->exec_head; e; e = e->next)
2863 if (e->param.index >= 0 && !e->param.mask)
2864 bra_list[n++] = e;
2865
2866 /* Make sure we don't have any single 32 bit instructions. */
2867 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
2868 pos += is_long(e) ? 2 : 1;
2869
2870 if ((pos & 1) && (!e->next || is_long(e->next))) {
2871 for (i = 0; i < n; ++i)
2872 if (bra_list[i]->param.index >= pos)
2873 bra_list[i]->param.index += 1;
2874 convert_to_long(pc, e);
2875 ++pos;
2876 }
2877 if (e->next)
2878 prev = e;
2879 }
2880
2881 assert(!is_immd(pc->p->exec_head));
2882 assert(!is_immd(pc->p->exec_tail));
2883
2884 /* last instruction must be long so it can have the end bit set */
2885 if (!is_long(pc->p->exec_tail)) {
2886 convert_to_long(pc, pc->p->exec_tail);
2887 if (prev)
2888 convert_to_long(pc, prev);
2889 }
2890 assert(!(pc->p->exec_tail->inst[1] & 2));
2891 /* set the end-bit */
2892 pc->p->exec_tail->inst[1] |= 1;
2893
2894 FREE(bra_list);
2895 }
2896
2897 static boolean
2898 nv50_program_tx(struct nv50_program *p)
2899 {
2900 struct tgsi_parse_context parse;
2901 struct nv50_pc *pc;
2902 boolean ret;
2903
2904 pc = CALLOC_STRUCT(nv50_pc);
2905 if (!pc)
2906 return FALSE;
2907
2908 ret = ctor_nv50_pc(pc, p);
2909 if (ret == FALSE)
2910 goto out_cleanup;
2911
2912 ret = nv50_program_tx_prep(pc);
2913 if (ret == FALSE)
2914 goto out_cleanup;
2915
2916 tgsi_parse_init(&parse, pc->p->pipe.tokens);
2917 while (!tgsi_parse_end_of_tokens(&parse)) {
2918 const union tgsi_full_token *tok = &parse.FullToken;
2919
2920 /* don't allow half insn/immd on first and last instruction */
2921 pc->allow32 = TRUE;
2922 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr)
2923 pc->allow32 = FALSE;
2924
2925 tgsi_parse_token(&parse);
2926
2927 switch (tok->Token.Type) {
2928 case TGSI_TOKEN_TYPE_INSTRUCTION:
2929 ++pc->insn_cur;
2930 ret = nv50_tgsi_insn(pc, tok);
2931 if (ret == FALSE)
2932 goto out_err;
2933 break;
2934 default:
2935 break;
2936 }
2937 }
2938
2939 if (pc->p->type == PIPE_SHADER_FRAGMENT)
2940 nv50_fp_move_results(pc);
2941
2942 nv50_program_fixup_insns(pc);
2943
2944 p->param_nr = pc->param_nr * 4;
2945 p->immd_nr = pc->immd_nr * 4;
2946 p->immd = pc->immd_buf;
2947
2948 out_err:
2949 tgsi_parse_free(&parse);
2950
2951 out_cleanup:
2952 free_nv50_pc(pc);
2953 return ret;
2954 }
2955
2956 static void
2957 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
2958 {
2959 if (nv50_program_tx(p) == FALSE)
2960 assert(0);
2961 p->translated = TRUE;
2962 }
2963
2964 static void
2965 nv50_program_upload_data(struct nv50_context *nv50, float *map,
2966 unsigned start, unsigned count, unsigned cbuf)
2967 {
2968 struct nouveau_channel *chan = nv50->screen->base.channel;
2969 struct nouveau_grobj *tesla = nv50->screen->tesla;
2970
2971 while (count) {
2972 unsigned nr = count > 2047 ? 2047 : count;
2973
2974 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
2975 OUT_RING (chan, (cbuf << 0) | (start << 8));
2976 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
2977 OUT_RINGp (chan, map, nr);
2978
2979 map += nr;
2980 start += nr;
2981 count -= nr;
2982 }
2983 }
2984
2985 static void
2986 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
2987 {
2988 struct pipe_screen *pscreen = nv50->pipe.screen;
2989
2990 if (!p->data[0] && p->immd_nr) {
2991 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
2992
2993 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
2994 while (heap->next && heap->size < p->immd_nr) {
2995 struct nv50_program *evict = heap->next->priv;
2996 nouveau_resource_free(&evict->data[0]);
2997 }
2998
2999 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3000 &p->data[0]))
3001 assert(0);
3002 }
3003
3004 /* immediates only need to be uploaded again when freed */
3005 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3006 p->immd_nr, NV50_CB_PMISC);
3007 }
3008
3009 assert(p->param_nr <= 512);
3010
3011 if (p->param_nr) {
3012 unsigned cb;
3013 float *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3014 PIPE_BUFFER_USAGE_CPU_READ);
3015
3016 if (p->type == PIPE_SHADER_VERTEX)
3017 cb = NV50_CB_PVP;
3018 else
3019 cb = NV50_CB_PFP;
3020
3021 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3022 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3023 }
3024 }
3025
3026 static void
3027 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3028 {
3029 struct nouveau_channel *chan = nv50->screen->base.channel;
3030 struct nv50_program_exec *e;
3031 uint32_t *up, i;
3032 boolean upload = FALSE;
3033
3034 if (!p->bo) {
3035 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3036 p->exec_size * 4, &p->bo);
3037 upload = TRUE;
3038 }
3039
3040 if (p->data[0] && p->data[0]->start != p->data_start[0])
3041 upload = TRUE;
3042
3043 if (!upload)
3044 return;
3045
3046 up = MALLOC(p->exec_size * 4);
3047
3048 for (i = 0, e = p->exec_head; e; e = e->next) {
3049 unsigned ei, ci, bs;
3050
3051 if (e->param.index >= 0 && e->param.mask) {
3052 bs = (e->inst[1] >> 22) & 0x07;
3053 assert(bs < 2);
3054 ei = e->param.shift >> 5;
3055 ci = e->param.index;
3056 if (bs == 0)
3057 ci += p->data[bs]->start;
3058
3059 e->inst[ei] &= ~e->param.mask;
3060 e->inst[ei] |= (ci << e->param.shift);
3061 } else
3062 if (e->param.index >= 0) {
3063 /* zero mask means param is a jump/branch offset */
3064 assert(!(e->param.index & 1));
3065 /* seem to be 8 byte steps */
3066 ei = (e->param.index >> 1) + 0 /* START_ID */;
3067
3068 e->inst[0] &= 0xf0000fff;
3069 e->inst[0] |= ei << 12;
3070 }
3071
3072 up[i++] = e->inst[0];
3073 if (is_long(e))
3074 up[i++] = e->inst[1];
3075 }
3076 assert(i == p->exec_size);
3077
3078 if (p->data[0])
3079 p->data_start[0] = p->data[0]->start;
3080
3081 #ifdef NV50_PROGRAM_DUMP
3082 NOUVEAU_ERR("-------\n");
3083 for (e = p->exec_head; e; e = e->next) {
3084 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3085 if (is_long(e))
3086 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3087 }
3088 #endif
3089 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3090 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3091 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3092 0, 0, p->exec_size * 4, 1, 1);
3093
3094 FREE(up);
3095 }
3096
3097 void
3098 nv50_vertprog_validate(struct nv50_context *nv50)
3099 {
3100 struct nouveau_grobj *tesla = nv50->screen->tesla;
3101 struct nv50_program *p = nv50->vertprog;
3102 struct nouveau_stateobj *so;
3103
3104 if (!p->translated) {
3105 nv50_program_validate(nv50, p);
3106 if (!p->translated)
3107 assert(0);
3108 }
3109
3110 nv50_program_validate_data(nv50, p);
3111 nv50_program_validate_code(nv50, p);
3112
3113 so = so_new(13, 2);
3114 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3115 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3116 NOUVEAU_BO_HIGH, 0, 0);
3117 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3118 NOUVEAU_BO_LOW, 0, 0);
3119 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3120 so_data (so, p->cfg.attr[0]);
3121 so_data (so, p->cfg.attr[1]);
3122 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3123 so_data (so, p->cfg.high_result);
3124 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3125 so_data (so, p->cfg.high_result); //8);
3126 so_data (so, p->cfg.high_temp);
3127 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3128 so_data (so, 0); /* program start offset */
3129 so_ref(so, &nv50->state.vertprog);
3130 so_ref(NULL, &so);
3131 }
3132
3133 void
3134 nv50_fragprog_validate(struct nv50_context *nv50)
3135 {
3136 struct nouveau_grobj *tesla = nv50->screen->tesla;
3137 struct nv50_program *p = nv50->fragprog;
3138 struct nouveau_stateobj *so;
3139
3140 if (!p->translated) {
3141 nv50_program_validate(nv50, p);
3142 if (!p->translated)
3143 assert(0);
3144 }
3145
3146 nv50_program_validate_data(nv50, p);
3147 nv50_program_validate_code(nv50, p);
3148
3149 so = so_new(64, 2);
3150 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3151 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3152 NOUVEAU_BO_HIGH, 0, 0);
3153 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3154 NOUVEAU_BO_LOW, 0, 0);
3155 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3156 so_data (so, p->cfg.high_temp);
3157 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3158 so_data (so, p->cfg.high_result);
3159 so_method(so, tesla, NV50TCL_FP_CTRL_UNK19A8, 1);
3160 so_data (so, p->cfg.regs[2]);
3161 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3162 so_data (so, p->cfg.regs[3]);
3163 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3164 so_data (so, 0); /* program start offset */
3165 so_ref(so, &nv50->state.fragprog);
3166 so_ref(NULL, &so);
3167 }
3168
3169 static void
3170 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3171 {
3172 struct nv50_program *fp = nv50->fragprog;
3173 struct nv50_program *vp = nv50->vertprog;
3174 unsigned i, c, m = base;
3175
3176 /* XXX: This can't work correctly in all cases yet, we either
3177 * have to create TGSI_SEMANTIC_PNTC or sprite_coord_mode has
3178 * to be per FP input instead of per VP output
3179 */
3180 memset(pntc, 0, 8 * sizeof(uint32_t));
3181
3182 for (i = 0; i < fp->cfg.io_nr; i++) {
3183 uint8_t sn, si;
3184 uint8_t j = fp->cfg.io[i].id_vp, k = fp->cfg.io[i].id_fp;
3185 unsigned n = popcnt4(fp->cfg.io[i].mask);
3186
3187 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3188 m += n;
3189 continue;
3190 }
3191
3192 sn = vp->info.input_semantic_name[j];
3193 si = vp->info.input_semantic_index[j];
3194
3195 if (j < fp->cfg.io_nr && sn == TGSI_SEMANTIC_GENERIC) {
3196 ubyte mode =
3197 nv50->rasterizer->pipe.sprite_coord_mode[si];
3198
3199 if (mode == PIPE_SPRITE_COORD_NONE) {
3200 m += n;
3201 continue;
3202 }
3203 }
3204
3205 /* this is either PointCoord or replaced by sprite coords */
3206 for (c = 0; c < 4; c++) {
3207 if (!(fp->cfg.io[i].mask & (1 << c)))
3208 continue;
3209 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3210 ++m;
3211 }
3212 }
3213 }
3214
3215 static int
3216 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3217 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3218 {
3219 int c;
3220 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3221 uint8_t *map = (uint8_t *)p_map;
3222
3223 for (c = 0; c < 4; ++c) {
3224 if (mf & 1) {
3225 if (fpi->linear == TRUE)
3226 lin[mid / 32] |= 1 << (mid % 32);
3227 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3228 }
3229
3230 oid += mv & 1;
3231 mf >>= 1;
3232 mv >>= 1;
3233 }
3234
3235 return mid;
3236 }
3237
3238 void
3239 nv50_linkage_validate(struct nv50_context *nv50)
3240 {
3241 struct nouveau_grobj *tesla = nv50->screen->tesla;
3242 struct nv50_program *vp = nv50->vertprog;
3243 struct nv50_program *fp = nv50->fragprog;
3244 struct nouveau_stateobj *so;
3245 struct nv50_sreg4 dummy, *vpo;
3246 int i, n, c, m = 0;
3247 uint32_t map[16], lin[4], reg[5], pcrd[8];
3248
3249 memset(map, 0, sizeof(map));
3250 memset(lin, 0, sizeof(lin));
3251
3252 reg[1] = 0x00000004; /* low and high clip distance map ids */
3253 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3254 reg[3] = 0x00000000; /* point size map id & enable */
3255 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3256 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3257
3258 dummy.linear = FALSE;
3259 dummy.mask = 0xf; /* map all components of HPOS */
3260 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3261
3262 dummy.mask = 0x0;
3263
3264 if (vp->cfg.clpd < 0x40) {
3265 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3266 map[m++] = vp->cfg.clpd + c;
3267 reg[1] = (m << 8);
3268 }
3269
3270 reg[0] |= m << 8; /* adjust BFC0 id */
3271
3272 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3273 if (nv50->rasterizer->pipe.light_twoside) {
3274 vpo = &vp->cfg.two_side[0];
3275
3276 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3277 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3278 }
3279
3280 reg[0] += m - 4; /* adjust FFC0 id */
3281 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3282
3283 i = 0;
3284 if (fp->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION)
3285 i = 1;
3286 for (; i < fp->cfg.io_nr; i++) {
3287 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id_fp];
3288 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id_fp];
3289
3290 n = fp->cfg.io[i].id_vp;
3291 if (n >= vp->cfg.io_nr ||
3292 vp->info.output_semantic_name[n] != sn ||
3293 vp->info.output_semantic_index[n] != si)
3294 vpo = &dummy;
3295 else
3296 vpo = &vp->cfg.io[n];
3297
3298 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3299 }
3300
3301 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3302 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3303 reg[3] = (m++ << 4) | 1;
3304 }
3305
3306 /* now fill the stateobj */
3307 so = so_new(64, 0);
3308
3309 n = (m + 3) / 4;
3310 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3311 so_data (so, m);
3312 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3313 so_datap (so, map, n);
3314
3315 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3316 so_datap (so, reg, 4);
3317
3318 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3319 so_data (so, reg[4]);
3320
3321 so_method(so, tesla, 0x1540, 4);
3322 so_datap (so, lin, 4);
3323
3324 if (nv50->rasterizer->pipe.point_sprite) {
3325 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3326
3327 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3328 so_datap (so, pcrd, 8);
3329 }
3330
3331 so_ref(so, &nv50->state.programs);
3332 so_ref(NULL, &so);
3333 }
3334
3335 void
3336 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3337 {
3338 while (p->exec_head) {
3339 struct nv50_program_exec *e = p->exec_head;
3340
3341 p->exec_head = e->next;
3342 FREE(e);
3343 }
3344 p->exec_tail = NULL;
3345 p->exec_size = 0;
3346
3347 nouveau_bo_ref(NULL, &p->bo);
3348
3349 nouveau_resource_free(&p->data[0]);
3350
3351 p->translated = 0;
3352 }