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nv50: support for geometry programs in nv50_program
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95
96 int vtx; /* vertex index, for GP inputs (TGSI Dimension.Index) */
97 int indirect[2]; /* index into pc->addr, or -1 */
98 };
99
100 #define NV50_MOD_NEG 1
101 #define NV50_MOD_ABS 2
102 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
103 #define NV50_MOD_SAT 4
104 #define NV50_MOD_I32 8
105
106 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
107
108 /* STACK: Conditionals and loops have to use the (per warp) stack.
109 * Stack entries consist of an entry type (divergent path, join at),
110 * a mask indicating the active threads of the warp, and an address.
111 * MPs can store 12 stack entries internally, if we need more (and
112 * we probably do), we have to create a stack buffer in VRAM.
113 */
114 /* impose low limits for now */
115 #define NV50_MAX_COND_NESTING 4
116 #define NV50_MAX_LOOP_NESTING 3
117
118 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
119
120 struct nv50_pc {
121 struct nv50_program *p;
122
123 /* hw resources */
124 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
125 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
126
127 /* tgsi resources */
128 struct nv50_reg *temp;
129 int temp_nr;
130 struct nv50_reg *attr;
131 int attr_nr;
132 struct nv50_reg *result;
133 int result_nr;
134 struct nv50_reg *param;
135 int param_nr;
136 struct nv50_reg *immd;
137 uint32_t *immd_buf;
138 int immd_nr;
139 struct nv50_reg **addr;
140 int addr_nr;
141
142 struct nv50_reg *temp_temp[16];
143 struct nv50_program_exec *temp_temp_exec[16];
144 unsigned temp_temp_nr;
145
146 /* broadcast and destination replacement regs */
147 struct nv50_reg *r_brdc;
148 struct nv50_reg *r_dst[4];
149
150 struct nv50_reg reg_instances[16];
151 unsigned reg_instance_nr;
152
153 unsigned interp_mode[32];
154 /* perspective interpolation registers */
155 struct nv50_reg *iv_p;
156 struct nv50_reg *iv_c;
157
158 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
159 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
160 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
161 int if_lvl, loop_lvl;
162 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
163
164 unsigned *insn_pos; /* actual program offset of each TGSI insn */
165 boolean in_subroutine;
166
167 /* current instruction and total number of insns */
168 unsigned insn_cur;
169 unsigned insn_nr;
170
171 boolean allow32;
172
173 uint8_t edgeflag_out;
174 };
175
176 static struct nv50_reg *get_address_reg(struct nv50_pc *, struct nv50_reg *);
177
178 static INLINE void
179 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
180 {
181 reg->type = type;
182 reg->index = index;
183 reg->hw = hw;
184 reg->mod = 0;
185 reg->rhw = -1;
186 reg->vtx = -1;
187 reg->acc = 0;
188 reg->indirect[0] = reg->indirect[1] = -1;
189 }
190
191 static INLINE unsigned
192 popcnt4(uint32_t val)
193 {
194 static const unsigned cnt[16]
195 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
196 return cnt[val & 0xf];
197 }
198
199 static void
200 terminate_mbb(struct nv50_pc *pc)
201 {
202 int i;
203
204 /* remove records of temporary address register values */
205 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
206 if (pc->r_addr[i].index < 0)
207 pc->r_addr[i].acc = 0;
208 }
209
210 static void
211 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
212 {
213 int i = 0;
214
215 if (reg->type == P_RESULT) {
216 if (pc->p->cfg.high_result < (reg->hw + 1))
217 pc->p->cfg.high_result = reg->hw + 1;
218 }
219
220 if (reg->type != P_TEMP)
221 return;
222
223 if (reg->hw >= 0) {
224 /*XXX: do this here too to catch FP temp-as-attr usage..
225 * not clean, but works */
226 if (pc->p->cfg.high_temp < (reg->hw + 1))
227 pc->p->cfg.high_temp = reg->hw + 1;
228 return;
229 }
230
231 if (reg->rhw != -1) {
232 /* try to allocate temporary with index rhw first */
233 if (!(pc->r_temp[reg->rhw])) {
234 pc->r_temp[reg->rhw] = reg;
235 reg->hw = reg->rhw;
236 if (pc->p->cfg.high_temp < (reg->rhw + 1))
237 pc->p->cfg.high_temp = reg->rhw + 1;
238 return;
239 }
240 /* make sure we don't get things like $r0 needs to go
241 * in $r1 and $r1 in $r0
242 */
243 i = pc->result_nr * 4;
244 }
245
246 for (; i < NV50_SU_MAX_TEMP; i++) {
247 if (!(pc->r_temp[i])) {
248 pc->r_temp[i] = reg;
249 reg->hw = i;
250 if (pc->p->cfg.high_temp < (i + 1))
251 pc->p->cfg.high_temp = i + 1;
252 return;
253 }
254 }
255
256 NOUVEAU_ERR("out of registers\n");
257 abort();
258 }
259
260 static INLINE struct nv50_reg *
261 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
262 {
263 struct nv50_reg *ri;
264
265 assert(pc->reg_instance_nr < 16);
266 ri = &pc->reg_instances[pc->reg_instance_nr++];
267 if (reg) {
268 alloc_reg(pc, reg);
269 *ri = *reg;
270 reg->indirect[0] = reg->indirect[1] = -1;
271 reg->mod = 0;
272 }
273 return ri;
274 }
275
276 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
277 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
278 * lest we risk temp_temps overwriting regs alloc'd "later".
279 */
280 static struct nv50_reg *
281 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
282 {
283 struct nv50_reg *r;
284 int i;
285
286 if (dst && dst->type == P_TEMP && dst->hw == -1)
287 return dst;
288
289 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
290 if (!pc->r_temp[i]) {
291 r = MALLOC_STRUCT(nv50_reg);
292 ctor_reg(r, P_TEMP, -1, i);
293 pc->r_temp[i] = r;
294 return r;
295 }
296 }
297
298 NOUVEAU_ERR("out of registers\n");
299 abort();
300 return NULL;
301 }
302
303 /* release the hardware resource held by r */
304 static void
305 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
306 {
307 assert(r->type == P_TEMP);
308 if (r->hw == -1)
309 return;
310
311 assert(pc->r_temp[r->hw] == r);
312 pc->r_temp[r->hw] = NULL;
313
314 r->acc = 0;
315 if (r->index == -1)
316 FREE(r);
317 }
318
319 static void
320 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
321 {
322 if (r->index == -1) {
323 unsigned hw = r->hw;
324
325 FREE(pc->r_temp[hw]);
326 pc->r_temp[hw] = NULL;
327 }
328 }
329
330 static int
331 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
332 {
333 int i;
334
335 if ((idx + 4) >= NV50_SU_MAX_TEMP)
336 return 1;
337
338 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
339 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
340 return alloc_temp4(pc, dst, idx + 4);
341
342 for (i = 0; i < 4; i++) {
343 dst[i] = MALLOC_STRUCT(nv50_reg);
344 ctor_reg(dst[i], P_TEMP, -1, idx + i);
345 pc->r_temp[idx + i] = dst[i];
346 }
347
348 return 0;
349 }
350
351 static void
352 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
353 {
354 int i;
355
356 for (i = 0; i < 4; i++)
357 free_temp(pc, reg[i]);
358 }
359
360 static struct nv50_reg *
361 temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
362 {
363 if (pc->temp_temp_nr >= 16)
364 assert(0);
365
366 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
367 pc->temp_temp_exec[pc->temp_temp_nr] = e;
368 return pc->temp_temp[pc->temp_temp_nr++];
369 }
370
371 /* This *must* be called for all nv50_program_exec that have been
372 * given as argument to temp_temp, or the temps will be leaked !
373 */
374 static void
375 kill_temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
376 {
377 int i;
378
379 for (i = 0; i < pc->temp_temp_nr; i++)
380 if (pc->temp_temp_exec[i] == e)
381 free_temp(pc, pc->temp_temp[i]);
382 if (!e)
383 pc->temp_temp_nr = 0;
384 }
385
386 static int
387 ctor_immd_4u32(struct nv50_pc *pc,
388 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
389 {
390 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
391
392 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
393
394 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
395 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
396 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
397 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
398
399 return pc->immd_nr++;
400 }
401
402 static INLINE int
403 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
404 {
405 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
406 }
407
408 static struct nv50_reg *
409 alloc_immd(struct nv50_pc *pc, float f)
410 {
411 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
412 unsigned hw;
413
414 for (hw = 0; hw < pc->immd_nr * 4; hw++)
415 if (pc->immd_buf[hw] == fui(f))
416 break;
417
418 if (hw == pc->immd_nr * 4)
419 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
420
421 ctor_reg(r, P_IMMD, -1, hw);
422 return r;
423 }
424
425 static struct nv50_program_exec *
426 exec(struct nv50_pc *pc)
427 {
428 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
429
430 e->param.index = -1;
431 return e;
432 }
433
434 static void
435 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
436 {
437 struct nv50_program *p = pc->p;
438
439 if (p->exec_tail)
440 p->exec_tail->next = e;
441 if (!p->exec_head)
442 p->exec_head = e;
443 p->exec_tail = e;
444 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
445
446 kill_temp_temp(pc, e);
447 }
448
449 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
450
451 static boolean
452 is_long(struct nv50_program_exec *e)
453 {
454 if (e->inst[0] & 1)
455 return TRUE;
456 return FALSE;
457 }
458
459 static boolean
460 is_immd(struct nv50_program_exec *e)
461 {
462 if (is_long(e) && (e->inst[1] & 3) == 3)
463 return TRUE;
464 return FALSE;
465 }
466
467 static boolean
468 is_join(struct nv50_program_exec *e)
469 {
470 if (is_long(e) && (e->inst[1] & 3) == 2)
471 return TRUE;
472 return FALSE;
473 }
474
475 static INLINE void
476 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
477 struct nv50_program_exec *e)
478 {
479 assert(!is_immd(e));
480 set_long(pc, e);
481 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
482 e->inst[1] |= (pred << 7) | (idx << 12);
483 }
484
485 static INLINE void
486 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
487 struct nv50_program_exec *e)
488 {
489 set_long(pc, e);
490 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
491 e->inst[1] |= (idx << 4) | (on << 6);
492 }
493
494 static INLINE void
495 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
496 {
497 if (is_long(e))
498 return;
499
500 e->inst[0] |= 1;
501 set_pred(pc, 0xf, 0, e);
502 set_pred_wr(pc, 0, 0, e);
503 }
504
505 static INLINE void
506 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
507 {
508 if (dst->type == P_RESULT) {
509 set_long(pc, e);
510 e->inst[1] |= 0x00000008;
511 }
512
513 alloc_reg(pc, dst);
514 if (dst->hw > 63)
515 set_long(pc, e);
516 e->inst[0] |= (dst->hw << 2);
517 }
518
519 static INLINE void
520 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
521 {
522 set_long(pc, e);
523 /* XXX: can't be predicated - bits overlap; cases where both
524 * are required should be avoided by using pc->allow32 */
525 set_pred(pc, 0, 0, e);
526 set_pred_wr(pc, 0, 0, e);
527
528 e->inst[1] |= 0x00000002 | 0x00000001;
529 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
530 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
531 }
532
533 static INLINE void
534 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
535 {
536 assert(a->type == P_ADDR);
537
538 assert(!(e->inst[0] & 0x0c000000));
539 assert(!(e->inst[1] & 0x00000004));
540
541 e->inst[0] |= (a->hw & 3) << 26;
542 e->inst[1] |= a->hw & 4;
543 }
544
545 static void
546 emit_arl(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, uint8_t);
547
548 static void
549 emit_shl_imm(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, int);
550
551 static void
552 emit_mov_from_addr(struct nv50_pc *pc, struct nv50_reg *dst,
553 struct nv50_reg *src)
554 {
555 struct nv50_program_exec *e = exec(pc);
556
557 e->inst[1] = 0x40000000;
558 set_long(pc, e);
559 set_dst(pc, dst, e);
560 set_addr(e, src);
561
562 emit(pc, e);
563 }
564
565 static void
566 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
567 struct nv50_reg *src0, uint16_t src1_val)
568 {
569 struct nv50_program_exec *e = exec(pc);
570
571 e->inst[0] = 0xd0000000 | (src1_val << 9);
572 e->inst[1] = 0x20000000;
573 set_long(pc, e);
574 e->inst[0] |= dst->hw << 2;
575 if (src0) /* otherwise will add to $a0, which is always 0 */
576 set_addr(e, src0);
577
578 emit(pc, e);
579 }
580
581 #define INTERP_LINEAR 0
582 #define INTERP_FLAT 1
583 #define INTERP_PERSPECTIVE 2
584 #define INTERP_CENTROID 4
585
586 /* interpolant index has been stored in dst->rhw */
587 static void
588 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
589 unsigned mode)
590 {
591 assert(dst->rhw != -1);
592 struct nv50_program_exec *e = exec(pc);
593
594 e->inst[0] |= 0x80000000;
595 set_dst(pc, dst, e);
596 e->inst[0] |= (dst->rhw << 16);
597
598 if (mode & INTERP_FLAT) {
599 e->inst[0] |= (1 << 8);
600 } else {
601 if (mode & INTERP_PERSPECTIVE) {
602 e->inst[0] |= (1 << 25);
603 alloc_reg(pc, iv);
604 e->inst[0] |= (iv->hw << 9);
605 }
606
607 if (mode & INTERP_CENTROID)
608 e->inst[0] |= (1 << 24);
609 }
610
611 emit(pc, e);
612 }
613
614 static void
615 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
616 struct nv50_program_exec *e)
617 {
618 set_long(pc, e);
619
620 e->param.index = src->hw & 127;
621 e->param.shift = s;
622 e->param.mask = m << (s % 32);
623
624 if (src->hw < 0 || src->hw > 127) /* need (additional) address reg */
625 set_addr(e, get_address_reg(pc, src));
626 else
627 if (src->acc < 0) {
628 assert(src->type == P_CONST);
629 set_addr(e, pc->addr[src->indirect[0]]);
630 }
631
632 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
633 }
634
635 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
636 static void
637 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
638 {
639 struct nv50_program_exec *e = exec(pc);
640
641 e->inst[0] = 0x10000000;
642 if (!pc->allow32)
643 set_long(pc, e);
644
645 set_dst(pc, dst, e);
646
647 if (!is_long(e) && src->type == P_IMMD) {
648 set_immd(pc, src, e);
649 /*XXX: 32-bit, but steals part of "half" reg space - need to
650 * catch and handle this case if/when we do half-regs
651 */
652 } else
653 if (src->type == P_IMMD || src->type == P_CONST) {
654 set_long(pc, e);
655 set_data(pc, src, 0x7f, 9, e);
656 e->inst[1] |= 0x20000000; /* mov from c[] */
657 } else {
658 if (src->type == P_ATTR) {
659 set_long(pc, e);
660 e->inst[1] |= 0x00200000;
661
662 if (src->vtx >= 0) {
663 /* indirect (vertex base + c) load from p[] */
664 e->inst[0] |= 0x01800000;
665 set_addr(e, get_address_reg(pc, src));
666 }
667 }
668
669 alloc_reg(pc, src);
670 if (src->hw > 63)
671 set_long(pc, e);
672 e->inst[0] |= (src->hw << 9);
673 }
674
675 if (is_long(e) && !is_immd(e)) {
676 e->inst[1] |= 0x04000000; /* 32-bit */
677 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
678 if (!(e->inst[1] & 0x20000000))
679 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
680 } else
681 e->inst[0] |= 0x00008000;
682
683 emit(pc, e);
684 }
685
686 static INLINE void
687 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
688 {
689 struct nv50_reg *imm = alloc_immd(pc, f);
690 emit_mov(pc, dst, imm);
691 FREE(imm);
692 }
693
694 /* Assign the hw of the discarded temporary register src
695 * to the tgsi register dst and free src.
696 */
697 static void
698 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
699 {
700 assert(src->index == -1 && src->hw != -1);
701
702 if (pc->if_lvl || pc->loop_lvl ||
703 (dst->type != P_TEMP) ||
704 (src->hw < pc->result_nr * 4 &&
705 pc->p->type == PIPE_SHADER_FRAGMENT) ||
706 pc->p->info.opcode_count[TGSI_OPCODE_CAL] ||
707 pc->p->info.opcode_count[TGSI_OPCODE_BRA]) {
708
709 emit_mov(pc, dst, src);
710 free_temp(pc, src);
711 return;
712 }
713
714 if (dst->hw != -1)
715 pc->r_temp[dst->hw] = NULL;
716 pc->r_temp[src->hw] = dst;
717 dst->hw = src->hw;
718
719 FREE(src);
720 }
721
722 static void
723 emit_nop(struct nv50_pc *pc)
724 {
725 struct nv50_program_exec *e = exec(pc);
726
727 e->inst[0] = 0xf0000000;
728 set_long(pc, e);
729 e->inst[1] = 0xe0000000;
730 emit(pc, e);
731 }
732
733 static boolean
734 check_swap_src_0_1(struct nv50_pc *pc,
735 struct nv50_reg **s0, struct nv50_reg **s1)
736 {
737 struct nv50_reg *src0 = *s0, *src1 = *s1;
738
739 if (src0->type == P_CONST) {
740 if (src1->type != P_CONST) {
741 *s0 = src1;
742 *s1 = src0;
743 return TRUE;
744 }
745 } else
746 if (src1->type == P_ATTR) {
747 if (src0->type != P_ATTR) {
748 *s0 = src1;
749 *s1 = src0;
750 return TRUE;
751 }
752 }
753
754 return FALSE;
755 }
756
757 static void
758 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
759 struct nv50_program_exec *e)
760 {
761 struct nv50_reg *temp;
762
763 if (src->type != P_TEMP) {
764 temp = temp_temp(pc, e);
765 emit_mov(pc, temp, src);
766 src = temp;
767 }
768
769 alloc_reg(pc, src);
770 if (src->hw > 63)
771 set_long(pc, e);
772 e->inst[0] |= (src->hw << 9);
773 }
774
775 static void
776 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
777 {
778 if (src->type == P_ATTR) {
779 set_long(pc, e);
780 e->inst[1] |= 0x00200000;
781
782 if (src->vtx >= 0) {
783 e->inst[0] |= 0x01800000; /* src from p[] */
784 set_addr(e, get_address_reg(pc, src));
785 }
786 } else
787 if (src->type == P_CONST || src->type == P_IMMD) {
788 struct nv50_reg *temp = temp_temp(pc, e);
789
790 emit_mov(pc, temp, src);
791 src = temp;
792 }
793
794 alloc_reg(pc, src);
795 if (src->hw > 63)
796 set_long(pc, e);
797 e->inst[0] |= (src->hw << 9);
798 }
799
800 static void
801 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
802 {
803 if (src->type == P_ATTR) {
804 struct nv50_reg *temp = temp_temp(pc, e);
805
806 emit_mov(pc, temp, src);
807 src = temp;
808 } else
809 if (src->type == P_CONST || src->type == P_IMMD) {
810 if (e->inst[0] & 0x01800000) {
811 struct nv50_reg *temp = temp_temp(pc, e);
812
813 emit_mov(pc, temp, src);
814 src = temp;
815 } else {
816 assert(!(e->inst[0] & 0x00800000));
817 set_data(pc, src, 0x7f, 16, e);
818 e->inst[0] |= 0x00800000;
819 }
820 }
821
822 alloc_reg(pc, src);
823 if (src->hw > 63)
824 set_long(pc, e);
825 e->inst[0] |= ((src->hw & 127) << 16);
826 }
827
828 static void
829 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
830 {
831 set_long(pc, e);
832
833 if (src->type == P_ATTR) {
834 struct nv50_reg *temp = temp_temp(pc, e);
835
836 emit_mov(pc, temp, src);
837 src = temp;
838 } else
839 if (src->type == P_CONST || src->type == P_IMMD) {
840 if (e->inst[0] & 0x01800000) {
841 struct nv50_reg *temp = temp_temp(pc, e);
842
843 emit_mov(pc, temp, src);
844 src = temp;
845 } else {
846 assert(!(e->inst[0] & 0x01000000));
847 set_data(pc, src, 0x7f, 32+14, e);
848 e->inst[0] |= 0x01000000;
849 }
850 }
851
852 alloc_reg(pc, src);
853 e->inst[1] |= ((src->hw & 127) << 14);
854 }
855
856 static void
857 set_half_src(struct nv50_pc *pc, struct nv50_reg *src, int lh,
858 struct nv50_program_exec *e, int pos)
859 {
860 struct nv50_reg *r = src;
861
862 alloc_reg(pc, r);
863 if (r->type != P_TEMP) {
864 r = temp_temp(pc, e);
865 emit_mov(pc, r, src);
866 }
867
868 if (r->hw > (NV50_SU_MAX_TEMP / 2)) {
869 NOUVEAU_ERR("out of low GPRs\n");
870 abort();
871 }
872
873 e->inst[pos / 32] |= ((src->hw * 2) + lh) << (pos % 32);
874 }
875
876 static void
877 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
878 {
879 struct nv50_program_exec *e = exec(pc);
880
881 assert(dst->type == P_TEMP);
882 e->inst[1] = 0x20000000 | (pred << 12);
883 set_long(pc, e);
884 set_dst(pc, dst, e);
885
886 emit(pc, e);
887 }
888
889 static void
890 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
891 {
892 struct nv50_program_exec *e = exec(pc);
893
894 e->inst[0] = 0x000001fc;
895 e->inst[1] = 0xa0000008;
896 set_long(pc, e);
897 set_pred_wr(pc, 1, pred, e);
898 set_src_0_restricted(pc, src, e);
899
900 emit(pc, e);
901 }
902
903 static void
904 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
905 struct nv50_reg *src1)
906 {
907 struct nv50_program_exec *e = exec(pc);
908
909 e->inst[0] |= 0xc0000000;
910
911 if (!pc->allow32)
912 set_long(pc, e);
913
914 check_swap_src_0_1(pc, &src0, &src1);
915 set_dst(pc, dst, e);
916 set_src_0(pc, src0, e);
917 if (src1->type == P_IMMD && !is_long(e)) {
918 if (src0->mod ^ src1->mod)
919 e->inst[0] |= 0x00008000;
920 set_immd(pc, src1, e);
921 } else {
922 set_src_1(pc, src1, e);
923 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
924 if (is_long(e))
925 e->inst[1] |= 0x08000000;
926 else
927 e->inst[0] |= 0x00008000;
928 }
929 }
930
931 emit(pc, e);
932 }
933
934 static void
935 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
936 struct nv50_reg *src0, struct nv50_reg *src1)
937 {
938 struct nv50_program_exec *e = exec(pc);
939
940 e->inst[0] = 0xb0000000;
941
942 alloc_reg(pc, src1);
943 check_swap_src_0_1(pc, &src0, &src1);
944
945 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
946 set_long(pc, e);
947 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
948 ((src1->mod & NV50_MOD_NEG) << 27);
949 }
950
951 set_dst(pc, dst, e);
952 set_src_0(pc, src0, e);
953 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
954 set_src_2(pc, src1, e);
955 else
956 if (src1->type == P_IMMD)
957 set_immd(pc, src1, e);
958 else
959 set_src_1(pc, src1, e);
960
961 emit(pc, e);
962 }
963
964 static void
965 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
966 uint8_t s)
967 {
968 struct nv50_program_exec *e = exec(pc);
969
970 set_long(pc, e);
971 e->inst[1] |= 0xc0000000;
972
973 e->inst[0] |= dst->hw << 2;
974 e->inst[0] |= s << 16; /* shift left */
975 set_src_0(pc, src, e);
976
977 emit(pc, e);
978 }
979
980 static boolean
981 address_reg_suitable(struct nv50_reg *a, struct nv50_reg *r)
982 {
983 if (!r)
984 return FALSE;
985
986 if (r->vtx != a->vtx)
987 return FALSE;
988 if (r->vtx >= 0)
989 return (r->indirect[1] == a->indirect[1]);
990
991 if (r->hw < a->rhw || (r->hw - a->rhw) >= 128)
992 return FALSE;
993
994 if (a->index >= 0)
995 return (a->index == r->indirect[0]);
996 return (a->indirect[0] == r->indirect[0]);
997 }
998
999 static void
1000 load_vertex_base(struct nv50_pc *pc, struct nv50_reg *dst,
1001 struct nv50_reg *a, int shift)
1002 {
1003 struct nv50_reg mem, *temp;
1004
1005 ctor_reg(&mem, P_ATTR, -1, dst->vtx);
1006
1007 assert(dst->type == P_ADDR);
1008 if (!a) {
1009 emit_arl(pc, dst, &mem, 0);
1010 return;
1011 }
1012 temp = alloc_temp(pc, NULL);
1013
1014 if (shift) {
1015 emit_mov_from_addr(pc, temp, a);
1016 if (shift < 0)
1017 emit_shl_imm(pc, temp, temp, shift);
1018 emit_arl(pc, dst, temp, MAX2(shift, 0));
1019 }
1020 emit_mov(pc, temp, &mem);
1021 set_addr(pc->p->exec_tail, dst);
1022
1023 emit_arl(pc, dst, temp, 0);
1024 free_temp(pc, temp);
1025 }
1026
1027 /* case (ref == NULL): allocate address register for TGSI_FILE_ADDRESS
1028 * case (vtx >= 0, acc >= 0): load vertex base from a[vtx * 4] to $aX
1029 * case (vtx >= 0, acc < 0): load vertex base from s[$aY + vtx * 4] to $aX
1030 * case (vtx < 0, acc >= 0): memory address too high to encode
1031 * case (vtx < 0, acc < 0): get source register for TGSI_FILE_ADDRESS
1032 */
1033 static struct nv50_reg *
1034 get_address_reg(struct nv50_pc *pc, struct nv50_reg *ref)
1035 {
1036 int i;
1037 struct nv50_reg *a_ref, *a = NULL;
1038
1039 for (i = 0; i < NV50_SU_MAX_ADDR; ++i) {
1040 if (pc->r_addr[i].acc == 0)
1041 a = &pc->r_addr[i]; /* an unused address reg */
1042 else
1043 if (address_reg_suitable(&pc->r_addr[i], ref)) {
1044 pc->r_addr[i].acc = pc->insn_cur;
1045 return &pc->r_addr[i];
1046 } else
1047 if (!a && pc->r_addr[i].index < 0 &&
1048 pc->r_addr[i].acc < pc->insn_cur)
1049 a = &pc->r_addr[i];
1050 }
1051 if (!a) {
1052 /* We'll be able to spill address regs when this
1053 * mess is replaced with a proper compiler ...
1054 */
1055 NOUVEAU_ERR("out of address regs\n");
1056 abort();
1057 return NULL;
1058 }
1059
1060 /* initialize and reserve for this TGSI instruction */
1061 a->rhw = 0;
1062 a->index = a->indirect[0] = a->indirect[1] = -1;
1063 a->acc = pc->insn_cur;
1064
1065 if (!ref) {
1066 a->vtx = -1;
1067 return a;
1068 }
1069 a->vtx = ref->vtx;
1070
1071 /* now put in the correct value ... */
1072
1073 if (ref->vtx >= 0) {
1074 a->indirect[1] = ref->indirect[1];
1075
1076 /* For an indirect vertex index, we need to shift address right
1077 * by 2, the address register will contain vtx * 16, we need to
1078 * load from a[vtx * 4].
1079 */
1080 load_vertex_base(pc, a, (ref->acc < 0) ?
1081 pc->addr[ref->indirect[1]] : NULL, -2);
1082 } else {
1083 assert(ref->acc < 0 || ref->indirect[0] < 0);
1084
1085 a->rhw = ref->hw & ~0x7f;
1086 a->indirect[0] = ref->indirect[0];
1087 a_ref = (ref->acc < 0) ? pc->addr[ref->indirect[0]] : NULL;
1088
1089 emit_add_addr_imm(pc, a, a_ref, a->rhw * 4);
1090 }
1091 return a;
1092 }
1093
1094 #define NV50_MAX_F32 0x880
1095 #define NV50_MAX_S32 0x08c
1096 #define NV50_MAX_U32 0x084
1097 #define NV50_MIN_F32 0x8a0
1098 #define NV50_MIN_S32 0x0ac
1099 #define NV50_MIN_U32 0x0a4
1100
1101 static void
1102 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
1103 struct nv50_reg *src0, struct nv50_reg *src1)
1104 {
1105 struct nv50_program_exec *e = exec(pc);
1106
1107 set_long(pc, e);
1108 e->inst[0] |= 0x30000000 | ((sub & 0x800) << 20);
1109 e->inst[1] |= (sub << 24);
1110
1111 check_swap_src_0_1(pc, &src0, &src1);
1112 set_dst(pc, dst, e);
1113 set_src_0(pc, src0, e);
1114 set_src_1(pc, src1, e);
1115
1116 if (src0->mod & NV50_MOD_ABS)
1117 e->inst[1] |= 0x00100000;
1118 if (src1->mod & NV50_MOD_ABS)
1119 e->inst[1] |= 0x00080000;
1120
1121 emit(pc, e);
1122 }
1123
1124 static INLINE void
1125 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1126 struct nv50_reg *src1)
1127 {
1128 src1->mod ^= NV50_MOD_NEG;
1129 emit_add(pc, dst, src0, src1);
1130 src1->mod ^= NV50_MOD_NEG;
1131 }
1132
1133 static void
1134 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1135 struct nv50_reg *src1, unsigned op)
1136 {
1137 struct nv50_program_exec *e = exec(pc);
1138
1139 e->inst[0] = 0xd0000000;
1140 set_long(pc, e);
1141
1142 check_swap_src_0_1(pc, &src0, &src1);
1143 set_dst(pc, dst, e);
1144 set_src_0(pc, src0, e);
1145
1146 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1147 op != TGSI_OPCODE_XOR)
1148 assert(!"invalid bit op");
1149
1150 assert(!(src0->mod | src1->mod));
1151
1152 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1153 set_immd(pc, src1, e);
1154 if (op == TGSI_OPCODE_OR)
1155 e->inst[0] |= 0x0100;
1156 else
1157 if (op == TGSI_OPCODE_XOR)
1158 e->inst[0] |= 0x8000;
1159 } else {
1160 set_src_1(pc, src1, e);
1161 e->inst[1] |= 0x04000000; /* 32 bit */
1162 if (op == TGSI_OPCODE_OR)
1163 e->inst[1] |= 0x4000;
1164 else
1165 if (op == TGSI_OPCODE_XOR)
1166 e->inst[1] |= 0x8000;
1167 }
1168
1169 emit(pc, e);
1170 }
1171
1172 static void
1173 emit_not(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1174 {
1175 struct nv50_program_exec *e = exec(pc);
1176
1177 e->inst[0] = 0xd0000000;
1178 e->inst[1] = 0x0402c000;
1179 set_long(pc, e);
1180 set_dst(pc, dst, e);
1181 set_src_1(pc, src, e);
1182
1183 emit(pc, e);
1184 }
1185
1186 static void
1187 emit_shift(struct nv50_pc *pc, struct nv50_reg *dst,
1188 struct nv50_reg *src0, struct nv50_reg *src1, unsigned dir)
1189 {
1190 struct nv50_program_exec *e = exec(pc);
1191
1192 e->inst[0] = 0x30000000;
1193 e->inst[1] = 0xc4000000;
1194
1195 set_long(pc, e);
1196 set_dst(pc, dst, e);
1197 set_src_0(pc, src0, e);
1198
1199 if (src1->type == P_IMMD) {
1200 e->inst[1] |= (1 << 20);
1201 e->inst[0] |= (pc->immd_buf[src1->hw] & 0x7f) << 16;
1202 } else
1203 set_src_1(pc, src1, e);
1204
1205 if (dir != TGSI_OPCODE_SHL)
1206 e->inst[1] |= (1 << 29);
1207
1208 if (dir == TGSI_OPCODE_ISHR)
1209 e->inst[1] |= (1 << 27);
1210
1211 emit(pc, e);
1212 }
1213
1214 static void
1215 emit_shl_imm(struct nv50_pc *pc, struct nv50_reg *dst,
1216 struct nv50_reg *src, int s)
1217 {
1218 struct nv50_program_exec *e = exec(pc);
1219
1220 e->inst[0] = 0x30000000;
1221 e->inst[1] = 0xc4100000;
1222 if (s < 0) {
1223 e->inst[1] |= 1 << 29;
1224 s = -s;
1225 }
1226 e->inst[1] |= ((s & 0x7f) << 16);
1227
1228 set_long(pc, e);
1229 set_dst(pc, dst, e);
1230 set_src_0(pc, src, e);
1231
1232 emit(pc, e);
1233 }
1234
1235 static void
1236 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1237 struct nv50_reg *src1, struct nv50_reg *src2)
1238 {
1239 struct nv50_program_exec *e = exec(pc);
1240
1241 e->inst[0] |= 0xe0000000;
1242
1243 check_swap_src_0_1(pc, &src0, &src1);
1244 set_dst(pc, dst, e);
1245 set_src_0(pc, src0, e);
1246 set_src_1(pc, src1, e);
1247 set_src_2(pc, src2, e);
1248
1249 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1250 e->inst[1] |= 0x04000000;
1251 if (src2->mod & NV50_MOD_NEG)
1252 e->inst[1] |= 0x08000000;
1253
1254 emit(pc, e);
1255 }
1256
1257 static INLINE void
1258 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1259 struct nv50_reg *src1, struct nv50_reg *src2)
1260 {
1261 src2->mod ^= NV50_MOD_NEG;
1262 emit_mad(pc, dst, src0, src1, src2);
1263 src2->mod ^= NV50_MOD_NEG;
1264 }
1265
1266 #define NV50_FLOP_RCP 0
1267 #define NV50_FLOP_RSQ 2
1268 #define NV50_FLOP_LG2 3
1269 #define NV50_FLOP_SIN 4
1270 #define NV50_FLOP_COS 5
1271 #define NV50_FLOP_EX2 6
1272
1273 /* rcp, rsqrt, lg2 support neg and abs */
1274 static void
1275 emit_flop(struct nv50_pc *pc, unsigned sub,
1276 struct nv50_reg *dst, struct nv50_reg *src)
1277 {
1278 struct nv50_program_exec *e = exec(pc);
1279
1280 e->inst[0] |= 0x90000000;
1281 if (sub || src->mod) {
1282 set_long(pc, e);
1283 e->inst[1] |= (sub << 29);
1284 }
1285
1286 set_dst(pc, dst, e);
1287 set_src_0_restricted(pc, src, e);
1288
1289 assert(!src->mod || sub < 4);
1290
1291 if (src->mod & NV50_MOD_NEG)
1292 e->inst[1] |= 0x04000000;
1293 if (src->mod & NV50_MOD_ABS)
1294 e->inst[1] |= 0x00100000;
1295
1296 emit(pc, e);
1297 }
1298
1299 static void
1300 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1301 {
1302 struct nv50_program_exec *e = exec(pc);
1303
1304 e->inst[0] |= 0xb0000000;
1305
1306 set_dst(pc, dst, e);
1307 set_src_0(pc, src, e);
1308 set_long(pc, e);
1309 e->inst[1] |= (6 << 29) | 0x00004000;
1310
1311 if (src->mod & NV50_MOD_NEG)
1312 e->inst[1] |= 0x04000000;
1313 if (src->mod & NV50_MOD_ABS)
1314 e->inst[1] |= 0x00100000;
1315
1316 emit(pc, e);
1317 }
1318
1319 static void
1320 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1321 {
1322 struct nv50_program_exec *e = exec(pc);
1323
1324 e->inst[0] |= 0xb0000000;
1325
1326 set_dst(pc, dst, e);
1327 set_src_0(pc, src, e);
1328 set_long(pc, e);
1329 e->inst[1] |= (6 << 29);
1330
1331 if (src->mod & NV50_MOD_NEG)
1332 e->inst[1] |= 0x04000000;
1333 if (src->mod & NV50_MOD_ABS)
1334 e->inst[1] |= 0x00100000;
1335
1336 emit(pc, e);
1337 }
1338
1339 #define CVT_RN (0x00 << 16)
1340 #define CVT_FLOOR (0x02 << 16)
1341 #define CVT_CEIL (0x04 << 16)
1342 #define CVT_TRUNC (0x06 << 16)
1343 #define CVT_SAT (0x08 << 16)
1344 #define CVT_ABS (0x10 << 16)
1345
1346 #define CVT_X32_X32 0x04004000
1347 #define CVT_X32_S32 0x04014000
1348 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1349 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1350 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1351 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1352 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1353 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1354 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1355 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1356
1357 #define CVT_NEG 0x20000000
1358 #define CVT_RI 0x08000000
1359
1360 static void
1361 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1362 int wp, uint32_t cvn)
1363 {
1364 struct nv50_program_exec *e;
1365
1366 e = exec(pc);
1367
1368 if (src->mod & NV50_MOD_NEG) cvn |= CVT_NEG;
1369 if (src->mod & NV50_MOD_ABS) cvn |= CVT_ABS;
1370
1371 e->inst[0] = 0xa0000000;
1372 e->inst[1] = cvn;
1373 set_long(pc, e);
1374 set_src_0(pc, src, e);
1375
1376 if (wp >= 0)
1377 set_pred_wr(pc, 1, wp, e);
1378
1379 if (dst)
1380 set_dst(pc, dst, e);
1381 else {
1382 e->inst[0] |= 0x000001fc;
1383 e->inst[1] |= 0x00000008;
1384 }
1385
1386 emit(pc, e);
1387 }
1388
1389 /* nv50 Condition codes:
1390 * 0x1 = LT
1391 * 0x2 = EQ
1392 * 0x3 = LE
1393 * 0x4 = GT
1394 * 0x5 = NE
1395 * 0x6 = GE
1396 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1397 * 0x8 = unordered bit (allows NaN)
1398 *
1399 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1400 */
1401 static void
1402 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1403 struct nv50_reg *src0, struct nv50_reg *src1, uint8_t mode)
1404 {
1405 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1406
1407 struct nv50_program_exec *e = exec(pc);
1408 struct nv50_reg *rdst;
1409
1410 assert(ccode < 16);
1411 if (check_swap_src_0_1(pc, &src0, &src1))
1412 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1413
1414 rdst = dst;
1415 if (dst && dst->type != P_TEMP)
1416 dst = alloc_temp(pc, NULL);
1417
1418 set_long(pc, e);
1419 e->inst[0] |= 0x30000000 | (mode << 24);
1420 e->inst[1] |= 0x60000000 | (ccode << 14);
1421
1422 if (wp >= 0)
1423 set_pred_wr(pc, 1, wp, e);
1424 if (dst)
1425 set_dst(pc, dst, e);
1426 else {
1427 e->inst[0] |= 0x000001fc;
1428 e->inst[1] |= 0x00000008;
1429 }
1430
1431 set_src_0(pc, src0, e);
1432 set_src_1(pc, src1, e);
1433
1434 emit(pc, e);
1435
1436 if (rdst && mode == 0x80) /* convert to float ? */
1437 emit_cvt(pc, rdst, dst, -1, CVT_ABS | CVT_F32_S32);
1438 if (rdst && rdst != dst)
1439 free_temp(pc, dst);
1440 }
1441
1442 static INLINE void
1443 map_tgsi_setop_hw(unsigned op, uint8_t *cc, uint8_t *ty)
1444 {
1445 switch (op) {
1446 case TGSI_OPCODE_SLT: *cc = 0x1; *ty = 0x80; break;
1447 case TGSI_OPCODE_SGE: *cc = 0x6; *ty = 0x80; break;
1448 case TGSI_OPCODE_SEQ: *cc = 0x2; *ty = 0x80; break;
1449 case TGSI_OPCODE_SGT: *cc = 0x4; *ty = 0x80; break;
1450 case TGSI_OPCODE_SLE: *cc = 0x3; *ty = 0x80; break;
1451 case TGSI_OPCODE_SNE: *cc = 0xd; *ty = 0x80; break;
1452
1453 case TGSI_OPCODE_ISLT: *cc = 0x1; *ty = 0x0c; break;
1454 case TGSI_OPCODE_ISGE: *cc = 0x6; *ty = 0x0c; break;
1455 case TGSI_OPCODE_USEQ: *cc = 0x2; *ty = 0x04; break;
1456 case TGSI_OPCODE_USGE: *cc = 0x6; *ty = 0x04; break;
1457 case TGSI_OPCODE_USLT: *cc = 0x1; *ty = 0x04; break;
1458 case TGSI_OPCODE_USNE: *cc = 0x5; *ty = 0x04; break;
1459 default:
1460 assert(0);
1461 return;
1462 }
1463 }
1464
1465 static void
1466 emit_add_b32(struct nv50_pc *pc, struct nv50_reg *dst,
1467 struct nv50_reg *src0, struct nv50_reg *rsrc1)
1468 {
1469 struct nv50_program_exec *e = exec(pc);
1470 struct nv50_reg *src1;
1471
1472 e->inst[0] = 0x20000000;
1473
1474 alloc_reg(pc, rsrc1);
1475 check_swap_src_0_1(pc, &src0, &rsrc1);
1476
1477 src1 = rsrc1;
1478 if (src0->mod & rsrc1->mod & NV50_MOD_NEG) {
1479 src1 = temp_temp(pc, e);
1480 emit_cvt(pc, src1, rsrc1, -1, CVT_S32_S32);
1481 }
1482
1483 if (!pc->allow32 || src1->hw > 63 ||
1484 (src1->type != P_TEMP && src1->type != P_IMMD))
1485 set_long(pc, e);
1486
1487 set_dst(pc, dst, e);
1488 set_src_0(pc, src0, e);
1489
1490 if (is_long(e)) {
1491 e->inst[1] |= 1 << 26;
1492 set_src_2(pc, src1, e);
1493 } else {
1494 e->inst[0] |= 0x8000;
1495 if (src1->type == P_IMMD)
1496 set_immd(pc, src1, e);
1497 else
1498 set_src_1(pc, src1, e);
1499 }
1500
1501 if (src0->mod & NV50_MOD_NEG)
1502 e->inst[0] |= 1 << 28;
1503 else
1504 if (src1->mod & NV50_MOD_NEG)
1505 e->inst[0] |= 1 << 22;
1506
1507 emit(pc, e);
1508 }
1509
1510 static void
1511 emit_mad_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1512 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1,
1513 struct nv50_reg *src2)
1514 {
1515 struct nv50_program_exec *e = exec(pc);
1516
1517 e->inst[0] = 0x60000000;
1518 if (!pc->allow32)
1519 set_long(pc, e);
1520 set_dst(pc, dst, e);
1521
1522 set_half_src(pc, src0, lh_0, e, 9);
1523 set_half_src(pc, src1, lh_1, e, 16);
1524 alloc_reg(pc, src2);
1525 if (is_long(e) || (src2->type != P_TEMP) || (src2->hw != dst->hw))
1526 set_src_2(pc, src2, e);
1527
1528 emit(pc, e);
1529 }
1530
1531 static void
1532 emit_mul_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1533 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1)
1534 {
1535 struct nv50_program_exec *e = exec(pc);
1536
1537 e->inst[0] = 0x40000000;
1538 set_long(pc, e);
1539 set_dst(pc, dst, e);
1540
1541 set_half_src(pc, src0, lh_0, e, 9);
1542 set_half_src(pc, src1, lh_1, e, 16);
1543
1544 emit(pc, e);
1545 }
1546
1547 static void
1548 emit_sad(struct nv50_pc *pc, struct nv50_reg *dst,
1549 struct nv50_reg *src0, struct nv50_reg *src1, struct nv50_reg *src2)
1550 {
1551 struct nv50_program_exec *e = exec(pc);
1552
1553 e->inst[0] = 0x50000000;
1554 if (!pc->allow32)
1555 set_long(pc, e);
1556 check_swap_src_0_1(pc, &src0, &src1);
1557 set_dst(pc, dst, e);
1558 set_src_0(pc, src0, e);
1559 set_src_1(pc, src1, e);
1560 alloc_reg(pc, src2);
1561 if (is_long(e) || (src2->type != dst->type) || (src2->hw != dst->hw))
1562 set_src_2(pc, src2, e);
1563
1564 if (is_long(e))
1565 e->inst[1] |= 0x0c << 24;
1566 else
1567 e->inst[0] |= 0x81 << 8;
1568
1569 emit(pc, e);
1570 }
1571
1572 static INLINE void
1573 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1574 {
1575 emit_cvt(pc, dst, src, -1, CVT_FLOOR | CVT_F32_F32 | CVT_RI);
1576 }
1577
1578 static void
1579 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1580 struct nv50_reg *v, struct nv50_reg *e)
1581 {
1582 struct nv50_reg *temp = alloc_temp(pc, NULL);
1583
1584 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1585 emit_mul(pc, temp, temp, e);
1586 emit_preex2(pc, temp, temp);
1587 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1588
1589 free_temp(pc, temp);
1590 }
1591
1592 static INLINE void
1593 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1594 {
1595 emit_cvt(pc, dst, src, -1, CVT_SAT | CVT_F32_F32);
1596 }
1597
1598 static void
1599 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1600 struct nv50_reg **src)
1601 {
1602 struct nv50_reg *one = alloc_immd(pc, 1.0);
1603 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1604 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1605 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1606 struct nv50_reg *tmp[4];
1607 boolean allow32 = pc->allow32;
1608
1609 pc->allow32 = FALSE;
1610
1611 if (mask & (3 << 1)) {
1612 tmp[0] = alloc_temp(pc, NULL);
1613 emit_minmax(pc, NV50_MAX_F32, tmp[0], src[0], zero);
1614 }
1615
1616 if (mask & (1 << 2)) {
1617 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1618
1619 tmp[1] = temp_temp(pc, NULL);
1620 emit_minmax(pc, NV50_MAX_F32, tmp[1], src[1], zero);
1621
1622 tmp[3] = temp_temp(pc, NULL);
1623 emit_minmax(pc, NV50_MAX_F32, tmp[3], src[3], neg128);
1624 emit_minmax(pc, NV50_MIN_F32, tmp[3], tmp[3], pos128);
1625
1626 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1627 emit_mov(pc, dst[2], zero);
1628 set_pred(pc, 3, 0, pc->p->exec_tail);
1629 }
1630
1631 if (mask & (1 << 1))
1632 assimilate_temp(pc, dst[1], tmp[0]);
1633 else
1634 if (mask & (1 << 2))
1635 free_temp(pc, tmp[0]);
1636
1637 pc->allow32 = allow32;
1638
1639 /* do this last, in case src[i,j] == dst[0,3] */
1640 if (mask & (1 << 0))
1641 emit_mov(pc, dst[0], one);
1642
1643 if (mask & (1 << 3))
1644 emit_mov(pc, dst[3], one);
1645
1646 FREE(pos128);
1647 FREE(neg128);
1648 FREE(zero);
1649 FREE(one);
1650 }
1651
1652 static void
1653 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1654 {
1655 struct nv50_program_exec *e;
1656 const int r_pred = 1;
1657
1658 e = exec(pc);
1659 e->inst[0] = 0x00000002; /* discard */
1660 set_long(pc, e); /* sets cond code to ALWAYS */
1661
1662 if (src) {
1663 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1664 /* write to predicate reg */
1665 emit_cvt(pc, NULL, src, r_pred, CVT_F32_F32);
1666 }
1667
1668 emit(pc, e);
1669 }
1670
1671 static struct nv50_program_exec *
1672 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1673 {
1674 struct nv50_program_exec *e = exec(pc);
1675
1676 e->inst[0] = (op << 28) | 2;
1677 set_long(pc, e);
1678 if (pred >= 0)
1679 set_pred(pc, cc, pred, e);
1680
1681 emit(pc, e);
1682 return e;
1683 }
1684
1685 static INLINE struct nv50_program_exec *
1686 emit_breakaddr(struct nv50_pc *pc)
1687 {
1688 return emit_control_flow(pc, 0x4, -1, 0);
1689 }
1690
1691 static INLINE void
1692 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1693 {
1694 emit_control_flow(pc, 0x5, pred, cc);
1695 }
1696
1697 static INLINE struct nv50_program_exec *
1698 emit_joinat(struct nv50_pc *pc)
1699 {
1700 return emit_control_flow(pc, 0xa, -1, 0);
1701 }
1702
1703 static INLINE struct nv50_program_exec *
1704 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1705 {
1706 return emit_control_flow(pc, 0x1, pred, cc);
1707 }
1708
1709 static INLINE struct nv50_program_exec *
1710 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1711 {
1712 return emit_control_flow(pc, 0x2, pred, cc);
1713 }
1714
1715 static INLINE void
1716 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1717 {
1718 emit_control_flow(pc, 0x3, pred, cc);
1719 }
1720
1721 static void
1722 emit_prim_cmd(struct nv50_pc *pc, unsigned cmd)
1723 {
1724 struct nv50_program_exec *e = exec(pc);
1725
1726 e->inst[0] = 0xf0000000 | (cmd << 9);
1727 e->inst[1] = 0xc0000000;
1728 set_long(pc, e);
1729
1730 emit(pc, e);
1731 }
1732
1733 #define QOP_ADD 0
1734 #define QOP_SUBR 1
1735 #define QOP_SUB 2
1736 #define QOP_MOV_SRC1 3
1737
1738 /* For a quad of threads / top left, top right, bottom left, bottom right
1739 * pixels, do a different operation, and take src0 from a specific thread.
1740 */
1741 static void
1742 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1743 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1744 {
1745 struct nv50_program_exec *e = exec(pc);
1746
1747 e->inst[0] = 0xc0000000;
1748 e->inst[1] = 0x80000000;
1749 set_long(pc, e);
1750 e->inst[0] |= lane_src0 << 16;
1751 set_src_0(pc, src0, e);
1752 set_src_2(pc, src1, e);
1753
1754 if (wp >= 0)
1755 set_pred_wr(pc, 1, wp, e);
1756
1757 if (dst)
1758 set_dst(pc, dst, e);
1759 else {
1760 e->inst[0] |= 0x000001fc;
1761 e->inst[1] |= 0x00000008;
1762 }
1763
1764 e->inst[0] |= (qop & 3) << 20;
1765 e->inst[1] |= (qop >> 2) << 22;
1766
1767 emit(pc, e);
1768 }
1769
1770 static void
1771 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1772 struct nv50_reg **src, unsigned arg, boolean proj)
1773 {
1774 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1775
1776 src[0]->mod |= NV50_MOD_ABS;
1777 src[1]->mod |= NV50_MOD_ABS;
1778 src[2]->mod |= NV50_MOD_ABS;
1779
1780 emit_minmax(pc, NV50_MAX_F32, t[2], src[0], src[1]);
1781 emit_minmax(pc, NV50_MAX_F32, t[2], src[2], t[2]);
1782
1783 src[0]->mod = mod[0];
1784 src[1]->mod = mod[1];
1785 src[2]->mod = mod[2];
1786
1787 if (proj && 0 /* looks more correct without this */)
1788 emit_mul(pc, t[2], t[2], src[3]);
1789 else
1790 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1791 emit_mov(pc, t[3], src[3]);
1792
1793 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1794
1795 emit_mul(pc, t[0], src[0], t[2]);
1796 emit_mul(pc, t[1], src[1], t[2]);
1797 emit_mul(pc, t[2], src[2], t[2]);
1798 }
1799
1800 static void
1801 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1802 struct nv50_reg **src, unsigned dim, unsigned arg)
1803 {
1804 unsigned c, mode;
1805
1806 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1807 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1808
1809 t[3]->rhw = src[3]->rhw;
1810 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1811 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1812
1813 for (c = 0; c < dim; ++c) {
1814 t[c]->rhw = src[c]->rhw;
1815 emit_interp(pc, t[c], t[3], mode);
1816 }
1817 if (arg != dim) { /* depth reference value */
1818 t[dim]->rhw = src[2]->rhw;
1819 emit_interp(pc, t[dim], t[3], mode);
1820 }
1821 } else {
1822 /* XXX: for some reason the blob sometimes uses MAD
1823 * (mad f32 $rX $rY $rZ neg $r63)
1824 */
1825 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1826 for (c = 0; c < dim; ++c)
1827 emit_mul(pc, t[c], src[c], t[3]);
1828 if (arg != dim) /* depth reference value */
1829 emit_mul(pc, t[dim], src[2], t[3]);
1830 }
1831 }
1832
1833 static INLINE void
1834 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1835 {
1836 switch (type) {
1837 case TGSI_TEXTURE_1D:
1838 *arg = *dim = 1;
1839 break;
1840 case TGSI_TEXTURE_SHADOW1D:
1841 *dim = 1;
1842 *arg = 2;
1843 break;
1844 case TGSI_TEXTURE_UNKNOWN:
1845 case TGSI_TEXTURE_2D:
1846 case TGSI_TEXTURE_RECT:
1847 *arg = *dim = 2;
1848 break;
1849 case TGSI_TEXTURE_SHADOW2D:
1850 case TGSI_TEXTURE_SHADOWRECT:
1851 *dim = 2;
1852 *arg = 3;
1853 break;
1854 case TGSI_TEXTURE_3D:
1855 case TGSI_TEXTURE_CUBE:
1856 *dim = *arg = 3;
1857 break;
1858 default:
1859 assert(0);
1860 break;
1861 }
1862 }
1863
1864 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1865 * different LOD values, so branch off groups of equal LOD.
1866 */
1867 static void
1868 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1869 struct nv50_reg *src, struct nv50_program_exec *tex)
1870 {
1871 struct nv50_program_exec *join_at;
1872 unsigned i, target = pc->p->exec_size + 9 * 2;
1873
1874 if (pc->p->type != PIPE_SHADER_FRAGMENT) {
1875 emit(pc, tex);
1876 return;
1877 }
1878 pc->allow32 = FALSE;
1879
1880 /* Subtract lod of each pixel from lod of top left pixel, jump
1881 * texlod insn if result is 0, then repeat for 2 other pixels.
1882 */
1883 join_at = emit_joinat(pc);
1884 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1885 emit_branch(pc, 0, 2)->param.index = target;
1886
1887 for (i = 1; i < 4; ++i) {
1888 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1889 emit_branch(pc, 0, 2)->param.index = target;
1890 }
1891
1892 emit_mov(pc, tlod, src); /* target */
1893 emit(pc, tex); /* texlod */
1894
1895 join_at->param.index = target + 2 * 2;
1896 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1897 }
1898
1899 static void
1900 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1901 struct nv50_program_exec *tex)
1902 {
1903 struct nv50_program_exec *e;
1904 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1905 int r_pred = 0;
1906 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1907
1908 pc->allow32 = FALSE;
1909 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1910
1911 /* Subtract bias value of thread i from bias values of each thread,
1912 * store result in r_pred, and set bit i in r_bits if result was 0.
1913 */
1914 assert(arg < 4);
1915 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1916 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1917 emit_mov(pc, r_bits, &imm_1248);
1918 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1919 }
1920 emit_mov_to_pred(pc, r_pred, r_bits);
1921
1922 /* The lanes of a quad are now grouped by the bit in r_pred they have
1923 * set. Put the input values for TEX into a new register set for each
1924 * group and execute TEX only for a specific group.
1925 * We cannot use the same register set for each group because we need
1926 * the derivatives, which are implicitly calculated, to be correct.
1927 */
1928 for (i = 1; i < 4; ++i) {
1929 alloc_temp4(pc, t123[i], 0);
1930
1931 for (c = 0; c <= arg; ++c)
1932 emit_mov(pc, t123[i][c], t[c]);
1933
1934 *(e = exec(pc)) = *(tex);
1935 e->inst[0] &= ~0x01fc;
1936 set_dst(pc, t123[i][0], e);
1937 set_pred(pc, cc[i], r_pred, e);
1938 emit(pc, e);
1939 }
1940 /* finally TEX on the original regs (where we kept the input) */
1941 set_pred(pc, cc[0], r_pred, tex);
1942 emit(pc, tex);
1943
1944 /* put the 3 * n other results into regs for lane 0 */
1945 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1946 for (i = 1; i < 4; ++i) {
1947 for (c = 0; c < n; ++c) {
1948 emit_mov(pc, t[c], t123[i][c]);
1949 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1950 }
1951 free_temp4(pc, t123[i]);
1952 }
1953
1954 emit_nop(pc);
1955 free_temp(pc, r_bits);
1956 }
1957
1958 static void
1959 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1960 struct nv50_reg **src, unsigned unit, unsigned type,
1961 boolean proj, int bias_lod)
1962 {
1963 struct nv50_reg *t[4];
1964 struct nv50_program_exec *e;
1965 unsigned c, dim, arg;
1966
1967 /* t[i] must be within a single 128 bit super-reg */
1968 alloc_temp4(pc, t, 0);
1969
1970 e = exec(pc);
1971 e->inst[0] = 0xf0000000;
1972 set_long(pc, e);
1973 set_dst(pc, t[0], e);
1974
1975 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1976 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1977
1978 /* live flag (don't set if TEX results affect input to another TEX): */
1979 /* e->inst[0] |= 0x00000004; */
1980
1981 get_tex_dim(type, &dim, &arg);
1982
1983 if (type == TGSI_TEXTURE_CUBE) {
1984 e->inst[0] |= 0x08000000;
1985 load_cube_tex_coords(pc, t, src, arg, proj);
1986 } else
1987 if (proj)
1988 load_proj_tex_coords(pc, t, src, dim, arg);
1989 else {
1990 for (c = 0; c < dim; c++)
1991 emit_mov(pc, t[c], src[c]);
1992 if (arg != dim) /* depth reference value (always src.z here) */
1993 emit_mov(pc, t[dim], src[2]);
1994 }
1995
1996 e->inst[0] |= (mask & 0x3) << 25;
1997 e->inst[1] |= (mask & 0xc) << 12;
1998
1999 if (!bias_lod) {
2000 e->inst[0] |= (arg - 1) << 22;
2001 emit(pc, e);
2002 } else
2003 if (bias_lod < 0) {
2004 assert(pc->p->type == PIPE_SHADER_FRAGMENT);
2005 e->inst[0] |= arg << 22;
2006 e->inst[1] |= 0x20000000; /* texbias */
2007 emit_mov(pc, t[arg], src[3]);
2008 emit_texbias_sequence(pc, t, arg, e);
2009 } else {
2010 e->inst[0] |= arg << 22;
2011 e->inst[1] |= 0x40000000; /* texlod */
2012 emit_mov(pc, t[arg], src[3]);
2013 emit_texlod_sequence(pc, t[arg], src[3], e);
2014 }
2015
2016 #if 1
2017 c = 0;
2018 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
2019 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
2020 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
2021 if (mask & 8) emit_mov(pc, dst[3], t[c]);
2022
2023 free_temp4(pc, t);
2024 #else
2025 /* XXX: if p.e. MUL is used directly after TEX, it would still use
2026 * the texture coordinates, not the fetched values: latency ? */
2027
2028 for (c = 0; c < 4; c++) {
2029 if (mask & (1 << c))
2030 assimilate_temp(pc, dst[c], t[c]);
2031 else
2032 free_temp(pc, t[c]);
2033 }
2034 #endif
2035 }
2036
2037 static void
2038 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2039 {
2040 struct nv50_program_exec *e = exec(pc);
2041
2042 assert(src->type == P_TEMP);
2043
2044 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
2045 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
2046 set_long(pc, e);
2047 set_dst(pc, dst, e);
2048 set_src_0(pc, src, e);
2049 set_src_2(pc, src, e);
2050
2051 emit(pc, e);
2052 }
2053
2054 static void
2055 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2056 {
2057 struct nv50_program_exec *e = exec(pc);
2058
2059 assert(src->type == P_TEMP);
2060
2061 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
2062 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
2063 set_long(pc, e);
2064 set_dst(pc, dst, e);
2065 set_src_0(pc, src, e);
2066 set_src_2(pc, src, e);
2067
2068 emit(pc, e);
2069 }
2070
2071 static void
2072 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
2073 {
2074 unsigned q = 0, m = ~0;
2075
2076 assert(!is_long(e));
2077
2078 switch (e->inst[0] >> 28) {
2079 case 0x1:
2080 /* MOV */
2081 q = 0x0403c000;
2082 m = 0xffff7fff;
2083 break;
2084 case 0x2:
2085 case 0x3:
2086 /* ADD, SUB, SUBR b32 */
2087 m = ~(0x8000 | (127 << 16));
2088 q = ((e->inst[0] & (~m)) >> 2) | (1 << 26);
2089 break;
2090 case 0x5:
2091 /* SAD */
2092 m = ~(0x81 << 8);
2093 q = (0x0c << 24) | ((e->inst[0] & (0x7f << 2)) << 12);
2094 break;
2095 case 0x6:
2096 /* MAD u16 */
2097 q = (e->inst[0] & (0x7f << 2)) << 12;
2098 break;
2099 case 0x8:
2100 /* INTERP (move centroid, perspective and flat bits) */
2101 m = ~0x03000100;
2102 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
2103 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
2104 break;
2105 case 0x9:
2106 /* RCP */
2107 break;
2108 case 0xB:
2109 /* ADD */
2110 m = ~(127 << 16);
2111 q = ((e->inst[0] & (~m)) >> 2);
2112 break;
2113 case 0xC:
2114 /* MUL */
2115 m = ~0x00008000;
2116 q = ((e->inst[0] & (~m)) << 12);
2117 break;
2118 case 0xE:
2119 /* MAD (if src2 == dst) */
2120 q = ((e->inst[0] & 0x1fc) << 12);
2121 break;
2122 default:
2123 assert(0);
2124 break;
2125 }
2126
2127 set_long(pc, e);
2128 pc->p->exec_size++;
2129
2130 e->inst[0] &= m;
2131 e->inst[1] |= q;
2132 }
2133
2134 /* Some operations support an optional negation flag. */
2135 static int
2136 get_supported_mods(const struct tgsi_full_instruction *insn, int i)
2137 {
2138 switch (insn->Instruction.Opcode) {
2139 case TGSI_OPCODE_ADD:
2140 case TGSI_OPCODE_COS:
2141 case TGSI_OPCODE_DDX:
2142 case TGSI_OPCODE_DDY:
2143 case TGSI_OPCODE_DP3:
2144 case TGSI_OPCODE_DP4:
2145 case TGSI_OPCODE_EX2:
2146 case TGSI_OPCODE_KIL:
2147 case TGSI_OPCODE_LG2:
2148 case TGSI_OPCODE_MAD:
2149 case TGSI_OPCODE_MUL:
2150 case TGSI_OPCODE_POW:
2151 case TGSI_OPCODE_RCP:
2152 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
2153 case TGSI_OPCODE_SCS:
2154 case TGSI_OPCODE_SIN:
2155 case TGSI_OPCODE_SUB:
2156 return NV50_MOD_NEG;
2157 case TGSI_OPCODE_MAX:
2158 case TGSI_OPCODE_MIN:
2159 case TGSI_OPCODE_INEG: /* tgsi src sign toggle/set would be stupid */
2160 return NV50_MOD_ABS;
2161 case TGSI_OPCODE_CEIL:
2162 case TGSI_OPCODE_FLR:
2163 case TGSI_OPCODE_TRUNC:
2164 return NV50_MOD_NEG | NV50_MOD_ABS;
2165 case TGSI_OPCODE_F2I:
2166 case TGSI_OPCODE_F2U:
2167 case TGSI_OPCODE_I2F:
2168 case TGSI_OPCODE_U2F:
2169 return NV50_MOD_NEG | NV50_MOD_ABS | NV50_MOD_I32;
2170 case TGSI_OPCODE_UADD:
2171 return NV50_MOD_NEG | NV50_MOD_I32;
2172 case TGSI_OPCODE_SAD:
2173 case TGSI_OPCODE_SHL:
2174 case TGSI_OPCODE_IMAX:
2175 case TGSI_OPCODE_IMIN:
2176 case TGSI_OPCODE_ISHR:
2177 case TGSI_OPCODE_NOT:
2178 case TGSI_OPCODE_UMAD:
2179 case TGSI_OPCODE_UMAX:
2180 case TGSI_OPCODE_UMIN:
2181 case TGSI_OPCODE_UMUL:
2182 case TGSI_OPCODE_USHR:
2183 return NV50_MOD_I32;
2184 default:
2185 return 0;
2186 }
2187 }
2188
2189 /* Return a read mask for source registers deduced from opcode & write mask. */
2190 static unsigned
2191 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
2192 {
2193 unsigned x, mask = insn->Dst[0].Register.WriteMask;
2194
2195 switch (insn->Instruction.Opcode) {
2196 case TGSI_OPCODE_COS:
2197 case TGSI_OPCODE_SIN:
2198 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
2199 case TGSI_OPCODE_DP3:
2200 return 0x7;
2201 case TGSI_OPCODE_DP4:
2202 case TGSI_OPCODE_DPH:
2203 case TGSI_OPCODE_KIL: /* WriteMask ignored */
2204 return 0xf;
2205 case TGSI_OPCODE_DST:
2206 return mask & (c ? 0xa : 0x6);
2207 case TGSI_OPCODE_EX2:
2208 case TGSI_OPCODE_EXP:
2209 case TGSI_OPCODE_LG2:
2210 case TGSI_OPCODE_LOG:
2211 case TGSI_OPCODE_POW:
2212 case TGSI_OPCODE_RCP:
2213 case TGSI_OPCODE_RSQ:
2214 case TGSI_OPCODE_SCS:
2215 return 0x1;
2216 case TGSI_OPCODE_IF:
2217 return 0x1;
2218 case TGSI_OPCODE_LIT:
2219 return 0xb;
2220 case TGSI_OPCODE_TEX:
2221 case TGSI_OPCODE_TXB:
2222 case TGSI_OPCODE_TXL:
2223 case TGSI_OPCODE_TXP:
2224 {
2225 const struct tgsi_instruction_texture *tex;
2226
2227 assert(insn->Instruction.Texture);
2228 tex = &insn->Texture;
2229
2230 mask = 0x7;
2231 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
2232 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
2233 mask |= 0x8; /* bias, lod or proj */
2234
2235 switch (tex->Texture) {
2236 case TGSI_TEXTURE_1D:
2237 mask &= 0x9;
2238 break;
2239 case TGSI_TEXTURE_SHADOW1D:
2240 mask &= 0x5;
2241 break;
2242 case TGSI_TEXTURE_2D:
2243 mask &= 0xb;
2244 break;
2245 default:
2246 break;
2247 }
2248 }
2249 return mask;
2250 case TGSI_OPCODE_XPD:
2251 x = 0;
2252 if (mask & 1) x |= 0x6;
2253 if (mask & 2) x |= 0x5;
2254 if (mask & 4) x |= 0x3;
2255 return x;
2256 default:
2257 break;
2258 }
2259
2260 return mask;
2261 }
2262
2263 static struct nv50_reg *
2264 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
2265 {
2266 switch (dst->Register.File) {
2267 case TGSI_FILE_TEMPORARY:
2268 return &pc->temp[dst->Register.Index * 4 + c];
2269 case TGSI_FILE_OUTPUT:
2270 return &pc->result[dst->Register.Index * 4 + c];
2271 case TGSI_FILE_ADDRESS:
2272 {
2273 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
2274 if (!r) {
2275 r = get_address_reg(pc, NULL);
2276 r->index = dst->Register.Index * 4 + c;
2277 pc->addr[r->index] = r;
2278 }
2279 assert(r);
2280 return r;
2281 }
2282 case TGSI_FILE_NULL:
2283 return NULL;
2284 default:
2285 break;
2286 }
2287
2288 return NULL;
2289 }
2290
2291 static struct nv50_reg *
2292 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
2293 int mod)
2294 {
2295 struct nv50_reg *r = NULL;
2296 struct nv50_reg *temp = NULL;
2297 unsigned sgn, c, swz, cvn;
2298
2299 if (src->Register.File != TGSI_FILE_CONSTANT)
2300 assert(!src->Register.Indirect);
2301
2302 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
2303
2304 c = tgsi_util_get_full_src_register_swizzle(src, chan);
2305 switch (c) {
2306 case TGSI_SWIZZLE_X:
2307 case TGSI_SWIZZLE_Y:
2308 case TGSI_SWIZZLE_Z:
2309 case TGSI_SWIZZLE_W:
2310 switch (src->Register.File) {
2311 case TGSI_FILE_INPUT:
2312 r = &pc->attr[src->Register.Index * 4 + c];
2313
2314 if (!src->Dimension.Dimension)
2315 break;
2316 r = reg_instance(pc, r);
2317 r->vtx = src->Dimension.Index;
2318
2319 if (!src->Dimension.Indirect)
2320 break;
2321 swz = tgsi_util_get_src_register_swizzle(
2322 &src->DimIndirect, 0);
2323 r->acc = -1;
2324 r->indirect[1] = src->DimIndirect.Index * 4 + swz;
2325 break;
2326 case TGSI_FILE_TEMPORARY:
2327 r = &pc->temp[src->Register.Index * 4 + c];
2328 break;
2329 case TGSI_FILE_CONSTANT:
2330 if (!src->Register.Indirect) {
2331 r = &pc->param[src->Register.Index * 4 + c];
2332 break;
2333 }
2334 /* Indicate indirection by setting r->acc < 0 and
2335 * use the index field to select the address reg.
2336 */
2337 r = reg_instance(pc, NULL);
2338 ctor_reg(r, P_CONST, -1, src->Register.Index * 4 + c);
2339
2340 swz = tgsi_util_get_src_register_swizzle(
2341 &src->Indirect, 0);
2342 r->acc = -1;
2343 r->indirect[0] = src->Indirect.Index * 4 + swz;
2344 break;
2345 case TGSI_FILE_IMMEDIATE:
2346 r = &pc->immd[src->Register.Index * 4 + c];
2347 break;
2348 case TGSI_FILE_SAMPLER:
2349 return NULL;
2350 case TGSI_FILE_ADDRESS:
2351 r = pc->addr[src->Register.Index * 4 + c];
2352 assert(r);
2353 break;
2354 default:
2355 assert(0);
2356 break;
2357 }
2358 break;
2359 default:
2360 assert(0);
2361 break;
2362 }
2363
2364 cvn = (mod & NV50_MOD_I32) ? CVT_S32_S32 : CVT_F32_F32;
2365
2366 switch (sgn) {
2367 case TGSI_UTIL_SIGN_CLEAR:
2368 r->mod = NV50_MOD_ABS;
2369 break;
2370 case TGSI_UTIL_SIGN_SET:
2371 r->mod = NV50_MOD_NEG_ABS;
2372 break;
2373 case TGSI_UTIL_SIGN_TOGGLE:
2374 r->mod = NV50_MOD_NEG;
2375 break;
2376 default:
2377 assert(!r->mod && sgn == TGSI_UTIL_SIGN_KEEP);
2378 break;
2379 }
2380
2381 if ((r->mod & mod) != r->mod) {
2382 temp = temp_temp(pc, NULL);
2383 emit_cvt(pc, temp, r, -1, cvn);
2384 r->mod = 0;
2385 r = temp;
2386 } else
2387 r->mod |= mod & NV50_MOD_I32;
2388
2389 assert(r);
2390 if (r->acc >= 0 && r->vtx < 0 && r != temp)
2391 return reg_instance(pc, r); /* will clear r->mod */
2392 return r;
2393 }
2394
2395 /* return TRUE for ops that produce only a single result */
2396 static boolean
2397 is_scalar_op(unsigned op)
2398 {
2399 switch (op) {
2400 case TGSI_OPCODE_COS:
2401 case TGSI_OPCODE_DP2:
2402 case TGSI_OPCODE_DP3:
2403 case TGSI_OPCODE_DP4:
2404 case TGSI_OPCODE_DPH:
2405 case TGSI_OPCODE_EX2:
2406 case TGSI_OPCODE_LG2:
2407 case TGSI_OPCODE_POW:
2408 case TGSI_OPCODE_RCP:
2409 case TGSI_OPCODE_RSQ:
2410 case TGSI_OPCODE_SIN:
2411 /*
2412 case TGSI_OPCODE_KIL:
2413 case TGSI_OPCODE_LIT:
2414 case TGSI_OPCODE_SCS:
2415 */
2416 return TRUE;
2417 default:
2418 return FALSE;
2419 }
2420 }
2421
2422 /* Returns a bitmask indicating which dst components depend
2423 * on source s, component c (reverse of nv50_tgsi_src_mask).
2424 */
2425 static unsigned
2426 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2427 {
2428 if (is_scalar_op(op))
2429 return 0x1;
2430
2431 switch (op) {
2432 case TGSI_OPCODE_DST:
2433 return (1 << c) & (s ? 0xa : 0x6);
2434 case TGSI_OPCODE_XPD:
2435 switch (c) {
2436 case 0: return 0x6;
2437 case 1: return 0x5;
2438 case 2: return 0x3;
2439 case 3: return 0x0;
2440 default:
2441 assert(0);
2442 return 0x0;
2443 }
2444 case TGSI_OPCODE_EXP:
2445 case TGSI_OPCODE_LOG:
2446 case TGSI_OPCODE_LIT:
2447 case TGSI_OPCODE_SCS:
2448 case TGSI_OPCODE_TEX:
2449 case TGSI_OPCODE_TXB:
2450 case TGSI_OPCODE_TXL:
2451 case TGSI_OPCODE_TXP:
2452 /* these take care of dangerous swizzles themselves */
2453 return 0x0;
2454 case TGSI_OPCODE_IF:
2455 case TGSI_OPCODE_KIL:
2456 /* don't call this function for these ops */
2457 assert(0);
2458 return 0;
2459 default:
2460 /* linear vector instruction */
2461 return (1 << c);
2462 }
2463 }
2464
2465 static INLINE boolean
2466 has_pred(struct nv50_program_exec *e, unsigned cc)
2467 {
2468 if (!is_long(e) || is_immd(e))
2469 return FALSE;
2470 return ((e->inst[1] & 0x780) == (cc << 7));
2471 }
2472
2473 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2474 * join_at ENDIF
2475 * @p0.eq bra ENDIF
2476 * single_op
2477 * ENDIF: nop.join
2478 */
2479 static boolean
2480 nv50_kill_branch(struct nv50_pc *pc)
2481 {
2482 int lvl = pc->if_lvl;
2483
2484 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2485 return FALSE;
2486 if (is_immd(pc->p->exec_tail))
2487 return FALSE;
2488
2489 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2490 * reg may no longer be valid, since we currently always use $p0
2491 */
2492 if (has_pred(pc->if_insn[lvl], 0xf))
2493 return FALSE;
2494 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2495
2496 /* We'll use the exec allocated for JOIN_AT (we can't easily
2497 * access nv50_program_exec's prev).
2498 */
2499 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2500
2501 *pc->if_join[lvl] = *pc->p->exec_tail;
2502
2503 FREE(pc->if_insn[lvl]);
2504 FREE(pc->p->exec_tail);
2505
2506 pc->p->exec_tail = pc->if_join[lvl];
2507 pc->p->exec_tail->next = NULL;
2508 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2509
2510 return TRUE;
2511 }
2512
2513 static void
2514 nv50_fp_move_results(struct nv50_pc *pc)
2515 {
2516 struct nv50_reg reg;
2517 unsigned i;
2518
2519 ctor_reg(&reg, P_TEMP, -1, -1);
2520
2521 for (i = 0; i < pc->result_nr * 4; ++i) {
2522 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2523 continue;
2524 if (pc->result[i].rhw != pc->result[i].hw) {
2525 reg.hw = pc->result[i].rhw;
2526 emit_mov(pc, &reg, &pc->result[i]);
2527 }
2528 }
2529 }
2530
2531 static boolean
2532 nv50_program_tx_insn(struct nv50_pc *pc,
2533 const struct tgsi_full_instruction *inst)
2534 {
2535 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2536 unsigned mask, sat, unit;
2537 int i, c;
2538
2539 mask = inst->Dst[0].Register.WriteMask;
2540 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2541
2542 memset(src, 0, sizeof(src));
2543
2544 for (c = 0; c < 4; c++) {
2545 if ((mask & (1 << c)) && !pc->r_dst[c])
2546 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2547 else
2548 dst[c] = pc->r_dst[c];
2549 rdst[c] = dst[c];
2550 }
2551
2552 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2553 const struct tgsi_full_src_register *fs = &inst->Src[i];
2554 unsigned src_mask;
2555 int mod_supp;
2556
2557 src_mask = nv50_tgsi_src_mask(inst, i);
2558 mod_supp = get_supported_mods(inst, i);
2559
2560 if (fs->Register.File == TGSI_FILE_SAMPLER)
2561 unit = fs->Register.Index;
2562
2563 for (c = 0; c < 4; c++)
2564 if (src_mask & (1 << c))
2565 src[i][c] = tgsi_src(pc, c, fs, mod_supp);
2566 }
2567
2568 brdc = temp = pc->r_brdc;
2569 if (brdc && brdc->type != P_TEMP) {
2570 temp = temp_temp(pc, NULL);
2571 if (sat)
2572 brdc = temp;
2573 } else
2574 if (sat) {
2575 for (c = 0; c < 4; c++) {
2576 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2577 continue;
2578 /* rdst[c] = dst[c]; */ /* done above */
2579 dst[c] = temp_temp(pc, NULL);
2580 }
2581 }
2582
2583 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2584
2585 switch (inst->Instruction.Opcode) {
2586 case TGSI_OPCODE_ABS:
2587 for (c = 0; c < 4; c++) {
2588 if (!(mask & (1 << c)))
2589 continue;
2590 emit_cvt(pc, dst[c], src[0][c], -1,
2591 CVT_ABS | CVT_F32_F32);
2592 }
2593 break;
2594 case TGSI_OPCODE_ADD:
2595 for (c = 0; c < 4; c++) {
2596 if (!(mask & (1 << c)))
2597 continue;
2598 emit_add(pc, dst[c], src[0][c], src[1][c]);
2599 }
2600 break;
2601 case TGSI_OPCODE_AND:
2602 case TGSI_OPCODE_XOR:
2603 case TGSI_OPCODE_OR:
2604 for (c = 0; c < 4; c++) {
2605 if (!(mask & (1 << c)))
2606 continue;
2607 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2608 inst->Instruction.Opcode);
2609 }
2610 break;
2611 case TGSI_OPCODE_ARL:
2612 temp = temp_temp(pc, NULL);
2613 for (c = 0; c < 4; c++) {
2614 if (!(mask & (1 << c)))
2615 continue;
2616 emit_cvt(pc, temp, src[0][c], -1,
2617 CVT_FLOOR | CVT_S32_F32);
2618 emit_arl(pc, dst[c], temp, 4);
2619 }
2620 break;
2621 case TGSI_OPCODE_BGNLOOP:
2622 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2623 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2624 terminate_mbb(pc);
2625 break;
2626 case TGSI_OPCODE_BGNSUB:
2627 assert(!pc->in_subroutine);
2628 pc->in_subroutine = TRUE;
2629 /* probably not necessary, but align to 8 byte boundary */
2630 if (!is_long(pc->p->exec_tail))
2631 convert_to_long(pc, pc->p->exec_tail);
2632 break;
2633 case TGSI_OPCODE_BRK:
2634 assert(pc->loop_lvl > 0);
2635 emit_break(pc, -1, 0);
2636 break;
2637 case TGSI_OPCODE_CAL:
2638 assert(inst->Label.Label < pc->insn_nr);
2639 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2640 /* replaced by actual offset in nv50_program_fixup_insns */
2641 break;
2642 case TGSI_OPCODE_CEIL:
2643 for (c = 0; c < 4; c++) {
2644 if (!(mask & (1 << c)))
2645 continue;
2646 emit_cvt(pc, dst[c], src[0][c], -1,
2647 CVT_CEIL | CVT_F32_F32 | CVT_RI);
2648 }
2649 break;
2650 case TGSI_OPCODE_CMP:
2651 pc->allow32 = FALSE;
2652 for (c = 0; c < 4; c++) {
2653 if (!(mask & (1 << c)))
2654 continue;
2655 emit_cvt(pc, NULL, src[0][c], 1, CVT_F32_F32);
2656 emit_mov(pc, dst[c], src[1][c]);
2657 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2658 emit_mov(pc, dst[c], src[2][c]);
2659 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2660 }
2661 break;
2662 case TGSI_OPCODE_CONT:
2663 assert(pc->loop_lvl > 0);
2664 emit_branch(pc, -1, 0)->param.index =
2665 pc->loop_pos[pc->loop_lvl - 1];
2666 break;
2667 case TGSI_OPCODE_COS:
2668 if (mask & 8) {
2669 emit_precossin(pc, temp, src[0][3]);
2670 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2671 if (!(mask &= 7))
2672 break;
2673 if (temp == dst[3])
2674 temp = brdc = temp_temp(pc, NULL);
2675 }
2676 emit_precossin(pc, temp, src[0][0]);
2677 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2678 break;
2679 case TGSI_OPCODE_DDX:
2680 for (c = 0; c < 4; c++) {
2681 if (!(mask & (1 << c)))
2682 continue;
2683 emit_ddx(pc, dst[c], src[0][c]);
2684 }
2685 break;
2686 case TGSI_OPCODE_DDY:
2687 for (c = 0; c < 4; c++) {
2688 if (!(mask & (1 << c)))
2689 continue;
2690 emit_ddy(pc, dst[c], src[0][c]);
2691 }
2692 break;
2693 case TGSI_OPCODE_DP3:
2694 emit_mul(pc, temp, src[0][0], src[1][0]);
2695 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2696 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2697 break;
2698 case TGSI_OPCODE_DP4:
2699 emit_mul(pc, temp, src[0][0], src[1][0]);
2700 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2701 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2702 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2703 break;
2704 case TGSI_OPCODE_DPH:
2705 emit_mul(pc, temp, src[0][0], src[1][0]);
2706 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2707 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2708 emit_add(pc, brdc, src[1][3], temp);
2709 break;
2710 case TGSI_OPCODE_DST:
2711 if (mask & (1 << 1))
2712 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2713 if (mask & (1 << 2))
2714 emit_mov(pc, dst[2], src[0][2]);
2715 if (mask & (1 << 3))
2716 emit_mov(pc, dst[3], src[1][3]);
2717 if (mask & (1 << 0))
2718 emit_mov_immdval(pc, dst[0], 1.0f);
2719 break;
2720 case TGSI_OPCODE_ELSE:
2721 emit_branch(pc, -1, 0);
2722 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2723 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2724 terminate_mbb(pc);
2725 break;
2726 case TGSI_OPCODE_EMIT:
2727 emit_prim_cmd(pc, 1);
2728 break;
2729 case TGSI_OPCODE_ENDIF:
2730 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2731
2732 /* try to replace branch over 1 insn with a predicated insn */
2733 if (nv50_kill_branch(pc) == TRUE)
2734 break;
2735
2736 if (pc->if_join[pc->if_lvl]) {
2737 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2738 pc->if_join[pc->if_lvl] = NULL;
2739 }
2740 terminate_mbb(pc);
2741 /* emit a NOP as join point, we could set it on the next
2742 * one, but would have to make sure it is long and !immd
2743 */
2744 JOIN_ON(emit_nop(pc));
2745 break;
2746 case TGSI_OPCODE_ENDLOOP:
2747 emit_branch(pc, -1, 0)->param.index =
2748 pc->loop_pos[--pc->loop_lvl];
2749 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2750 terminate_mbb(pc);
2751 break;
2752 case TGSI_OPCODE_ENDPRIM:
2753 emit_prim_cmd(pc, 2);
2754 break;
2755 case TGSI_OPCODE_ENDSUB:
2756 assert(pc->in_subroutine);
2757 terminate_mbb(pc);
2758 pc->in_subroutine = FALSE;
2759 break;
2760 case TGSI_OPCODE_EX2:
2761 emit_preex2(pc, temp, src[0][0]);
2762 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2763 break;
2764 case TGSI_OPCODE_EXP:
2765 {
2766 struct nv50_reg *t[2];
2767
2768 assert(!temp);
2769 t[0] = temp_temp(pc, NULL);
2770 t[1] = temp_temp(pc, NULL);
2771
2772 if (mask & 0x6)
2773 emit_mov(pc, t[0], src[0][0]);
2774 if (mask & 0x3)
2775 emit_flr(pc, t[1], src[0][0]);
2776
2777 if (mask & (1 << 1))
2778 emit_sub(pc, dst[1], t[0], t[1]);
2779 if (mask & (1 << 0)) {
2780 emit_preex2(pc, t[1], t[1]);
2781 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2782 }
2783 if (mask & (1 << 2)) {
2784 emit_preex2(pc, t[0], t[0]);
2785 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2786 }
2787 if (mask & (1 << 3))
2788 emit_mov_immdval(pc, dst[3], 1.0f);
2789 }
2790 break;
2791 case TGSI_OPCODE_F2I:
2792 for (c = 0; c < 4; c++) {
2793 if (!(mask & (1 << c)))
2794 continue;
2795 emit_cvt(pc, dst[c], src[0][c], -1,
2796 CVT_TRUNC | CVT_S32_F32);
2797 }
2798 break;
2799 case TGSI_OPCODE_F2U:
2800 for (c = 0; c < 4; c++) {
2801 if (!(mask & (1 << c)))
2802 continue;
2803 emit_cvt(pc, dst[c], src[0][c], -1,
2804 CVT_TRUNC | CVT_U32_F32);
2805 }
2806 break;
2807 case TGSI_OPCODE_FLR:
2808 for (c = 0; c < 4; c++) {
2809 if (!(mask & (1 << c)))
2810 continue;
2811 emit_flr(pc, dst[c], src[0][c]);
2812 }
2813 break;
2814 case TGSI_OPCODE_FRC:
2815 temp = temp_temp(pc, NULL);
2816 for (c = 0; c < 4; c++) {
2817 if (!(mask & (1 << c)))
2818 continue;
2819 emit_flr(pc, temp, src[0][c]);
2820 emit_sub(pc, dst[c], src[0][c], temp);
2821 }
2822 break;
2823 case TGSI_OPCODE_I2F:
2824 for (c = 0; c < 4; c++) {
2825 if (!(mask & (1 << c)))
2826 continue;
2827 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_S32);
2828 }
2829 break;
2830 case TGSI_OPCODE_IF:
2831 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2832 emit_cvt(pc, NULL, src[0][0], 0, CVT_ABS | CVT_F32_F32);
2833 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2834 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2835 terminate_mbb(pc);
2836 break;
2837 case TGSI_OPCODE_IMAX:
2838 for (c = 0; c < 4; c++) {
2839 if (!(mask & (1 << c)))
2840 continue;
2841 emit_minmax(pc, 0x08c, dst[c], src[0][c], src[1][c]);
2842 }
2843 break;
2844 case TGSI_OPCODE_IMIN:
2845 for (c = 0; c < 4; c++) {
2846 if (!(mask & (1 << c)))
2847 continue;
2848 emit_minmax(pc, 0x0ac, dst[c], src[0][c], src[1][c]);
2849 }
2850 break;
2851 case TGSI_OPCODE_INEG:
2852 for (c = 0; c < 4; c++) {
2853 if (!(mask & (1 << c)))
2854 continue;
2855 emit_cvt(pc, dst[c], src[0][c], -1,
2856 CVT_S32_S32 | CVT_NEG);
2857 }
2858 break;
2859 case TGSI_OPCODE_KIL:
2860 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2861 emit_kil(pc, src[0][0]);
2862 emit_kil(pc, src[0][1]);
2863 emit_kil(pc, src[0][2]);
2864 emit_kil(pc, src[0][3]);
2865 break;
2866 case TGSI_OPCODE_KILP:
2867 emit_kil(pc, NULL);
2868 break;
2869 case TGSI_OPCODE_LIT:
2870 emit_lit(pc, &dst[0], mask, &src[0][0]);
2871 break;
2872 case TGSI_OPCODE_LG2:
2873 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2874 break;
2875 case TGSI_OPCODE_LOG:
2876 {
2877 struct nv50_reg *t[2];
2878
2879 t[0] = temp_temp(pc, NULL);
2880 if (mask & (1 << 1))
2881 t[1] = temp_temp(pc, NULL);
2882 else
2883 t[1] = t[0];
2884
2885 emit_cvt(pc, t[0], src[0][0], -1, CVT_ABS | CVT_F32_F32);
2886 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2887 if (mask & (1 << 2))
2888 emit_mov(pc, dst[2], t[1]);
2889 emit_flr(pc, t[1], t[1]);
2890 if (mask & (1 << 0))
2891 emit_mov(pc, dst[0], t[1]);
2892 if (mask & (1 << 1)) {
2893 t[1]->mod = NV50_MOD_NEG;
2894 emit_preex2(pc, t[1], t[1]);
2895 t[1]->mod = 0;
2896 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2897 emit_mul(pc, dst[1], t[0], t[1]);
2898 }
2899 if (mask & (1 << 3))
2900 emit_mov_immdval(pc, dst[3], 1.0f);
2901 }
2902 break;
2903 case TGSI_OPCODE_LRP:
2904 temp = temp_temp(pc, NULL);
2905 for (c = 0; c < 4; c++) {
2906 if (!(mask & (1 << c)))
2907 continue;
2908 emit_sub(pc, temp, src[1][c], src[2][c]);
2909 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2910 }
2911 break;
2912 case TGSI_OPCODE_MAD:
2913 for (c = 0; c < 4; c++) {
2914 if (!(mask & (1 << c)))
2915 continue;
2916 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2917 }
2918 break;
2919 case TGSI_OPCODE_MAX:
2920 for (c = 0; c < 4; c++) {
2921 if (!(mask & (1 << c)))
2922 continue;
2923 emit_minmax(pc, 0x880, dst[c], src[0][c], src[1][c]);
2924 }
2925 break;
2926 case TGSI_OPCODE_MIN:
2927 for (c = 0; c < 4; c++) {
2928 if (!(mask & (1 << c)))
2929 continue;
2930 emit_minmax(pc, 0x8a0, dst[c], src[0][c], src[1][c]);
2931 }
2932 break;
2933 case TGSI_OPCODE_MOV:
2934 for (c = 0; c < 4; c++) {
2935 if (!(mask & (1 << c)))
2936 continue;
2937 emit_mov(pc, dst[c], src[0][c]);
2938 }
2939 break;
2940 case TGSI_OPCODE_MUL:
2941 for (c = 0; c < 4; c++) {
2942 if (!(mask & (1 << c)))
2943 continue;
2944 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2945 }
2946 break;
2947 case TGSI_OPCODE_NOT:
2948 for (c = 0; c < 4; c++) {
2949 if (!(mask & (1 << c)))
2950 continue;
2951 emit_not(pc, dst[c], src[0][c]);
2952 }
2953 break;
2954 case TGSI_OPCODE_POW:
2955 emit_pow(pc, brdc, src[0][0], src[1][0]);
2956 break;
2957 case TGSI_OPCODE_RCP:
2958 if (!sat && popcnt4(mask) == 1)
2959 brdc = dst[ffs(mask) - 1];
2960 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2961 break;
2962 case TGSI_OPCODE_RET:
2963 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2964 nv50_fp_move_results(pc);
2965 emit_ret(pc, -1, 0);
2966 break;
2967 case TGSI_OPCODE_RSQ:
2968 if (!sat && popcnt4(mask) == 1)
2969 brdc = dst[ffs(mask) - 1];
2970 src[0][0]->mod |= NV50_MOD_ABS;
2971 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2972 break;
2973 case TGSI_OPCODE_SAD:
2974 for (c = 0; c < 4; c++) {
2975 if (!(mask & (1 << c)))
2976 continue;
2977 emit_sad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2978 }
2979 break;
2980 case TGSI_OPCODE_SCS:
2981 temp = temp_temp(pc, NULL);
2982 if (mask & 3)
2983 emit_precossin(pc, temp, src[0][0]);
2984 if (mask & (1 << 0))
2985 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
2986 if (mask & (1 << 1))
2987 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
2988 if (mask & (1 << 2))
2989 emit_mov_immdval(pc, dst[2], 0.0);
2990 if (mask & (1 << 3))
2991 emit_mov_immdval(pc, dst[3], 1.0);
2992 break;
2993 case TGSI_OPCODE_SHL:
2994 case TGSI_OPCODE_ISHR:
2995 case TGSI_OPCODE_USHR:
2996 for (c = 0; c < 4; c++) {
2997 if (!(mask & (1 << c)))
2998 continue;
2999 emit_shift(pc, dst[c], src[0][c], src[1][c],
3000 inst->Instruction.Opcode);
3001 }
3002 break;
3003 case TGSI_OPCODE_SIN:
3004 if (mask & 8) {
3005 emit_precossin(pc, temp, src[0][3]);
3006 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
3007 if (!(mask &= 7))
3008 break;
3009 if (temp == dst[3])
3010 temp = brdc = temp_temp(pc, NULL);
3011 }
3012 emit_precossin(pc, temp, src[0][0]);
3013 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
3014 break;
3015 case TGSI_OPCODE_SLT:
3016 case TGSI_OPCODE_SGE:
3017 case TGSI_OPCODE_SEQ:
3018 case TGSI_OPCODE_SGT:
3019 case TGSI_OPCODE_SLE:
3020 case TGSI_OPCODE_SNE:
3021 case TGSI_OPCODE_ISLT:
3022 case TGSI_OPCODE_ISGE:
3023 case TGSI_OPCODE_USEQ:
3024 case TGSI_OPCODE_USGE:
3025 case TGSI_OPCODE_USLT:
3026 case TGSI_OPCODE_USNE:
3027 {
3028 uint8_t cc, ty;
3029
3030 map_tgsi_setop_hw(inst->Instruction.Opcode, &cc, &ty);
3031
3032 for (c = 0; c < 4; c++) {
3033 if (!(mask & (1 << c)))
3034 continue;
3035 emit_set(pc, cc, dst[c], -1, src[0][c], src[1][c], ty);
3036 }
3037 }
3038 break;
3039 case TGSI_OPCODE_SUB:
3040 for (c = 0; c < 4; c++) {
3041 if (!(mask & (1 << c)))
3042 continue;
3043 emit_sub(pc, dst[c], src[0][c], src[1][c]);
3044 }
3045 break;
3046 case TGSI_OPCODE_TEX:
3047 emit_tex(pc, dst, mask, src[0], unit,
3048 inst->Texture.Texture, FALSE, 0);
3049 break;
3050 case TGSI_OPCODE_TXB:
3051 emit_tex(pc, dst, mask, src[0], unit,
3052 inst->Texture.Texture, FALSE, -1);
3053 break;
3054 case TGSI_OPCODE_TXL:
3055 emit_tex(pc, dst, mask, src[0], unit,
3056 inst->Texture.Texture, FALSE, 1);
3057 break;
3058 case TGSI_OPCODE_TXP:
3059 emit_tex(pc, dst, mask, src[0], unit,
3060 inst->Texture.Texture, TRUE, 0);
3061 break;
3062 case TGSI_OPCODE_TRUNC:
3063 for (c = 0; c < 4; c++) {
3064 if (!(mask & (1 << c)))
3065 continue;
3066 emit_cvt(pc, dst[c], src[0][c], -1,
3067 CVT_TRUNC | CVT_F32_F32 | CVT_RI);
3068 }
3069 break;
3070 case TGSI_OPCODE_U2F:
3071 for (c = 0; c < 4; c++) {
3072 if (!(mask & (1 << c)))
3073 continue;
3074 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_U32);
3075 }
3076 break;
3077 case TGSI_OPCODE_UADD:
3078 for (c = 0; c < 4; c++) {
3079 if (!(mask & (1 << c)))
3080 continue;
3081 emit_add_b32(pc, dst[c], src[0][c], src[1][c]);
3082 }
3083 break;
3084 case TGSI_OPCODE_UMAX:
3085 for (c = 0; c < 4; c++) {
3086 if (!(mask & (1 << c)))
3087 continue;
3088 emit_minmax(pc, 0x084, dst[c], src[0][c], src[1][c]);
3089 }
3090 break;
3091 case TGSI_OPCODE_UMIN:
3092 for (c = 0; c < 4; c++) {
3093 if (!(mask & (1 << c)))
3094 continue;
3095 emit_minmax(pc, 0x0a4, dst[c], src[0][c], src[1][c]);
3096 }
3097 break;
3098 case TGSI_OPCODE_UMAD:
3099 {
3100 assert(!temp);
3101 temp = temp_temp(pc, NULL);
3102 for (c = 0; c < 4; c++) {
3103 if (!(mask & (1 << c)))
3104 continue;
3105 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3106 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3107 temp);
3108 emit_shl_imm(pc, temp, temp, 16);
3109 emit_mad_u16(pc, temp, src[0][c], 0, src[1][c], 0,
3110 temp);
3111 emit_add_b32(pc, dst[c], temp, src[2][c]);
3112 }
3113 }
3114 break;
3115 case TGSI_OPCODE_UMUL:
3116 {
3117 assert(!temp);
3118 temp = temp_temp(pc, NULL);
3119 for (c = 0; c < 4; c++) {
3120 if (!(mask & (1 << c)))
3121 continue;
3122 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3123 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3124 temp);
3125 emit_shl_imm(pc, temp, temp, 16);
3126 emit_mad_u16(pc, dst[c], src[0][c], 0, src[1][c], 0,
3127 temp);
3128 }
3129 }
3130 break;
3131 case TGSI_OPCODE_XPD:
3132 temp = temp_temp(pc, NULL);
3133 if (mask & (1 << 0)) {
3134 emit_mul(pc, temp, src[0][2], src[1][1]);
3135 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
3136 }
3137 if (mask & (1 << 1)) {
3138 emit_mul(pc, temp, src[0][0], src[1][2]);
3139 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
3140 }
3141 if (mask & (1 << 2)) {
3142 emit_mul(pc, temp, src[0][1], src[1][0]);
3143 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
3144 }
3145 if (mask & (1 << 3))
3146 emit_mov_immdval(pc, dst[3], 1.0);
3147 break;
3148 case TGSI_OPCODE_END:
3149 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3150 nv50_fp_move_results(pc);
3151
3152 /* last insn must be long so it can have the exit bit set */
3153 if (!is_long(pc->p->exec_tail))
3154 convert_to_long(pc, pc->p->exec_tail);
3155 else
3156 if (is_immd(pc->p->exec_tail) || is_join(pc->p->exec_tail))
3157 emit_nop(pc);
3158
3159 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
3160
3161 terminate_mbb(pc);
3162 break;
3163 default:
3164 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
3165 return FALSE;
3166 }
3167
3168 if (brdc) {
3169 if (sat)
3170 emit_sat(pc, brdc, brdc);
3171 for (c = 0; c < 4; c++)
3172 if ((mask & (1 << c)) && dst[c] != brdc)
3173 emit_mov(pc, dst[c], brdc);
3174 } else
3175 if (sat) {
3176 for (c = 0; c < 4; c++) {
3177 if (!(mask & (1 << c)))
3178 continue;
3179 /* In this case we saturate later, and dst[c] won't
3180 * be another temp_temp (and thus lost), since rdst
3181 * already is TEMP (see above). */
3182 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
3183 continue;
3184 emit_sat(pc, rdst[c], dst[c]);
3185 }
3186 }
3187
3188 kill_temp_temp(pc, NULL);
3189 pc->reg_instance_nr = 0;
3190
3191 return TRUE;
3192 }
3193
3194 static void
3195 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
3196 {
3197 struct nv50_reg *r, *reg = NULL;
3198 const struct tgsi_full_src_register *src;
3199 const struct tgsi_dst_register *dst;
3200 unsigned i, c, k, mask;
3201
3202 dst = &insn->Dst[0].Register;
3203 mask = dst->WriteMask;
3204
3205 if (dst->File == TGSI_FILE_TEMPORARY)
3206 reg = pc->temp;
3207 else
3208 if (dst->File == TGSI_FILE_OUTPUT) {
3209 reg = pc->result;
3210
3211 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
3212 dst->Index == pc->edgeflag_out &&
3213 insn->Src[0].Register.File == TGSI_FILE_INPUT)
3214 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
3215 }
3216
3217 if (reg) {
3218 for (c = 0; c < 4; c++) {
3219 if (!(mask & (1 << c)))
3220 continue;
3221 reg[dst->Index * 4 + c].acc = pc->insn_nr;
3222 }
3223 }
3224
3225 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3226 src = &insn->Src[i];
3227
3228 if (src->Register.File == TGSI_FILE_TEMPORARY)
3229 reg = pc->temp;
3230 else
3231 if (src->Register.File == TGSI_FILE_INPUT)
3232 reg = pc->attr;
3233 else
3234 continue;
3235
3236 mask = nv50_tgsi_src_mask(insn, i);
3237
3238 for (c = 0; c < 4; c++) {
3239 if (!(mask & (1 << c)))
3240 continue;
3241 k = tgsi_util_get_full_src_register_swizzle(src, c);
3242
3243 r = &reg[src->Register.Index * 4 + k];
3244
3245 /* If used before written, pre-allocate the reg,
3246 * lest we overwrite results from a subroutine.
3247 */
3248 if (!r->acc && r->type == P_TEMP)
3249 alloc_reg(pc, r);
3250
3251 r->acc = pc->insn_nr;
3252 }
3253 }
3254 }
3255
3256 /* Returns a bitmask indicating which dst components need to be
3257 * written to temporaries first to avoid 'corrupting' sources.
3258 *
3259 * m[i] (out) indicate component to write in the i-th position
3260 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
3261 */
3262 static unsigned
3263 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
3264 {
3265 unsigned i, c, x, unsafe;
3266
3267 for (c = 0; c < 4; c++)
3268 m[c] = c;
3269
3270 /* Swap as long as a dst component written earlier is depended on
3271 * by one written later, but the next one isn't depended on by it.
3272 */
3273 for (c = 0; c < 3; c++) {
3274 if (rdep[m[c + 1]] & (1 << m[c]))
3275 continue; /* if next one is depended on by us */
3276 for (i = c + 1; i < 4; i++)
3277 /* if we are depended on by a later one */
3278 if (rdep[m[c]] & (1 << m[i]))
3279 break;
3280 if (i == 4)
3281 continue;
3282 /* now, swap */
3283 x = m[c];
3284 m[c] = m[c + 1];
3285 m[c + 1] = x;
3286
3287 /* restart */
3288 c = 0;
3289 }
3290
3291 /* mark dependencies that could not be resolved by reordering */
3292 for (i = 0; i < 3; ++i)
3293 for (c = i + 1; c < 4; ++c)
3294 if (rdep[m[i]] & (1 << m[c]))
3295 unsafe |= (1 << i);
3296
3297 /* NOTE: $unsafe is with respect to order, not component */
3298 return unsafe;
3299 }
3300
3301 /* Select a suitable dst register for broadcasting scalar results,
3302 * or return NULL if we have to allocate an extra TEMP.
3303 *
3304 * If e.g. only 1 component is written, we may also emit the final
3305 * result to a write-only register.
3306 */
3307 static struct nv50_reg *
3308 tgsi_broadcast_dst(struct nv50_pc *pc,
3309 const struct tgsi_full_dst_register *fd, unsigned mask)
3310 {
3311 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
3312 int c = ffs(~mask & fd->Register.WriteMask);
3313 if (c)
3314 return tgsi_dst(pc, c - 1, fd);
3315 } else {
3316 int c = ffs(fd->Register.WriteMask) - 1;
3317 if ((1 << c) == fd->Register.WriteMask)
3318 return tgsi_dst(pc, c, fd);
3319 }
3320
3321 return NULL;
3322 }
3323
3324 /* Scan source swizzles and return a bitmask indicating dst regs that
3325 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
3326 */
3327 static unsigned
3328 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
3329 unsigned rdep[4])
3330 {
3331 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
3332 const struct tgsi_full_src_register *fs;
3333 unsigned i, deqs = 0;
3334
3335 for (i = 0; i < 4; ++i)
3336 rdep[i] = 0;
3337
3338 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3339 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
3340 int ms = get_supported_mods(insn, i);
3341
3342 fs = &insn->Src[i];
3343 if (fs->Register.File != fd->Register.File ||
3344 fs->Register.Index != fd->Register.Index)
3345 continue;
3346
3347 for (chn = 0; chn < 4; ++chn) {
3348 unsigned s, c;
3349
3350 if (!(mask & (1 << chn))) /* src is not read */
3351 continue;
3352 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
3353 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
3354
3355 if (!(fd->Register.WriteMask & (1 << c)))
3356 continue;
3357
3358 if (s == TGSI_UTIL_SIGN_TOGGLE && !(ms & NV50_MOD_NEG))
3359 continue;
3360 if (s == TGSI_UTIL_SIGN_CLEAR && !(ms & NV50_MOD_ABS))
3361 continue;
3362 if ((s == TGSI_UTIL_SIGN_SET) && ((ms & 3) != 3))
3363 continue;
3364
3365 rdep[c] |= nv50_tgsi_dst_revdep(
3366 insn->Instruction.Opcode, i, chn);
3367 deqs |= (1 << c);
3368 }
3369 }
3370
3371 return deqs;
3372 }
3373
3374 static boolean
3375 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
3376 {
3377 struct tgsi_full_instruction insn = tok->FullInstruction;
3378 const struct tgsi_full_dst_register *fd;
3379 unsigned i, deqs, rdep[4], m[4];
3380
3381 fd = &tok->FullInstruction.Dst[0];
3382 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
3383
3384 if (is_scalar_op(insn.Instruction.Opcode)) {
3385 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
3386 if (!pc->r_brdc)
3387 pc->r_brdc = temp_temp(pc, NULL);
3388 return nv50_program_tx_insn(pc, &insn);
3389 }
3390 pc->r_brdc = NULL;
3391
3392 if (!deqs || (!rdep[0] && !rdep[1] && !rdep[2] && !rdep[3]))
3393 return nv50_program_tx_insn(pc, &insn);
3394
3395 deqs = nv50_revdep_reorder(m, rdep);
3396
3397 for (i = 0; i < 4; ++i) {
3398 assert(pc->r_dst[m[i]] == NULL);
3399
3400 insn.Dst[0].Register.WriteMask =
3401 fd->Register.WriteMask & (1 << m[i]);
3402
3403 if (!insn.Dst[0].Register.WriteMask)
3404 continue;
3405
3406 if (deqs & (1 << i))
3407 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
3408
3409 if (!nv50_program_tx_insn(pc, &insn))
3410 return FALSE;
3411 }
3412
3413 for (i = 0; i < 4; i++) {
3414 struct nv50_reg *reg = pc->r_dst[i];
3415 if (!reg)
3416 continue;
3417 pc->r_dst[i] = NULL;
3418
3419 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
3420 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
3421 else
3422 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
3423 free_temp(pc, reg);
3424 }
3425
3426 return TRUE;
3427 }
3428
3429 static void
3430 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
3431 {
3432 struct nv50_reg *iv, **ppiv;
3433 unsigned mode = pc->interp_mode[reg->index];
3434
3435 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
3436 iv = *ppiv;
3437
3438 if ((mode & INTERP_PERSPECTIVE) && !iv) {
3439 iv = *ppiv = alloc_temp(pc, NULL);
3440 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
3441
3442 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
3443 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
3444
3445 /* XXX: when loading interpolants dynamically, move these
3446 * to the program head, or make sure it can't be skipped.
3447 */
3448 }
3449
3450 emit_interp(pc, reg, iv, mode);
3451 }
3452
3453 /* The face input is always at v[255] (varying space), with a
3454 * value of 0 for back-facing, and 0xffffffff for front-facing.
3455 */
3456 static void
3457 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
3458 {
3459 struct nv50_reg *one = alloc_immd(pc, 1.0f);
3460
3461 assert(a->rhw == -1);
3462 alloc_reg(pc, a); /* do this before rhw is set */
3463 a->rhw = 255;
3464 load_interpolant(pc, a);
3465 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
3466
3467 FREE(one);
3468 }
3469
3470 static void
3471 copy_semantic_info(struct nv50_program *p)
3472 {
3473 unsigned i, id;
3474
3475 for (i = 0; i < p->cfg.in_nr; ++i) {
3476 id = p->cfg.in[i].id;
3477 p->cfg.in[i].sn = p->info.input_semantic_name[id];
3478 p->cfg.in[i].si = p->info.input_semantic_index[id];
3479 }
3480
3481 for (i = 0; i < p->cfg.out_nr; ++i) {
3482 id = p->cfg.out[i].id;
3483 p->cfg.out[i].sn = p->info.output_semantic_name[id];
3484 p->cfg.out[i].si = p->info.output_semantic_index[id];
3485 }
3486 }
3487
3488 static boolean
3489 nv50_program_tx_prep(struct nv50_pc *pc)
3490 {
3491 struct tgsi_parse_context tp;
3492 struct nv50_program *p = pc->p;
3493 boolean ret = FALSE;
3494 unsigned i, c, flat_nr = 0;
3495
3496 tgsi_parse_init(&tp, pc->p->pipe.tokens);
3497 while (!tgsi_parse_end_of_tokens(&tp)) {
3498 const union tgsi_full_token *tok = &tp.FullToken;
3499
3500 tgsi_parse_token(&tp);
3501 switch (tok->Token.Type) {
3502 case TGSI_TOKEN_TYPE_IMMEDIATE:
3503 {
3504 const struct tgsi_full_immediate *imm =
3505 &tp.FullToken.FullImmediate;
3506
3507 ctor_immd_4f32(pc, imm->u[0].Float,
3508 imm->u[1].Float,
3509 imm->u[2].Float,
3510 imm->u[3].Float);
3511 }
3512 break;
3513 case TGSI_TOKEN_TYPE_DECLARATION:
3514 {
3515 const struct tgsi_full_declaration *d;
3516 unsigned si, last, first, mode;
3517
3518 d = &tp.FullToken.FullDeclaration;
3519 first = d->Range.First;
3520 last = d->Range.Last;
3521
3522 switch (d->Declaration.File) {
3523 case TGSI_FILE_TEMPORARY:
3524 break;
3525 case TGSI_FILE_OUTPUT:
3526 if (!d->Declaration.Semantic ||
3527 p->type == PIPE_SHADER_FRAGMENT)
3528 break;
3529
3530 si = d->Semantic.Index;
3531 switch (d->Semantic.Name) {
3532 case TGSI_SEMANTIC_BCOLOR:
3533 p->cfg.two_side[si].hw = first;
3534 if (p->cfg.out_nr > first)
3535 p->cfg.out_nr = first;
3536 break;
3537 case TGSI_SEMANTIC_PSIZE:
3538 p->cfg.psiz = first;
3539 if (p->cfg.out_nr > first)
3540 p->cfg.out_nr = first;
3541 break;
3542 case TGSI_SEMANTIC_EDGEFLAG:
3543 pc->edgeflag_out = first;
3544 break;
3545 /*
3546 case TGSI_SEMANTIC_CLIP_DISTANCE:
3547 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3548 break;
3549 */
3550 default:
3551 break;
3552 }
3553 break;
3554 case TGSI_FILE_INPUT:
3555 {
3556 if (p->type != PIPE_SHADER_FRAGMENT)
3557 break;
3558
3559 switch (d->Declaration.Interpolate) {
3560 case TGSI_INTERPOLATE_CONSTANT:
3561 mode = INTERP_FLAT;
3562 flat_nr++;
3563 break;
3564 case TGSI_INTERPOLATE_PERSPECTIVE:
3565 mode = INTERP_PERSPECTIVE;
3566 p->cfg.regs[1] |= 0x08 << 24;
3567 break;
3568 default:
3569 mode = INTERP_LINEAR;
3570 break;
3571 }
3572 if (d->Declaration.Centroid)
3573 mode |= INTERP_CENTROID;
3574
3575 assert(last < 32);
3576 for (i = first; i <= last; i++)
3577 pc->interp_mode[i] = mode;
3578 }
3579 break;
3580 case TGSI_FILE_ADDRESS:
3581 case TGSI_FILE_CONSTANT:
3582 case TGSI_FILE_SAMPLER:
3583 break;
3584 default:
3585 NOUVEAU_ERR("bad decl file %d\n",
3586 d->Declaration.File);
3587 goto out_err;
3588 }
3589 }
3590 break;
3591 case TGSI_TOKEN_TYPE_INSTRUCTION:
3592 pc->insn_nr++;
3593 prep_inspect_insn(pc, &tok->FullInstruction);
3594 break;
3595 default:
3596 break;
3597 }
3598 }
3599
3600 if (p->type == PIPE_SHADER_VERTEX || p->type == PIPE_SHADER_GEOMETRY) {
3601 int rid = 0;
3602
3603 if (p->type == PIPE_SHADER_GEOMETRY) {
3604 for (i = 0; i < pc->attr_nr; ++i) {
3605 p->cfg.in[i].hw = rid;
3606 p->cfg.in[i].id = i;
3607
3608 for (c = 0; c < 4; ++c) {
3609 int n = i * 4 + c;
3610 if (!pc->attr[n].acc)
3611 continue;
3612 pc->attr[n].hw = rid++;
3613 p->cfg.in[i].mask |= 1 << c;
3614 }
3615 }
3616 } else {
3617 for (i = 0; i < pc->attr_nr * 4; ++i) {
3618 if (pc->attr[i].acc) {
3619 pc->attr[i].hw = rid++;
3620 p->cfg.attr[i / 32] |= 1 << (i % 32);
3621 }
3622 }
3623 }
3624
3625 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3626 p->cfg.out[i].hw = rid;
3627 p->cfg.out[i].id = i;
3628
3629 for (c = 0; c < 4; ++c) {
3630 int n = i * 4 + c;
3631 if (!pc->result[n].acc)
3632 continue;
3633 pc->result[n].hw = rid++;
3634 p->cfg.out[i].mask |= 1 << c;
3635 }
3636 }
3637
3638 for (c = 0; c < 2; ++c)
3639 if (p->cfg.two_side[c].hw < 0x40)
3640 p->cfg.two_side[c] = p->cfg.out[
3641 p->cfg.two_side[c].hw];
3642
3643 if (p->cfg.psiz < 0x40)
3644 p->cfg.psiz = p->cfg.out[p->cfg.psiz].hw;
3645
3646 copy_semantic_info(p);
3647 } else
3648 if (p->type == PIPE_SHADER_FRAGMENT) {
3649 int rid, aid, base;
3650 unsigned n = 0, m = pc->attr_nr - flat_nr;
3651
3652 pc->allow32 = TRUE;
3653
3654 base = (TGSI_SEMANTIC_POSITION ==
3655 p->info.input_semantic_name[0]) ? 0 : 1;
3656
3657 /* non-flat interpolants have to be mapped to
3658 * the lower hardware IDs, so sort them:
3659 */
3660 for (i = 0; i < pc->attr_nr; i++) {
3661 if (pc->interp_mode[i] == INTERP_FLAT)
3662 p->cfg.in[m++].id = i;
3663 else {
3664 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3665 p->cfg.in[n].linear = TRUE;
3666 p->cfg.in[n++].id = i;
3667 }
3668 }
3669 copy_semantic_info(p);
3670
3671 if (!base) /* set w-coordinate mask from perspective interp */
3672 p->cfg.in[0].mask |= p->cfg.regs[1] >> 24;
3673
3674 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
3675 base ? (p->cfg.regs[1] >> 24) : p->cfg.in[0].mask);
3676
3677 for (n = 0; n < pc->attr_nr; ++n) {
3678 p->cfg.in[n].hw = rid = aid;
3679 i = p->cfg.in[n].id;
3680
3681 if (p->info.input_semantic_name[n] ==
3682 TGSI_SEMANTIC_FACE) {
3683 load_frontfacing(pc, &pc->attr[i * 4]);
3684 continue;
3685 }
3686
3687 for (c = 0; c < 4; ++c) {
3688 if (!pc->attr[i * 4 + c].acc)
3689 continue;
3690 pc->attr[i * 4 + c].rhw = rid++;
3691 p->cfg.in[n].mask |= 1 << c;
3692
3693 load_interpolant(pc, &pc->attr[i * 4 + c]);
3694 }
3695 aid += popcnt4(p->cfg.in[n].mask);
3696 }
3697
3698 if (!base)
3699 p->cfg.regs[1] |= p->cfg.in[0].mask << 24;
3700
3701 m = popcnt4(p->cfg.regs[1] >> 24);
3702
3703 /* set count of non-position inputs and of non-flat
3704 * non-position inputs for FP_INTERPOLANT_CTRL
3705 */
3706 p->cfg.regs[1] |= aid - m;
3707
3708 if (flat_nr) {
3709 i = p->cfg.in[pc->attr_nr - flat_nr].hw;
3710 p->cfg.regs[1] |= (i - m) << 16;
3711 } else
3712 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3713
3714 /* mark color semantic for light-twoside */
3715 n = 0x80;
3716 for (i = 0; i < p->cfg.in_nr; i++) {
3717 if (p->cfg.in[i].sn == TGSI_SEMANTIC_COLOR) {
3718 n = MIN2(n, p->cfg.in[i].hw - m);
3719 p->cfg.two_side[p->cfg.in[i].si] = p->cfg.in[i];
3720
3721 p->cfg.regs[0] += /* increase colour count */
3722 popcnt4(p->cfg.in[i].mask) << 16;
3723 }
3724 }
3725 if (n < 0x80)
3726 p->cfg.regs[0] += n;
3727
3728 /* Initialize FP results:
3729 * FragDepth is always first TGSI and last hw output
3730 */
3731 i = p->info.writes_z ? 4 : 0;
3732 for (rid = 0; i < pc->result_nr * 4; i++)
3733 pc->result[i].rhw = rid++;
3734 if (p->info.writes_z)
3735 pc->result[2].rhw = rid;
3736
3737 p->cfg.high_result = rid;
3738
3739 /* separate/different colour results for MRTs ? */
3740 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3741 p->cfg.regs[2] |= 1;
3742 }
3743
3744 if (pc->immd_nr) {
3745 int rid = 0;
3746
3747 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3748 if (!pc->immd)
3749 goto out_err;
3750
3751 for (i = 0; i < pc->immd_nr; i++) {
3752 for (c = 0; c < 4; c++, rid++)
3753 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3754 }
3755 }
3756
3757 ret = TRUE;
3758 out_err:
3759 if (pc->iv_p)
3760 free_temp(pc, pc->iv_p);
3761 if (pc->iv_c)
3762 free_temp(pc, pc->iv_c);
3763
3764 tgsi_parse_free(&tp);
3765 return ret;
3766 }
3767
3768 static void
3769 free_nv50_pc(struct nv50_pc *pc)
3770 {
3771 if (pc->immd)
3772 FREE(pc->immd);
3773 if (pc->param)
3774 FREE(pc->param);
3775 if (pc->result)
3776 FREE(pc->result);
3777 if (pc->attr)
3778 FREE(pc->attr);
3779 if (pc->temp)
3780 FREE(pc->temp);
3781 if (pc->insn_pos)
3782 FREE(pc->insn_pos);
3783
3784 FREE(pc);
3785 }
3786
3787 static INLINE uint32_t
3788 nv50_map_gs_output_prim(unsigned pprim)
3789 {
3790 switch (pprim) {
3791 case PIPE_PRIM_POINTS:
3792 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_POINTS;
3793 case PIPE_PRIM_LINE_STRIP:
3794 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP;
3795 case PIPE_PRIM_TRIANGLE_STRIP:
3796 return NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP;
3797 default:
3798 NOUVEAU_ERR("invalid GS_OUTPUT_PRIMITIVE: %u\n", pprim);
3799 abort();
3800 return 0;
3801 }
3802 }
3803
3804 static boolean
3805 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3806 {
3807 int i, c;
3808 unsigned rtype[2] = { P_ATTR, P_RESULT };
3809
3810 pc->p = p;
3811 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3812 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3813 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3814 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3815 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3816 assert(pc->addr_nr <= 2);
3817
3818 p->cfg.high_temp = 4;
3819
3820 p->cfg.two_side[0].hw = 0x40;
3821 p->cfg.two_side[1].hw = 0x40;
3822
3823 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3824
3825 for (i = 0; i < p->info.num_properties; ++i) {
3826 unsigned *data = &p->info.properties[i].data[0];
3827
3828 switch (p->info.properties[i].name) {
3829 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
3830 p->cfg.prim_type = nv50_map_gs_output_prim(data[0]);
3831 break;
3832 case TGSI_PROPERTY_GS_MAX_VERTICES:
3833 p->cfg.vert_count = data[0];
3834 break;
3835 default:
3836 break;
3837 }
3838 }
3839
3840 switch (p->type) {
3841 case PIPE_SHADER_VERTEX:
3842 p->cfg.psiz = 0x40;
3843 p->cfg.clpd = 0x40;
3844 p->cfg.out_nr = pc->result_nr;
3845 break;
3846 case PIPE_SHADER_GEOMETRY:
3847 assert(p->cfg.prim_type);
3848 assert(p->cfg.vert_count);
3849
3850 p->cfg.psiz = 0x80;
3851 p->cfg.clpd = 0x80;
3852 p->cfg.out_nr = pc->result_nr;
3853 p->cfg.in_nr = pc->attr_nr;
3854
3855 p->cfg.two_side[0].hw = 0x80;
3856 p->cfg.two_side[1].hw = 0x80;
3857 break;
3858 case PIPE_SHADER_FRAGMENT:
3859 rtype[0] = rtype[1] = P_TEMP;
3860
3861 p->cfg.regs[0] = 0x01000004;
3862 p->cfg.in_nr = pc->attr_nr;
3863
3864 if (p->info.writes_z) {
3865 p->cfg.regs[2] |= 0x00000100;
3866 p->cfg.regs[3] |= 0x00000011;
3867 }
3868 if (p->info.uses_kill)
3869 p->cfg.regs[2] |= 0x00100000;
3870 break;
3871 }
3872
3873 if (pc->temp_nr) {
3874 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3875 if (!pc->temp)
3876 return FALSE;
3877
3878 for (i = 0; i < pc->temp_nr * 4; ++i)
3879 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3880 }
3881
3882 if (pc->attr_nr) {
3883 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3884 if (!pc->attr)
3885 return FALSE;
3886
3887 for (i = 0; i < pc->attr_nr * 4; ++i)
3888 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3889 }
3890
3891 if (pc->result_nr) {
3892 unsigned nr = pc->result_nr * 4;
3893
3894 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3895 if (!pc->result)
3896 return FALSE;
3897
3898 for (i = 0; i < nr; ++i)
3899 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3900 }
3901
3902 if (pc->param_nr) {
3903 int rid = 0;
3904
3905 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3906 if (!pc->param)
3907 return FALSE;
3908
3909 for (i = 0; i < pc->param_nr; ++i)
3910 for (c = 0; c < 4; ++c, ++rid)
3911 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3912 }
3913
3914 if (pc->addr_nr) {
3915 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3916 if (!pc->addr)
3917 return FALSE;
3918 }
3919 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3920 ctor_reg(&pc->r_addr[i], P_ADDR, -1, i + 1);
3921
3922 return TRUE;
3923 }
3924
3925 static void
3926 nv50_program_fixup_insns(struct nv50_pc *pc)
3927 {
3928 struct nv50_program_exec *e, **bra_list;
3929 unsigned i, n, pos;
3930
3931 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3932
3933 /* Collect branch instructions, we need to adjust their offsets
3934 * when converting 32 bit instructions to 64 bit ones
3935 */
3936 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3937 if (e->param.index >= 0 && !e->param.mask)
3938 bra_list[n++] = e;
3939
3940 /* Make sure we don't have any single 32 bit instructions. */
3941 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3942 pos += is_long(e) ? 2 : 1;
3943
3944 if ((pos & 1) && (!e->next || is_long(e->next))) {
3945 for (i = 0; i < n; ++i)
3946 if (bra_list[i]->param.index >= pos)
3947 bra_list[i]->param.index += 1;
3948 for (i = 0; i < pc->insn_nr; ++i)
3949 if (pc->insn_pos[i] >= pos)
3950 pc->insn_pos[i] += 1;
3951 convert_to_long(pc, e);
3952 ++pos;
3953 }
3954 }
3955
3956 FREE(bra_list);
3957
3958 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
3959 return;
3960
3961 /* fill in CALL offsets */
3962 for (e = pc->p->exec_head; e; e = e->next) {
3963 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
3964 e->param.index = pc->insn_pos[e->param.index];
3965 }
3966 }
3967
3968 static boolean
3969 nv50_program_tx(struct nv50_program *p)
3970 {
3971 struct tgsi_parse_context parse;
3972 struct nv50_pc *pc;
3973 boolean ret;
3974
3975 pc = CALLOC_STRUCT(nv50_pc);
3976 if (!pc)
3977 return FALSE;
3978
3979 ret = ctor_nv50_pc(pc, p);
3980 if (ret == FALSE)
3981 goto out_cleanup;
3982
3983 ret = nv50_program_tx_prep(pc);
3984 if (ret == FALSE)
3985 goto out_cleanup;
3986
3987 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
3988
3989 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3990 while (!tgsi_parse_end_of_tokens(&parse)) {
3991 const union tgsi_full_token *tok = &parse.FullToken;
3992
3993 /* previously allow32 was FALSE for first & last instruction */
3994 pc->allow32 = TRUE;
3995
3996 tgsi_parse_token(&parse);
3997
3998 switch (tok->Token.Type) {
3999 case TGSI_TOKEN_TYPE_INSTRUCTION:
4000 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
4001 ++pc->insn_cur;
4002 ret = nv50_tgsi_insn(pc, tok);
4003 if (ret == FALSE)
4004 goto out_err;
4005 break;
4006 default:
4007 break;
4008 }
4009 }
4010
4011 nv50_program_fixup_insns(pc);
4012
4013 p->param_nr = pc->param_nr * 4;
4014 p->immd_nr = pc->immd_nr * 4;
4015 p->immd = pc->immd_buf;
4016
4017 out_err:
4018 tgsi_parse_free(&parse);
4019
4020 out_cleanup:
4021 free_nv50_pc(pc);
4022 return ret;
4023 }
4024
4025 static void
4026 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
4027 {
4028 if (nv50_program_tx(p) == FALSE)
4029 assert(0);
4030 p->translated = TRUE;
4031 }
4032
4033 static void
4034 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
4035 unsigned start, unsigned count, unsigned cbuf)
4036 {
4037 struct nouveau_channel *chan = nv50->screen->base.channel;
4038 struct nouveau_grobj *tesla = nv50->screen->tesla;
4039
4040 while (count) {
4041 unsigned nr = count > 2047 ? 2047 : count;
4042
4043 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
4044 OUT_RING (chan, (cbuf << 0) | (start << 8));
4045 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
4046 OUT_RINGp (chan, map, nr);
4047
4048 map += nr;
4049 start += nr;
4050 count -= nr;
4051 }
4052 }
4053
4054 static void
4055 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
4056 {
4057 struct pipe_screen *pscreen = nv50->pipe.screen;
4058
4059 if (!p->data[0] && p->immd_nr) {
4060 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
4061
4062 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
4063 while (heap->next && heap->size < p->immd_nr) {
4064 struct nv50_program *evict = heap->next->priv;
4065 nouveau_resource_free(&evict->data[0]);
4066 }
4067
4068 if (nouveau_resource_alloc(heap, p->immd_nr, p,
4069 &p->data[0]))
4070 assert(0);
4071 }
4072
4073 /* immediates only need to be uploaded again when freed */
4074 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
4075 p->immd_nr, NV50_CB_PMISC);
4076 }
4077
4078 assert(p->param_nr <= 512);
4079
4080 if (p->param_nr) {
4081 unsigned cb;
4082 uint32_t *map = pipe_buffer_map(pscreen,
4083 nv50->constbuf[p->type],
4084 PIPE_BUFFER_USAGE_CPU_READ);
4085 switch (p->type) {
4086 case PIPE_SHADER_GEOMETRY: cb = NV50_CB_PGP; break;
4087 case PIPE_SHADER_FRAGMENT: cb = NV50_CB_PFP; break;
4088 default:
4089 cb = NV50_CB_PVP;
4090 assert(p->type == PIPE_SHADER_VERTEX);
4091 break;
4092 }
4093
4094 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
4095 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
4096 }
4097 }
4098
4099 static void
4100 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
4101 {
4102 struct nouveau_channel *chan = nv50->screen->base.channel;
4103 struct nv50_program_exec *e;
4104 uint32_t *up, i;
4105 boolean upload = FALSE;
4106
4107 if (!p->bo) {
4108 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
4109 p->exec_size * 4, &p->bo);
4110 upload = TRUE;
4111 }
4112
4113 if (p->data[0] && p->data[0]->start != p->data_start[0])
4114 upload = TRUE;
4115
4116 if (!upload)
4117 return;
4118
4119 up = MALLOC(p->exec_size * 4);
4120
4121 for (i = 0, e = p->exec_head; e; e = e->next) {
4122 unsigned ei, ci, bs;
4123
4124 if (e->param.index >= 0 && e->param.mask) {
4125 bs = (e->inst[1] >> 22) & 0x07;
4126 assert(bs < 2);
4127 ei = e->param.shift >> 5;
4128 ci = e->param.index;
4129 if (bs == 0)
4130 ci += p->data[bs]->start;
4131
4132 e->inst[ei] &= ~e->param.mask;
4133 e->inst[ei] |= (ci << e->param.shift);
4134 } else
4135 if (e->param.index >= 0) {
4136 /* zero mask means param is a jump/branch offset */
4137 assert(!(e->param.index & 1));
4138 /* seem to be 8 byte steps */
4139 ei = (e->param.index >> 1) + 0 /* START_ID */;
4140
4141 e->inst[0] &= 0xf0000fff;
4142 e->inst[0] |= ei << 12;
4143 }
4144
4145 up[i++] = e->inst[0];
4146 if (is_long(e))
4147 up[i++] = e->inst[1];
4148 }
4149 assert(i == p->exec_size);
4150
4151 if (p->data[0])
4152 p->data_start[0] = p->data[0]->start;
4153
4154 #ifdef NV50_PROGRAM_DUMP
4155 NOUVEAU_ERR("-------\n");
4156 for (e = p->exec_head; e; e = e->next) {
4157 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
4158 if (is_long(e))
4159 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
4160 }
4161 #endif
4162 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
4163 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
4164 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
4165 0, 0, p->exec_size * 4, 1, 1);
4166
4167 FREE(up);
4168 }
4169
4170 void
4171 nv50_vertprog_validate(struct nv50_context *nv50)
4172 {
4173 struct nouveau_grobj *tesla = nv50->screen->tesla;
4174 struct nv50_program *p = nv50->vertprog;
4175 struct nouveau_stateobj *so;
4176
4177 if (!p->translated) {
4178 nv50_program_validate(nv50, p);
4179 if (!p->translated)
4180 assert(0);
4181 }
4182
4183 nv50_program_validate_data(nv50, p);
4184 nv50_program_validate_code(nv50, p);
4185
4186 so = so_new(5, 7, 2);
4187 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
4188 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4189 NOUVEAU_BO_HIGH, 0, 0);
4190 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4191 NOUVEAU_BO_LOW, 0, 0);
4192 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
4193 so_data (so, p->cfg.attr[0]);
4194 so_data (so, p->cfg.attr[1]);
4195 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
4196 so_data (so, p->cfg.high_result);
4197 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_TEMP, 1);
4198 so_data (so, p->cfg.high_temp);
4199 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
4200 so_data (so, 0); /* program start offset */
4201 so_ref(so, &nv50->state.vertprog);
4202 so_ref(NULL, &so);
4203 }
4204
4205 void
4206 nv50_fragprog_validate(struct nv50_context *nv50)
4207 {
4208 struct nouveau_grobj *tesla = nv50->screen->tesla;
4209 struct nv50_program *p = nv50->fragprog;
4210 struct nouveau_stateobj *so;
4211
4212 if (!p->translated) {
4213 nv50_program_validate(nv50, p);
4214 if (!p->translated)
4215 assert(0);
4216 }
4217
4218 nv50_program_validate_data(nv50, p);
4219 nv50_program_validate_code(nv50, p);
4220
4221 so = so_new(6, 7, 2);
4222 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
4223 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4224 NOUVEAU_BO_HIGH, 0, 0);
4225 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4226 NOUVEAU_BO_LOW, 0, 0);
4227 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
4228 so_data (so, p->cfg.high_temp);
4229 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
4230 so_data (so, p->cfg.high_result);
4231 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
4232 so_data (so, p->cfg.regs[2]);
4233 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
4234 so_data (so, p->cfg.regs[3]);
4235 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
4236 so_data (so, 0); /* program start offset */
4237 so_ref(so, &nv50->state.fragprog);
4238 so_ref(NULL, &so);
4239 }
4240
4241 void
4242 nv50_geomprog_validate(struct nv50_context *nv50)
4243 {
4244 struct nouveau_grobj *tesla = nv50->screen->tesla;
4245 struct nv50_program *p = nv50->geomprog;
4246 struct nouveau_stateobj *so;
4247
4248 if (!p->translated) {
4249 nv50_program_validate(nv50, p);
4250 if (!p->translated)
4251 assert(0);
4252 }
4253
4254 nv50_program_validate_data(nv50, p);
4255 nv50_program_validate_code(nv50, p);
4256
4257 so = so_new(6, 7, 2);
4258 so_method(so, tesla, NV50TCL_GP_ADDRESS_HIGH, 2);
4259 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4260 NOUVEAU_BO_HIGH, 0, 0);
4261 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4262 NOUVEAU_BO_LOW, 0, 0);
4263 so_method(so, tesla, NV50TCL_GP_REG_ALLOC_TEMP, 1);
4264 so_data (so, p->cfg.high_temp);
4265 so_method(so, tesla, NV50TCL_GP_REG_ALLOC_RESULT, 1);
4266 so_data (so, p->cfg.high_result);
4267 so_method(so, tesla, NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE, 1);
4268 so_data (so, p->cfg.prim_type);
4269 so_method(so, tesla, NV50TCL_GP_VERTEX_OUTPUT_COUNT, 1);
4270 so_data (so, p->cfg.vert_count);
4271 so_method(so, tesla, NV50TCL_GP_START_ID, 1);
4272 so_data (so, 0);
4273 so_ref(so, &nv50->state.geomprog);
4274 so_ref(NULL, &so);
4275 }
4276
4277 static uint32_t
4278 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
4279 {
4280 struct nv50_program *vp;
4281 struct nv50_program *fp = nv50->fragprog;
4282 unsigned i, c, m = base;
4283 uint32_t origin = 0x00000010;
4284
4285 vp = nv50->geomprog ? nv50->geomprog : nv50->vertprog;
4286
4287 /* XXX: this might not work correctly in all cases yet - we'll
4288 * just assume that an FP generic input that is not written in
4289 * the VP is PointCoord.
4290 */
4291 memset(pntc, 0, 8 * sizeof(uint32_t));
4292
4293 for (i = 0; i < fp->cfg.in_nr; i++) {
4294 unsigned j, n = popcnt4(fp->cfg.in[i].mask);
4295
4296 if (fp->cfg.in[i].sn != TGSI_SEMANTIC_GENERIC) {
4297 m += n;
4298 continue;
4299 }
4300
4301 for (j = 0; j < vp->cfg.out_nr; ++j)
4302 if (vp->cfg.out[j].sn == fp->cfg.in[i].sn &&
4303 vp->cfg.out[j].si == fp->cfg.in[i].si)
4304 break;
4305
4306 if (j < vp->cfg.out_nr) {
4307 ubyte mode = nv50->rasterizer->pipe.sprite_coord_mode[
4308 vp->cfg.out[j].si];
4309
4310 if (mode == PIPE_SPRITE_COORD_NONE) {
4311 m += n;
4312 continue;
4313 } else
4314 if (mode == PIPE_SPRITE_COORD_LOWER_LEFT)
4315 origin = 0;
4316 }
4317
4318 /* this is either PointCoord or replaced by sprite coords */
4319 for (c = 0; c < 4; c++) {
4320 if (!(fp->cfg.in[i].mask & (1 << c)))
4321 continue;
4322 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
4323 ++m;
4324 }
4325 }
4326 return origin;
4327 }
4328
4329 static int
4330 nv50_vec4_map(uint32_t *map32, int mid, uint8_t zval, uint32_t lin[4],
4331 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
4332 {
4333 int c;
4334 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
4335 uint8_t *map = (uint8_t *)map32;
4336
4337 for (c = 0; c < 4; ++c) {
4338 if (mf & 1) {
4339 if (fpi->linear == TRUE)
4340 lin[mid / 32] |= 1 << (mid % 32);
4341 if (mv & 1)
4342 map[mid] = oid;
4343 else
4344 map[mid] = (c == 3) ? (zval + 1) : zval;
4345 ++mid;
4346 }
4347
4348 oid += mv & 1;
4349 mf >>= 1;
4350 mv >>= 1;
4351 }
4352
4353 return mid;
4354 }
4355
4356 void
4357 nv50_fp_linkage_validate(struct nv50_context *nv50)
4358 {
4359 struct nouveau_grobj *tesla = nv50->screen->tesla;
4360 struct nv50_program *vp = nv50->vertprog;
4361 struct nv50_program *fp = nv50->fragprog;
4362 struct nouveau_stateobj *so;
4363 struct nv50_sreg4 dummy;
4364 int i, n, c, m = 0;
4365 uint32_t map[16], lin[4], reg[5], pcrd[8];
4366 uint8_t zval = 0x40;
4367
4368 if (nv50->geomprog) {
4369 vp = nv50->geomprog;
4370 zval = 0x80;
4371 }
4372 memset(map, 0, sizeof(map));
4373 memset(lin, 0, sizeof(lin));
4374
4375 reg[1] = 0x00000004; /* low and high clip distance map ids */
4376 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
4377 reg[3] = 0x00000000; /* point size map id & enable */
4378 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
4379 reg[4] = fp->cfg.regs[1]; /* interpolant info */
4380
4381 dummy.linear = FALSE;
4382 dummy.mask = 0xf; /* map all components of HPOS */
4383 m = nv50_vec4_map(map, m, zval, lin, &dummy, &vp->cfg.out[0]);
4384
4385 dummy.mask = 0x0;
4386
4387 if (vp->cfg.clpd < 0x40) {
4388 for (c = 0; c < vp->cfg.clpd_nr; ++c) {
4389 map[m / 4] |= (vp->cfg.clpd + c) << ((m % 4) * 8);
4390 ++m;
4391 }
4392 reg[1] = (m << 8);
4393 }
4394
4395 reg[0] |= m << 8; /* adjust BFC0 id */
4396
4397 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
4398 if (nv50->rasterizer->pipe.light_twoside) {
4399 struct nv50_sreg4 *vpo = &vp->cfg.two_side[0];
4400 struct nv50_sreg4 *fpi = &fp->cfg.two_side[0];
4401
4402 m = nv50_vec4_map(map, m, zval, lin, &fpi[0], &vpo[0]);
4403 m = nv50_vec4_map(map, m, zval, lin, &fpi[1], &vpo[1]);
4404 }
4405
4406 reg[0] += m - 4; /* adjust FFC0 id */
4407 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
4408
4409 for (i = 0; i < fp->cfg.in_nr; i++) {
4410 /* maybe even remove these from cfg.io */
4411 if (fp->cfg.in[i].sn == TGSI_SEMANTIC_POSITION ||
4412 fp->cfg.in[i].sn == TGSI_SEMANTIC_FACE)
4413 continue;
4414
4415 for (n = 0; n < vp->cfg.out_nr; ++n)
4416 if (vp->cfg.out[n].sn == fp->cfg.in[i].sn &&
4417 vp->cfg.out[n].si == fp->cfg.in[i].si)
4418 break;
4419
4420 m = nv50_vec4_map(map, m, zval, lin, &fp->cfg.in[i],
4421 (n < vp->cfg.out_nr) ?
4422 &vp->cfg.out[n] : &dummy);
4423 }
4424
4425 if (nv50->rasterizer->pipe.point_size_per_vertex) {
4426 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
4427 reg[3] = (m++ << 4) | 1;
4428 }
4429
4430 /* now fill the stateobj (at most 28 so_data) */
4431 so = so_new(8, 56, 0);
4432
4433 n = (m + 3) / 4;
4434 assert(m <= 32);
4435 if (vp->type == PIPE_SHADER_GEOMETRY) {
4436 so_method(so, tesla, NV50TCL_GP_RESULT_MAP_SIZE, 1);
4437 so_data (so, m);
4438 so_method(so, tesla, NV50TCL_GP_RESULT_MAP(0), n);
4439 so_datap (so, map, n);
4440 } else {
4441 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4442 so_data (so, m);
4443 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
4444 so_datap (so, map, n);
4445 }
4446
4447 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
4448 so_datap (so, reg, 4);
4449
4450 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
4451 so_data (so, reg[4]);
4452
4453 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
4454 so_datap (so, lin, 4);
4455
4456 if (nv50->rasterizer->pipe.point_sprite) {
4457 so_method(so, tesla, NV50TCL_POINT_SPRITE_CTRL, 1);
4458 so_data (so,
4459 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff));
4460
4461 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
4462 so_datap (so, pcrd, 8);
4463 }
4464
4465 so_method(so, tesla, NV50TCL_GP_ENABLE, 1);
4466 so_data (so, (vp->type == PIPE_SHADER_GEOMETRY) ? 1 : 0);
4467
4468 so_ref(so, &nv50->state.fp_linkage);
4469 so_ref(NULL, &so);
4470 }
4471
4472 static int
4473 construct_vp_gp_mapping(uint32_t *map32, int m,
4474 struct nv50_program *vp, struct nv50_program *gp)
4475 {
4476 uint8_t *map = (uint8_t *)map32;
4477 int i, j, c;
4478
4479 for (i = 0; i < gp->cfg.in_nr; ++i) {
4480 uint8_t oid, mv = 0, mg = gp->cfg.in[i].mask;
4481
4482 for (j = 0; j < vp->cfg.out_nr; ++j) {
4483 if (vp->cfg.out[j].sn == gp->cfg.in[i].sn &&
4484 vp->cfg.out[j].si == gp->cfg.in[i].si) {
4485 mv = vp->cfg.out[j].mask;
4486 oid = vp->cfg.out[j].hw;
4487 break;
4488 }
4489 }
4490
4491 for (c = 0; c < 4; ++c, mv >>= 1, mg >>= 1) {
4492 if (mg & mv & 1)
4493 map[m++] = oid;
4494 else
4495 if (mg & 1)
4496 map[m++] = (c == 3) ? 0x41 : 0x40;
4497 oid += mv & 1;
4498 }
4499 }
4500 return m;
4501 }
4502
4503 void
4504 nv50_gp_linkage_validate(struct nv50_context *nv50)
4505 {
4506 struct nouveau_grobj *tesla = nv50->screen->tesla;
4507 struct nouveau_stateobj *so;
4508 struct nv50_program *vp = nv50->vertprog;
4509 struct nv50_program *gp = nv50->geomprog;
4510 uint32_t map[16];
4511 int m = 0;
4512
4513 if (!gp) {
4514 so_ref(NULL, &nv50->state.gp_linkage);
4515 return;
4516 }
4517 memset(map, 0, sizeof(map));
4518
4519 m = construct_vp_gp_mapping(map, m, vp, gp);
4520
4521 so = so_new(2, 14, 0);
4522
4523 assert(m <= 32);
4524 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4525 so_data (so, m);
4526
4527 m = (m + 3) / 4;
4528 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), m);
4529 so_datap (so, map, m);
4530
4531 so_ref(so, &nv50->state.gp_linkage);
4532 so_ref(NULL, &so);
4533 }
4534
4535 void
4536 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
4537 {
4538 while (p->exec_head) {
4539 struct nv50_program_exec *e = p->exec_head;
4540
4541 p->exec_head = e->next;
4542 FREE(e);
4543 }
4544 p->exec_tail = NULL;
4545 p->exec_size = 0;
4546
4547 nouveau_bo_ref(NULL, &p->bo);
4548
4549 nouveau_resource_free(&p->data[0]);
4550
4551 p->translated = 0;
4552 }