2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
32 #include "nv50_context.h"
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
40 /* ARL - gallium craps itself on progs/vp/arl.txt
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
93 int rhw
; /* result hw for FP outputs, or interpolant index */
94 int acc
; /* instruction where this reg is last read (first insn == 1) */
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
100 #define NV50_MOD_SAT 4
101 #define NV50_MOD_I32 8
103 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
105 /* STACK: Conditionals and loops have to use the (per warp) stack.
106 * Stack entries consist of an entry type (divergent path, join at),
107 * a mask indicating the active threads of the warp, and an address.
108 * MPs can store 12 stack entries internally, if we need more (and
109 * we probably do), we have to create a stack buffer in VRAM.
111 /* impose low limits for now */
112 #define NV50_MAX_COND_NESTING 4
113 #define NV50_MAX_LOOP_NESTING 3
115 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
118 struct nv50_program
*p
;
121 struct nv50_reg
*r_temp
[NV50_SU_MAX_TEMP
];
122 struct nv50_reg r_addr
[NV50_SU_MAX_ADDR
];
125 struct nv50_reg
*temp
;
127 struct nv50_reg
*attr
;
129 struct nv50_reg
*result
;
131 struct nv50_reg
*param
;
133 struct nv50_reg
*immd
;
136 struct nv50_reg
**addr
;
138 uint8_t addr_alloc
; /* set bit indicates used for TGSI_FILE_ADDRESS */
140 struct nv50_reg
*temp_temp
[16];
141 struct nv50_program_exec
*temp_temp_exec
[16];
142 unsigned temp_temp_nr
;
144 /* broadcast and destination replacement regs */
145 struct nv50_reg
*r_brdc
;
146 struct nv50_reg
*r_dst
[4];
148 struct nv50_reg reg_instances
[16];
149 unsigned reg_instance_nr
;
151 unsigned interp_mode
[32];
152 /* perspective interpolation registers */
153 struct nv50_reg
*iv_p
;
154 struct nv50_reg
*iv_c
;
156 struct nv50_program_exec
*if_insn
[NV50_MAX_COND_NESTING
];
157 struct nv50_program_exec
*if_join
[NV50_MAX_COND_NESTING
];
158 struct nv50_program_exec
*loop_brka
[NV50_MAX_LOOP_NESTING
];
159 int if_lvl
, loop_lvl
;
160 unsigned loop_pos
[NV50_MAX_LOOP_NESTING
];
162 unsigned *insn_pos
; /* actual program offset of each TGSI insn */
163 boolean in_subroutine
;
165 /* current instruction and total number of insns */
171 uint8_t edgeflag_out
;
175 ctor_reg(struct nv50_reg
*reg
, unsigned type
, int index
, int hw
)
185 static INLINE
unsigned
186 popcnt4(uint32_t val
)
188 static const unsigned cnt
[16]
189 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
190 return cnt
[val
& 0xf];
194 terminate_mbb(struct nv50_pc
*pc
)
198 /* remove records of temporary address register values */
199 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
200 pc
->r_addr
[i
].rhw
= -1;
204 alloc_reg(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
208 if (reg
->type
== P_RESULT
) {
209 if (pc
->p
->cfg
.high_result
< (reg
->hw
+ 1))
210 pc
->p
->cfg
.high_result
= reg
->hw
+ 1;
213 if (reg
->type
!= P_TEMP
)
217 /*XXX: do this here too to catch FP temp-as-attr usage..
218 * not clean, but works */
219 if (pc
->p
->cfg
.high_temp
< (reg
->hw
+ 1))
220 pc
->p
->cfg
.high_temp
= reg
->hw
+ 1;
224 if (reg
->rhw
!= -1) {
225 /* try to allocate temporary with index rhw first */
226 if (!(pc
->r_temp
[reg
->rhw
])) {
227 pc
->r_temp
[reg
->rhw
] = reg
;
229 if (pc
->p
->cfg
.high_temp
< (reg
->rhw
+ 1))
230 pc
->p
->cfg
.high_temp
= reg
->rhw
+ 1;
233 /* make sure we don't get things like $r0 needs to go
234 * in $r1 and $r1 in $r0
236 i
= pc
->result_nr
* 4;
239 for (; i
< NV50_SU_MAX_TEMP
; i
++) {
240 if (!(pc
->r_temp
[i
])) {
243 if (pc
->p
->cfg
.high_temp
< (i
+ 1))
244 pc
->p
->cfg
.high_temp
= i
+ 1;
249 NOUVEAU_ERR("out of registers\n");
253 static INLINE
struct nv50_reg
*
254 reg_instance(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
258 assert(pc
->reg_instance_nr
< 16);
259 ri
= &pc
->reg_instances
[pc
->reg_instance_nr
++];
268 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
269 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
270 * lest we risk temp_temps overwriting regs alloc'd "later".
272 static struct nv50_reg
*
273 alloc_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
)
278 if (dst
&& dst
->type
== P_TEMP
&& dst
->hw
== -1)
281 for (i
= 0; i
< NV50_SU_MAX_TEMP
; i
++) {
282 if (!pc
->r_temp
[i
]) {
283 r
= MALLOC_STRUCT(nv50_reg
);
284 ctor_reg(r
, P_TEMP
, -1, i
);
290 NOUVEAU_ERR("out of registers\n");
295 /* release the hardware resource held by r */
297 release_hw(struct nv50_pc
*pc
, struct nv50_reg
*r
)
299 assert(r
->type
== P_TEMP
);
303 assert(pc
->r_temp
[r
->hw
] == r
);
304 pc
->r_temp
[r
->hw
] = NULL
;
312 free_temp(struct nv50_pc
*pc
, struct nv50_reg
*r
)
314 if (r
->index
== -1) {
317 FREE(pc
->r_temp
[hw
]);
318 pc
->r_temp
[hw
] = NULL
;
323 alloc_temp4(struct nv50_pc
*pc
, struct nv50_reg
*dst
[4], int idx
)
327 if ((idx
+ 4) >= NV50_SU_MAX_TEMP
)
330 if (pc
->r_temp
[idx
] || pc
->r_temp
[idx
+ 1] ||
331 pc
->r_temp
[idx
+ 2] || pc
->r_temp
[idx
+ 3])
332 return alloc_temp4(pc
, dst
, idx
+ 4);
334 for (i
= 0; i
< 4; i
++) {
335 dst
[i
] = MALLOC_STRUCT(nv50_reg
);
336 ctor_reg(dst
[i
], P_TEMP
, -1, idx
+ i
);
337 pc
->r_temp
[idx
+ i
] = dst
[i
];
344 free_temp4(struct nv50_pc
*pc
, struct nv50_reg
*reg
[4])
348 for (i
= 0; i
< 4; i
++)
349 free_temp(pc
, reg
[i
]);
352 static struct nv50_reg
*
353 temp_temp(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
355 if (pc
->temp_temp_nr
>= 16)
358 pc
->temp_temp
[pc
->temp_temp_nr
] = alloc_temp(pc
, NULL
);
359 pc
->temp_temp_exec
[pc
->temp_temp_nr
] = e
;
360 return pc
->temp_temp
[pc
->temp_temp_nr
++];
363 /* This *must* be called for all nv50_program_exec that have been
364 * given as argument to temp_temp, or the temps will be leaked !
367 kill_temp_temp(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
371 for (i
= 0; i
< pc
->temp_temp_nr
; i
++)
372 if (pc
->temp_temp_exec
[i
] == e
)
373 free_temp(pc
, pc
->temp_temp
[i
]);
375 pc
->temp_temp_nr
= 0;
379 ctor_immd_4u32(struct nv50_pc
*pc
,
380 uint32_t x
, uint32_t y
, uint32_t z
, uint32_t w
)
382 unsigned size
= pc
->immd_nr
* 4 * sizeof(uint32_t);
384 pc
->immd_buf
= REALLOC(pc
->immd_buf
, size
, size
+ 4 * sizeof(uint32_t));
386 pc
->immd_buf
[(pc
->immd_nr
* 4) + 0] = x
;
387 pc
->immd_buf
[(pc
->immd_nr
* 4) + 1] = y
;
388 pc
->immd_buf
[(pc
->immd_nr
* 4) + 2] = z
;
389 pc
->immd_buf
[(pc
->immd_nr
* 4) + 3] = w
;
391 return pc
->immd_nr
++;
395 ctor_immd_4f32(struct nv50_pc
*pc
, float x
, float y
, float z
, float w
)
397 return ctor_immd_4u32(pc
, fui(x
), fui(y
), fui(z
), fui(w
));
400 static struct nv50_reg
*
401 alloc_immd(struct nv50_pc
*pc
, float f
)
403 struct nv50_reg
*r
= MALLOC_STRUCT(nv50_reg
);
406 for (hw
= 0; hw
< pc
->immd_nr
* 4; hw
++)
407 if (pc
->immd_buf
[hw
] == fui(f
))
410 if (hw
== pc
->immd_nr
* 4)
411 hw
= ctor_immd_4f32(pc
, f
, -f
, 0.5 * f
, 0) * 4;
413 ctor_reg(r
, P_IMMD
, -1, hw
);
417 static struct nv50_program_exec
*
418 exec(struct nv50_pc
*pc
)
420 struct nv50_program_exec
*e
= CALLOC_STRUCT(nv50_program_exec
);
427 emit(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
429 struct nv50_program
*p
= pc
->p
;
432 p
->exec_tail
->next
= e
;
436 p
->exec_size
+= (e
->inst
[0] & 1) ? 2 : 1;
438 kill_temp_temp(pc
, e
);
441 static INLINE
void set_long(struct nv50_pc
*, struct nv50_program_exec
*);
444 is_long(struct nv50_program_exec
*e
)
452 is_immd(struct nv50_program_exec
*e
)
454 if (is_long(e
) && (e
->inst
[1] & 3) == 3)
460 is_join(struct nv50_program_exec
*e
)
462 if (is_long(e
) && (e
->inst
[1] & 3) == 2)
468 set_pred(struct nv50_pc
*pc
, unsigned pred
, unsigned idx
,
469 struct nv50_program_exec
*e
)
473 e
->inst
[1] &= ~((0x1f << 7) | (0x3 << 12));
474 e
->inst
[1] |= (pred
<< 7) | (idx
<< 12);
478 set_pred_wr(struct nv50_pc
*pc
, unsigned on
, unsigned idx
,
479 struct nv50_program_exec
*e
)
482 e
->inst
[1] &= ~((0x3 << 4) | (1 << 6));
483 e
->inst
[1] |= (idx
<< 4) | (on
<< 6);
487 set_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
493 set_pred(pc
, 0xf, 0, e
);
494 set_pred_wr(pc
, 0, 0, e
);
498 set_dst(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_program_exec
*e
)
500 if (dst
->type
== P_RESULT
) {
502 e
->inst
[1] |= 0x00000008;
508 e
->inst
[0] |= (dst
->hw
<< 2);
512 set_immd(struct nv50_pc
*pc
, struct nv50_reg
*imm
, struct nv50_program_exec
*e
)
515 /* XXX: can't be predicated - bits overlap; cases where both
516 * are required should be avoided by using pc->allow32 */
517 set_pred(pc
, 0, 0, e
);
518 set_pred_wr(pc
, 0, 0, e
);
520 e
->inst
[1] |= 0x00000002 | 0x00000001;
521 e
->inst
[0] |= (pc
->immd_buf
[imm
->hw
] & 0x3f) << 16;
522 e
->inst
[1] |= (pc
->immd_buf
[imm
->hw
] >> 6) << 2;
526 set_addr(struct nv50_program_exec
*e
, struct nv50_reg
*a
)
528 assert(!(e
->inst
[0] & 0x0c000000));
529 assert(!(e
->inst
[1] & 0x00000004));
531 e
->inst
[0] |= (a
->hw
& 3) << 26;
532 e
->inst
[1] |= (a
->hw
>> 2) << 2;
536 emit_add_addr_imm(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
537 struct nv50_reg
*src0
, uint16_t src1_val
)
539 struct nv50_program_exec
*e
= exec(pc
);
541 e
->inst
[0] = 0xd0000000 | (src1_val
<< 9);
542 e
->inst
[1] = 0x20000000;
544 e
->inst
[0] |= dst
->hw
<< 2;
545 if (src0
) /* otherwise will add to $a0, which is always 0 */
551 static struct nv50_reg
*
552 alloc_addr(struct nv50_pc
*pc
, struct nv50_reg
*ref
)
554 struct nv50_reg
*a_tgsi
= NULL
, *a
= NULL
;
556 uint8_t avail
= ~pc
->addr_alloc
;
559 /* allocate for TGSI_FILE_ADDRESS */
563 if (pc
->r_addr
[i
].rhw
< 0 ||
564 pc
->r_addr
[i
].acc
!= pc
->insn_cur
) {
565 pc
->addr_alloc
|= (1 << i
);
567 pc
->r_addr
[i
].rhw
= -1;
568 pc
->r_addr
[i
].index
= i
;
569 return &pc
->r_addr
[i
];
577 /* Allocate and set an address reg so we can access 'ref'.
579 * If and r_addr->index will be -1 or the hw index the value
580 * value in rhw is relative to. If rhw < 0, the reg has not
581 * been initialized or is in use for TGSI_FILE_ADDRESS.
583 while (avail
) { /* only consider regs that are not TGSI */
587 if ((!a
|| a
->rhw
>= 0) && pc
->r_addr
[i
].rhw
< 0) {
588 /* prefer an usused reg with low hw index */
592 if (!a
&& pc
->r_addr
[i
].acc
!= pc
->insn_cur
)
595 if (ref
->hw
- pc
->r_addr
[i
].rhw
>= 128)
598 if ((ref
->acc
>= 0 && pc
->r_addr
[i
].index
< 0) ||
599 (ref
->acc
< 0 && pc
->r_addr
[i
].index
== ref
->index
)) {
600 pc
->r_addr
[i
].acc
= pc
->insn_cur
;
601 return &pc
->r_addr
[i
];
607 a_tgsi
= pc
->addr
[ref
->index
];
609 emit_add_addr_imm(pc
, a
, a_tgsi
, (ref
->hw
& ~0x7f) * 4);
611 a
->rhw
= ref
->hw
& ~0x7f;
612 a
->acc
= pc
->insn_cur
;
613 a
->index
= a_tgsi
? ref
->index
: -1;
617 #define INTERP_LINEAR 0
618 #define INTERP_FLAT 1
619 #define INTERP_PERSPECTIVE 2
620 #define INTERP_CENTROID 4
622 /* interpolant index has been stored in dst->rhw */
624 emit_interp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*iv
,
627 assert(dst
->rhw
!= -1);
628 struct nv50_program_exec
*e
= exec(pc
);
630 e
->inst
[0] |= 0x80000000;
632 e
->inst
[0] |= (dst
->rhw
<< 16);
634 if (mode
& INTERP_FLAT
) {
635 e
->inst
[0] |= (1 << 8);
637 if (mode
& INTERP_PERSPECTIVE
) {
638 e
->inst
[0] |= (1 << 25);
640 e
->inst
[0] |= (iv
->hw
<< 9);
643 if (mode
& INTERP_CENTROID
)
644 e
->inst
[0] |= (1 << 24);
651 set_data(struct nv50_pc
*pc
, struct nv50_reg
*src
, unsigned m
, unsigned s
,
652 struct nv50_program_exec
*e
)
656 e
->param
.index
= src
->hw
& 127;
658 e
->param
.mask
= m
<< (s
% 32);
661 set_addr(e
, alloc_addr(pc
, src
));
664 assert(src
->type
== P_CONST
);
665 set_addr(e
, pc
->addr
[src
->index
]);
668 e
->inst
[1] |= (((src
->type
== P_IMMD
) ? 0 : 1) << 22);
671 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
673 emit_mov(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
675 struct nv50_program_exec
*e
= exec(pc
);
677 e
->inst
[0] = 0x10000000;
683 if (!is_long(e
) && src
->type
== P_IMMD
) {
684 set_immd(pc
, src
, e
);
685 /*XXX: 32-bit, but steals part of "half" reg space - need to
686 * catch and handle this case if/when we do half-regs
689 if (src
->type
== P_IMMD
|| src
->type
== P_CONST
) {
691 set_data(pc
, src
, 0x7f, 9, e
);
692 e
->inst
[1] |= 0x20000000; /* mov from c[] */
694 if (src
->type
== P_ATTR
) {
696 e
->inst
[1] |= 0x00200000;
702 e
->inst
[0] |= (src
->hw
<< 9);
705 if (is_long(e
) && !is_immd(e
)) {
706 e
->inst
[1] |= 0x04000000; /* 32-bit */
707 e
->inst
[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
708 if (!(e
->inst
[1] & 0x20000000))
709 e
->inst
[1] |= 0x00030000; /* lane mask 2:3 */
711 e
->inst
[0] |= 0x00008000;
717 emit_mov_immdval(struct nv50_pc
*pc
, struct nv50_reg
*dst
, float f
)
719 struct nv50_reg
*imm
= alloc_immd(pc
, f
);
720 emit_mov(pc
, dst
, imm
);
724 /* Assign the hw of the discarded temporary register src
725 * to the tgsi register dst and free src.
728 assimilate_temp(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
730 assert(src
->index
== -1 && src
->hw
!= -1);
732 if (pc
->if_lvl
|| pc
->loop_lvl
||
733 (dst
->type
!= P_TEMP
) ||
734 (src
->hw
< pc
->result_nr
* 4 &&
735 pc
->p
->type
== PIPE_SHADER_FRAGMENT
) ||
736 pc
->p
->info
.opcode_count
[TGSI_OPCODE_CAL
] ||
737 pc
->p
->info
.opcode_count
[TGSI_OPCODE_BRA
]) {
739 emit_mov(pc
, dst
, src
);
745 pc
->r_temp
[dst
->hw
] = NULL
;
746 pc
->r_temp
[src
->hw
] = dst
;
753 emit_nop(struct nv50_pc
*pc
)
755 struct nv50_program_exec
*e
= exec(pc
);
757 e
->inst
[0] = 0xf0000000;
759 e
->inst
[1] = 0xe0000000;
764 check_swap_src_0_1(struct nv50_pc
*pc
,
765 struct nv50_reg
**s0
, struct nv50_reg
**s1
)
767 struct nv50_reg
*src0
= *s0
, *src1
= *s1
;
769 if (src0
->type
== P_CONST
) {
770 if (src1
->type
!= P_CONST
) {
776 if (src1
->type
== P_ATTR
) {
777 if (src0
->type
!= P_ATTR
) {
788 set_src_0_restricted(struct nv50_pc
*pc
, struct nv50_reg
*src
,
789 struct nv50_program_exec
*e
)
791 struct nv50_reg
*temp
;
793 if (src
->type
!= P_TEMP
) {
794 temp
= temp_temp(pc
, e
);
795 emit_mov(pc
, temp
, src
);
802 e
->inst
[0] |= (src
->hw
<< 9);
806 set_src_0(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
808 if (src
->type
== P_ATTR
) {
810 e
->inst
[1] |= 0x00200000;
812 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
813 struct nv50_reg
*temp
= temp_temp(pc
, e
);
815 emit_mov(pc
, temp
, src
);
822 e
->inst
[0] |= (src
->hw
<< 9);
826 set_src_1(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
828 if (src
->type
== P_ATTR
) {
829 struct nv50_reg
*temp
= temp_temp(pc
, e
);
831 emit_mov(pc
, temp
, src
);
834 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
835 assert(!(e
->inst
[0] & 0x00800000));
836 if (e
->inst
[0] & 0x01000000) {
837 struct nv50_reg
*temp
= temp_temp(pc
, e
);
839 emit_mov(pc
, temp
, src
);
842 set_data(pc
, src
, 0x7f, 16, e
);
843 e
->inst
[0] |= 0x00800000;
850 e
->inst
[0] |= ((src
->hw
& 127) << 16);
854 set_src_2(struct nv50_pc
*pc
, struct nv50_reg
*src
, struct nv50_program_exec
*e
)
858 if (src
->type
== P_ATTR
) {
859 struct nv50_reg
*temp
= temp_temp(pc
, e
);
861 emit_mov(pc
, temp
, src
);
864 if (src
->type
== P_CONST
|| src
->type
== P_IMMD
) {
865 assert(!(e
->inst
[0] & 0x01000000));
866 if (e
->inst
[0] & 0x00800000) {
867 struct nv50_reg
*temp
= temp_temp(pc
, e
);
869 emit_mov(pc
, temp
, src
);
872 set_data(pc
, src
, 0x7f, 32+14, e
);
873 e
->inst
[0] |= 0x01000000;
878 e
->inst
[1] |= ((src
->hw
& 127) << 14);
882 set_half_src(struct nv50_pc
*pc
, struct nv50_reg
*src
, int lh
,
883 struct nv50_program_exec
*e
, int pos
)
885 struct nv50_reg
*r
= src
;
888 if (r
->type
!= P_TEMP
) {
889 r
= temp_temp(pc
, e
);
890 emit_mov(pc
, r
, src
);
893 if (r
->hw
> (NV50_SU_MAX_TEMP
/ 2)) {
894 NOUVEAU_ERR("out of low GPRs\n");
898 e
->inst
[pos
/ 32] |= ((src
->hw
* 2) + lh
) << (pos
% 32);
902 emit_mov_from_pred(struct nv50_pc
*pc
, struct nv50_reg
*dst
, int pred
)
904 struct nv50_program_exec
*e
= exec(pc
);
906 assert(dst
->type
== P_TEMP
);
907 e
->inst
[1] = 0x20000000 | (pred
<< 12);
915 emit_mov_to_pred(struct nv50_pc
*pc
, int pred
, struct nv50_reg
*src
)
917 struct nv50_program_exec
*e
= exec(pc
);
919 e
->inst
[0] = 0x000001fc;
920 e
->inst
[1] = 0xa0000008;
922 set_pred_wr(pc
, 1, pred
, e
);
923 set_src_0_restricted(pc
, src
, e
);
929 emit_mul(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
930 struct nv50_reg
*src1
)
932 struct nv50_program_exec
*e
= exec(pc
);
934 e
->inst
[0] |= 0xc0000000;
939 check_swap_src_0_1(pc
, &src0
, &src1
);
941 set_src_0(pc
, src0
, e
);
942 if (src1
->type
== P_IMMD
&& !is_long(e
)) {
943 if (src0
->mod
^ src1
->mod
)
944 e
->inst
[0] |= 0x00008000;
945 set_immd(pc
, src1
, e
);
947 set_src_1(pc
, src1
, e
);
948 if ((src0
->mod
^ src1
->mod
) & NV50_MOD_NEG
) {
950 e
->inst
[1] |= 0x08000000;
952 e
->inst
[0] |= 0x00008000;
960 emit_add(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
961 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
963 struct nv50_program_exec
*e
= exec(pc
);
965 e
->inst
[0] = 0xb0000000;
968 check_swap_src_0_1(pc
, &src0
, &src1
);
970 if (!pc
->allow32
|| (src0
->mod
| src1
->mod
) || src1
->hw
> 63) {
972 e
->inst
[1] |= ((src0
->mod
& NV50_MOD_NEG
) << 26) |
973 ((src1
->mod
& NV50_MOD_NEG
) << 27);
977 set_src_0(pc
, src0
, e
);
978 if (src1
->type
== P_CONST
|| src1
->type
== P_ATTR
|| is_long(e
))
979 set_src_2(pc
, src1
, e
);
981 if (src1
->type
== P_IMMD
)
982 set_immd(pc
, src1
, e
);
984 set_src_1(pc
, src1
, e
);
990 emit_arl(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
993 struct nv50_program_exec
*e
= exec(pc
);
996 e
->inst
[1] |= 0xc0000000;
998 e
->inst
[0] |= dst
->hw
<< 2;
999 e
->inst
[0] |= s
<< 16; /* shift left */
1000 set_src_0_restricted(pc
, src
, e
);
1005 #define NV50_MAX_F32 0x880
1006 #define NV50_MAX_S32 0x08c
1007 #define NV50_MAX_U32 0x084
1008 #define NV50_MIN_F32 0x8a0
1009 #define NV50_MIN_S32 0x0ac
1010 #define NV50_MIN_U32 0x0a4
1013 emit_minmax(struct nv50_pc
*pc
, unsigned sub
, struct nv50_reg
*dst
,
1014 struct nv50_reg
*src0
, struct nv50_reg
*src1
)
1016 struct nv50_program_exec
*e
= exec(pc
);
1019 e
->inst
[0] |= 0x30000000 | ((sub
& 0x800) << 20);
1020 e
->inst
[1] |= (sub
<< 24);
1022 check_swap_src_0_1(pc
, &src0
, &src1
);
1023 set_dst(pc
, dst
, e
);
1024 set_src_0(pc
, src0
, e
);
1025 set_src_1(pc
, src1
, e
);
1027 if (src0
->mod
& NV50_MOD_ABS
)
1028 e
->inst
[1] |= 0x00100000;
1029 if (src1
->mod
& NV50_MOD_ABS
)
1030 e
->inst
[1] |= 0x00080000;
1036 emit_sub(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
1037 struct nv50_reg
*src1
)
1039 src1
->mod
^= NV50_MOD_NEG
;
1040 emit_add(pc
, dst
, src0
, src1
);
1041 src1
->mod
^= NV50_MOD_NEG
;
1045 emit_bitop2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
1046 struct nv50_reg
*src1
, unsigned op
)
1048 struct nv50_program_exec
*e
= exec(pc
);
1050 e
->inst
[0] = 0xd0000000;
1053 check_swap_src_0_1(pc
, &src0
, &src1
);
1054 set_dst(pc
, dst
, e
);
1055 set_src_0(pc
, src0
, e
);
1057 if (op
!= TGSI_OPCODE_AND
&& op
!= TGSI_OPCODE_OR
&&
1058 op
!= TGSI_OPCODE_XOR
)
1059 assert(!"invalid bit op");
1061 assert(!(src0
->mod
| src1
->mod
));
1063 if (src1
->type
== P_IMMD
&& src0
->type
== P_TEMP
&& pc
->allow32
) {
1064 set_immd(pc
, src1
, e
);
1065 if (op
== TGSI_OPCODE_OR
)
1066 e
->inst
[0] |= 0x0100;
1068 if (op
== TGSI_OPCODE_XOR
)
1069 e
->inst
[0] |= 0x8000;
1071 set_src_1(pc
, src1
, e
);
1072 e
->inst
[1] |= 0x04000000; /* 32 bit */
1073 if (op
== TGSI_OPCODE_OR
)
1074 e
->inst
[1] |= 0x4000;
1076 if (op
== TGSI_OPCODE_XOR
)
1077 e
->inst
[1] |= 0x8000;
1084 emit_not(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1086 struct nv50_program_exec
*e
= exec(pc
);
1088 e
->inst
[0] = 0xd0000000;
1089 e
->inst
[1] = 0x0402c000;
1091 set_dst(pc
, dst
, e
);
1092 set_src_1(pc
, src
, e
);
1098 emit_shift(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1099 struct nv50_reg
*src0
, struct nv50_reg
*src1
, unsigned dir
)
1101 struct nv50_program_exec
*e
= exec(pc
);
1103 e
->inst
[0] = 0x30000000;
1104 e
->inst
[1] = 0xc4000000;
1107 set_dst(pc
, dst
, e
);
1108 set_src_0(pc
, src0
, e
);
1110 if (src1
->type
== P_IMMD
) {
1111 e
->inst
[1] |= (1 << 20);
1112 e
->inst
[0] |= (pc
->immd_buf
[src1
->hw
] & 0x7f) << 16;
1114 set_src_1(pc
, src1
, e
);
1116 if (dir
!= TGSI_OPCODE_SHL
)
1117 e
->inst
[1] |= (1 << 29);
1119 if (dir
== TGSI_OPCODE_ISHR
)
1120 e
->inst
[1] |= (1 << 27);
1126 emit_shl_imm(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1127 struct nv50_reg
*src
, int s
)
1129 struct nv50_program_exec
*e
= exec(pc
);
1131 e
->inst
[0] = 0x30000000;
1132 e
->inst
[1] = 0xc4100000;
1134 e
->inst
[1] |= 1 << 29;
1137 e
->inst
[1] |= ((s
& 0x7f) << 16);
1140 set_dst(pc
, dst
, e
);
1141 set_src_0(pc
, src
, e
);
1147 emit_mad(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
1148 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
1150 struct nv50_program_exec
*e
= exec(pc
);
1152 e
->inst
[0] |= 0xe0000000;
1154 check_swap_src_0_1(pc
, &src0
, &src1
);
1155 set_dst(pc
, dst
, e
);
1156 set_src_0(pc
, src0
, e
);
1157 set_src_1(pc
, src1
, e
);
1158 set_src_2(pc
, src2
, e
);
1160 if ((src0
->mod
^ src1
->mod
) & NV50_MOD_NEG
)
1161 e
->inst
[1] |= 0x04000000;
1162 if (src2
->mod
& NV50_MOD_NEG
)
1163 e
->inst
[1] |= 0x08000000;
1169 emit_msb(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src0
,
1170 struct nv50_reg
*src1
, struct nv50_reg
*src2
)
1172 src2
->mod
^= NV50_MOD_NEG
;
1173 emit_mad(pc
, dst
, src0
, src1
, src2
);
1174 src2
->mod
^= NV50_MOD_NEG
;
1177 #define NV50_FLOP_RCP 0
1178 #define NV50_FLOP_RSQ 2
1179 #define NV50_FLOP_LG2 3
1180 #define NV50_FLOP_SIN 4
1181 #define NV50_FLOP_COS 5
1182 #define NV50_FLOP_EX2 6
1184 /* rcp, rsqrt, lg2 support neg and abs */
1186 emit_flop(struct nv50_pc
*pc
, unsigned sub
,
1187 struct nv50_reg
*dst
, struct nv50_reg
*src
)
1189 struct nv50_program_exec
*e
= exec(pc
);
1191 e
->inst
[0] |= 0x90000000;
1192 if (sub
|| src
->mod
) {
1194 e
->inst
[1] |= (sub
<< 29);
1197 set_dst(pc
, dst
, e
);
1198 set_src_0_restricted(pc
, src
, e
);
1200 assert(!src
->mod
|| sub
< 4);
1202 if (src
->mod
& NV50_MOD_NEG
)
1203 e
->inst
[1] |= 0x04000000;
1204 if (src
->mod
& NV50_MOD_ABS
)
1205 e
->inst
[1] |= 0x00100000;
1211 emit_preex2(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1213 struct nv50_program_exec
*e
= exec(pc
);
1215 e
->inst
[0] |= 0xb0000000;
1217 set_dst(pc
, dst
, e
);
1218 set_src_0(pc
, src
, e
);
1220 e
->inst
[1] |= (6 << 29) | 0x00004000;
1222 if (src
->mod
& NV50_MOD_NEG
)
1223 e
->inst
[1] |= 0x04000000;
1224 if (src
->mod
& NV50_MOD_ABS
)
1225 e
->inst
[1] |= 0x00100000;
1231 emit_precossin(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1233 struct nv50_program_exec
*e
= exec(pc
);
1235 e
->inst
[0] |= 0xb0000000;
1237 set_dst(pc
, dst
, e
);
1238 set_src_0(pc
, src
, e
);
1240 e
->inst
[1] |= (6 << 29);
1242 if (src
->mod
& NV50_MOD_NEG
)
1243 e
->inst
[1] |= 0x04000000;
1244 if (src
->mod
& NV50_MOD_ABS
)
1245 e
->inst
[1] |= 0x00100000;
1250 #define CVT_RN (0x00 << 16)
1251 #define CVT_FLOOR (0x02 << 16)
1252 #define CVT_CEIL (0x04 << 16)
1253 #define CVT_TRUNC (0x06 << 16)
1254 #define CVT_SAT (0x08 << 16)
1255 #define CVT_ABS (0x10 << 16)
1257 #define CVT_X32_X32 0x04004000
1258 #define CVT_X32_S32 0x04014000
1259 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1260 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1261 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1262 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1263 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1264 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1265 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1266 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1268 #define CVT_NEG 0x20000000
1269 #define CVT_RI 0x08000000
1272 emit_cvt(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
,
1273 int wp
, uint32_t cvn
)
1275 struct nv50_program_exec
*e
;
1279 if (src
->mod
& NV50_MOD_NEG
) cvn
|= CVT_NEG
;
1280 if (src
->mod
& NV50_MOD_ABS
) cvn
|= CVT_ABS
;
1282 e
->inst
[0] = 0xa0000000;
1285 set_src_0(pc
, src
, e
);
1288 set_pred_wr(pc
, 1, wp
, e
);
1291 set_dst(pc
, dst
, e
);
1293 e
->inst
[0] |= 0x000001fc;
1294 e
->inst
[1] |= 0x00000008;
1300 /* nv50 Condition codes:
1307 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1308 * 0x8 = unordered bit (allows NaN)
1310 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1313 emit_set(struct nv50_pc
*pc
, unsigned ccode
, struct nv50_reg
*dst
, int wp
,
1314 struct nv50_reg
*src0
, struct nv50_reg
*src1
, uint8_t mode
)
1316 static const unsigned cc_swapped
[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1318 struct nv50_program_exec
*e
= exec(pc
);
1319 struct nv50_reg
*rdst
;
1322 if (check_swap_src_0_1(pc
, &src0
, &src1
))
1323 ccode
= cc_swapped
[ccode
& 7] | (ccode
& 8);
1326 if (dst
&& dst
->type
!= P_TEMP
)
1327 dst
= alloc_temp(pc
, NULL
);
1330 e
->inst
[0] |= 0x30000000 | (mode
<< 24);
1331 e
->inst
[1] |= 0x60000000 | (ccode
<< 14);
1334 set_pred_wr(pc
, 1, wp
, e
);
1336 set_dst(pc
, dst
, e
);
1338 e
->inst
[0] |= 0x000001fc;
1339 e
->inst
[1] |= 0x00000008;
1342 set_src_0(pc
, src0
, e
);
1343 set_src_1(pc
, src1
, e
);
1347 if (rdst
&& mode
== 0x80) /* convert to float ? */
1348 emit_cvt(pc
, rdst
, dst
, -1, CVT_ABS
| CVT_F32_S32
);
1349 if (rdst
&& rdst
!= dst
)
1354 map_tgsi_setop_hw(unsigned op
, uint8_t *cc
, uint8_t *ty
)
1357 case TGSI_OPCODE_SLT
: *cc
= 0x1; *ty
= 0x80; break;
1358 case TGSI_OPCODE_SGE
: *cc
= 0x6; *ty
= 0x80; break;
1359 case TGSI_OPCODE_SEQ
: *cc
= 0x2; *ty
= 0x80; break;
1360 case TGSI_OPCODE_SGT
: *cc
= 0x4; *ty
= 0x80; break;
1361 case TGSI_OPCODE_SLE
: *cc
= 0x3; *ty
= 0x80; break;
1362 case TGSI_OPCODE_SNE
: *cc
= 0xd; *ty
= 0x80; break;
1364 case TGSI_OPCODE_ISLT
: *cc
= 0x1; *ty
= 0x0c; break;
1365 case TGSI_OPCODE_ISGE
: *cc
= 0x6; *ty
= 0x0c; break;
1366 case TGSI_OPCODE_USEQ
: *cc
= 0x2; *ty
= 0x04; break;
1367 case TGSI_OPCODE_USGE
: *cc
= 0x6; *ty
= 0x04; break;
1368 case TGSI_OPCODE_USLT
: *cc
= 0x1; *ty
= 0x04; break;
1369 case TGSI_OPCODE_USNE
: *cc
= 0x5; *ty
= 0x04; break;
1377 emit_add_b32(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1378 struct nv50_reg
*src0
, struct nv50_reg
*rsrc1
)
1380 struct nv50_program_exec
*e
= exec(pc
);
1381 struct nv50_reg
*src1
;
1383 e
->inst
[0] = 0x20000000;
1385 alloc_reg(pc
, rsrc1
);
1386 check_swap_src_0_1(pc
, &src0
, &rsrc1
);
1389 if (src0
->mod
& rsrc1
->mod
& NV50_MOD_NEG
) {
1390 src1
= temp_temp(pc
, e
);
1391 emit_cvt(pc
, src1
, rsrc1
, -1, CVT_S32_S32
);
1394 if (!pc
->allow32
|| src1
->hw
> 63 ||
1395 (src1
->type
!= P_TEMP
&& src1
->type
!= P_IMMD
))
1398 set_dst(pc
, dst
, e
);
1399 set_src_0(pc
, src0
, e
);
1402 e
->inst
[1] |= 1 << 26;
1403 set_src_2(pc
, src1
, e
);
1405 e
->inst
[0] |= 0x8000;
1406 if (src1
->type
== P_IMMD
)
1407 set_immd(pc
, src1
, e
);
1409 set_src_1(pc
, src1
, e
);
1412 if (src0
->mod
& NV50_MOD_NEG
)
1413 e
->inst
[0] |= 1 << 28;
1415 if (src1
->mod
& NV50_MOD_NEG
)
1416 e
->inst
[0] |= 1 << 22;
1422 emit_mad_u16(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1423 struct nv50_reg
*src0
, int lh_0
, struct nv50_reg
*src1
, int lh_1
,
1424 struct nv50_reg
*src2
)
1426 struct nv50_program_exec
*e
= exec(pc
);
1428 e
->inst
[0] = 0x60000000;
1431 set_dst(pc
, dst
, e
);
1433 set_half_src(pc
, src0
, lh_0
, e
, 9);
1434 set_half_src(pc
, src1
, lh_1
, e
, 16);
1435 alloc_reg(pc
, src2
);
1436 if (is_long(e
) || (src2
->type
!= P_TEMP
) || (src2
->hw
!= dst
->hw
))
1437 set_src_2(pc
, src2
, e
);
1443 emit_mul_u16(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1444 struct nv50_reg
*src0
, int lh_0
, struct nv50_reg
*src1
, int lh_1
)
1446 struct nv50_program_exec
*e
= exec(pc
);
1448 e
->inst
[0] = 0x40000000;
1450 set_dst(pc
, dst
, e
);
1452 set_half_src(pc
, src0
, lh_0
, e
, 9);
1453 set_half_src(pc
, src1
, lh_1
, e
, 16);
1459 emit_sad(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1460 struct nv50_reg
*src0
, struct nv50_reg
*src1
, struct nv50_reg
*src2
)
1462 struct nv50_program_exec
*e
= exec(pc
);
1464 e
->inst
[0] = 0x50000000;
1467 check_swap_src_0_1(pc
, &src0
, &src1
);
1468 set_dst(pc
, dst
, e
);
1469 set_src_0(pc
, src0
, e
);
1470 set_src_1(pc
, src1
, e
);
1471 alloc_reg(pc
, src2
);
1472 if (is_long(e
) || (src2
->type
!= dst
->type
) || (src2
->hw
!= dst
->hw
))
1473 set_src_2(pc
, src2
, e
);
1476 e
->inst
[1] |= 0x0c << 24;
1478 e
->inst
[0] |= 0x81 << 8;
1484 emit_flr(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1486 emit_cvt(pc
, dst
, src
, -1, CVT_FLOOR
| CVT_F32_F32
| CVT_RI
);
1490 emit_pow(struct nv50_pc
*pc
, struct nv50_reg
*dst
,
1491 struct nv50_reg
*v
, struct nv50_reg
*e
)
1493 struct nv50_reg
*temp
= alloc_temp(pc
, NULL
);
1495 emit_flop(pc
, NV50_FLOP_LG2
, temp
, v
);
1496 emit_mul(pc
, temp
, temp
, e
);
1497 emit_preex2(pc
, temp
, temp
);
1498 emit_flop(pc
, NV50_FLOP_EX2
, dst
, temp
);
1500 free_temp(pc
, temp
);
1504 emit_sat(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1506 emit_cvt(pc
, dst
, src
, -1, CVT_SAT
| CVT_F32_F32
);
1510 emit_lit(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1511 struct nv50_reg
**src
)
1513 struct nv50_reg
*one
= alloc_immd(pc
, 1.0);
1514 struct nv50_reg
*zero
= alloc_immd(pc
, 0.0);
1515 struct nv50_reg
*neg128
= alloc_immd(pc
, -127.999999);
1516 struct nv50_reg
*pos128
= alloc_immd(pc
, 127.999999);
1517 struct nv50_reg
*tmp
[4];
1518 boolean allow32
= pc
->allow32
;
1520 pc
->allow32
= FALSE
;
1522 if (mask
& (3 << 1)) {
1523 tmp
[0] = alloc_temp(pc
, NULL
);
1524 emit_minmax(pc
, NV50_MAX_F32
, tmp
[0], src
[0], zero
);
1527 if (mask
& (1 << 2)) {
1528 set_pred_wr(pc
, 1, 0, pc
->p
->exec_tail
);
1530 tmp
[1] = temp_temp(pc
, NULL
);
1531 emit_minmax(pc
, NV50_MAX_F32
, tmp
[1], src
[1], zero
);
1533 tmp
[3] = temp_temp(pc
, NULL
);
1534 emit_minmax(pc
, NV50_MAX_F32
, tmp
[3], src
[3], neg128
);
1535 emit_minmax(pc
, NV50_MIN_F32
, tmp
[3], tmp
[3], pos128
);
1537 emit_pow(pc
, dst
[2], tmp
[1], tmp
[3]);
1538 emit_mov(pc
, dst
[2], zero
);
1539 set_pred(pc
, 3, 0, pc
->p
->exec_tail
);
1542 if (mask
& (1 << 1))
1543 assimilate_temp(pc
, dst
[1], tmp
[0]);
1545 if (mask
& (1 << 2))
1546 free_temp(pc
, tmp
[0]);
1548 pc
->allow32
= allow32
;
1550 /* do this last, in case src[i,j] == dst[0,3] */
1551 if (mask
& (1 << 0))
1552 emit_mov(pc
, dst
[0], one
);
1554 if (mask
& (1 << 3))
1555 emit_mov(pc
, dst
[3], one
);
1564 emit_kil(struct nv50_pc
*pc
, struct nv50_reg
*src
)
1566 struct nv50_program_exec
*e
;
1567 const int r_pred
= 1;
1570 e
->inst
[0] = 0x00000002; /* discard */
1571 set_long(pc
, e
); /* sets cond code to ALWAYS */
1574 set_pred(pc
, 0x1 /* cc = LT */, r_pred
, e
);
1575 /* write to predicate reg */
1576 emit_cvt(pc
, NULL
, src
, r_pred
, CVT_F32_F32
);
1582 static struct nv50_program_exec
*
1583 emit_control_flow(struct nv50_pc
*pc
, unsigned op
, int pred
, unsigned cc
)
1585 struct nv50_program_exec
*e
= exec(pc
);
1587 e
->inst
[0] = (op
<< 28) | 2;
1590 set_pred(pc
, cc
, pred
, e
);
1596 static INLINE
struct nv50_program_exec
*
1597 emit_breakaddr(struct nv50_pc
*pc
)
1599 return emit_control_flow(pc
, 0x4, -1, 0);
1603 emit_break(struct nv50_pc
*pc
, int pred
, unsigned cc
)
1605 emit_control_flow(pc
, 0x5, pred
, cc
);
1608 static INLINE
struct nv50_program_exec
*
1609 emit_joinat(struct nv50_pc
*pc
)
1611 return emit_control_flow(pc
, 0xa, -1, 0);
1614 static INLINE
struct nv50_program_exec
*
1615 emit_branch(struct nv50_pc
*pc
, int pred
, unsigned cc
)
1617 return emit_control_flow(pc
, 0x1, pred
, cc
);
1620 static INLINE
struct nv50_program_exec
*
1621 emit_call(struct nv50_pc
*pc
, int pred
, unsigned cc
)
1623 return emit_control_flow(pc
, 0x2, pred
, cc
);
1627 emit_ret(struct nv50_pc
*pc
, int pred
, unsigned cc
)
1629 emit_control_flow(pc
, 0x3, pred
, cc
);
1635 #define QOP_MOV_SRC1 3
1637 /* For a quad of threads / top left, top right, bottom left, bottom right
1638 * pixels, do a different operation, and take src0 from a specific thread.
1641 emit_quadop(struct nv50_pc
*pc
, struct nv50_reg
*dst
, int wp
, int lane_src0
,
1642 struct nv50_reg
*src0
, struct nv50_reg
*src1
, ubyte qop
)
1644 struct nv50_program_exec
*e
= exec(pc
);
1646 e
->inst
[0] = 0xc0000000;
1647 e
->inst
[1] = 0x80000000;
1649 e
->inst
[0] |= lane_src0
<< 16;
1650 set_src_0(pc
, src0
, e
);
1651 set_src_2(pc
, src1
, e
);
1654 set_pred_wr(pc
, 1, wp
, e
);
1657 set_dst(pc
, dst
, e
);
1659 e
->inst
[0] |= 0x000001fc;
1660 e
->inst
[1] |= 0x00000008;
1663 e
->inst
[0] |= (qop
& 3) << 20;
1664 e
->inst
[1] |= (qop
>> 2) << 22;
1670 load_cube_tex_coords(struct nv50_pc
*pc
, struct nv50_reg
*t
[4],
1671 struct nv50_reg
**src
, unsigned arg
, boolean proj
)
1673 int mod
[3] = { src
[0]->mod
, src
[1]->mod
, src
[2]->mod
};
1675 src
[0]->mod
|= NV50_MOD_ABS
;
1676 src
[1]->mod
|= NV50_MOD_ABS
;
1677 src
[2]->mod
|= NV50_MOD_ABS
;
1679 emit_minmax(pc
, NV50_MAX_F32
, t
[2], src
[0], src
[1]);
1680 emit_minmax(pc
, NV50_MAX_F32
, t
[2], src
[2], t
[2]);
1682 src
[0]->mod
= mod
[0];
1683 src
[1]->mod
= mod
[1];
1684 src
[2]->mod
= mod
[2];
1686 if (proj
&& 0 /* looks more correct without this */)
1687 emit_mul(pc
, t
[2], t
[2], src
[3]);
1689 if (arg
== 4) /* there is no textureProj(samplerCubeShadow) */
1690 emit_mov(pc
, t
[3], src
[3]);
1692 emit_flop(pc
, NV50_FLOP_RCP
, t
[2], t
[2]);
1694 emit_mul(pc
, t
[0], src
[0], t
[2]);
1695 emit_mul(pc
, t
[1], src
[1], t
[2]);
1696 emit_mul(pc
, t
[2], src
[2], t
[2]);
1700 load_proj_tex_coords(struct nv50_pc
*pc
, struct nv50_reg
*t
[4],
1701 struct nv50_reg
**src
, unsigned dim
, unsigned arg
)
1705 if (src
[0]->type
== P_TEMP
&& src
[0]->rhw
!= -1) {
1706 mode
= pc
->interp_mode
[src
[0]->index
] | INTERP_PERSPECTIVE
;
1708 t
[3]->rhw
= src
[3]->rhw
;
1709 emit_interp(pc
, t
[3], NULL
, (mode
& INTERP_CENTROID
));
1710 emit_flop(pc
, NV50_FLOP_RCP
, t
[3], t
[3]);
1712 for (c
= 0; c
< dim
; ++c
) {
1713 t
[c
]->rhw
= src
[c
]->rhw
;
1714 emit_interp(pc
, t
[c
], t
[3], mode
);
1716 if (arg
!= dim
) { /* depth reference value */
1717 t
[dim
]->rhw
= src
[2]->rhw
;
1718 emit_interp(pc
, t
[dim
], t
[3], mode
);
1721 /* XXX: for some reason the blob sometimes uses MAD
1722 * (mad f32 $rX $rY $rZ neg $r63)
1724 emit_flop(pc
, NV50_FLOP_RCP
, t
[3], src
[3]);
1725 for (c
= 0; c
< dim
; ++c
)
1726 emit_mul(pc
, t
[c
], src
[c
], t
[3]);
1727 if (arg
!= dim
) /* depth reference value */
1728 emit_mul(pc
, t
[dim
], src
[2], t
[3]);
1733 get_tex_dim(unsigned type
, unsigned *dim
, unsigned *arg
)
1736 case TGSI_TEXTURE_1D
:
1739 case TGSI_TEXTURE_SHADOW1D
:
1743 case TGSI_TEXTURE_UNKNOWN
:
1744 case TGSI_TEXTURE_2D
:
1745 case TGSI_TEXTURE_RECT
:
1748 case TGSI_TEXTURE_SHADOW2D
:
1749 case TGSI_TEXTURE_SHADOWRECT
:
1753 case TGSI_TEXTURE_3D
:
1754 case TGSI_TEXTURE_CUBE
:
1763 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1764 * different LOD values, so branch off groups of equal LOD.
1767 emit_texlod_sequence(struct nv50_pc
*pc
, struct nv50_reg
*tlod
,
1768 struct nv50_reg
*src
, struct nv50_program_exec
*tex
)
1770 struct nv50_program_exec
*join_at
;
1771 unsigned i
, target
= pc
->p
->exec_size
+ 9 * 2;
1773 if (pc
->p
->type
!= PIPE_SHADER_FRAGMENT
) {
1777 pc
->allow32
= FALSE
;
1779 /* Subtract lod of each pixel from lod of top left pixel, jump
1780 * texlod insn if result is 0, then repeat for 2 other pixels.
1782 join_at
= emit_joinat(pc
);
1783 emit_quadop(pc
, NULL
, 0, 0, tlod
, tlod
, 0x55);
1784 emit_branch(pc
, 0, 2)->param
.index
= target
;
1786 for (i
= 1; i
< 4; ++i
) {
1787 emit_quadop(pc
, NULL
, 0, i
, tlod
, tlod
, 0x55);
1788 emit_branch(pc
, 0, 2)->param
.index
= target
;
1791 emit_mov(pc
, tlod
, src
); /* target */
1792 emit(pc
, tex
); /* texlod */
1794 join_at
->param
.index
= target
+ 2 * 2;
1795 JOIN_ON(emit_nop(pc
)); /* join _after_ tex */
1799 emit_texbias_sequence(struct nv50_pc
*pc
, struct nv50_reg
*t
[4], unsigned arg
,
1800 struct nv50_program_exec
*tex
)
1802 struct nv50_program_exec
*e
;
1803 struct nv50_reg imm_1248
, *t123
[4][4], *r_bits
= alloc_temp(pc
, NULL
);
1805 unsigned n
, c
, i
, cc
[4] = { 0x0a, 0x13, 0x11, 0x10 };
1807 pc
->allow32
= FALSE
;
1808 ctor_reg(&imm_1248
, P_IMMD
, -1, ctor_immd_4u32(pc
, 1, 2, 4, 8) * 4);
1810 /* Subtract bias value of thread i from bias values of each thread,
1811 * store result in r_pred, and set bit i in r_bits if result was 0.
1814 for (i
= 0; i
< 4; ++i
, ++imm_1248
.hw
) {
1815 emit_quadop(pc
, NULL
, r_pred
, i
, t
[arg
], t
[arg
], 0x55);
1816 emit_mov(pc
, r_bits
, &imm_1248
);
1817 set_pred(pc
, 2, r_pred
, pc
->p
->exec_tail
);
1819 emit_mov_to_pred(pc
, r_pred
, r_bits
);
1821 /* The lanes of a quad are now grouped by the bit in r_pred they have
1822 * set. Put the input values for TEX into a new register set for each
1823 * group and execute TEX only for a specific group.
1824 * We cannot use the same register set for each group because we need
1825 * the derivatives, which are implicitly calculated, to be correct.
1827 for (i
= 1; i
< 4; ++i
) {
1828 alloc_temp4(pc
, t123
[i
], 0);
1830 for (c
= 0; c
<= arg
; ++c
)
1831 emit_mov(pc
, t123
[i
][c
], t
[c
]);
1833 *(e
= exec(pc
)) = *(tex
);
1834 e
->inst
[0] &= ~0x01fc;
1835 set_dst(pc
, t123
[i
][0], e
);
1836 set_pred(pc
, cc
[i
], r_pred
, e
);
1839 /* finally TEX on the original regs (where we kept the input) */
1840 set_pred(pc
, cc
[0], r_pred
, tex
);
1843 /* put the 3 * n other results into regs for lane 0 */
1844 n
= popcnt4(((e
->inst
[0] >> 25) & 0x3) | ((e
->inst
[1] >> 12) & 0xc));
1845 for (i
= 1; i
< 4; ++i
) {
1846 for (c
= 0; c
< n
; ++c
) {
1847 emit_mov(pc
, t
[c
], t123
[i
][c
]);
1848 set_pred(pc
, cc
[i
], r_pred
, pc
->p
->exec_tail
);
1850 free_temp4(pc
, t123
[i
]);
1854 free_temp(pc
, r_bits
);
1858 emit_tex(struct nv50_pc
*pc
, struct nv50_reg
**dst
, unsigned mask
,
1859 struct nv50_reg
**src
, unsigned unit
, unsigned type
,
1860 boolean proj
, int bias_lod
)
1862 struct nv50_reg
*t
[4];
1863 struct nv50_program_exec
*e
;
1864 unsigned c
, dim
, arg
;
1866 /* t[i] must be within a single 128 bit super-reg */
1867 alloc_temp4(pc
, t
, 0);
1870 e
->inst
[0] = 0xf0000000;
1872 set_dst(pc
, t
[0], e
);
1874 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1875 e
->inst
[0] |= (unit
<< 9) /* | (unit << 17) */;
1877 /* live flag (don't set if TEX results affect input to another TEX): */
1878 /* e->inst[0] |= 0x00000004; */
1880 get_tex_dim(type
, &dim
, &arg
);
1882 if (type
== TGSI_TEXTURE_CUBE
) {
1883 e
->inst
[0] |= 0x08000000;
1884 load_cube_tex_coords(pc
, t
, src
, arg
, proj
);
1887 load_proj_tex_coords(pc
, t
, src
, dim
, arg
);
1889 for (c
= 0; c
< dim
; c
++)
1890 emit_mov(pc
, t
[c
], src
[c
]);
1891 if (arg
!= dim
) /* depth reference value (always src.z here) */
1892 emit_mov(pc
, t
[dim
], src
[2]);
1895 e
->inst
[0] |= (mask
& 0x3) << 25;
1896 e
->inst
[1] |= (mask
& 0xc) << 12;
1899 e
->inst
[0] |= (arg
- 1) << 22;
1903 assert(pc
->p
->type
== PIPE_SHADER_FRAGMENT
);
1904 e
->inst
[0] |= arg
<< 22;
1905 e
->inst
[1] |= 0x20000000; /* texbias */
1906 emit_mov(pc
, t
[arg
], src
[3]);
1907 emit_texbias_sequence(pc
, t
, arg
, e
);
1909 e
->inst
[0] |= arg
<< 22;
1910 e
->inst
[1] |= 0x40000000; /* texlod */
1911 emit_mov(pc
, t
[arg
], src
[3]);
1912 emit_texlod_sequence(pc
, t
[arg
], src
[3], e
);
1917 if (mask
& 1) emit_mov(pc
, dst
[0], t
[c
++]);
1918 if (mask
& 2) emit_mov(pc
, dst
[1], t
[c
++]);
1919 if (mask
& 4) emit_mov(pc
, dst
[2], t
[c
++]);
1920 if (mask
& 8) emit_mov(pc
, dst
[3], t
[c
]);
1924 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1925 * the texture coordinates, not the fetched values: latency ? */
1927 for (c
= 0; c
< 4; c
++) {
1928 if (mask
& (1 << c
))
1929 assimilate_temp(pc
, dst
[c
], t
[c
]);
1931 free_temp(pc
, t
[c
]);
1937 emit_ddx(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1939 struct nv50_program_exec
*e
= exec(pc
);
1941 assert(src
->type
== P_TEMP
);
1943 e
->inst
[0] = (src
->mod
& NV50_MOD_NEG
) ? 0xc0240000 : 0xc0140000;
1944 e
->inst
[1] = (src
->mod
& NV50_MOD_NEG
) ? 0x86400000 : 0x89800000;
1946 set_dst(pc
, dst
, e
);
1947 set_src_0(pc
, src
, e
);
1948 set_src_2(pc
, src
, e
);
1954 emit_ddy(struct nv50_pc
*pc
, struct nv50_reg
*dst
, struct nv50_reg
*src
)
1956 struct nv50_program_exec
*e
= exec(pc
);
1958 assert(src
->type
== P_TEMP
);
1960 e
->inst
[0] = (src
->mod
& NV50_MOD_NEG
) ? 0xc0250000 : 0xc0150000;
1961 e
->inst
[1] = (src
->mod
& NV50_MOD_NEG
) ? 0x85800000 : 0x8a400000;
1963 set_dst(pc
, dst
, e
);
1964 set_src_0(pc
, src
, e
);
1965 set_src_2(pc
, src
, e
);
1971 convert_to_long(struct nv50_pc
*pc
, struct nv50_program_exec
*e
)
1973 unsigned q
= 0, m
= ~0;
1975 assert(!is_long(e
));
1977 switch (e
->inst
[0] >> 28) {
1985 /* ADD, SUB, SUBR b32 */
1986 m
= ~(0x8000 | (127 << 16));
1987 q
= ((e
->inst
[0] & (~m
)) >> 2) | (1 << 26);
1992 q
= (0x0c << 24) | ((e
->inst
[0] & (0x7f << 2)) << 12);
1996 q
= (e
->inst
[0] & (0x7f << 2)) << 12;
1999 /* INTERP (move centroid, perspective and flat bits) */
2001 q
= (e
->inst
[0] & (3 << 24)) >> (24 - 16);
2002 q
|= (e
->inst
[0] & (1 << 8)) << (18 - 8);
2010 q
= ((e
->inst
[0] & (~m
)) >> 2);
2015 q
= ((e
->inst
[0] & (~m
)) << 12);
2018 /* MAD (if src2 == dst) */
2019 q
= ((e
->inst
[0] & 0x1fc) << 12);
2033 /* Some operations support an optional negation flag. */
2035 get_supported_mods(const struct tgsi_full_instruction
*insn
, int i
)
2037 switch (insn
->Instruction
.Opcode
) {
2038 case TGSI_OPCODE_ADD
:
2039 case TGSI_OPCODE_COS
:
2040 case TGSI_OPCODE_DDX
:
2041 case TGSI_OPCODE_DDY
:
2042 case TGSI_OPCODE_DP3
:
2043 case TGSI_OPCODE_DP4
:
2044 case TGSI_OPCODE_EX2
:
2045 case TGSI_OPCODE_KIL
:
2046 case TGSI_OPCODE_LG2
:
2047 case TGSI_OPCODE_MAD
:
2048 case TGSI_OPCODE_MUL
:
2049 case TGSI_OPCODE_POW
:
2050 case TGSI_OPCODE_RCP
:
2051 case TGSI_OPCODE_RSQ
: /* ignored, RSQ = rsqrt(abs(src.x)) */
2052 case TGSI_OPCODE_SCS
:
2053 case TGSI_OPCODE_SIN
:
2054 case TGSI_OPCODE_SUB
:
2055 return NV50_MOD_NEG
;
2056 case TGSI_OPCODE_MAX
:
2057 case TGSI_OPCODE_MIN
:
2058 case TGSI_OPCODE_INEG
: /* tgsi src sign toggle/set would be stupid */
2059 return NV50_MOD_ABS
;
2060 case TGSI_OPCODE_CEIL
:
2061 case TGSI_OPCODE_FLR
:
2062 case TGSI_OPCODE_TRUNC
:
2063 return NV50_MOD_NEG
| NV50_MOD_ABS
;
2064 case TGSI_OPCODE_F2I
:
2065 case TGSI_OPCODE_F2U
:
2066 case TGSI_OPCODE_I2F
:
2067 case TGSI_OPCODE_U2F
:
2068 return NV50_MOD_NEG
| NV50_MOD_ABS
| NV50_MOD_I32
;
2069 case TGSI_OPCODE_UADD
:
2070 return NV50_MOD_NEG
| NV50_MOD_I32
;
2071 case TGSI_OPCODE_SAD
:
2072 case TGSI_OPCODE_SHL
:
2073 case TGSI_OPCODE_IMAX
:
2074 case TGSI_OPCODE_IMIN
:
2075 case TGSI_OPCODE_ISHR
:
2076 case TGSI_OPCODE_NOT
:
2077 case TGSI_OPCODE_UMAD
:
2078 case TGSI_OPCODE_UMAX
:
2079 case TGSI_OPCODE_UMIN
:
2080 case TGSI_OPCODE_UMUL
:
2081 case TGSI_OPCODE_USHR
:
2082 return NV50_MOD_I32
;
2088 /* Return a read mask for source registers deduced from opcode & write mask. */
2090 nv50_tgsi_src_mask(const struct tgsi_full_instruction
*insn
, int c
)
2092 unsigned x
, mask
= insn
->Dst
[0].Register
.WriteMask
;
2094 switch (insn
->Instruction
.Opcode
) {
2095 case TGSI_OPCODE_COS
:
2096 case TGSI_OPCODE_SIN
:
2097 return (mask
& 0x8) | ((mask
& 0x7) ? 0x1 : 0x0);
2098 case TGSI_OPCODE_DP3
:
2100 case TGSI_OPCODE_DP4
:
2101 case TGSI_OPCODE_DPH
:
2102 case TGSI_OPCODE_KIL
: /* WriteMask ignored */
2104 case TGSI_OPCODE_DST
:
2105 return mask
& (c
? 0xa : 0x6);
2106 case TGSI_OPCODE_EX2
:
2107 case TGSI_OPCODE_EXP
:
2108 case TGSI_OPCODE_LG2
:
2109 case TGSI_OPCODE_LOG
:
2110 case TGSI_OPCODE_POW
:
2111 case TGSI_OPCODE_RCP
:
2112 case TGSI_OPCODE_RSQ
:
2113 case TGSI_OPCODE_SCS
:
2115 case TGSI_OPCODE_IF
:
2117 case TGSI_OPCODE_LIT
:
2119 case TGSI_OPCODE_TEX
:
2120 case TGSI_OPCODE_TXB
:
2121 case TGSI_OPCODE_TXL
:
2122 case TGSI_OPCODE_TXP
:
2124 const struct tgsi_instruction_texture
*tex
;
2126 assert(insn
->Instruction
.Texture
);
2127 tex
= &insn
->Texture
;
2130 if (insn
->Instruction
.Opcode
!= TGSI_OPCODE_TEX
&&
2131 insn
->Instruction
.Opcode
!= TGSI_OPCODE_TXD
)
2132 mask
|= 0x8; /* bias, lod or proj */
2134 switch (tex
->Texture
) {
2135 case TGSI_TEXTURE_1D
:
2138 case TGSI_TEXTURE_SHADOW1D
:
2141 case TGSI_TEXTURE_2D
:
2149 case TGSI_OPCODE_XPD
:
2151 if (mask
& 1) x
|= 0x6;
2152 if (mask
& 2) x
|= 0x5;
2153 if (mask
& 4) x
|= 0x3;
2162 static struct nv50_reg
*
2163 tgsi_dst(struct nv50_pc
*pc
, int c
, const struct tgsi_full_dst_register
*dst
)
2165 switch (dst
->Register
.File
) {
2166 case TGSI_FILE_TEMPORARY
:
2167 return &pc
->temp
[dst
->Register
.Index
* 4 + c
];
2168 case TGSI_FILE_OUTPUT
:
2169 return &pc
->result
[dst
->Register
.Index
* 4 + c
];
2170 case TGSI_FILE_ADDRESS
:
2172 struct nv50_reg
*r
= pc
->addr
[dst
->Register
.Index
* 4 + c
];
2174 r
= alloc_addr(pc
, NULL
);
2175 pc
->addr
[dst
->Register
.Index
* 4 + c
] = r
;
2180 case TGSI_FILE_NULL
:
2189 static struct nv50_reg
*
2190 tgsi_src(struct nv50_pc
*pc
, int chan
, const struct tgsi_full_src_register
*src
,
2193 struct nv50_reg
*r
= NULL
;
2194 struct nv50_reg
*temp
= NULL
;
2195 unsigned sgn
, c
, swz
, cvn
;
2197 if (src
->Register
.File
!= TGSI_FILE_CONSTANT
)
2198 assert(!src
->Register
.Indirect
);
2200 sgn
= tgsi_util_get_full_src_register_sign_mode(src
, chan
);
2202 c
= tgsi_util_get_full_src_register_swizzle(src
, chan
);
2204 case TGSI_SWIZZLE_X
:
2205 case TGSI_SWIZZLE_Y
:
2206 case TGSI_SWIZZLE_Z
:
2207 case TGSI_SWIZZLE_W
:
2208 switch (src
->Register
.File
) {
2209 case TGSI_FILE_INPUT
:
2210 r
= &pc
->attr
[src
->Register
.Index
* 4 + c
];
2212 case TGSI_FILE_TEMPORARY
:
2213 r
= &pc
->temp
[src
->Register
.Index
* 4 + c
];
2215 case TGSI_FILE_CONSTANT
:
2216 if (!src
->Register
.Indirect
) {
2217 r
= &pc
->param
[src
->Register
.Index
* 4 + c
];
2220 /* Indicate indirection by setting r->acc < 0 and
2221 * use the index field to select the address reg.
2223 r
= reg_instance(pc
, NULL
);
2224 swz
= tgsi_util_get_src_register_swizzle(
2226 ctor_reg(r
, P_CONST
,
2227 src
->Indirect
.Index
* 4 + swz
,
2228 src
->Register
.Index
* 4 + c
);
2231 case TGSI_FILE_IMMEDIATE
:
2232 r
= &pc
->immd
[src
->Register
.Index
* 4 + c
];
2234 case TGSI_FILE_SAMPLER
:
2236 case TGSI_FILE_ADDRESS
:
2237 r
= pc
->addr
[src
->Register
.Index
* 4 + c
];
2250 cvn
= (mod
& NV50_MOD_I32
) ? CVT_S32_S32
: CVT_F32_F32
;
2253 case TGSI_UTIL_SIGN_CLEAR
:
2254 r
->mod
= NV50_MOD_ABS
;
2256 case TGSI_UTIL_SIGN_SET
:
2257 r
->mod
= NV50_MOD_NEG_ABS
;
2259 case TGSI_UTIL_SIGN_TOGGLE
:
2260 r
->mod
= NV50_MOD_NEG
;
2263 assert(!r
->mod
&& sgn
== TGSI_UTIL_SIGN_KEEP
);
2267 if ((r
->mod
& mod
) != r
->mod
) {
2268 temp
= temp_temp(pc
, NULL
);
2269 emit_cvt(pc
, temp
, r
, -1, cvn
);
2273 r
->mod
|= mod
& NV50_MOD_I32
;
2276 if (r
->acc
>= 0 && r
!= temp
)
2277 return reg_instance(pc
, r
); /* will clear r->mod */
2281 /* return TRUE for ops that produce only a single result */
2283 is_scalar_op(unsigned op
)
2286 case TGSI_OPCODE_COS
:
2287 case TGSI_OPCODE_DP2
:
2288 case TGSI_OPCODE_DP3
:
2289 case TGSI_OPCODE_DP4
:
2290 case TGSI_OPCODE_DPH
:
2291 case TGSI_OPCODE_EX2
:
2292 case TGSI_OPCODE_LG2
:
2293 case TGSI_OPCODE_POW
:
2294 case TGSI_OPCODE_RCP
:
2295 case TGSI_OPCODE_RSQ
:
2296 case TGSI_OPCODE_SIN
:
2298 case TGSI_OPCODE_KIL:
2299 case TGSI_OPCODE_LIT:
2300 case TGSI_OPCODE_SCS:
2308 /* Returns a bitmask indicating which dst components depend
2309 * on source s, component c (reverse of nv50_tgsi_src_mask).
2312 nv50_tgsi_dst_revdep(unsigned op
, int s
, int c
)
2314 if (is_scalar_op(op
))
2318 case TGSI_OPCODE_DST
:
2319 return (1 << c
) & (s
? 0xa : 0x6);
2320 case TGSI_OPCODE_XPD
:
2330 case TGSI_OPCODE_EXP
:
2331 case TGSI_OPCODE_LOG
:
2332 case TGSI_OPCODE_LIT
:
2333 case TGSI_OPCODE_SCS
:
2334 case TGSI_OPCODE_TEX
:
2335 case TGSI_OPCODE_TXB
:
2336 case TGSI_OPCODE_TXL
:
2337 case TGSI_OPCODE_TXP
:
2338 /* these take care of dangerous swizzles themselves */
2340 case TGSI_OPCODE_IF
:
2341 case TGSI_OPCODE_KIL
:
2342 /* don't call this function for these ops */
2346 /* linear vector instruction */
2351 static INLINE boolean
2352 has_pred(struct nv50_program_exec
*e
, unsigned cc
)
2354 if (!is_long(e
) || is_immd(e
))
2356 return ((e
->inst
[1] & 0x780) == (cc
<< 7));
2359 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2366 nv50_kill_branch(struct nv50_pc
*pc
)
2368 int lvl
= pc
->if_lvl
;
2370 if (pc
->if_insn
[lvl
]->next
!= pc
->p
->exec_tail
)
2372 if (is_immd(pc
->p
->exec_tail
))
2375 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2376 * reg may no longer be valid, since we currently always use $p0
2378 if (has_pred(pc
->if_insn
[lvl
], 0xf))
2380 assert(pc
->if_insn
[lvl
] && pc
->if_join
[lvl
]);
2382 /* We'll use the exec allocated for JOIN_AT (we can't easily
2383 * access nv50_program_exec's prev).
2385 pc
->p
->exec_size
-= 4; /* remove JOIN_AT and BRA */
2387 *pc
->if_join
[lvl
] = *pc
->p
->exec_tail
;
2389 FREE(pc
->if_insn
[lvl
]);
2390 FREE(pc
->p
->exec_tail
);
2392 pc
->p
->exec_tail
= pc
->if_join
[lvl
];
2393 pc
->p
->exec_tail
->next
= NULL
;
2394 set_pred(pc
, 0xd, 0, pc
->p
->exec_tail
);
2400 nv50_fp_move_results(struct nv50_pc
*pc
)
2402 struct nv50_reg reg
;
2405 ctor_reg(®
, P_TEMP
, -1, -1);
2407 for (i
= 0; i
< pc
->result_nr
* 4; ++i
) {
2408 if (pc
->result
[i
].rhw
< 0 || pc
->result
[i
].hw
< 0)
2410 if (pc
->result
[i
].rhw
!= pc
->result
[i
].hw
) {
2411 reg
.hw
= pc
->result
[i
].rhw
;
2412 emit_mov(pc
, ®
, &pc
->result
[i
]);
2418 nv50_program_tx_insn(struct nv50_pc
*pc
,
2419 const struct tgsi_full_instruction
*inst
)
2421 struct nv50_reg
*rdst
[4], *dst
[4], *brdc
, *src
[3][4], *temp
;
2422 unsigned mask
, sat
, unit
;
2425 mask
= inst
->Dst
[0].Register
.WriteMask
;
2426 sat
= inst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
;
2428 memset(src
, 0, sizeof(src
));
2430 for (c
= 0; c
< 4; c
++) {
2431 if ((mask
& (1 << c
)) && !pc
->r_dst
[c
])
2432 dst
[c
] = tgsi_dst(pc
, c
, &inst
->Dst
[0]);
2434 dst
[c
] = pc
->r_dst
[c
];
2438 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
2439 const struct tgsi_full_src_register
*fs
= &inst
->Src
[i
];
2443 src_mask
= nv50_tgsi_src_mask(inst
, i
);
2444 mod_supp
= get_supported_mods(inst
, i
);
2446 if (fs
->Register
.File
== TGSI_FILE_SAMPLER
)
2447 unit
= fs
->Register
.Index
;
2449 for (c
= 0; c
< 4; c
++)
2450 if (src_mask
& (1 << c
))
2451 src
[i
][c
] = tgsi_src(pc
, c
, fs
, mod_supp
);
2454 brdc
= temp
= pc
->r_brdc
;
2455 if (brdc
&& brdc
->type
!= P_TEMP
) {
2456 temp
= temp_temp(pc
, NULL
);
2461 for (c
= 0; c
< 4; c
++) {
2462 if (!(mask
& (1 << c
)) || dst
[c
]->type
== P_TEMP
)
2464 /* rdst[c] = dst[c]; */ /* done above */
2465 dst
[c
] = temp_temp(pc
, NULL
);
2469 assert(brdc
|| !is_scalar_op(inst
->Instruction
.Opcode
));
2471 switch (inst
->Instruction
.Opcode
) {
2472 case TGSI_OPCODE_ABS
:
2473 for (c
= 0; c
< 4; c
++) {
2474 if (!(mask
& (1 << c
)))
2476 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2477 CVT_ABS
| CVT_F32_F32
);
2480 case TGSI_OPCODE_ADD
:
2481 for (c
= 0; c
< 4; c
++) {
2482 if (!(mask
& (1 << c
)))
2484 emit_add(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2487 case TGSI_OPCODE_AND
:
2488 case TGSI_OPCODE_XOR
:
2489 case TGSI_OPCODE_OR
:
2490 for (c
= 0; c
< 4; c
++) {
2491 if (!(mask
& (1 << c
)))
2493 emit_bitop2(pc
, dst
[c
], src
[0][c
], src
[1][c
],
2494 inst
->Instruction
.Opcode
);
2497 case TGSI_OPCODE_ARL
:
2499 temp
= temp_temp(pc
, NULL
);
2500 emit_cvt(pc
, temp
, src
[0][0], -1, CVT_FLOOR
| CVT_S32_F32
);
2501 emit_arl(pc
, dst
[0], temp
, 4);
2503 case TGSI_OPCODE_BGNLOOP
:
2504 pc
->loop_brka
[pc
->loop_lvl
] = emit_breakaddr(pc
);
2505 pc
->loop_pos
[pc
->loop_lvl
++] = pc
->p
->exec_size
;
2508 case TGSI_OPCODE_BGNSUB
:
2509 assert(!pc
->in_subroutine
);
2510 pc
->in_subroutine
= TRUE
;
2511 /* probably not necessary, but align to 8 byte boundary */
2512 if (!is_long(pc
->p
->exec_tail
))
2513 convert_to_long(pc
, pc
->p
->exec_tail
);
2515 case TGSI_OPCODE_BRK
:
2516 assert(pc
->loop_lvl
> 0);
2517 emit_break(pc
, -1, 0);
2519 case TGSI_OPCODE_CAL
:
2520 assert(inst
->Label
.Label
< pc
->insn_nr
);
2521 emit_call(pc
, -1, 0)->param
.index
= inst
->Label
.Label
;
2522 /* replaced by actual offset in nv50_program_fixup_insns */
2524 case TGSI_OPCODE_CEIL
:
2525 for (c
= 0; c
< 4; c
++) {
2526 if (!(mask
& (1 << c
)))
2528 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2529 CVT_CEIL
| CVT_F32_F32
| CVT_RI
);
2532 case TGSI_OPCODE_CMP
:
2533 pc
->allow32
= FALSE
;
2534 for (c
= 0; c
< 4; c
++) {
2535 if (!(mask
& (1 << c
)))
2537 emit_cvt(pc
, NULL
, src
[0][c
], 1, CVT_F32_F32
);
2538 emit_mov(pc
, dst
[c
], src
[1][c
]);
2539 set_pred(pc
, 0x1, 1, pc
->p
->exec_tail
); /* @SF */
2540 emit_mov(pc
, dst
[c
], src
[2][c
]);
2541 set_pred(pc
, 0x6, 1, pc
->p
->exec_tail
); /* @NSF */
2544 case TGSI_OPCODE_CONT
:
2545 assert(pc
->loop_lvl
> 0);
2546 emit_branch(pc
, -1, 0)->param
.index
=
2547 pc
->loop_pos
[pc
->loop_lvl
- 1];
2549 case TGSI_OPCODE_COS
:
2551 emit_precossin(pc
, temp
, src
[0][3]);
2552 emit_flop(pc
, NV50_FLOP_COS
, dst
[3], temp
);
2556 temp
= brdc
= temp_temp(pc
, NULL
);
2558 emit_precossin(pc
, temp
, src
[0][0]);
2559 emit_flop(pc
, NV50_FLOP_COS
, brdc
, temp
);
2561 case TGSI_OPCODE_DDX
:
2562 for (c
= 0; c
< 4; c
++) {
2563 if (!(mask
& (1 << c
)))
2565 emit_ddx(pc
, dst
[c
], src
[0][c
]);
2568 case TGSI_OPCODE_DDY
:
2569 for (c
= 0; c
< 4; c
++) {
2570 if (!(mask
& (1 << c
)))
2572 emit_ddy(pc
, dst
[c
], src
[0][c
]);
2575 case TGSI_OPCODE_DP3
:
2576 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
2577 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
2578 emit_mad(pc
, brdc
, src
[0][2], src
[1][2], temp
);
2580 case TGSI_OPCODE_DP4
:
2581 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
2582 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
2583 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
2584 emit_mad(pc
, brdc
, src
[0][3], src
[1][3], temp
);
2586 case TGSI_OPCODE_DPH
:
2587 emit_mul(pc
, temp
, src
[0][0], src
[1][0]);
2588 emit_mad(pc
, temp
, src
[0][1], src
[1][1], temp
);
2589 emit_mad(pc
, temp
, src
[0][2], src
[1][2], temp
);
2590 emit_add(pc
, brdc
, src
[1][3], temp
);
2592 case TGSI_OPCODE_DST
:
2593 if (mask
& (1 << 1))
2594 emit_mul(pc
, dst
[1], src
[0][1], src
[1][1]);
2595 if (mask
& (1 << 2))
2596 emit_mov(pc
, dst
[2], src
[0][2]);
2597 if (mask
& (1 << 3))
2598 emit_mov(pc
, dst
[3], src
[1][3]);
2599 if (mask
& (1 << 0))
2600 emit_mov_immdval(pc
, dst
[0], 1.0f
);
2602 case TGSI_OPCODE_ELSE
:
2603 emit_branch(pc
, -1, 0);
2604 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
2605 pc
->if_insn
[pc
->if_lvl
++] = pc
->p
->exec_tail
;
2608 case TGSI_OPCODE_ENDIF
:
2609 pc
->if_insn
[--pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
2611 /* try to replace branch over 1 insn with a predicated insn */
2612 if (nv50_kill_branch(pc
) == TRUE
)
2615 if (pc
->if_join
[pc
->if_lvl
]) {
2616 pc
->if_join
[pc
->if_lvl
]->param
.index
= pc
->p
->exec_size
;
2617 pc
->if_join
[pc
->if_lvl
] = NULL
;
2620 /* emit a NOP as join point, we could set it on the next
2621 * one, but would have to make sure it is long and !immd
2623 JOIN_ON(emit_nop(pc
));
2625 case TGSI_OPCODE_ENDLOOP
:
2626 emit_branch(pc
, -1, 0)->param
.index
=
2627 pc
->loop_pos
[--pc
->loop_lvl
];
2628 pc
->loop_brka
[pc
->loop_lvl
]->param
.index
= pc
->p
->exec_size
;
2631 case TGSI_OPCODE_ENDSUB
:
2632 assert(pc
->in_subroutine
);
2633 pc
->in_subroutine
= FALSE
;
2635 case TGSI_OPCODE_EX2
:
2636 emit_preex2(pc
, temp
, src
[0][0]);
2637 emit_flop(pc
, NV50_FLOP_EX2
, brdc
, temp
);
2639 case TGSI_OPCODE_EXP
:
2641 struct nv50_reg
*t
[2];
2644 t
[0] = temp_temp(pc
, NULL
);
2645 t
[1] = temp_temp(pc
, NULL
);
2648 emit_mov(pc
, t
[0], src
[0][0]);
2650 emit_flr(pc
, t
[1], src
[0][0]);
2652 if (mask
& (1 << 1))
2653 emit_sub(pc
, dst
[1], t
[0], t
[1]);
2654 if (mask
& (1 << 0)) {
2655 emit_preex2(pc
, t
[1], t
[1]);
2656 emit_flop(pc
, NV50_FLOP_EX2
, dst
[0], t
[1]);
2658 if (mask
& (1 << 2)) {
2659 emit_preex2(pc
, t
[0], t
[0]);
2660 emit_flop(pc
, NV50_FLOP_EX2
, dst
[2], t
[0]);
2662 if (mask
& (1 << 3))
2663 emit_mov_immdval(pc
, dst
[3], 1.0f
);
2666 case TGSI_OPCODE_F2I
:
2667 for (c
= 0; c
< 4; c
++) {
2668 if (!(mask
& (1 << c
)))
2670 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2671 CVT_TRUNC
| CVT_S32_F32
);
2674 case TGSI_OPCODE_F2U
:
2675 for (c
= 0; c
< 4; c
++) {
2676 if (!(mask
& (1 << c
)))
2678 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2679 CVT_TRUNC
| CVT_U32_F32
);
2682 case TGSI_OPCODE_FLR
:
2683 for (c
= 0; c
< 4; c
++) {
2684 if (!(mask
& (1 << c
)))
2686 emit_flr(pc
, dst
[c
], src
[0][c
]);
2689 case TGSI_OPCODE_FRC
:
2690 temp
= temp_temp(pc
, NULL
);
2691 for (c
= 0; c
< 4; c
++) {
2692 if (!(mask
& (1 << c
)))
2694 emit_flr(pc
, temp
, src
[0][c
]);
2695 emit_sub(pc
, dst
[c
], src
[0][c
], temp
);
2698 case TGSI_OPCODE_I2F
:
2699 for (c
= 0; c
< 4; c
++) {
2700 if (!(mask
& (1 << c
)))
2702 emit_cvt(pc
, dst
[c
], src
[0][c
], -1, CVT_F32_S32
);
2705 case TGSI_OPCODE_IF
:
2706 assert(pc
->if_lvl
< NV50_MAX_COND_NESTING
);
2707 emit_cvt(pc
, NULL
, src
[0][0], 0, CVT_ABS
| CVT_F32_F32
);
2708 pc
->if_join
[pc
->if_lvl
] = emit_joinat(pc
);
2709 pc
->if_insn
[pc
->if_lvl
++] = emit_branch(pc
, 0, 2);;
2712 case TGSI_OPCODE_IMAX
:
2713 for (c
= 0; c
< 4; c
++) {
2714 if (!(mask
& (1 << c
)))
2716 emit_minmax(pc
, 0x08c, dst
[c
], src
[0][c
], src
[1][c
]);
2719 case TGSI_OPCODE_IMIN
:
2720 for (c
= 0; c
< 4; c
++) {
2721 if (!(mask
& (1 << c
)))
2723 emit_minmax(pc
, 0x0ac, dst
[c
], src
[0][c
], src
[1][c
]);
2726 case TGSI_OPCODE_INEG
:
2727 for (c
= 0; c
< 4; c
++) {
2728 if (!(mask
& (1 << c
)))
2730 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2731 CVT_S32_S32
| CVT_NEG
);
2734 case TGSI_OPCODE_KIL
:
2735 assert(src
[0][0] && src
[0][1] && src
[0][2] && src
[0][3]);
2736 emit_kil(pc
, src
[0][0]);
2737 emit_kil(pc
, src
[0][1]);
2738 emit_kil(pc
, src
[0][2]);
2739 emit_kil(pc
, src
[0][3]);
2741 case TGSI_OPCODE_KILP
:
2744 case TGSI_OPCODE_LIT
:
2745 emit_lit(pc
, &dst
[0], mask
, &src
[0][0]);
2747 case TGSI_OPCODE_LG2
:
2748 emit_flop(pc
, NV50_FLOP_LG2
, brdc
, src
[0][0]);
2750 case TGSI_OPCODE_LOG
:
2752 struct nv50_reg
*t
[2];
2754 t
[0] = temp_temp(pc
, NULL
);
2755 if (mask
& (1 << 1))
2756 t
[1] = temp_temp(pc
, NULL
);
2760 emit_cvt(pc
, t
[0], src
[0][0], -1, CVT_ABS
| CVT_F32_F32
);
2761 emit_flop(pc
, NV50_FLOP_LG2
, t
[1], t
[0]);
2762 if (mask
& (1 << 2))
2763 emit_mov(pc
, dst
[2], t
[1]);
2764 emit_flr(pc
, t
[1], t
[1]);
2765 if (mask
& (1 << 0))
2766 emit_mov(pc
, dst
[0], t
[1]);
2767 if (mask
& (1 << 1)) {
2768 t
[1]->mod
= NV50_MOD_NEG
;
2769 emit_preex2(pc
, t
[1], t
[1]);
2771 emit_flop(pc
, NV50_FLOP_EX2
, t
[1], t
[1]);
2772 emit_mul(pc
, dst
[1], t
[0], t
[1]);
2774 if (mask
& (1 << 3))
2775 emit_mov_immdval(pc
, dst
[3], 1.0f
);
2778 case TGSI_OPCODE_LRP
:
2779 temp
= temp_temp(pc
, NULL
);
2780 for (c
= 0; c
< 4; c
++) {
2781 if (!(mask
& (1 << c
)))
2783 emit_sub(pc
, temp
, src
[1][c
], src
[2][c
]);
2784 emit_mad(pc
, dst
[c
], temp
, src
[0][c
], src
[2][c
]);
2787 case TGSI_OPCODE_MAD
:
2788 for (c
= 0; c
< 4; c
++) {
2789 if (!(mask
& (1 << c
)))
2791 emit_mad(pc
, dst
[c
], src
[0][c
], src
[1][c
], src
[2][c
]);
2794 case TGSI_OPCODE_MAX
:
2795 for (c
= 0; c
< 4; c
++) {
2796 if (!(mask
& (1 << c
)))
2798 emit_minmax(pc
, 0x880, dst
[c
], src
[0][c
], src
[1][c
]);
2801 case TGSI_OPCODE_MIN
:
2802 for (c
= 0; c
< 4; c
++) {
2803 if (!(mask
& (1 << c
)))
2805 emit_minmax(pc
, 0x8a0, dst
[c
], src
[0][c
], src
[1][c
]);
2808 case TGSI_OPCODE_MOV
:
2809 for (c
= 0; c
< 4; c
++) {
2810 if (!(mask
& (1 << c
)))
2812 emit_mov(pc
, dst
[c
], src
[0][c
]);
2815 case TGSI_OPCODE_MUL
:
2816 for (c
= 0; c
< 4; c
++) {
2817 if (!(mask
& (1 << c
)))
2819 emit_mul(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2822 case TGSI_OPCODE_NOT
:
2823 for (c
= 0; c
< 4; c
++) {
2824 if (!(mask
& (1 << c
)))
2826 emit_not(pc
, dst
[c
], src
[0][c
]);
2829 case TGSI_OPCODE_POW
:
2830 emit_pow(pc
, brdc
, src
[0][0], src
[1][0]);
2832 case TGSI_OPCODE_RCP
:
2833 if (!sat
&& popcnt4(mask
) == 1)
2834 brdc
= dst
[ffs(mask
) - 1];
2835 emit_flop(pc
, NV50_FLOP_RCP
, brdc
, src
[0][0]);
2837 case TGSI_OPCODE_RET
:
2838 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
&& !pc
->in_subroutine
)
2839 nv50_fp_move_results(pc
);
2840 emit_ret(pc
, -1, 0);
2842 case TGSI_OPCODE_RSQ
:
2843 if (!sat
&& popcnt4(mask
) == 1)
2844 brdc
= dst
[ffs(mask
) - 1];
2845 src
[0][0]->mod
|= NV50_MOD_ABS
;
2846 emit_flop(pc
, NV50_FLOP_RSQ
, brdc
, src
[0][0]);
2848 case TGSI_OPCODE_SAD
:
2849 for (c
= 0; c
< 4; c
++) {
2850 if (!(mask
& (1 << c
)))
2852 emit_sad(pc
, dst
[c
], src
[0][c
], src
[1][c
], src
[2][c
]);
2855 case TGSI_OPCODE_SCS
:
2856 temp
= temp_temp(pc
, NULL
);
2858 emit_precossin(pc
, temp
, src
[0][0]);
2859 if (mask
& (1 << 0))
2860 emit_flop(pc
, NV50_FLOP_COS
, dst
[0], temp
);
2861 if (mask
& (1 << 1))
2862 emit_flop(pc
, NV50_FLOP_SIN
, dst
[1], temp
);
2863 if (mask
& (1 << 2))
2864 emit_mov_immdval(pc
, dst
[2], 0.0);
2865 if (mask
& (1 << 3))
2866 emit_mov_immdval(pc
, dst
[3], 1.0);
2868 case TGSI_OPCODE_SHL
:
2869 case TGSI_OPCODE_ISHR
:
2870 case TGSI_OPCODE_USHR
:
2871 for (c
= 0; c
< 4; c
++) {
2872 if (!(mask
& (1 << c
)))
2874 emit_shift(pc
, dst
[c
], src
[0][c
], src
[1][c
],
2875 inst
->Instruction
.Opcode
);
2878 case TGSI_OPCODE_SIN
:
2880 emit_precossin(pc
, temp
, src
[0][3]);
2881 emit_flop(pc
, NV50_FLOP_SIN
, dst
[3], temp
);
2885 temp
= brdc
= temp_temp(pc
, NULL
);
2887 emit_precossin(pc
, temp
, src
[0][0]);
2888 emit_flop(pc
, NV50_FLOP_SIN
, brdc
, temp
);
2890 case TGSI_OPCODE_SLT
:
2891 case TGSI_OPCODE_SGE
:
2892 case TGSI_OPCODE_SEQ
:
2893 case TGSI_OPCODE_SGT
:
2894 case TGSI_OPCODE_SLE
:
2895 case TGSI_OPCODE_SNE
:
2896 case TGSI_OPCODE_ISLT
:
2897 case TGSI_OPCODE_ISGE
:
2898 case TGSI_OPCODE_USEQ
:
2899 case TGSI_OPCODE_USGE
:
2900 case TGSI_OPCODE_USLT
:
2901 case TGSI_OPCODE_USNE
:
2905 map_tgsi_setop_hw(inst
->Instruction
.Opcode
, &cc
, &ty
);
2907 for (c
= 0; c
< 4; c
++) {
2908 if (!(mask
& (1 << c
)))
2910 emit_set(pc
, cc
, dst
[c
], -1, src
[0][c
], src
[1][c
], ty
);
2914 case TGSI_OPCODE_SUB
:
2915 for (c
= 0; c
< 4; c
++) {
2916 if (!(mask
& (1 << c
)))
2918 emit_sub(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2921 case TGSI_OPCODE_TEX
:
2922 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2923 inst
->Texture
.Texture
, FALSE
, 0);
2925 case TGSI_OPCODE_TXB
:
2926 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2927 inst
->Texture
.Texture
, FALSE
, -1);
2929 case TGSI_OPCODE_TXL
:
2930 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2931 inst
->Texture
.Texture
, FALSE
, 1);
2933 case TGSI_OPCODE_TXP
:
2934 emit_tex(pc
, dst
, mask
, src
[0], unit
,
2935 inst
->Texture
.Texture
, TRUE
, 0);
2937 case TGSI_OPCODE_TRUNC
:
2938 for (c
= 0; c
< 4; c
++) {
2939 if (!(mask
& (1 << c
)))
2941 emit_cvt(pc
, dst
[c
], src
[0][c
], -1,
2942 CVT_TRUNC
| CVT_F32_F32
| CVT_RI
);
2945 case TGSI_OPCODE_U2F
:
2946 for (c
= 0; c
< 4; c
++) {
2947 if (!(mask
& (1 << c
)))
2949 emit_cvt(pc
, dst
[c
], src
[0][c
], -1, CVT_F32_U32
);
2952 case TGSI_OPCODE_UADD
:
2953 for (c
= 0; c
< 4; c
++) {
2954 if (!(mask
& (1 << c
)))
2956 emit_add_b32(pc
, dst
[c
], src
[0][c
], src
[1][c
]);
2959 case TGSI_OPCODE_UMAX
:
2960 for (c
= 0; c
< 4; c
++) {
2961 if (!(mask
& (1 << c
)))
2963 emit_minmax(pc
, 0x084, dst
[c
], src
[0][c
], src
[1][c
]);
2966 case TGSI_OPCODE_UMIN
:
2967 for (c
= 0; c
< 4; c
++) {
2968 if (!(mask
& (1 << c
)))
2970 emit_minmax(pc
, 0x0a4, dst
[c
], src
[0][c
], src
[1][c
]);
2973 case TGSI_OPCODE_UMAD
:
2976 temp
= temp_temp(pc
, NULL
);
2977 for (c
= 0; c
< 4; c
++) {
2978 if (!(mask
& (1 << c
)))
2980 emit_mul_u16(pc
, temp
, src
[0][c
], 0, src
[1][c
], 1);
2981 emit_mad_u16(pc
, temp
, src
[0][c
], 1, src
[1][c
], 0,
2983 emit_shl_imm(pc
, temp
, temp
, 16);
2984 emit_mad_u16(pc
, temp
, src
[0][c
], 0, src
[1][c
], 0,
2986 emit_add_b32(pc
, dst
[c
], temp
, src
[2][c
]);
2990 case TGSI_OPCODE_UMUL
:
2993 temp
= temp_temp(pc
, NULL
);
2994 for (c
= 0; c
< 4; c
++) {
2995 if (!(mask
& (1 << c
)))
2997 emit_mul_u16(pc
, temp
, src
[0][c
], 0, src
[1][c
], 1);
2998 emit_mad_u16(pc
, temp
, src
[0][c
], 1, src
[1][c
], 0,
3000 emit_shl_imm(pc
, temp
, temp
, 16);
3001 emit_mad_u16(pc
, dst
[c
], src
[0][c
], 0, src
[1][c
], 0,
3006 case TGSI_OPCODE_XPD
:
3007 temp
= temp_temp(pc
, NULL
);
3008 if (mask
& (1 << 0)) {
3009 emit_mul(pc
, temp
, src
[0][2], src
[1][1]);
3010 emit_msb(pc
, dst
[0], src
[0][1], src
[1][2], temp
);
3012 if (mask
& (1 << 1)) {
3013 emit_mul(pc
, temp
, src
[0][0], src
[1][2]);
3014 emit_msb(pc
, dst
[1], src
[0][2], src
[1][0], temp
);
3016 if (mask
& (1 << 2)) {
3017 emit_mul(pc
, temp
, src
[0][1], src
[1][0]);
3018 emit_msb(pc
, dst
[2], src
[0][0], src
[1][1], temp
);
3020 if (mask
& (1 << 3))
3021 emit_mov_immdval(pc
, dst
[3], 1.0);
3023 case TGSI_OPCODE_END
:
3024 if (pc
->p
->type
== PIPE_SHADER_FRAGMENT
)
3025 nv50_fp_move_results(pc
);
3027 /* last insn must be long so it can have the exit bit set */
3028 if (!is_long(pc
->p
->exec_tail
))
3029 convert_to_long(pc
, pc
->p
->exec_tail
);
3031 if (is_immd(pc
->p
->exec_tail
) || is_join(pc
->p
->exec_tail
))
3034 pc
->p
->exec_tail
->inst
[1] |= 1; /* set exit bit */
3037 NOUVEAU_ERR("invalid opcode %d\n", inst
->Instruction
.Opcode
);
3043 emit_sat(pc
, brdc
, brdc
);
3044 for (c
= 0; c
< 4; c
++)
3045 if ((mask
& (1 << c
)) && dst
[c
] != brdc
)
3046 emit_mov(pc
, dst
[c
], brdc
);
3049 for (c
= 0; c
< 4; c
++) {
3050 if (!(mask
& (1 << c
)))
3052 /* In this case we saturate later, and dst[c] won't
3053 * be another temp_temp (and thus lost), since rdst
3054 * already is TEMP (see above). */
3055 if (rdst
[c
]->type
== P_TEMP
&& rdst
[c
]->index
< 0)
3057 emit_sat(pc
, rdst
[c
], dst
[c
]);
3061 kill_temp_temp(pc
, NULL
);
3062 pc
->reg_instance_nr
= 0;
3068 prep_inspect_insn(struct nv50_pc
*pc
, const struct tgsi_full_instruction
*insn
)
3070 struct nv50_reg
*r
, *reg
= NULL
;
3071 const struct tgsi_full_src_register
*src
;
3072 const struct tgsi_dst_register
*dst
;
3073 unsigned i
, c
, k
, mask
;
3075 dst
= &insn
->Dst
[0].Register
;
3076 mask
= dst
->WriteMask
;
3078 if (dst
->File
== TGSI_FILE_TEMPORARY
)
3081 if (dst
->File
== TGSI_FILE_OUTPUT
) {
3084 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_MOV
&&
3085 dst
->Index
== pc
->edgeflag_out
&&
3086 insn
->Src
[0].Register
.File
== TGSI_FILE_INPUT
)
3087 pc
->p
->cfg
.edgeflag_in
= insn
->Src
[0].Register
.Index
;
3091 for (c
= 0; c
< 4; c
++) {
3092 if (!(mask
& (1 << c
)))
3094 reg
[dst
->Index
* 4 + c
].acc
= pc
->insn_nr
;
3098 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
3099 src
= &insn
->Src
[i
];
3101 if (src
->Register
.File
== TGSI_FILE_TEMPORARY
)
3104 if (src
->Register
.File
== TGSI_FILE_INPUT
)
3109 mask
= nv50_tgsi_src_mask(insn
, i
);
3111 for (c
= 0; c
< 4; c
++) {
3112 if (!(mask
& (1 << c
)))
3114 k
= tgsi_util_get_full_src_register_swizzle(src
, c
);
3116 r
= ®
[src
->Register
.Index
* 4 + k
];
3118 /* If used before written, pre-allocate the reg,
3119 * lest we overwrite results from a subroutine.
3121 if (!r
->acc
&& r
->type
== P_TEMP
)
3124 r
->acc
= pc
->insn_nr
;
3129 /* Returns a bitmask indicating which dst components need to be
3130 * written to temporaries first to avoid 'corrupting' sources.
3132 * m[i] (out) indicate component to write in the i-th position
3133 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
3136 nv50_revdep_reorder(unsigned m
[4], unsigned rdep
[4])
3138 unsigned i
, c
, x
, unsafe
;
3140 for (c
= 0; c
< 4; c
++)
3143 /* Swap as long as a dst component written earlier is depended on
3144 * by one written later, but the next one isn't depended on by it.
3146 for (c
= 0; c
< 3; c
++) {
3147 if (rdep
[m
[c
+ 1]] & (1 << m
[c
]))
3148 continue; /* if next one is depended on by us */
3149 for (i
= c
+ 1; i
< 4; i
++)
3150 /* if we are depended on by a later one */
3151 if (rdep
[m
[c
]] & (1 << m
[i
]))
3164 /* mark dependencies that could not be resolved by reordering */
3165 for (i
= 0; i
< 3; ++i
)
3166 for (c
= i
+ 1; c
< 4; ++c
)
3167 if (rdep
[m
[i
]] & (1 << m
[c
]))
3170 /* NOTE: $unsafe is with respect to order, not component */
3174 /* Select a suitable dst register for broadcasting scalar results,
3175 * or return NULL if we have to allocate an extra TEMP.
3177 * If e.g. only 1 component is written, we may also emit the final
3178 * result to a write-only register.
3180 static struct nv50_reg
*
3181 tgsi_broadcast_dst(struct nv50_pc
*pc
,
3182 const struct tgsi_full_dst_register
*fd
, unsigned mask
)
3184 if (fd
->Register
.File
== TGSI_FILE_TEMPORARY
) {
3185 int c
= ffs(~mask
& fd
->Register
.WriteMask
);
3187 return tgsi_dst(pc
, c
- 1, fd
);
3189 int c
= ffs(fd
->Register
.WriteMask
) - 1;
3190 if ((1 << c
) == fd
->Register
.WriteMask
)
3191 return tgsi_dst(pc
, c
, fd
);
3197 /* Scan source swizzles and return a bitmask indicating dst regs that
3198 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
3201 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction
*insn
,
3204 const struct tgsi_full_dst_register
*fd
= &insn
->Dst
[0];
3205 const struct tgsi_full_src_register
*fs
;
3206 unsigned i
, deqs
= 0;
3208 for (i
= 0; i
< 4; ++i
)
3211 for (i
= 0; i
< insn
->Instruction
.NumSrcRegs
; i
++) {
3212 unsigned chn
, mask
= nv50_tgsi_src_mask(insn
, i
);
3213 int ms
= get_supported_mods(insn
, i
);
3216 if (fs
->Register
.File
!= fd
->Register
.File
||
3217 fs
->Register
.Index
!= fd
->Register
.Index
)
3220 for (chn
= 0; chn
< 4; ++chn
) {
3223 if (!(mask
& (1 << chn
))) /* src is not read */
3225 c
= tgsi_util_get_full_src_register_swizzle(fs
, chn
);
3226 s
= tgsi_util_get_full_src_register_sign_mode(fs
, chn
);
3228 if (!(fd
->Register
.WriteMask
& (1 << c
)))
3231 if (s
== TGSI_UTIL_SIGN_TOGGLE
&& !(ms
& NV50_MOD_NEG
))
3233 if (s
== TGSI_UTIL_SIGN_CLEAR
&& !(ms
& NV50_MOD_ABS
))
3235 if ((s
== TGSI_UTIL_SIGN_SET
) && ((ms
& 3) != 3))
3238 rdep
[c
] |= nv50_tgsi_dst_revdep(
3239 insn
->Instruction
.Opcode
, i
, chn
);
3248 nv50_tgsi_insn(struct nv50_pc
*pc
, const union tgsi_full_token
*tok
)
3250 struct tgsi_full_instruction insn
= tok
->FullInstruction
;
3251 const struct tgsi_full_dst_register
*fd
;
3252 unsigned i
, deqs
, rdep
[4], m
[4];
3254 fd
= &tok
->FullInstruction
.Dst
[0];
3255 deqs
= nv50_tgsi_scan_swizzle(&insn
, rdep
);
3257 if (is_scalar_op(insn
.Instruction
.Opcode
)) {
3258 pc
->r_brdc
= tgsi_broadcast_dst(pc
, fd
, deqs
);
3260 pc
->r_brdc
= temp_temp(pc
, NULL
);
3261 return nv50_program_tx_insn(pc
, &insn
);
3265 if (!deqs
|| (!rdep
[0] && !rdep
[1] && !rdep
[2] && !rdep
[3]))
3266 return nv50_program_tx_insn(pc
, &insn
);
3268 deqs
= nv50_revdep_reorder(m
, rdep
);
3270 for (i
= 0; i
< 4; ++i
) {
3271 assert(pc
->r_dst
[m
[i
]] == NULL
);
3273 insn
.Dst
[0].Register
.WriteMask
=
3274 fd
->Register
.WriteMask
& (1 << m
[i
]);
3276 if (!insn
.Dst
[0].Register
.WriteMask
)
3279 if (deqs
& (1 << i
))
3280 pc
->r_dst
[m
[i
]] = alloc_temp(pc
, NULL
);
3282 if (!nv50_program_tx_insn(pc
, &insn
))
3286 for (i
= 0; i
< 4; i
++) {
3287 struct nv50_reg
*reg
= pc
->r_dst
[i
];
3290 pc
->r_dst
[i
] = NULL
;
3292 if (insn
.Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
)
3293 emit_sat(pc
, tgsi_dst(pc
, i
, fd
), reg
);
3295 emit_mov(pc
, tgsi_dst(pc
, i
, fd
), reg
);
3303 load_interpolant(struct nv50_pc
*pc
, struct nv50_reg
*reg
)
3305 struct nv50_reg
*iv
, **ppiv
;
3306 unsigned mode
= pc
->interp_mode
[reg
->index
];
3308 ppiv
= (mode
& INTERP_CENTROID
) ? &pc
->iv_c
: &pc
->iv_p
;
3311 if ((mode
& INTERP_PERSPECTIVE
) && !iv
) {
3312 iv
= *ppiv
= alloc_temp(pc
, NULL
);
3313 iv
->rhw
= popcnt4(pc
->p
->cfg
.regs
[1] >> 24) - 1;
3315 emit_interp(pc
, iv
, NULL
, mode
& INTERP_CENTROID
);
3316 emit_flop(pc
, NV50_FLOP_RCP
, iv
, iv
);
3318 /* XXX: when loading interpolants dynamically, move these
3319 * to the program head, or make sure it can't be skipped.
3323 emit_interp(pc
, reg
, iv
, mode
);
3326 /* The face input is always at v[255] (varying space), with a
3327 * value of 0 for back-facing, and 0xffffffff for front-facing.
3330 load_frontfacing(struct nv50_pc
*pc
, struct nv50_reg
*a
)
3332 struct nv50_reg
*one
= alloc_immd(pc
, 1.0f
);
3334 assert(a
->rhw
== -1);
3335 alloc_reg(pc
, a
); /* do this before rhw is set */
3337 load_interpolant(pc
, a
);
3338 emit_bitop2(pc
, a
, a
, one
, TGSI_OPCODE_AND
);
3344 nv50_program_tx_prep(struct nv50_pc
*pc
)
3346 struct tgsi_parse_context tp
;
3347 struct nv50_program
*p
= pc
->p
;
3348 boolean ret
= FALSE
;
3349 unsigned i
, c
, flat_nr
= 0;
3351 tgsi_parse_init(&tp
, pc
->p
->pipe
.tokens
);
3352 while (!tgsi_parse_end_of_tokens(&tp
)) {
3353 const union tgsi_full_token
*tok
= &tp
.FullToken
;
3355 tgsi_parse_token(&tp
);
3356 switch (tok
->Token
.Type
) {
3357 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3359 const struct tgsi_full_immediate
*imm
=
3360 &tp
.FullToken
.FullImmediate
;
3362 ctor_immd_4f32(pc
, imm
->u
[0].Float
,
3368 case TGSI_TOKEN_TYPE_DECLARATION
:
3370 const struct tgsi_full_declaration
*d
;
3371 unsigned si
, last
, first
, mode
;
3373 d
= &tp
.FullToken
.FullDeclaration
;
3374 first
= d
->Range
.First
;
3375 last
= d
->Range
.Last
;
3377 switch (d
->Declaration
.File
) {
3378 case TGSI_FILE_TEMPORARY
:
3380 case TGSI_FILE_OUTPUT
:
3381 if (!d
->Declaration
.Semantic
||
3382 p
->type
== PIPE_SHADER_FRAGMENT
)
3385 si
= d
->Semantic
.Index
;
3386 switch (d
->Semantic
.Name
) {
3387 case TGSI_SEMANTIC_BCOLOR
:
3388 p
->cfg
.two_side
[si
].hw
= first
;
3389 if (p
->cfg
.io_nr
> first
)
3390 p
->cfg
.io_nr
= first
;
3392 case TGSI_SEMANTIC_PSIZE
:
3393 p
->cfg
.psiz
= first
;
3394 if (p
->cfg
.io_nr
> first
)
3395 p
->cfg
.io_nr
= first
;
3397 case TGSI_SEMANTIC_EDGEFLAG
:
3398 pc
->edgeflag_out
= first
;
3401 case TGSI_SEMANTIC_CLIP_DISTANCE:
3402 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3409 case TGSI_FILE_INPUT
:
3411 if (p
->type
!= PIPE_SHADER_FRAGMENT
)
3414 switch (d
->Declaration
.Interpolate
) {
3415 case TGSI_INTERPOLATE_CONSTANT
:
3419 case TGSI_INTERPOLATE_PERSPECTIVE
:
3420 mode
= INTERP_PERSPECTIVE
;
3421 p
->cfg
.regs
[1] |= 0x08 << 24;
3424 mode
= INTERP_LINEAR
;
3427 if (d
->Declaration
.Centroid
)
3428 mode
|= INTERP_CENTROID
;
3431 for (i
= first
; i
<= last
; i
++)
3432 pc
->interp_mode
[i
] = mode
;
3435 case TGSI_FILE_ADDRESS
:
3436 case TGSI_FILE_CONSTANT
:
3437 case TGSI_FILE_SAMPLER
:
3440 NOUVEAU_ERR("bad decl file %d\n",
3441 d
->Declaration
.File
);
3446 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3448 prep_inspect_insn(pc
, &tok
->FullInstruction
);
3455 if (p
->type
== PIPE_SHADER_VERTEX
) {
3458 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
) {
3459 if (pc
->attr
[i
].acc
) {
3460 pc
->attr
[i
].hw
= rid
++;
3461 p
->cfg
.attr
[i
/ 32] |= 1 << (i
% 32);
3465 for (i
= 0, rid
= 0; i
< pc
->result_nr
; ++i
) {
3466 p
->cfg
.io
[i
].hw
= rid
;
3467 p
->cfg
.io
[i
].id
= i
;
3469 for (c
= 0; c
< 4; ++c
) {
3471 if (!pc
->result
[n
].acc
)
3473 pc
->result
[n
].hw
= rid
++;
3474 p
->cfg
.io
[i
].mask
|= 1 << c
;
3478 for (c
= 0; c
< 2; ++c
)
3479 if (p
->cfg
.two_side
[c
].hw
< 0x40)
3480 p
->cfg
.two_side
[c
] = p
->cfg
.io
[
3481 p
->cfg
.two_side
[c
].hw
];
3483 if (p
->cfg
.psiz
< 0x40)
3484 p
->cfg
.psiz
= p
->cfg
.io
[p
->cfg
.psiz
].hw
;
3486 if (p
->type
== PIPE_SHADER_FRAGMENT
) {
3488 unsigned n
= 0, m
= pc
->attr_nr
- flat_nr
;
3492 int base
= (TGSI_SEMANTIC_POSITION
==
3493 p
->info
.input_semantic_name
[0]) ? 0 : 1;
3495 /* non-flat interpolants have to be mapped to
3496 * the lower hardware IDs, so sort them:
3498 for (i
= 0; i
< pc
->attr_nr
; i
++) {
3499 if (pc
->interp_mode
[i
] == INTERP_FLAT
)
3500 p
->cfg
.io
[m
++].id
= i
;
3502 if (!(pc
->interp_mode
[i
] & INTERP_PERSPECTIVE
))
3503 p
->cfg
.io
[n
].linear
= TRUE
;
3504 p
->cfg
.io
[n
++].id
= i
;
3508 if (!base
) /* set w-coordinate mask from perspective interp */
3509 p
->cfg
.io
[0].mask
|= p
->cfg
.regs
[1] >> 24;
3511 aid
= popcnt4( /* if fcrd isn't contained in cfg.io */
3512 base
? (p
->cfg
.regs
[1] >> 24) : p
->cfg
.io
[0].mask
);
3514 for (n
= 0; n
< pc
->attr_nr
; ++n
) {
3515 p
->cfg
.io
[n
].hw
= rid
= aid
;
3516 i
= p
->cfg
.io
[n
].id
;
3518 if (p
->info
.input_semantic_name
[n
] ==
3519 TGSI_SEMANTIC_FACE
) {
3520 load_frontfacing(pc
, &pc
->attr
[i
* 4]);
3524 for (c
= 0; c
< 4; ++c
) {
3525 if (!pc
->attr
[i
* 4 + c
].acc
)
3527 pc
->attr
[i
* 4 + c
].rhw
= rid
++;
3528 p
->cfg
.io
[n
].mask
|= 1 << c
;
3530 load_interpolant(pc
, &pc
->attr
[i
* 4 + c
]);
3532 aid
+= popcnt4(p
->cfg
.io
[n
].mask
);
3536 p
->cfg
.regs
[1] |= p
->cfg
.io
[0].mask
<< 24;
3538 m
= popcnt4(p
->cfg
.regs
[1] >> 24);
3540 /* set count of non-position inputs and of non-flat
3541 * non-position inputs for FP_INTERPOLANT_CTRL
3543 p
->cfg
.regs
[1] |= aid
- m
;
3546 i
= p
->cfg
.io
[pc
->attr_nr
- flat_nr
].hw
;
3547 p
->cfg
.regs
[1] |= (i
- m
) << 16;
3549 p
->cfg
.regs
[1] |= p
->cfg
.regs
[1] << 16;
3551 /* mark color semantic for light-twoside */
3553 for (i
= 0; i
< pc
->attr_nr
; i
++) {
3556 sn
= p
->info
.input_semantic_name
[p
->cfg
.io
[i
].id
];
3557 si
= p
->info
.input_semantic_index
[p
->cfg
.io
[i
].id
];
3559 if (sn
== TGSI_SEMANTIC_COLOR
) {
3560 p
->cfg
.two_side
[si
] = p
->cfg
.io
[i
];
3562 /* increase colour count */
3563 p
->cfg
.regs
[0] += popcnt4(
3564 p
->cfg
.two_side
[si
].mask
) << 16;
3566 n
= MIN2(n
, p
->cfg
.io
[i
].hw
- m
);
3570 p
->cfg
.regs
[0] += n
;
3572 /* Initialize FP results:
3573 * FragDepth is always first TGSI and last hw output
3575 i
= p
->info
.writes_z
? 4 : 0;
3576 for (rid
= 0; i
< pc
->result_nr
* 4; i
++)
3577 pc
->result
[i
].rhw
= rid
++;
3578 if (p
->info
.writes_z
)
3579 pc
->result
[2].rhw
= rid
;
3581 p
->cfg
.high_result
= rid
;
3583 /* separate/different colour results for MRTs ? */
3584 if (pc
->result_nr
- (p
->info
.writes_z
? 1 : 0) > 1)
3585 p
->cfg
.regs
[2] |= 1;
3591 pc
->immd
= MALLOC(pc
->immd_nr
* 4 * sizeof(struct nv50_reg
));
3595 for (i
= 0; i
< pc
->immd_nr
; i
++) {
3596 for (c
= 0; c
< 4; c
++, rid
++)
3597 ctor_reg(&pc
->immd
[rid
], P_IMMD
, i
, rid
);
3604 free_temp(pc
, pc
->iv_p
);
3606 free_temp(pc
, pc
->iv_c
);
3608 tgsi_parse_free(&tp
);
3613 free_nv50_pc(struct nv50_pc
*pc
)
3630 ctor_nv50_pc(struct nv50_pc
*pc
, struct nv50_program
*p
)
3633 unsigned rtype
[2] = { P_ATTR
, P_RESULT
};
3636 pc
->temp_nr
= p
->info
.file_max
[TGSI_FILE_TEMPORARY
] + 1;
3637 pc
->attr_nr
= p
->info
.file_max
[TGSI_FILE_INPUT
] + 1;
3638 pc
->result_nr
= p
->info
.file_max
[TGSI_FILE_OUTPUT
] + 1;
3639 pc
->param_nr
= p
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
3640 pc
->addr_nr
= p
->info
.file_max
[TGSI_FILE_ADDRESS
] + 1;
3641 assert(pc
->addr_nr
<= 2);
3643 p
->cfg
.high_temp
= 4;
3645 p
->cfg
.two_side
[0].hw
= 0x40;
3646 p
->cfg
.two_side
[1].hw
= 0x40;
3648 p
->cfg
.edgeflag_in
= pc
->edgeflag_out
= 0xff;
3651 case PIPE_SHADER_VERTEX
:
3654 p
->cfg
.io_nr
= pc
->result_nr
;
3656 case PIPE_SHADER_FRAGMENT
:
3657 rtype
[0] = rtype
[1] = P_TEMP
;
3659 p
->cfg
.regs
[0] = 0x01000004;
3660 p
->cfg
.io_nr
= pc
->attr_nr
;
3662 if (p
->info
.writes_z
) {
3663 p
->cfg
.regs
[2] |= 0x00000100;
3664 p
->cfg
.regs
[3] |= 0x00000011;
3666 if (p
->info
.uses_kill
)
3667 p
->cfg
.regs
[2] |= 0x00100000;
3672 pc
->temp
= MALLOC(pc
->temp_nr
* 4 * sizeof(struct nv50_reg
));
3676 for (i
= 0; i
< pc
->temp_nr
* 4; ++i
)
3677 ctor_reg(&pc
->temp
[i
], P_TEMP
, i
/ 4, -1);
3681 pc
->attr
= MALLOC(pc
->attr_nr
* 4 * sizeof(struct nv50_reg
));
3685 for (i
= 0; i
< pc
->attr_nr
* 4; ++i
)
3686 ctor_reg(&pc
->attr
[i
], rtype
[0], i
/ 4, -1);
3689 if (pc
->result_nr
) {
3690 unsigned nr
= pc
->result_nr
* 4;
3692 pc
->result
= MALLOC(nr
* sizeof(struct nv50_reg
));
3696 for (i
= 0; i
< nr
; ++i
)
3697 ctor_reg(&pc
->result
[i
], rtype
[1], i
/ 4, -1);
3703 pc
->param
= MALLOC(pc
->param_nr
* 4 * sizeof(struct nv50_reg
));
3707 for (i
= 0; i
< pc
->param_nr
; ++i
)
3708 for (c
= 0; c
< 4; ++c
, ++rid
)
3709 ctor_reg(&pc
->param
[rid
], P_CONST
, i
, rid
);
3713 pc
->addr
= CALLOC(pc
->addr_nr
* 4, sizeof(struct nv50_reg
*));
3717 for (i
= 0; i
< NV50_SU_MAX_ADDR
; ++i
)
3718 ctor_reg(&pc
->r_addr
[i
], P_ADDR
, -256, i
+ 1);
3724 nv50_program_fixup_insns(struct nv50_pc
*pc
)
3726 struct nv50_program_exec
*e
, **bra_list
;
3729 bra_list
= CALLOC(pc
->p
->exec_size
, sizeof(struct nv50_program_exec
*));
3731 /* Collect branch instructions, we need to adjust their offsets
3732 * when converting 32 bit instructions to 64 bit ones
3734 for (n
= 0, e
= pc
->p
->exec_head
; e
; e
= e
->next
)
3735 if (e
->param
.index
>= 0 && !e
->param
.mask
)
3738 /* Make sure we don't have any single 32 bit instructions. */
3739 for (e
= pc
->p
->exec_head
, pos
= 0; e
; e
= e
->next
) {
3740 pos
+= is_long(e
) ? 2 : 1;
3742 if ((pos
& 1) && (!e
->next
|| is_long(e
->next
))) {
3743 for (i
= 0; i
< n
; ++i
)
3744 if (bra_list
[i
]->param
.index
>= pos
)
3745 bra_list
[i
]->param
.index
+= 1;
3746 for (i
= 0; i
< pc
->insn_nr
; ++i
)
3747 if (pc
->insn_pos
[i
] >= pos
)
3748 pc
->insn_pos
[i
] += 1;
3749 convert_to_long(pc
, e
);
3756 if (!pc
->p
->info
.opcode_count
[TGSI_OPCODE_CAL
])
3759 /* fill in CALL offsets */
3760 for (e
= pc
->p
->exec_head
; e
; e
= e
->next
) {
3761 if ((e
->inst
[0] & 2) && (e
->inst
[0] >> 28) == 0x2)
3762 e
->param
.index
= pc
->insn_pos
[e
->param
.index
];
3767 nv50_program_tx(struct nv50_program
*p
)
3769 struct tgsi_parse_context parse
;
3773 pc
= CALLOC_STRUCT(nv50_pc
);
3777 ret
= ctor_nv50_pc(pc
, p
);
3781 ret
= nv50_program_tx_prep(pc
);
3785 pc
->insn_pos
= MALLOC(pc
->insn_nr
* sizeof(unsigned));
3787 tgsi_parse_init(&parse
, pc
->p
->pipe
.tokens
);
3788 while (!tgsi_parse_end_of_tokens(&parse
)) {
3789 const union tgsi_full_token
*tok
= &parse
.FullToken
;
3791 /* previously allow32 was FALSE for first & last instruction */
3794 tgsi_parse_token(&parse
);
3796 switch (tok
->Token
.Type
) {
3797 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3798 pc
->insn_pos
[pc
->insn_cur
] = pc
->p
->exec_size
;
3800 ret
= nv50_tgsi_insn(pc
, tok
);
3809 nv50_program_fixup_insns(pc
);
3811 p
->param_nr
= pc
->param_nr
* 4;
3812 p
->immd_nr
= pc
->immd_nr
* 4;
3813 p
->immd
= pc
->immd_buf
;
3816 tgsi_parse_free(&parse
);
3824 nv50_program_validate(struct nv50_context
*nv50
, struct nv50_program
*p
)
3826 if (nv50_program_tx(p
) == FALSE
)
3828 p
->translated
= TRUE
;
3832 nv50_program_upload_data(struct nv50_context
*nv50
, uint32_t *map
,
3833 unsigned start
, unsigned count
, unsigned cbuf
)
3835 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
3836 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3839 unsigned nr
= count
> 2047 ? 2047 : count
;
3841 BEGIN_RING(chan
, tesla
, NV50TCL_CB_ADDR
, 1);
3842 OUT_RING (chan
, (cbuf
<< 0) | (start
<< 8));
3843 BEGIN_RING(chan
, tesla
, NV50TCL_CB_DATA(0) | 0x40000000, nr
);
3844 OUT_RINGp (chan
, map
, nr
);
3853 nv50_program_validate_data(struct nv50_context
*nv50
, struct nv50_program
*p
)
3855 struct pipe_screen
*pscreen
= nv50
->pipe
.screen
;
3857 if (!p
->data
[0] && p
->immd_nr
) {
3858 struct nouveau_resource
*heap
= nv50
->screen
->immd_heap
[0];
3860 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
, &p
->data
[0])) {
3861 while (heap
->next
&& heap
->size
< p
->immd_nr
) {
3862 struct nv50_program
*evict
= heap
->next
->priv
;
3863 nouveau_resource_free(&evict
->data
[0]);
3866 if (nouveau_resource_alloc(heap
, p
->immd_nr
, p
,
3871 /* immediates only need to be uploaded again when freed */
3872 nv50_program_upload_data(nv50
, p
->immd
, p
->data
[0]->start
,
3873 p
->immd_nr
, NV50_CB_PMISC
);
3876 assert(p
->param_nr
<= 512);
3880 uint32_t *map
= pipe_buffer_map(pscreen
, nv50
->constbuf
[p
->type
],
3881 PIPE_BUFFER_USAGE_CPU_READ
);
3883 if (p
->type
== PIPE_SHADER_VERTEX
)
3888 nv50_program_upload_data(nv50
, map
, 0, p
->param_nr
, cb
);
3889 pipe_buffer_unmap(pscreen
, nv50
->constbuf
[p
->type
]);
3894 nv50_program_validate_code(struct nv50_context
*nv50
, struct nv50_program
*p
)
3896 struct nouveau_channel
*chan
= nv50
->screen
->base
.channel
;
3897 struct nv50_program_exec
*e
;
3899 boolean upload
= FALSE
;
3902 nouveau_bo_new(chan
->device
, NOUVEAU_BO_VRAM
, 0x100,
3903 p
->exec_size
* 4, &p
->bo
);
3907 if (p
->data
[0] && p
->data
[0]->start
!= p
->data_start
[0])
3913 up
= MALLOC(p
->exec_size
* 4);
3915 for (i
= 0, e
= p
->exec_head
; e
; e
= e
->next
) {
3916 unsigned ei
, ci
, bs
;
3918 if (e
->param
.index
>= 0 && e
->param
.mask
) {
3919 bs
= (e
->inst
[1] >> 22) & 0x07;
3921 ei
= e
->param
.shift
>> 5;
3922 ci
= e
->param
.index
;
3924 ci
+= p
->data
[bs
]->start
;
3926 e
->inst
[ei
] &= ~e
->param
.mask
;
3927 e
->inst
[ei
] |= (ci
<< e
->param
.shift
);
3929 if (e
->param
.index
>= 0) {
3930 /* zero mask means param is a jump/branch offset */
3931 assert(!(e
->param
.index
& 1));
3932 /* seem to be 8 byte steps */
3933 ei
= (e
->param
.index
>> 1) + 0 /* START_ID */;
3935 e
->inst
[0] &= 0xf0000fff;
3936 e
->inst
[0] |= ei
<< 12;
3939 up
[i
++] = e
->inst
[0];
3941 up
[i
++] = e
->inst
[1];
3943 assert(i
== p
->exec_size
);
3946 p
->data_start
[0] = p
->data
[0]->start
;
3948 #ifdef NV50_PROGRAM_DUMP
3949 NOUVEAU_ERR("-------\n");
3950 for (e
= p
->exec_head
; e
; e
= e
->next
) {
3951 NOUVEAU_ERR("0x%08x\n", e
->inst
[0]);
3953 NOUVEAU_ERR("0x%08x\n", e
->inst
[1]);
3956 nv50_upload_sifc(nv50
, p
->bo
, 0, NOUVEAU_BO_VRAM
,
3957 NV50_2D_DST_FORMAT_R8_UNORM
, 65536, 1, 262144,
3958 up
, NV50_2D_SIFC_FORMAT_R8_UNORM
, 0,
3959 0, 0, p
->exec_size
* 4, 1, 1);
3965 nv50_vertprog_validate(struct nv50_context
*nv50
)
3967 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
3968 struct nv50_program
*p
= nv50
->vertprog
;
3969 struct nouveau_stateobj
*so
;
3971 if (!p
->translated
) {
3972 nv50_program_validate(nv50
, p
);
3977 nv50_program_validate_data(nv50
, p
);
3978 nv50_program_validate_code(nv50
, p
);
3980 so
= so_new(5, 8, 2);
3981 so_method(so
, tesla
, NV50TCL_VP_ADDRESS_HIGH
, 2);
3982 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3983 NOUVEAU_BO_HIGH
, 0, 0);
3984 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
3985 NOUVEAU_BO_LOW
, 0, 0);
3986 so_method(so
, tesla
, NV50TCL_VP_ATTR_EN_0
, 2);
3987 so_data (so
, p
->cfg
.attr
[0]);
3988 so_data (so
, p
->cfg
.attr
[1]);
3989 so_method(so
, tesla
, NV50TCL_VP_REG_ALLOC_RESULT
, 1);
3990 so_data (so
, p
->cfg
.high_result
);
3991 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 2);
3992 so_data (so
, p
->cfg
.high_result
); //8);
3993 so_data (so
, p
->cfg
.high_temp
);
3994 so_method(so
, tesla
, NV50TCL_VP_START_ID
, 1);
3995 so_data (so
, 0); /* program start offset */
3996 so_ref(so
, &nv50
->state
.vertprog
);
4001 nv50_fragprog_validate(struct nv50_context
*nv50
)
4003 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
4004 struct nv50_program
*p
= nv50
->fragprog
;
4005 struct nouveau_stateobj
*so
;
4007 if (!p
->translated
) {
4008 nv50_program_validate(nv50
, p
);
4013 nv50_program_validate_data(nv50
, p
);
4014 nv50_program_validate_code(nv50
, p
);
4016 so
= so_new(6, 7, 2);
4017 so_method(so
, tesla
, NV50TCL_FP_ADDRESS_HIGH
, 2);
4018 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
4019 NOUVEAU_BO_HIGH
, 0, 0);
4020 so_reloc (so
, p
->bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
|
4021 NOUVEAU_BO_LOW
, 0, 0);
4022 so_method(so
, tesla
, NV50TCL_FP_REG_ALLOC_TEMP
, 1);
4023 so_data (so
, p
->cfg
.high_temp
);
4024 so_method(so
, tesla
, NV50TCL_FP_RESULT_COUNT
, 1);
4025 so_data (so
, p
->cfg
.high_result
);
4026 so_method(so
, tesla
, NV50TCL_FP_CONTROL
, 1);
4027 so_data (so
, p
->cfg
.regs
[2]);
4028 so_method(so
, tesla
, NV50TCL_FP_CTRL_UNK196C
, 1);
4029 so_data (so
, p
->cfg
.regs
[3]);
4030 so_method(so
, tesla
, NV50TCL_FP_START_ID
, 1);
4031 so_data (so
, 0); /* program start offset */
4032 so_ref(so
, &nv50
->state
.fragprog
);
4037 nv50_pntc_replace(struct nv50_context
*nv50
, uint32_t pntc
[8], unsigned base
)
4039 struct nv50_program
*fp
= nv50
->fragprog
;
4040 struct nv50_program
*vp
= nv50
->vertprog
;
4041 unsigned i
, c
, m
= base
;
4042 uint32_t origin
= 0x00000010;
4044 /* XXX: this might not work correctly in all cases yet - we'll
4045 * just assume that an FP generic input that is not written in
4046 * the VP is PointCoord.
4048 memset(pntc
, 0, 8 * sizeof(uint32_t));
4050 for (i
= 0; i
< fp
->cfg
.io_nr
; i
++) {
4052 uint8_t j
, k
= fp
->cfg
.io
[i
].id
;
4053 unsigned n
= popcnt4(fp
->cfg
.io
[i
].mask
);
4055 if (fp
->info
.input_semantic_name
[k
] != TGSI_SEMANTIC_GENERIC
) {
4060 for (j
= 0; j
< vp
->info
.num_outputs
; ++j
) {
4061 sn
= vp
->info
.output_semantic_name
[j
];
4062 si
= vp
->info
.output_semantic_index
[j
];
4064 if (sn
== fp
->info
.input_semantic_name
[k
] &&
4065 si
== fp
->info
.input_semantic_index
[k
])
4069 if (j
< vp
->info
.num_outputs
) {
4071 nv50
->rasterizer
->pipe
.sprite_coord_mode
[si
];
4073 if (mode
== PIPE_SPRITE_COORD_NONE
) {
4077 if (mode
== PIPE_SPRITE_COORD_LOWER_LEFT
)
4081 /* this is either PointCoord or replaced by sprite coords */
4082 for (c
= 0; c
< 4; c
++) {
4083 if (!(fp
->cfg
.io
[i
].mask
& (1 << c
)))
4085 pntc
[m
/ 8] |= (c
+ 1) << ((m
% 8) * 4);
4093 nv50_sreg4_map(uint32_t *p_map
, int mid
, uint32_t lin
[4],
4094 struct nv50_sreg4
*fpi
, struct nv50_sreg4
*vpo
)
4097 uint8_t mv
= vpo
->mask
, mf
= fpi
->mask
, oid
= vpo
->hw
;
4098 uint8_t *map
= (uint8_t *)p_map
;
4100 for (c
= 0; c
< 4; ++c
) {
4102 if (fpi
->linear
== TRUE
)
4103 lin
[mid
/ 32] |= 1 << (mid
% 32);
4104 map
[mid
++] = (mv
& 1) ? oid
: ((c
== 3) ? 0x41 : 0x40);
4116 nv50_linkage_validate(struct nv50_context
*nv50
)
4118 struct nouveau_grobj
*tesla
= nv50
->screen
->tesla
;
4119 struct nv50_program
*vp
= nv50
->vertprog
;
4120 struct nv50_program
*fp
= nv50
->fragprog
;
4121 struct nouveau_stateobj
*so
;
4122 struct nv50_sreg4 dummy
, *vpo
;
4124 uint32_t map
[16], lin
[4], reg
[5], pcrd
[8];
4126 memset(map
, 0, sizeof(map
));
4127 memset(lin
, 0, sizeof(lin
));
4129 reg
[1] = 0x00000004; /* low and high clip distance map ids */
4130 reg
[2] = 0x00000000; /* layer index map id (disabled, GP only) */
4131 reg
[3] = 0x00000000; /* point size map id & enable */
4132 reg
[0] = fp
->cfg
.regs
[0]; /* colour semantic reg */
4133 reg
[4] = fp
->cfg
.regs
[1]; /* interpolant info */
4135 dummy
.linear
= FALSE
;
4136 dummy
.mask
= 0xf; /* map all components of HPOS */
4137 m
= nv50_sreg4_map(map
, m
, lin
, &dummy
, &vp
->cfg
.io
[0]);
4141 if (vp
->cfg
.clpd
< 0x40) {
4142 for (c
= 0; c
< vp
->cfg
.clpd_nr
; ++c
)
4143 map
[m
++] = vp
->cfg
.clpd
+ c
;
4147 reg
[0] |= m
<< 8; /* adjust BFC0 id */
4149 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
4150 if (nv50
->rasterizer
->pipe
.light_twoside
) {
4151 vpo
= &vp
->cfg
.two_side
[0];
4153 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[0], &vpo
[0]);
4154 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.two_side
[1], &vpo
[1]);
4157 reg
[0] += m
- 4; /* adjust FFC0 id */
4158 reg
[4] |= m
<< 8; /* set mid where 'normal' FP inputs start */
4160 for (i
= 0; i
< fp
->cfg
.io_nr
; i
++) {
4161 ubyte sn
= fp
->info
.input_semantic_name
[fp
->cfg
.io
[i
].id
];
4162 ubyte si
= fp
->info
.input_semantic_index
[fp
->cfg
.io
[i
].id
];
4164 /* position must be mapped first */
4165 assert(i
== 0 || sn
!= TGSI_SEMANTIC_POSITION
);
4167 /* maybe even remove these from cfg.io */
4168 if (sn
== TGSI_SEMANTIC_POSITION
|| sn
== TGSI_SEMANTIC_FACE
)
4171 /* VP outputs and vp->cfg.io are in the same order */
4172 for (n
= 0; n
< vp
->info
.num_outputs
; ++n
) {
4173 if (vp
->info
.output_semantic_name
[n
] == sn
&&
4174 vp
->info
.output_semantic_index
[n
] == si
)
4177 vpo
= (n
< vp
->info
.num_outputs
) ? &vp
->cfg
.io
[n
] : &dummy
;
4179 m
= nv50_sreg4_map(map
, m
, lin
, &fp
->cfg
.io
[i
], vpo
);
4182 if (nv50
->rasterizer
->pipe
.point_size_per_vertex
) {
4183 map
[m
/ 4] |= vp
->cfg
.psiz
<< ((m
% 4) * 8);
4184 reg
[3] = (m
++ << 4) | 1;
4187 /* now fill the stateobj */
4188 so
= so_new(7, 57, 0);
4191 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP_SIZE
, 1);
4193 so_method(so
, tesla
, NV50TCL_VP_RESULT_MAP(0), n
);
4194 so_datap (so
, map
, n
);
4196 so_method(so
, tesla
, NV50TCL_MAP_SEMANTIC_0
, 4);
4197 so_datap (so
, reg
, 4);
4199 so_method(so
, tesla
, NV50TCL_FP_INTERPOLANT_CTRL
, 1);
4200 so_data (so
, reg
[4]);
4202 so_method(so
, tesla
, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
4203 so_datap (so
, lin
, 4);
4205 if (nv50
->rasterizer
->pipe
.point_sprite
) {
4206 so_method(so
, tesla
, NV50TCL_POINT_SPRITE_CTRL
, 1);
4208 nv50_pntc_replace(nv50
, pcrd
, (reg
[4] >> 8) & 0xff));
4210 so_method(so
, tesla
, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
4211 so_datap (so
, pcrd
, 8);
4214 so_ref(so
, &nv50
->state
.programs
);
4219 nv50_program_destroy(struct nv50_context
*nv50
, struct nv50_program
*p
)
4221 while (p
->exec_head
) {
4222 struct nv50_program_exec
*e
= p
->exec_head
;
4224 p
->exec_head
= e
->next
;
4227 p
->exec_tail
= NULL
;
4230 nouveau_bo_ref(NULL
, &p
->bo
);
4232 nouveau_resource_free(&p
->data
[0]);