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Merge commit 'origin/gallium-draw-retval'
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_SAT 4
100
101 /* STACK: Conditionals and loops have to use the (per warp) stack.
102 * Stack entries consist of an entry type (divergent path, join at),
103 * a mask indicating the active threads of the warp, and an address.
104 * MPs can store 12 stack entries internally, if we need more (and
105 * we probably do), we have to create a stack buffer in VRAM.
106 */
107 /* impose low limits for now */
108 #define NV50_MAX_COND_NESTING 4
109 #define NV50_MAX_LOOP_NESTING 3
110
111 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
112
113 struct nv50_pc {
114 struct nv50_program *p;
115
116 /* hw resources */
117 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
118 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
119
120 /* tgsi resources */
121 struct nv50_reg *temp;
122 int temp_nr;
123 struct nv50_reg *attr;
124 int attr_nr;
125 struct nv50_reg *result;
126 int result_nr;
127 struct nv50_reg *param;
128 int param_nr;
129 struct nv50_reg *immd;
130 uint32_t *immd_buf;
131 int immd_nr;
132 struct nv50_reg **addr;
133 int addr_nr;
134 uint8_t addr_alloc; /* set bit indicates used for TGSI_FILE_ADDRESS */
135
136 struct nv50_reg *temp_temp[16];
137 unsigned temp_temp_nr;
138
139 /* broadcast and destination replacement regs */
140 struct nv50_reg *r_brdc;
141 struct nv50_reg *r_dst[4];
142
143 struct nv50_reg reg_instances[16];
144 unsigned reg_instance_nr;
145
146 unsigned interp_mode[32];
147 /* perspective interpolation registers */
148 struct nv50_reg *iv_p;
149 struct nv50_reg *iv_c;
150
151 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
152 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
153 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
154 int if_lvl, loop_lvl;
155 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
156
157 unsigned *insn_pos; /* actual program offset of each TGSI insn */
158 boolean in_subroutine;
159
160 /* current instruction and total number of insns */
161 unsigned insn_cur;
162 unsigned insn_nr;
163
164 boolean allow32;
165
166 uint8_t edgeflag_out;
167 };
168
169 static INLINE void
170 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
171 {
172 reg->type = type;
173 reg->index = index;
174 reg->hw = hw;
175 reg->mod = 0;
176 reg->rhw = -1;
177 reg->acc = 0;
178 }
179
180 static INLINE unsigned
181 popcnt4(uint32_t val)
182 {
183 static const unsigned cnt[16]
184 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
185 return cnt[val & 0xf];
186 }
187
188 static void
189 terminate_mbb(struct nv50_pc *pc)
190 {
191 int i;
192
193 /* remove records of temporary address register values */
194 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
195 pc->r_addr[i].rhw = -1;
196 }
197
198 static void
199 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
200 {
201 int i = 0;
202
203 if (reg->type == P_RESULT) {
204 if (pc->p->cfg.high_result < (reg->hw + 1))
205 pc->p->cfg.high_result = reg->hw + 1;
206 }
207
208 if (reg->type != P_TEMP)
209 return;
210
211 if (reg->hw >= 0) {
212 /*XXX: do this here too to catch FP temp-as-attr usage..
213 * not clean, but works */
214 if (pc->p->cfg.high_temp < (reg->hw + 1))
215 pc->p->cfg.high_temp = reg->hw + 1;
216 return;
217 }
218
219 if (reg->rhw != -1) {
220 /* try to allocate temporary with index rhw first */
221 if (!(pc->r_temp[reg->rhw])) {
222 pc->r_temp[reg->rhw] = reg;
223 reg->hw = reg->rhw;
224 if (pc->p->cfg.high_temp < (reg->rhw + 1))
225 pc->p->cfg.high_temp = reg->rhw + 1;
226 return;
227 }
228 /* make sure we don't get things like $r0 needs to go
229 * in $r1 and $r1 in $r0
230 */
231 i = pc->result_nr * 4;
232 }
233
234 for (; i < NV50_SU_MAX_TEMP; i++) {
235 if (!(pc->r_temp[i])) {
236 pc->r_temp[i] = reg;
237 reg->hw = i;
238 if (pc->p->cfg.high_temp < (i + 1))
239 pc->p->cfg.high_temp = i + 1;
240 return;
241 }
242 }
243
244 assert(0);
245 }
246
247 static INLINE struct nv50_reg *
248 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
249 {
250 struct nv50_reg *ri;
251
252 assert(pc->reg_instance_nr < 16);
253 ri = &pc->reg_instances[pc->reg_instance_nr++];
254 if (reg) {
255 alloc_reg(pc, reg);
256 *ri = *reg;
257 reg->mod = 0;
258 }
259 return ri;
260 }
261
262 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
263 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
264 * lest we risk temp_temps overwriting regs alloc'd "later".
265 */
266 static struct nv50_reg *
267 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
268 {
269 struct nv50_reg *r;
270 int i;
271
272 if (dst && dst->type == P_TEMP && dst->hw == -1)
273 return dst;
274
275 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
276 if (!pc->r_temp[i]) {
277 r = MALLOC_STRUCT(nv50_reg);
278 ctor_reg(r, P_TEMP, -1, i);
279 pc->r_temp[i] = r;
280 return r;
281 }
282 }
283
284 assert(0);
285 return NULL;
286 }
287
288 /* release the hardware resource held by r */
289 static void
290 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
291 {
292 assert(r->type == P_TEMP);
293 if (r->hw == -1)
294 return;
295
296 assert(pc->r_temp[r->hw] == r);
297 pc->r_temp[r->hw] = NULL;
298
299 r->acc = 0;
300 if (r->index == -1)
301 FREE(r);
302 }
303
304 static void
305 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
306 {
307 if (r->index == -1) {
308 unsigned hw = r->hw;
309
310 FREE(pc->r_temp[hw]);
311 pc->r_temp[hw] = NULL;
312 }
313 }
314
315 static int
316 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
317 {
318 int i;
319
320 if ((idx + 4) >= NV50_SU_MAX_TEMP)
321 return 1;
322
323 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
324 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
325 return alloc_temp4(pc, dst, idx + 4);
326
327 for (i = 0; i < 4; i++) {
328 dst[i] = MALLOC_STRUCT(nv50_reg);
329 ctor_reg(dst[i], P_TEMP, -1, idx + i);
330 pc->r_temp[idx + i] = dst[i];
331 }
332
333 return 0;
334 }
335
336 static void
337 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
338 {
339 int i;
340
341 for (i = 0; i < 4; i++)
342 free_temp(pc, reg[i]);
343 }
344
345 static struct nv50_reg *
346 temp_temp(struct nv50_pc *pc)
347 {
348 if (pc->temp_temp_nr >= 16)
349 assert(0);
350
351 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
352 return pc->temp_temp[pc->temp_temp_nr++];
353 }
354
355 static void
356 kill_temp_temp(struct nv50_pc *pc)
357 {
358 int i;
359
360 for (i = 0; i < pc->temp_temp_nr; i++)
361 free_temp(pc, pc->temp_temp[i]);
362 pc->temp_temp_nr = 0;
363 }
364
365 static int
366 ctor_immd_4u32(struct nv50_pc *pc,
367 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
368 {
369 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
370
371 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
372
373 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
374 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
375 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
376 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
377
378 return pc->immd_nr++;
379 }
380
381 static INLINE int
382 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
383 {
384 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
385 }
386
387 static struct nv50_reg *
388 alloc_immd(struct nv50_pc *pc, float f)
389 {
390 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
391 unsigned hw;
392
393 for (hw = 0; hw < pc->immd_nr * 4; hw++)
394 if (pc->immd_buf[hw] == fui(f))
395 break;
396
397 if (hw == pc->immd_nr * 4)
398 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
399
400 ctor_reg(r, P_IMMD, -1, hw);
401 return r;
402 }
403
404 static struct nv50_program_exec *
405 exec(struct nv50_pc *pc)
406 {
407 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
408
409 e->param.index = -1;
410 return e;
411 }
412
413 static void
414 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
415 {
416 struct nv50_program *p = pc->p;
417
418 if (p->exec_tail)
419 p->exec_tail->next = e;
420 if (!p->exec_head)
421 p->exec_head = e;
422 p->exec_tail = e;
423 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
424 }
425
426 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
427
428 static boolean
429 is_long(struct nv50_program_exec *e)
430 {
431 if (e->inst[0] & 1)
432 return TRUE;
433 return FALSE;
434 }
435
436 static boolean
437 is_immd(struct nv50_program_exec *e)
438 {
439 if (is_long(e) && (e->inst[1] & 3) == 3)
440 return TRUE;
441 return FALSE;
442 }
443
444 static boolean
445 is_join(struct nv50_program_exec *e)
446 {
447 if (is_long(e) && (e->inst[1] & 3) == 2)
448 return TRUE;
449 return FALSE;
450 }
451
452 static INLINE void
453 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
454 struct nv50_program_exec *e)
455 {
456 assert(!is_immd(e));
457 set_long(pc, e);
458 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
459 e->inst[1] |= (pred << 7) | (idx << 12);
460 }
461
462 static INLINE void
463 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
464 struct nv50_program_exec *e)
465 {
466 set_long(pc, e);
467 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
468 e->inst[1] |= (idx << 4) | (on << 6);
469 }
470
471 static INLINE void
472 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
473 {
474 if (is_long(e))
475 return;
476
477 e->inst[0] |= 1;
478 set_pred(pc, 0xf, 0, e);
479 set_pred_wr(pc, 0, 0, e);
480 }
481
482 static INLINE void
483 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
484 {
485 if (dst->type == P_RESULT) {
486 set_long(pc, e);
487 e->inst[1] |= 0x00000008;
488 }
489
490 alloc_reg(pc, dst);
491 if (dst->hw > 63)
492 set_long(pc, e);
493 e->inst[0] |= (dst->hw << 2);
494 }
495
496 static INLINE void
497 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
498 {
499 set_long(pc, e);
500 /* XXX: can't be predicated - bits overlap; cases where both
501 * are required should be avoided by using pc->allow32 */
502 set_pred(pc, 0, 0, e);
503 set_pred_wr(pc, 0, 0, e);
504
505 e->inst[1] |= 0x00000002 | 0x00000001;
506 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
507 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
508 }
509
510 static INLINE void
511 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
512 {
513 assert(!(e->inst[0] & 0x0c000000));
514 assert(!(e->inst[1] & 0x00000004));
515
516 e->inst[0] |= (a->hw & 3) << 26;
517 e->inst[1] |= (a->hw >> 2) << 2;
518 }
519
520 static void
521 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
522 struct nv50_reg *src0, uint16_t src1_val)
523 {
524 struct nv50_program_exec *e = exec(pc);
525
526 e->inst[0] = 0xd0000000 | (src1_val << 9);
527 e->inst[1] = 0x20000000;
528 set_long(pc, e);
529 e->inst[0] |= dst->hw << 2;
530 if (src0) /* otherwise will add to $a0, which is always 0 */
531 set_addr(e, src0);
532
533 emit(pc, e);
534 }
535
536 static struct nv50_reg *
537 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
538 {
539 struct nv50_reg *a_tgsi = NULL, *a = NULL;
540 int i;
541 uint8_t avail = ~pc->addr_alloc;
542
543 if (!ref) {
544 /* allocate for TGSI_FILE_ADDRESS */
545 while (avail) {
546 i = ffs(avail) - 1;
547
548 if (pc->r_addr[i].rhw < 0 ||
549 pc->r_addr[i].acc != pc->insn_cur) {
550 pc->addr_alloc |= (1 << i);
551
552 pc->r_addr[i].rhw = -1;
553 pc->r_addr[i].index = i;
554 return &pc->r_addr[i];
555 }
556 avail &= ~(1 << i);
557 }
558 assert(0);
559 return NULL;
560 }
561
562 /* Allocate and set an address reg so we can access 'ref'.
563 *
564 * If and r_addr->index will be -1 or the hw index the value
565 * value in rhw is relative to. If rhw < 0, the reg has not
566 * been initialized or is in use for TGSI_FILE_ADDRESS.
567 */
568 while (avail) { /* only consider regs that are not TGSI */
569 i = ffs(avail) - 1;
570 avail &= ~(1 << i);
571
572 if ((!a || a->rhw >= 0) && pc->r_addr[i].rhw < 0) {
573 /* prefer an usused reg with low hw index */
574 a = &pc->r_addr[i];
575 continue;
576 }
577 if (!a && pc->r_addr[i].acc != pc->insn_cur)
578 a = &pc->r_addr[i];
579
580 if (ref->hw - pc->r_addr[i].rhw >= 128)
581 continue;
582
583 if ((ref->acc >= 0 && pc->r_addr[i].index < 0) ||
584 (ref->acc < 0 && pc->r_addr[i].index == ref->index)) {
585 pc->r_addr[i].acc = pc->insn_cur;
586 return &pc->r_addr[i];
587 }
588 }
589 assert(a);
590
591 if (ref->acc < 0)
592 a_tgsi = pc->addr[ref->index];
593
594 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
595
596 a->rhw = ref->hw & ~0x7f;
597 a->acc = pc->insn_cur;
598 a->index = a_tgsi ? ref->index : -1;
599 return a;
600 }
601
602 #define INTERP_LINEAR 0
603 #define INTERP_FLAT 1
604 #define INTERP_PERSPECTIVE 2
605 #define INTERP_CENTROID 4
606
607 /* interpolant index has been stored in dst->rhw */
608 static void
609 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
610 unsigned mode)
611 {
612 assert(dst->rhw != -1);
613 struct nv50_program_exec *e = exec(pc);
614
615 e->inst[0] |= 0x80000000;
616 set_dst(pc, dst, e);
617 e->inst[0] |= (dst->rhw << 16);
618
619 if (mode & INTERP_FLAT) {
620 e->inst[0] |= (1 << 8);
621 } else {
622 if (mode & INTERP_PERSPECTIVE) {
623 e->inst[0] |= (1 << 25);
624 alloc_reg(pc, iv);
625 e->inst[0] |= (iv->hw << 9);
626 }
627
628 if (mode & INTERP_CENTROID)
629 e->inst[0] |= (1 << 24);
630 }
631
632 emit(pc, e);
633 }
634
635 static void
636 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
637 struct nv50_program_exec *e)
638 {
639 set_long(pc, e);
640
641 e->param.index = src->hw & 127;
642 e->param.shift = s;
643 e->param.mask = m << (s % 32);
644
645 if (src->hw > 127)
646 set_addr(e, alloc_addr(pc, src));
647 else
648 if (src->acc < 0) {
649 assert(src->type == P_CONST);
650 set_addr(e, pc->addr[src->index]);
651 }
652
653 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
654 }
655
656 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
657 static void
658 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
659 {
660 struct nv50_program_exec *e = exec(pc);
661
662 e->inst[0] = 0x10000000;
663 if (!pc->allow32)
664 set_long(pc, e);
665
666 set_dst(pc, dst, e);
667
668 if (!is_long(e) && src->type == P_IMMD) {
669 set_immd(pc, src, e);
670 /*XXX: 32-bit, but steals part of "half" reg space - need to
671 * catch and handle this case if/when we do half-regs
672 */
673 } else
674 if (src->type == P_IMMD || src->type == P_CONST) {
675 set_long(pc, e);
676 set_data(pc, src, 0x7f, 9, e);
677 e->inst[1] |= 0x20000000; /* mov from c[] */
678 } else {
679 if (src->type == P_ATTR) {
680 set_long(pc, e);
681 e->inst[1] |= 0x00200000;
682 }
683
684 alloc_reg(pc, src);
685 if (src->hw > 63)
686 set_long(pc, e);
687 e->inst[0] |= (src->hw << 9);
688 }
689
690 if (is_long(e) && !is_immd(e)) {
691 e->inst[1] |= 0x04000000; /* 32-bit */
692 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
693 if (!(e->inst[1] & 0x20000000))
694 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
695 } else
696 e->inst[0] |= 0x00008000;
697
698 emit(pc, e);
699 }
700
701 static INLINE void
702 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
703 {
704 struct nv50_reg *imm = alloc_immd(pc, f);
705 emit_mov(pc, dst, imm);
706 FREE(imm);
707 }
708
709 /* Assign the hw of the discarded temporary register src
710 * to the tgsi register dst and free src.
711 */
712 static void
713 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
714 {
715 assert(src->index == -1 && src->hw != -1);
716
717 if (pc->if_lvl || pc->loop_lvl ||
718 (dst->type != P_TEMP) ||
719 (src->hw < pc->result_nr * 4 &&
720 pc->p->type == PIPE_SHADER_FRAGMENT) ||
721 pc->p->info.opcode_count[TGSI_OPCODE_CAL] ||
722 pc->p->info.opcode_count[TGSI_OPCODE_BRA]) {
723
724 emit_mov(pc, dst, src);
725 free_temp(pc, src);
726 return;
727 }
728
729 if (dst->hw != -1)
730 pc->r_temp[dst->hw] = NULL;
731 pc->r_temp[src->hw] = dst;
732 dst->hw = src->hw;
733
734 FREE(src);
735 }
736
737 static void
738 emit_nop(struct nv50_pc *pc)
739 {
740 struct nv50_program_exec *e = exec(pc);
741
742 e->inst[0] = 0xf0000000;
743 set_long(pc, e);
744 e->inst[1] = 0xe0000000;
745 emit(pc, e);
746 }
747
748 static boolean
749 check_swap_src_0_1(struct nv50_pc *pc,
750 struct nv50_reg **s0, struct nv50_reg **s1)
751 {
752 struct nv50_reg *src0 = *s0, *src1 = *s1;
753
754 if (src0->type == P_CONST) {
755 if (src1->type != P_CONST) {
756 *s0 = src1;
757 *s1 = src0;
758 return TRUE;
759 }
760 } else
761 if (src1->type == P_ATTR) {
762 if (src0->type != P_ATTR) {
763 *s0 = src1;
764 *s1 = src0;
765 return TRUE;
766 }
767 }
768
769 return FALSE;
770 }
771
772 static void
773 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
774 struct nv50_program_exec *e)
775 {
776 struct nv50_reg *temp;
777
778 if (src->type != P_TEMP) {
779 temp = temp_temp(pc);
780 emit_mov(pc, temp, src);
781 src = temp;
782 }
783
784 alloc_reg(pc, src);
785 if (src->hw > 63)
786 set_long(pc, e);
787 e->inst[0] |= (src->hw << 9);
788 }
789
790 static void
791 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
792 {
793 if (src->type == P_ATTR) {
794 set_long(pc, e);
795 e->inst[1] |= 0x00200000;
796 } else
797 if (src->type == P_CONST || src->type == P_IMMD) {
798 struct nv50_reg *temp = temp_temp(pc);
799
800 emit_mov(pc, temp, src);
801 src = temp;
802 }
803
804 alloc_reg(pc, src);
805 if (src->hw > 63)
806 set_long(pc, e);
807 e->inst[0] |= (src->hw << 9);
808 }
809
810 static void
811 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
812 {
813 if (src->type == P_ATTR) {
814 struct nv50_reg *temp = temp_temp(pc);
815
816 emit_mov(pc, temp, src);
817 src = temp;
818 } else
819 if (src->type == P_CONST || src->type == P_IMMD) {
820 assert(!(e->inst[0] & 0x00800000));
821 if (e->inst[0] & 0x01000000) {
822 struct nv50_reg *temp = temp_temp(pc);
823
824 emit_mov(pc, temp, src);
825 src = temp;
826 } else {
827 set_data(pc, src, 0x7f, 16, e);
828 e->inst[0] |= 0x00800000;
829 }
830 }
831
832 alloc_reg(pc, src);
833 if (src->hw > 63)
834 set_long(pc, e);
835 e->inst[0] |= ((src->hw & 127) << 16);
836 }
837
838 static void
839 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
840 {
841 set_long(pc, e);
842
843 if (src->type == P_ATTR) {
844 struct nv50_reg *temp = temp_temp(pc);
845
846 emit_mov(pc, temp, src);
847 src = temp;
848 } else
849 if (src->type == P_CONST || src->type == P_IMMD) {
850 assert(!(e->inst[0] & 0x01000000));
851 if (e->inst[0] & 0x00800000) {
852 struct nv50_reg *temp = temp_temp(pc);
853
854 emit_mov(pc, temp, src);
855 src = temp;
856 } else {
857 set_data(pc, src, 0x7f, 32+14, e);
858 e->inst[0] |= 0x01000000;
859 }
860 }
861
862 alloc_reg(pc, src);
863 e->inst[1] |= ((src->hw & 127) << 14);
864 }
865
866 static void
867 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
868 {
869 struct nv50_program_exec *e = exec(pc);
870
871 assert(dst->type == P_TEMP);
872 e->inst[1] = 0x20000000 | (pred << 12);
873 set_long(pc, e);
874 set_dst(pc, dst, e);
875
876 emit(pc, e);
877 }
878
879 static void
880 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
881 {
882 struct nv50_program_exec *e = exec(pc);
883
884 e->inst[0] = 0x000001fc;
885 e->inst[1] = 0xa0000008;
886 set_long(pc, e);
887 set_pred_wr(pc, 1, pred, e);
888 set_src_0_restricted(pc, src, e);
889
890 emit(pc, e);
891 }
892
893 static void
894 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
895 struct nv50_reg *src1)
896 {
897 struct nv50_program_exec *e = exec(pc);
898
899 e->inst[0] |= 0xc0000000;
900
901 if (!pc->allow32)
902 set_long(pc, e);
903
904 check_swap_src_0_1(pc, &src0, &src1);
905 set_dst(pc, dst, e);
906 set_src_0(pc, src0, e);
907 if (src1->type == P_IMMD && !is_long(e)) {
908 if (src0->mod ^ src1->mod)
909 e->inst[0] |= 0x00008000;
910 set_immd(pc, src1, e);
911 } else {
912 set_src_1(pc, src1, e);
913 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
914 if (is_long(e))
915 e->inst[1] |= 0x08000000;
916 else
917 e->inst[0] |= 0x00008000;
918 }
919 }
920
921 emit(pc, e);
922 }
923
924 static void
925 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
926 struct nv50_reg *src0, struct nv50_reg *src1)
927 {
928 struct nv50_program_exec *e = exec(pc);
929
930 e->inst[0] = 0xb0000000;
931
932 alloc_reg(pc, src1);
933 check_swap_src_0_1(pc, &src0, &src1);
934
935 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
936 set_long(pc, e);
937 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
938 ((src1->mod & NV50_MOD_NEG) << 27);
939 }
940
941 set_dst(pc, dst, e);
942 set_src_0(pc, src0, e);
943 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
944 set_src_2(pc, src1, e);
945 else
946 if (src1->type == P_IMMD)
947 set_immd(pc, src1, e);
948 else
949 set_src_1(pc, src1, e);
950
951 emit(pc, e);
952 }
953
954 static void
955 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
956 uint8_t s)
957 {
958 struct nv50_program_exec *e = exec(pc);
959
960 set_long(pc, e);
961 e->inst[1] |= 0xc0000000;
962
963 e->inst[0] |= dst->hw << 2;
964 e->inst[0] |= s << 16; /* shift left */
965 set_src_0_restricted(pc, src, e);
966
967 emit(pc, e);
968 }
969
970 static void
971 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
972 struct nv50_reg *src0, struct nv50_reg *src1)
973 {
974 struct nv50_program_exec *e = exec(pc);
975
976 set_long(pc, e);
977 e->inst[0] |= 0xb0000000;
978 e->inst[1] |= (sub << 29);
979
980 check_swap_src_0_1(pc, &src0, &src1);
981 set_dst(pc, dst, e);
982 set_src_0(pc, src0, e);
983 set_src_1(pc, src1, e);
984
985 if (src0->mod & NV50_MOD_ABS)
986 e->inst[1] |= 0x00100000;
987 if (src1->mod & NV50_MOD_ABS)
988 e->inst[1] |= 0x00080000;
989
990 emit(pc, e);
991 }
992
993 static INLINE void
994 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
995 struct nv50_reg *src1)
996 {
997 src1->mod ^= NV50_MOD_NEG;
998 emit_add(pc, dst, src0, src1);
999 src1->mod ^= NV50_MOD_NEG;
1000 }
1001
1002 static void
1003 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1004 struct nv50_reg *src1, unsigned op)
1005 {
1006 struct nv50_program_exec *e = exec(pc);
1007
1008 e->inst[0] = 0xd0000000;
1009 set_long(pc, e);
1010
1011 check_swap_src_0_1(pc, &src0, &src1);
1012 set_dst(pc, dst, e);
1013 set_src_0(pc, src0, e);
1014
1015 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1016 op != TGSI_OPCODE_XOR)
1017 assert(!"invalid bit op");
1018
1019 assert(!(src0->mod | src1->mod));
1020
1021 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1022 set_immd(pc, src1, e);
1023 if (op == TGSI_OPCODE_OR)
1024 e->inst[0] |= 0x0100;
1025 else
1026 if (op == TGSI_OPCODE_XOR)
1027 e->inst[0] |= 0x8000;
1028 } else {
1029 set_src_1(pc, src1, e);
1030 e->inst[1] |= 0x04000000; /* 32 bit */
1031 if (op == TGSI_OPCODE_OR)
1032 e->inst[1] |= 0x4000;
1033 else
1034 if (op == TGSI_OPCODE_XOR)
1035 e->inst[1] |= 0x8000;
1036 }
1037
1038 emit(pc, e);
1039 }
1040
1041 static void
1042 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1043 struct nv50_reg *src1, struct nv50_reg *src2)
1044 {
1045 struct nv50_program_exec *e = exec(pc);
1046
1047 e->inst[0] |= 0xe0000000;
1048
1049 check_swap_src_0_1(pc, &src0, &src1);
1050 set_dst(pc, dst, e);
1051 set_src_0(pc, src0, e);
1052 set_src_1(pc, src1, e);
1053 set_src_2(pc, src2, e);
1054
1055 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1056 e->inst[1] |= 0x04000000;
1057 if (src2->mod & NV50_MOD_NEG)
1058 e->inst[1] |= 0x08000000;
1059
1060 emit(pc, e);
1061 }
1062
1063 static INLINE void
1064 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1065 struct nv50_reg *src1, struct nv50_reg *src2)
1066 {
1067 src2->mod ^= NV50_MOD_NEG;
1068 emit_mad(pc, dst, src0, src1, src2);
1069 src2->mod ^= NV50_MOD_NEG;
1070 }
1071
1072 #define NV50_FLOP_RCP 0
1073 #define NV50_FLOP_RSQ 2
1074 #define NV50_FLOP_LG2 3
1075 #define NV50_FLOP_SIN 4
1076 #define NV50_FLOP_COS 5
1077 #define NV50_FLOP_EX2 6
1078
1079 /* rcp, rsqrt, lg2 support neg and abs */
1080 static void
1081 emit_flop(struct nv50_pc *pc, unsigned sub,
1082 struct nv50_reg *dst, struct nv50_reg *src)
1083 {
1084 struct nv50_program_exec *e = exec(pc);
1085
1086 e->inst[0] |= 0x90000000;
1087 if (sub || src->mod) {
1088 set_long(pc, e);
1089 e->inst[1] |= (sub << 29);
1090 }
1091
1092 set_dst(pc, dst, e);
1093 set_src_0_restricted(pc, src, e);
1094
1095 assert(!src->mod || sub < 4);
1096
1097 if (src->mod & NV50_MOD_NEG)
1098 e->inst[1] |= 0x04000000;
1099 if (src->mod & NV50_MOD_ABS)
1100 e->inst[1] |= 0x00100000;
1101
1102 emit(pc, e);
1103 }
1104
1105 static void
1106 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1107 {
1108 struct nv50_program_exec *e = exec(pc);
1109
1110 e->inst[0] |= 0xb0000000;
1111
1112 set_dst(pc, dst, e);
1113 set_src_0(pc, src, e);
1114 set_long(pc, e);
1115 e->inst[1] |= (6 << 29) | 0x00004000;
1116
1117 if (src->mod & NV50_MOD_NEG)
1118 e->inst[1] |= 0x04000000;
1119 if (src->mod & NV50_MOD_ABS)
1120 e->inst[1] |= 0x00100000;
1121
1122 emit(pc, e);
1123 }
1124
1125 static void
1126 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1127 {
1128 struct nv50_program_exec *e = exec(pc);
1129
1130 e->inst[0] |= 0xb0000000;
1131
1132 set_dst(pc, dst, e);
1133 set_src_0(pc, src, e);
1134 set_long(pc, e);
1135 e->inst[1] |= (6 << 29);
1136
1137 if (src->mod & NV50_MOD_NEG)
1138 e->inst[1] |= 0x04000000;
1139 if (src->mod & NV50_MOD_ABS)
1140 e->inst[1] |= 0x00100000;
1141
1142 emit(pc, e);
1143 }
1144
1145 #define CVTOP_RN 0x01
1146 #define CVTOP_FLOOR 0x03
1147 #define CVTOP_CEIL 0x05
1148 #define CVTOP_TRUNC 0x07
1149 #define CVTOP_SAT 0x08
1150 #define CVTOP_ABS 0x10
1151
1152 /* 0x04 == 32 bit dst */
1153 /* 0x40 == dst is float */
1154 /* 0x80 == src is float */
1155 #define CVT_F32_F32 0xc4
1156 #define CVT_F32_S32 0x44
1157 #define CVT_S32_F32 0x8c
1158 #define CVT_S32_S32 0x0c
1159 #define CVT_NEG 0x20
1160 #define CVT_RI 0x08
1161
1162 static void
1163 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1164 int wp, unsigned cvn, unsigned fmt)
1165 {
1166 struct nv50_program_exec *e;
1167
1168 e = exec(pc);
1169 set_long(pc, e);
1170
1171 e->inst[0] |= 0xa0000000;
1172 e->inst[1] |= 0x00004000; /* 32 bit src */
1173 e->inst[1] |= (cvn << 16);
1174 e->inst[1] |= (fmt << 24);
1175 set_src_0(pc, src, e);
1176
1177 if (wp >= 0)
1178 set_pred_wr(pc, 1, wp, e);
1179
1180 if (dst)
1181 set_dst(pc, dst, e);
1182 else {
1183 e->inst[0] |= 0x000001fc;
1184 e->inst[1] |= 0x00000008;
1185 }
1186
1187 emit(pc, e);
1188 }
1189
1190 /* nv50 Condition codes:
1191 * 0x1 = LT
1192 * 0x2 = EQ
1193 * 0x3 = LE
1194 * 0x4 = GT
1195 * 0x5 = NE
1196 * 0x6 = GE
1197 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1198 * 0x8 = unordered bit (allows NaN)
1199 */
1200 static void
1201 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1202 struct nv50_reg *src0, struct nv50_reg *src1)
1203 {
1204 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1205
1206 struct nv50_program_exec *e = exec(pc);
1207 struct nv50_reg *rdst;
1208
1209 assert(ccode < 16);
1210 if (check_swap_src_0_1(pc, &src0, &src1))
1211 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1212
1213 rdst = dst;
1214 if (dst && dst->type != P_TEMP)
1215 dst = alloc_temp(pc, NULL);
1216
1217 /* set.u32 */
1218 set_long(pc, e);
1219 e->inst[0] |= 0xb0000000;
1220 e->inst[1] |= 0x60000000 | (ccode << 14);
1221
1222 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1223 * that doesn't seem to match what the hw actually does
1224 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1225 */
1226
1227 if (wp >= 0)
1228 set_pred_wr(pc, 1, wp, e);
1229 if (dst)
1230 set_dst(pc, dst, e);
1231 else {
1232 e->inst[0] |= 0x000001fc;
1233 e->inst[1] |= 0x00000008;
1234 }
1235
1236 set_src_0(pc, src0, e);
1237 set_src_1(pc, src1, e);
1238
1239 emit(pc, e);
1240
1241 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1242 if (rdst)
1243 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
1244 if (rdst && rdst != dst)
1245 free_temp(pc, dst);
1246 }
1247
1248 static INLINE unsigned
1249 map_tgsi_setop_cc(unsigned op)
1250 {
1251 switch (op) {
1252 case TGSI_OPCODE_SLT: return 0x1;
1253 case TGSI_OPCODE_SGE: return 0x6;
1254 case TGSI_OPCODE_SEQ: return 0x2;
1255 case TGSI_OPCODE_SGT: return 0x4;
1256 case TGSI_OPCODE_SLE: return 0x3;
1257 case TGSI_OPCODE_SNE: return 0xd;
1258 default:
1259 assert(0);
1260 return 0;
1261 }
1262 }
1263
1264 static INLINE void
1265 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1266 {
1267 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
1268 }
1269
1270 static void
1271 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1272 struct nv50_reg *v, struct nv50_reg *e)
1273 {
1274 struct nv50_reg *temp = alloc_temp(pc, NULL);
1275
1276 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1277 emit_mul(pc, temp, temp, e);
1278 emit_preex2(pc, temp, temp);
1279 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1280
1281 free_temp(pc, temp);
1282 }
1283
1284 static INLINE void
1285 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1286 {
1287 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
1288 }
1289
1290 static INLINE void
1291 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1292 {
1293 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
1294 }
1295
1296 static void
1297 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1298 struct nv50_reg **src)
1299 {
1300 struct nv50_reg *one = alloc_immd(pc, 1.0);
1301 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1302 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1303 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1304 struct nv50_reg *tmp[4];
1305 boolean allow32 = pc->allow32;
1306
1307 pc->allow32 = FALSE;
1308
1309 if (mask & (3 << 1)) {
1310 tmp[0] = alloc_temp(pc, NULL);
1311 emit_minmax(pc, 4, tmp[0], src[0], zero);
1312 }
1313
1314 if (mask & (1 << 2)) {
1315 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1316
1317 tmp[1] = temp_temp(pc);
1318 emit_minmax(pc, 4, tmp[1], src[1], zero);
1319
1320 tmp[3] = temp_temp(pc);
1321 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1322 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1323
1324 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1325 emit_mov(pc, dst[2], zero);
1326 set_pred(pc, 3, 0, pc->p->exec_tail);
1327 }
1328
1329 if (mask & (1 << 1))
1330 assimilate_temp(pc, dst[1], tmp[0]);
1331 else
1332 if (mask & (1 << 2))
1333 free_temp(pc, tmp[0]);
1334
1335 pc->allow32 = allow32;
1336
1337 /* do this last, in case src[i,j] == dst[0,3] */
1338 if (mask & (1 << 0))
1339 emit_mov(pc, dst[0], one);
1340
1341 if (mask & (1 << 3))
1342 emit_mov(pc, dst[3], one);
1343
1344 FREE(pos128);
1345 FREE(neg128);
1346 FREE(zero);
1347 FREE(one);
1348 }
1349
1350 static INLINE void
1351 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1352 {
1353 emit_cvt(pc, dst, src, -1, CVTOP_RN, CVT_F32_F32 | CVT_NEG);
1354 }
1355
1356 static void
1357 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1358 {
1359 struct nv50_program_exec *e;
1360 const int r_pred = 1;
1361
1362 e = exec(pc);
1363 e->inst[0] = 0x00000002; /* discard */
1364 set_long(pc, e); /* sets cond code to ALWAYS */
1365
1366 if (src) {
1367 unsigned cvn = CVT_F32_F32;
1368
1369 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1370
1371 if (src->mod & NV50_MOD_NEG)
1372 cvn |= CVT_NEG;
1373 /* write predicate reg */
1374 emit_cvt(pc, NULL, src, r_pred, CVTOP_RN, cvn);
1375 }
1376
1377 emit(pc, e);
1378 }
1379
1380 static struct nv50_program_exec *
1381 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1382 {
1383 struct nv50_program_exec *e = exec(pc);
1384
1385 e->inst[0] = (op << 28) | 2;
1386 set_long(pc, e);
1387 if (pred >= 0)
1388 set_pred(pc, cc, pred, e);
1389
1390 emit(pc, e);
1391 return e;
1392 }
1393
1394 static INLINE struct nv50_program_exec *
1395 emit_breakaddr(struct nv50_pc *pc)
1396 {
1397 return emit_control_flow(pc, 0x4, -1, 0);
1398 }
1399
1400 static INLINE void
1401 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1402 {
1403 emit_control_flow(pc, 0x5, pred, cc);
1404 }
1405
1406 static INLINE struct nv50_program_exec *
1407 emit_joinat(struct nv50_pc *pc)
1408 {
1409 return emit_control_flow(pc, 0xa, -1, 0);
1410 }
1411
1412 static INLINE struct nv50_program_exec *
1413 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1414 {
1415 return emit_control_flow(pc, 0x1, pred, cc);
1416 }
1417
1418 static INLINE struct nv50_program_exec *
1419 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1420 {
1421 return emit_control_flow(pc, 0x2, pred, cc);
1422 }
1423
1424 static INLINE void
1425 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1426 {
1427 emit_control_flow(pc, 0x3, pred, cc);
1428 }
1429
1430 #define QOP_ADD 0
1431 #define QOP_SUBR 1
1432 #define QOP_SUB 2
1433 #define QOP_MOV_SRC1 3
1434
1435 /* For a quad of threads / top left, top right, bottom left, bottom right
1436 * pixels, do a different operation, and take src0 from a specific thread.
1437 */
1438 static void
1439 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1440 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1441 {
1442 struct nv50_program_exec *e = exec(pc);
1443
1444 e->inst[0] = 0xc0000000;
1445 e->inst[1] = 0x80000000;
1446 set_long(pc, e);
1447 e->inst[0] |= lane_src0 << 16;
1448 set_src_0(pc, src0, e);
1449 set_src_2(pc, src1, e);
1450
1451 if (wp >= 0)
1452 set_pred_wr(pc, 1, wp, e);
1453
1454 if (dst)
1455 set_dst(pc, dst, e);
1456 else {
1457 e->inst[0] |= 0x000001fc;
1458 e->inst[1] |= 0x00000008;
1459 }
1460
1461 e->inst[0] |= (qop & 3) << 20;
1462 e->inst[1] |= (qop >> 2) << 22;
1463
1464 emit(pc, e);
1465 }
1466
1467 static void
1468 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1469 struct nv50_reg **src, unsigned arg, boolean proj)
1470 {
1471 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1472
1473 src[0]->mod |= NV50_MOD_ABS;
1474 src[1]->mod |= NV50_MOD_ABS;
1475 src[2]->mod |= NV50_MOD_ABS;
1476
1477 emit_minmax(pc, 4, t[2], src[0], src[1]);
1478 emit_minmax(pc, 4, t[2], src[2], t[2]);
1479
1480 src[0]->mod = mod[0];
1481 src[1]->mod = mod[1];
1482 src[2]->mod = mod[2];
1483
1484 if (proj && 0 /* looks more correct without this */)
1485 emit_mul(pc, t[2], t[2], src[3]);
1486 else
1487 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1488 emit_mov(pc, t[3], src[3]);
1489
1490 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1491
1492 emit_mul(pc, t[0], src[0], t[2]);
1493 emit_mul(pc, t[1], src[1], t[2]);
1494 emit_mul(pc, t[2], src[2], t[2]);
1495 }
1496
1497 static void
1498 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1499 struct nv50_reg **src, unsigned dim, unsigned arg)
1500 {
1501 unsigned c, mode;
1502
1503 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1504 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1505
1506 t[3]->rhw = src[3]->rhw;
1507 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1508 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1509
1510 for (c = 0; c < dim; ++c) {
1511 t[c]->rhw = src[c]->rhw;
1512 emit_interp(pc, t[c], t[3], mode);
1513 }
1514 if (arg != dim) { /* depth reference value */
1515 t[dim]->rhw = src[2]->rhw;
1516 emit_interp(pc, t[dim], t[3], mode);
1517 }
1518 } else {
1519 /* XXX: for some reason the blob sometimes uses MAD
1520 * (mad f32 $rX $rY $rZ neg $r63)
1521 */
1522 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1523 for (c = 0; c < dim; ++c)
1524 emit_mul(pc, t[c], src[c], t[3]);
1525 if (arg != dim) /* depth reference value */
1526 emit_mul(pc, t[dim], src[2], t[3]);
1527 }
1528 }
1529
1530 static INLINE void
1531 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1532 {
1533 switch (type) {
1534 case TGSI_TEXTURE_1D:
1535 *arg = *dim = 1;
1536 break;
1537 case TGSI_TEXTURE_SHADOW1D:
1538 *dim = 1;
1539 *arg = 2;
1540 break;
1541 case TGSI_TEXTURE_UNKNOWN:
1542 case TGSI_TEXTURE_2D:
1543 case TGSI_TEXTURE_RECT:
1544 *arg = *dim = 2;
1545 break;
1546 case TGSI_TEXTURE_SHADOW2D:
1547 case TGSI_TEXTURE_SHADOWRECT:
1548 *dim = 2;
1549 *arg = 3;
1550 break;
1551 case TGSI_TEXTURE_3D:
1552 case TGSI_TEXTURE_CUBE:
1553 *dim = *arg = 3;
1554 break;
1555 default:
1556 assert(0);
1557 break;
1558 }
1559 }
1560
1561 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1562 * different LOD values, so branch off groups of equal LOD.
1563 */
1564 static void
1565 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1566 struct nv50_reg *src, struct nv50_program_exec *tex)
1567 {
1568 struct nv50_program_exec *join_at;
1569 unsigned i, target = pc->p->exec_size + 9 * 2;
1570
1571 if (pc->p->type != PIPE_SHADER_FRAGMENT) {
1572 emit(pc, tex);
1573 return;
1574 }
1575 pc->allow32 = FALSE;
1576
1577 /* Subtract lod of each pixel from lod of top left pixel, jump
1578 * texlod insn if result is 0, then repeat for 2 other pixels.
1579 */
1580 join_at = emit_joinat(pc);
1581 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1582 emit_branch(pc, 0, 2)->param.index = target;
1583
1584 for (i = 1; i < 4; ++i) {
1585 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1586 emit_branch(pc, 0, 2)->param.index = target;
1587 }
1588
1589 emit_mov(pc, tlod, src); /* target */
1590 emit(pc, tex); /* texlod */
1591
1592 join_at->param.index = target + 2 * 2;
1593 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1594 }
1595
1596 static void
1597 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1598 struct nv50_program_exec *tex)
1599 {
1600 struct nv50_program_exec *e;
1601 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1602 int r_pred = 0;
1603 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1604
1605 pc->allow32 = FALSE;
1606 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1607
1608 /* Subtract bias value of thread i from bias values of each thread,
1609 * store result in r_pred, and set bit i in r_bits if result was 0.
1610 */
1611 assert(arg < 4);
1612 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1613 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1614 emit_mov(pc, r_bits, &imm_1248);
1615 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1616 }
1617 emit_mov_to_pred(pc, r_pred, r_bits);
1618
1619 /* The lanes of a quad are now grouped by the bit in r_pred they have
1620 * set. Put the input values for TEX into a new register set for each
1621 * group and execute TEX only for a specific group.
1622 * We cannot use the same register set for each group because we need
1623 * the derivatives, which are implicitly calculated, to be correct.
1624 */
1625 for (i = 1; i < 4; ++i) {
1626 alloc_temp4(pc, t123[i], 0);
1627
1628 for (c = 0; c <= arg; ++c)
1629 emit_mov(pc, t123[i][c], t[c]);
1630
1631 *(e = exec(pc)) = *(tex);
1632 e->inst[0] &= ~0x01fc;
1633 set_dst(pc, t123[i][0], e);
1634 set_pred(pc, cc[i], r_pred, e);
1635 emit(pc, e);
1636 }
1637 /* finally TEX on the original regs (where we kept the input) */
1638 set_pred(pc, cc[0], r_pred, tex);
1639 emit(pc, tex);
1640
1641 /* put the 3 * n other results into regs for lane 0 */
1642 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1643 for (i = 1; i < 4; ++i) {
1644 for (c = 0; c < n; ++c) {
1645 emit_mov(pc, t[c], t123[i][c]);
1646 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1647 }
1648 free_temp4(pc, t123[i]);
1649 }
1650
1651 emit_nop(pc);
1652 free_temp(pc, r_bits);
1653 }
1654
1655 static void
1656 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1657 struct nv50_reg **src, unsigned unit, unsigned type,
1658 boolean proj, int bias_lod)
1659 {
1660 struct nv50_reg *t[4];
1661 struct nv50_program_exec *e;
1662 unsigned c, dim, arg;
1663
1664 /* t[i] must be within a single 128 bit super-reg */
1665 alloc_temp4(pc, t, 0);
1666
1667 e = exec(pc);
1668 e->inst[0] = 0xf0000000;
1669 set_long(pc, e);
1670 set_dst(pc, t[0], e);
1671
1672 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1673 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1674
1675 /* live flag (don't set if TEX results affect input to another TEX): */
1676 /* e->inst[0] |= 0x00000004; */
1677
1678 get_tex_dim(type, &dim, &arg);
1679
1680 if (type == TGSI_TEXTURE_CUBE) {
1681 e->inst[0] |= 0x08000000;
1682 load_cube_tex_coords(pc, t, src, arg, proj);
1683 } else
1684 if (proj)
1685 load_proj_tex_coords(pc, t, src, dim, arg);
1686 else {
1687 for (c = 0; c < dim; c++)
1688 emit_mov(pc, t[c], src[c]);
1689 if (arg != dim) /* depth reference value (always src.z here) */
1690 emit_mov(pc, t[dim], src[2]);
1691 }
1692
1693 e->inst[0] |= (mask & 0x3) << 25;
1694 e->inst[1] |= (mask & 0xc) << 12;
1695
1696 if (!bias_lod) {
1697 e->inst[0] |= (arg - 1) << 22;
1698 emit(pc, e);
1699 } else
1700 if (bias_lod < 0) {
1701 assert(pc->p->type == PIPE_SHADER_FRAGMENT);
1702 e->inst[0] |= arg << 22;
1703 e->inst[1] |= 0x20000000; /* texbias */
1704 emit_mov(pc, t[arg], src[3]);
1705 emit_texbias_sequence(pc, t, arg, e);
1706 } else {
1707 e->inst[0] |= arg << 22;
1708 e->inst[1] |= 0x40000000; /* texlod */
1709 emit_mov(pc, t[arg], src[3]);
1710 emit_texlod_sequence(pc, t[arg], src[3], e);
1711 }
1712
1713 #if 1
1714 c = 0;
1715 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1716 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1717 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1718 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1719
1720 free_temp4(pc, t);
1721 #else
1722 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1723 * the texture coordinates, not the fetched values: latency ? */
1724
1725 for (c = 0; c < 4; c++) {
1726 if (mask & (1 << c))
1727 assimilate_temp(pc, dst[c], t[c]);
1728 else
1729 free_temp(pc, t[c]);
1730 }
1731 #endif
1732 }
1733
1734 static void
1735 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1736 {
1737 struct nv50_program_exec *e = exec(pc);
1738
1739 assert(src->type == P_TEMP);
1740
1741 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
1742 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
1743 set_long(pc, e);
1744 set_dst(pc, dst, e);
1745 set_src_0(pc, src, e);
1746 set_src_2(pc, src, e);
1747
1748 emit(pc, e);
1749 }
1750
1751 static void
1752 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1753 {
1754 struct nv50_program_exec *e = exec(pc);
1755
1756 assert(src->type == P_TEMP);
1757
1758 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
1759 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
1760 set_long(pc, e);
1761 set_dst(pc, dst, e);
1762 set_src_0(pc, src, e);
1763 set_src_2(pc, src, e);
1764
1765 emit(pc, e);
1766 }
1767
1768 static void
1769 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1770 {
1771 unsigned q = 0, m = ~0;
1772
1773 assert(!is_long(e));
1774
1775 switch (e->inst[0] >> 28) {
1776 case 0x1:
1777 /* MOV */
1778 q = 0x0403c000;
1779 m = 0xffff7fff;
1780 break;
1781 case 0x8:
1782 /* INTERP (move centroid, perspective and flat bits) */
1783 m = ~0x03000100;
1784 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1785 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1786 break;
1787 case 0x9:
1788 /* RCP */
1789 break;
1790 case 0xB:
1791 /* ADD */
1792 m = ~(127 << 16);
1793 q = ((e->inst[0] & (~m)) >> 2);
1794 break;
1795 case 0xC:
1796 /* MUL */
1797 m = ~0x00008000;
1798 q = ((e->inst[0] & (~m)) << 12);
1799 break;
1800 case 0xE:
1801 /* MAD (if src2 == dst) */
1802 q = ((e->inst[0] & 0x1fc) << 12);
1803 break;
1804 default:
1805 assert(0);
1806 break;
1807 }
1808
1809 set_long(pc, e);
1810 pc->p->exec_size++;
1811
1812 e->inst[0] &= m;
1813 e->inst[1] |= q;
1814 }
1815
1816 /* Some operations support an optional negation flag. */
1817 static boolean
1818 negate_supported(const struct tgsi_full_instruction *insn, int i)
1819 {
1820 switch (insn->Instruction.Opcode) {
1821 case TGSI_OPCODE_ADD:
1822 case TGSI_OPCODE_COS:
1823 case TGSI_OPCODE_DDX:
1824 case TGSI_OPCODE_DDY:
1825 case TGSI_OPCODE_DP3:
1826 case TGSI_OPCODE_DP4:
1827 case TGSI_OPCODE_EX2:
1828 case TGSI_OPCODE_KIL:
1829 case TGSI_OPCODE_LG2:
1830 case TGSI_OPCODE_MAD:
1831 case TGSI_OPCODE_MUL:
1832 case TGSI_OPCODE_POW:
1833 case TGSI_OPCODE_RCP:
1834 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
1835 case TGSI_OPCODE_SCS:
1836 case TGSI_OPCODE_SIN:
1837 case TGSI_OPCODE_SUB:
1838 return TRUE;
1839 default:
1840 return FALSE;
1841 }
1842 }
1843
1844 /* Return a read mask for source registers deduced from opcode & write mask. */
1845 static unsigned
1846 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1847 {
1848 unsigned x, mask = insn->Dst[0].Register.WriteMask;
1849
1850 switch (insn->Instruction.Opcode) {
1851 case TGSI_OPCODE_COS:
1852 case TGSI_OPCODE_SIN:
1853 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1854 case TGSI_OPCODE_DP3:
1855 return 0x7;
1856 case TGSI_OPCODE_DP4:
1857 case TGSI_OPCODE_DPH:
1858 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1859 return 0xf;
1860 case TGSI_OPCODE_DST:
1861 return mask & (c ? 0xa : 0x6);
1862 case TGSI_OPCODE_EX2:
1863 case TGSI_OPCODE_EXP:
1864 case TGSI_OPCODE_LG2:
1865 case TGSI_OPCODE_LOG:
1866 case TGSI_OPCODE_POW:
1867 case TGSI_OPCODE_RCP:
1868 case TGSI_OPCODE_RSQ:
1869 case TGSI_OPCODE_SCS:
1870 return 0x1;
1871 case TGSI_OPCODE_IF:
1872 return 0x1;
1873 case TGSI_OPCODE_LIT:
1874 return 0xb;
1875 case TGSI_OPCODE_TEX:
1876 case TGSI_OPCODE_TXB:
1877 case TGSI_OPCODE_TXL:
1878 case TGSI_OPCODE_TXP:
1879 {
1880 const struct tgsi_instruction_texture *tex;
1881
1882 assert(insn->Instruction.Texture);
1883 tex = &insn->Texture;
1884
1885 mask = 0x7;
1886 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
1887 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
1888 mask |= 0x8; /* bias, lod or proj */
1889
1890 switch (tex->Texture) {
1891 case TGSI_TEXTURE_1D:
1892 mask &= 0x9;
1893 break;
1894 case TGSI_TEXTURE_SHADOW1D:
1895 mask &= 0x5;
1896 break;
1897 case TGSI_TEXTURE_2D:
1898 mask &= 0xb;
1899 break;
1900 default:
1901 break;
1902 }
1903 }
1904 return mask;
1905 case TGSI_OPCODE_XPD:
1906 x = 0;
1907 if (mask & 1) x |= 0x6;
1908 if (mask & 2) x |= 0x5;
1909 if (mask & 4) x |= 0x3;
1910 return x;
1911 default:
1912 break;
1913 }
1914
1915 return mask;
1916 }
1917
1918 static struct nv50_reg *
1919 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1920 {
1921 switch (dst->Register.File) {
1922 case TGSI_FILE_TEMPORARY:
1923 return &pc->temp[dst->Register.Index * 4 + c];
1924 case TGSI_FILE_OUTPUT:
1925 return &pc->result[dst->Register.Index * 4 + c];
1926 case TGSI_FILE_ADDRESS:
1927 {
1928 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
1929 if (!r) {
1930 r = alloc_addr(pc, NULL);
1931 pc->addr[dst->Register.Index * 4 + c] = r;
1932 }
1933 assert(r);
1934 return r;
1935 }
1936 case TGSI_FILE_NULL:
1937 return NULL;
1938 default:
1939 break;
1940 }
1941
1942 return NULL;
1943 }
1944
1945 static struct nv50_reg *
1946 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1947 boolean neg)
1948 {
1949 struct nv50_reg *r = NULL;
1950 struct nv50_reg *temp;
1951 unsigned sgn, c, swz;
1952
1953 if (src->Register.File != TGSI_FILE_CONSTANT)
1954 assert(!src->Register.Indirect);
1955
1956 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1957
1958 c = tgsi_util_get_full_src_register_swizzle(src, chan);
1959 switch (c) {
1960 case TGSI_SWIZZLE_X:
1961 case TGSI_SWIZZLE_Y:
1962 case TGSI_SWIZZLE_Z:
1963 case TGSI_SWIZZLE_W:
1964 switch (src->Register.File) {
1965 case TGSI_FILE_INPUT:
1966 r = &pc->attr[src->Register.Index * 4 + c];
1967 break;
1968 case TGSI_FILE_TEMPORARY:
1969 r = &pc->temp[src->Register.Index * 4 + c];
1970 break;
1971 case TGSI_FILE_CONSTANT:
1972 if (!src->Register.Indirect) {
1973 r = &pc->param[src->Register.Index * 4 + c];
1974 break;
1975 }
1976 /* Indicate indirection by setting r->acc < 0 and
1977 * use the index field to select the address reg.
1978 */
1979 r = reg_instance(pc, NULL);
1980 swz = tgsi_util_get_src_register_swizzle(
1981 &src->Indirect, 0);
1982 ctor_reg(r, P_CONST,
1983 src->Indirect.Index * 4 + swz,
1984 src->Register.Index * 4 + c);
1985 r->acc = -1;
1986 break;
1987 case TGSI_FILE_IMMEDIATE:
1988 r = &pc->immd[src->Register.Index * 4 + c];
1989 break;
1990 case TGSI_FILE_SAMPLER:
1991 break;
1992 case TGSI_FILE_ADDRESS:
1993 r = pc->addr[src->Register.Index * 4 + c];
1994 assert(r);
1995 break;
1996 default:
1997 assert(0);
1998 break;
1999 }
2000 break;
2001 default:
2002 assert(0);
2003 break;
2004 }
2005
2006 switch (sgn) {
2007 case TGSI_UTIL_SIGN_KEEP:
2008 break;
2009 case TGSI_UTIL_SIGN_CLEAR:
2010 temp = temp_temp(pc);
2011 emit_abs(pc, temp, r);
2012 r = temp;
2013 break;
2014 case TGSI_UTIL_SIGN_TOGGLE:
2015 if (neg)
2016 r->mod = NV50_MOD_NEG;
2017 else {
2018 temp = temp_temp(pc);
2019 emit_neg(pc, temp, r);
2020 r = temp;
2021 }
2022 break;
2023 case TGSI_UTIL_SIGN_SET:
2024 temp = temp_temp(pc);
2025 emit_cvt(pc, temp, r, -1, CVTOP_ABS, CVT_F32_F32 | CVT_NEG);
2026 r = temp;
2027 break;
2028 default:
2029 assert(0);
2030 break;
2031 }
2032
2033 if (r && r->acc >= 0 && r != temp)
2034 return reg_instance(pc, r);
2035 return r;
2036 }
2037
2038 /* return TRUE for ops that produce only a single result */
2039 static boolean
2040 is_scalar_op(unsigned op)
2041 {
2042 switch (op) {
2043 case TGSI_OPCODE_COS:
2044 case TGSI_OPCODE_DP2:
2045 case TGSI_OPCODE_DP3:
2046 case TGSI_OPCODE_DP4:
2047 case TGSI_OPCODE_DPH:
2048 case TGSI_OPCODE_EX2:
2049 case TGSI_OPCODE_LG2:
2050 case TGSI_OPCODE_POW:
2051 case TGSI_OPCODE_RCP:
2052 case TGSI_OPCODE_RSQ:
2053 case TGSI_OPCODE_SIN:
2054 /*
2055 case TGSI_OPCODE_KIL:
2056 case TGSI_OPCODE_LIT:
2057 case TGSI_OPCODE_SCS:
2058 */
2059 return TRUE;
2060 default:
2061 return FALSE;
2062 }
2063 }
2064
2065 /* Returns a bitmask indicating which dst components depend
2066 * on source s, component c (reverse of nv50_tgsi_src_mask).
2067 */
2068 static unsigned
2069 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2070 {
2071 if (is_scalar_op(op))
2072 return 0x1;
2073
2074 switch (op) {
2075 case TGSI_OPCODE_DST:
2076 return (1 << c) & (s ? 0xa : 0x6);
2077 case TGSI_OPCODE_XPD:
2078 switch (c) {
2079 case 0: return 0x6;
2080 case 1: return 0x5;
2081 case 2: return 0x3;
2082 case 3: return 0x0;
2083 default:
2084 assert(0);
2085 return 0x0;
2086 }
2087 case TGSI_OPCODE_EXP:
2088 case TGSI_OPCODE_LOG:
2089 case TGSI_OPCODE_LIT:
2090 case TGSI_OPCODE_SCS:
2091 case TGSI_OPCODE_TEX:
2092 case TGSI_OPCODE_TXB:
2093 case TGSI_OPCODE_TXL:
2094 case TGSI_OPCODE_TXP:
2095 /* these take care of dangerous swizzles themselves */
2096 return 0x0;
2097 case TGSI_OPCODE_IF:
2098 case TGSI_OPCODE_KIL:
2099 /* don't call this function for these ops */
2100 assert(0);
2101 return 0;
2102 default:
2103 /* linear vector instruction */
2104 return (1 << c);
2105 }
2106 }
2107
2108 static INLINE boolean
2109 has_pred(struct nv50_program_exec *e, unsigned cc)
2110 {
2111 if (!is_long(e) || is_immd(e))
2112 return FALSE;
2113 return ((e->inst[1] & 0x780) == (cc << 7));
2114 }
2115
2116 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2117 * join_at ENDIF
2118 * @p0.eq bra ENDIF
2119 * single_op
2120 * ENDIF: nop.join
2121 */
2122 static boolean
2123 nv50_kill_branch(struct nv50_pc *pc)
2124 {
2125 int lvl = pc->if_lvl;
2126
2127 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2128 return FALSE;
2129 if (is_immd(pc->p->exec_tail))
2130 return FALSE;
2131
2132 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2133 * reg may no longer be valid, since we currently always use $p0
2134 */
2135 if (has_pred(pc->if_insn[lvl], 0xf))
2136 return FALSE;
2137 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2138
2139 /* We'll use the exec allocated for JOIN_AT (we can't easily
2140 * access nv50_program_exec's prev).
2141 */
2142 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2143
2144 *pc->if_join[lvl] = *pc->p->exec_tail;
2145
2146 FREE(pc->if_insn[lvl]);
2147 FREE(pc->p->exec_tail);
2148
2149 pc->p->exec_tail = pc->if_join[lvl];
2150 pc->p->exec_tail->next = NULL;
2151 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2152
2153 return TRUE;
2154 }
2155
2156 static void
2157 nv50_fp_move_results(struct nv50_pc *pc)
2158 {
2159 struct nv50_reg reg;
2160 unsigned i;
2161
2162 ctor_reg(&reg, P_TEMP, -1, -1);
2163
2164 for (i = 0; i < pc->result_nr * 4; ++i) {
2165 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2166 continue;
2167 if (pc->result[i].rhw != pc->result[i].hw) {
2168 reg.hw = pc->result[i].rhw;
2169 emit_mov(pc, &reg, &pc->result[i]);
2170 }
2171 }
2172 }
2173
2174 static boolean
2175 nv50_program_tx_insn(struct nv50_pc *pc,
2176 const struct tgsi_full_instruction *inst)
2177 {
2178 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2179 unsigned mask, sat, unit;
2180 int i, c;
2181
2182 mask = inst->Dst[0].Register.WriteMask;
2183 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2184
2185 memset(src, 0, sizeof(src));
2186
2187 for (c = 0; c < 4; c++) {
2188 if ((mask & (1 << c)) && !pc->r_dst[c])
2189 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2190 else
2191 dst[c] = pc->r_dst[c];
2192 rdst[c] = dst[c];
2193 }
2194
2195 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2196 const struct tgsi_full_src_register *fs = &inst->Src[i];
2197 unsigned src_mask;
2198 boolean neg_supp;
2199
2200 src_mask = nv50_tgsi_src_mask(inst, i);
2201 neg_supp = negate_supported(inst, i);
2202
2203 if (fs->Register.File == TGSI_FILE_SAMPLER)
2204 unit = fs->Register.Index;
2205
2206 for (c = 0; c < 4; c++)
2207 if (src_mask & (1 << c))
2208 src[i][c] = tgsi_src(pc, c, fs, neg_supp);
2209 }
2210
2211 brdc = temp = pc->r_brdc;
2212 if (brdc && brdc->type != P_TEMP) {
2213 temp = temp_temp(pc);
2214 if (sat)
2215 brdc = temp;
2216 } else
2217 if (sat) {
2218 for (c = 0; c < 4; c++) {
2219 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2220 continue;
2221 /* rdst[c] = dst[c]; */ /* done above */
2222 dst[c] = temp_temp(pc);
2223 }
2224 }
2225
2226 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2227
2228 switch (inst->Instruction.Opcode) {
2229 case TGSI_OPCODE_ABS:
2230 for (c = 0; c < 4; c++) {
2231 if (!(mask & (1 << c)))
2232 continue;
2233 emit_abs(pc, dst[c], src[0][c]);
2234 }
2235 break;
2236 case TGSI_OPCODE_ADD:
2237 for (c = 0; c < 4; c++) {
2238 if (!(mask & (1 << c)))
2239 continue;
2240 emit_add(pc, dst[c], src[0][c], src[1][c]);
2241 }
2242 break;
2243 case TGSI_OPCODE_AND:
2244 case TGSI_OPCODE_XOR:
2245 case TGSI_OPCODE_OR:
2246 for (c = 0; c < 4; c++) {
2247 if (!(mask & (1 << c)))
2248 continue;
2249 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2250 inst->Instruction.Opcode);
2251 }
2252 break;
2253 case TGSI_OPCODE_ARL:
2254 assert(src[0][0]);
2255 temp = temp_temp(pc);
2256 emit_cvt(pc, temp, src[0][0], -1, CVTOP_FLOOR, CVT_S32_F32);
2257 emit_arl(pc, dst[0], temp, 4);
2258 break;
2259 case TGSI_OPCODE_BGNLOOP:
2260 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2261 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2262 terminate_mbb(pc);
2263 break;
2264 case TGSI_OPCODE_BGNSUB:
2265 assert(!pc->in_subroutine);
2266 pc->in_subroutine = TRUE;
2267 /* probably not necessary, but align to 8 byte boundary */
2268 if (!is_long(pc->p->exec_tail))
2269 convert_to_long(pc, pc->p->exec_tail);
2270 break;
2271 case TGSI_OPCODE_BRK:
2272 assert(pc->loop_lvl > 0);
2273 emit_break(pc, -1, 0);
2274 break;
2275 case TGSI_OPCODE_CAL:
2276 assert(inst->Label.Label < pc->insn_nr);
2277 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2278 /* replaced by actual offset in nv50_program_fixup_insns */
2279 break;
2280 case TGSI_OPCODE_CEIL:
2281 for (c = 0; c < 4; c++) {
2282 if (!(mask & (1 << c)))
2283 continue;
2284 emit_cvt(pc, dst[c], src[0][c], -1,
2285 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
2286 }
2287 break;
2288 case TGSI_OPCODE_CMP:
2289 pc->allow32 = FALSE;
2290 for (c = 0; c < 4; c++) {
2291 if (!(mask & (1 << c)))
2292 continue;
2293 emit_cvt(pc, NULL, src[0][c], 1, CVTOP_RN, CVT_F32_F32);
2294 emit_mov(pc, dst[c], src[1][c]);
2295 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2296 emit_mov(pc, dst[c], src[2][c]);
2297 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2298 }
2299 break;
2300 case TGSI_OPCODE_CONT:
2301 assert(pc->loop_lvl > 0);
2302 emit_branch(pc, -1, 0)->param.index =
2303 pc->loop_pos[pc->loop_lvl - 1];
2304 break;
2305 case TGSI_OPCODE_COS:
2306 if (mask & 8) {
2307 emit_precossin(pc, temp, src[0][3]);
2308 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2309 if (!(mask &= 7))
2310 break;
2311 if (temp == dst[3])
2312 temp = brdc = temp_temp(pc);
2313 }
2314 emit_precossin(pc, temp, src[0][0]);
2315 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2316 break;
2317 case TGSI_OPCODE_DDX:
2318 for (c = 0; c < 4; c++) {
2319 if (!(mask & (1 << c)))
2320 continue;
2321 emit_ddx(pc, dst[c], src[0][c]);
2322 }
2323 break;
2324 case TGSI_OPCODE_DDY:
2325 for (c = 0; c < 4; c++) {
2326 if (!(mask & (1 << c)))
2327 continue;
2328 emit_ddy(pc, dst[c], src[0][c]);
2329 }
2330 break;
2331 case TGSI_OPCODE_DP3:
2332 emit_mul(pc, temp, src[0][0], src[1][0]);
2333 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2334 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2335 break;
2336 case TGSI_OPCODE_DP4:
2337 emit_mul(pc, temp, src[0][0], src[1][0]);
2338 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2339 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2340 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2341 break;
2342 case TGSI_OPCODE_DPH:
2343 emit_mul(pc, temp, src[0][0], src[1][0]);
2344 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2345 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2346 emit_add(pc, brdc, src[1][3], temp);
2347 break;
2348 case TGSI_OPCODE_DST:
2349 if (mask & (1 << 1))
2350 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2351 if (mask & (1 << 2))
2352 emit_mov(pc, dst[2], src[0][2]);
2353 if (mask & (1 << 3))
2354 emit_mov(pc, dst[3], src[1][3]);
2355 if (mask & (1 << 0))
2356 emit_mov_immdval(pc, dst[0], 1.0f);
2357 break;
2358 case TGSI_OPCODE_ELSE:
2359 emit_branch(pc, -1, 0);
2360 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2361 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2362 terminate_mbb(pc);
2363 break;
2364 case TGSI_OPCODE_ENDIF:
2365 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2366
2367 /* try to replace branch over 1 insn with a predicated insn */
2368 if (nv50_kill_branch(pc) == TRUE)
2369 break;
2370
2371 if (pc->if_join[pc->if_lvl]) {
2372 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2373 pc->if_join[pc->if_lvl] = NULL;
2374 }
2375 terminate_mbb(pc);
2376 /* emit a NOP as join point, we could set it on the next
2377 * one, but would have to make sure it is long and !immd
2378 */
2379 JOIN_ON(emit_nop(pc));
2380 break;
2381 case TGSI_OPCODE_ENDLOOP:
2382 emit_branch(pc, -1, 0)->param.index =
2383 pc->loop_pos[--pc->loop_lvl];
2384 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2385 terminate_mbb(pc);
2386 break;
2387 case TGSI_OPCODE_ENDSUB:
2388 assert(pc->in_subroutine);
2389 pc->in_subroutine = FALSE;
2390 break;
2391 case TGSI_OPCODE_EX2:
2392 emit_preex2(pc, temp, src[0][0]);
2393 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2394 break;
2395 case TGSI_OPCODE_EXP:
2396 {
2397 struct nv50_reg *t[2];
2398
2399 assert(!temp);
2400 t[0] = temp_temp(pc);
2401 t[1] = temp_temp(pc);
2402
2403 if (mask & 0x6)
2404 emit_mov(pc, t[0], src[0][0]);
2405 if (mask & 0x3)
2406 emit_flr(pc, t[1], src[0][0]);
2407
2408 if (mask & (1 << 1))
2409 emit_sub(pc, dst[1], t[0], t[1]);
2410 if (mask & (1 << 0)) {
2411 emit_preex2(pc, t[1], t[1]);
2412 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2413 }
2414 if (mask & (1 << 2)) {
2415 emit_preex2(pc, t[0], t[0]);
2416 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2417 }
2418 if (mask & (1 << 3))
2419 emit_mov_immdval(pc, dst[3], 1.0f);
2420 }
2421 break;
2422 case TGSI_OPCODE_FLR:
2423 for (c = 0; c < 4; c++) {
2424 if (!(mask & (1 << c)))
2425 continue;
2426 emit_flr(pc, dst[c], src[0][c]);
2427 }
2428 break;
2429 case TGSI_OPCODE_FRC:
2430 temp = temp_temp(pc);
2431 for (c = 0; c < 4; c++) {
2432 if (!(mask & (1 << c)))
2433 continue;
2434 emit_flr(pc, temp, src[0][c]);
2435 emit_sub(pc, dst[c], src[0][c], temp);
2436 }
2437 break;
2438 case TGSI_OPCODE_IF:
2439 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2440 emit_cvt(pc, NULL, src[0][0], 0, CVTOP_ABS | CVTOP_RN,
2441 CVT_F32_F32);
2442 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2443 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2444 terminate_mbb(pc);
2445 break;
2446 case TGSI_OPCODE_KIL:
2447 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2448 emit_kil(pc, src[0][0]);
2449 emit_kil(pc, src[0][1]);
2450 emit_kil(pc, src[0][2]);
2451 emit_kil(pc, src[0][3]);
2452 break;
2453 case TGSI_OPCODE_KILP:
2454 emit_kil(pc, NULL);
2455 break;
2456 case TGSI_OPCODE_LIT:
2457 emit_lit(pc, &dst[0], mask, &src[0][0]);
2458 break;
2459 case TGSI_OPCODE_LG2:
2460 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2461 break;
2462 case TGSI_OPCODE_LOG:
2463 {
2464 struct nv50_reg *t[2];
2465
2466 t[0] = temp_temp(pc);
2467 if (mask & (1 << 1))
2468 t[1] = temp_temp(pc);
2469 else
2470 t[1] = t[0];
2471
2472 emit_abs(pc, t[0], src[0][0]);
2473 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2474 if (mask & (1 << 2))
2475 emit_mov(pc, dst[2], t[1]);
2476 emit_flr(pc, t[1], t[1]);
2477 if (mask & (1 << 0))
2478 emit_mov(pc, dst[0], t[1]);
2479 if (mask & (1 << 1)) {
2480 t[1]->mod = NV50_MOD_NEG;
2481 emit_preex2(pc, t[1], t[1]);
2482 t[1]->mod = 0;
2483 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2484 emit_mul(pc, dst[1], t[0], t[1]);
2485 }
2486 if (mask & (1 << 3))
2487 emit_mov_immdval(pc, dst[3], 1.0f);
2488 }
2489 break;
2490 case TGSI_OPCODE_LRP:
2491 temp = temp_temp(pc);
2492 for (c = 0; c < 4; c++) {
2493 if (!(mask & (1 << c)))
2494 continue;
2495 emit_sub(pc, temp, src[1][c], src[2][c]);
2496 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2497 }
2498 break;
2499 case TGSI_OPCODE_MAD:
2500 for (c = 0; c < 4; c++) {
2501 if (!(mask & (1 << c)))
2502 continue;
2503 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2504 }
2505 break;
2506 case TGSI_OPCODE_MAX:
2507 for (c = 0; c < 4; c++) {
2508 if (!(mask & (1 << c)))
2509 continue;
2510 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
2511 }
2512 break;
2513 case TGSI_OPCODE_MIN:
2514 for (c = 0; c < 4; c++) {
2515 if (!(mask & (1 << c)))
2516 continue;
2517 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
2518 }
2519 break;
2520 case TGSI_OPCODE_MOV:
2521 for (c = 0; c < 4; c++) {
2522 if (!(mask & (1 << c)))
2523 continue;
2524 emit_mov(pc, dst[c], src[0][c]);
2525 }
2526 break;
2527 case TGSI_OPCODE_MUL:
2528 for (c = 0; c < 4; c++) {
2529 if (!(mask & (1 << c)))
2530 continue;
2531 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2532 }
2533 break;
2534 case TGSI_OPCODE_POW:
2535 emit_pow(pc, brdc, src[0][0], src[1][0]);
2536 break;
2537 case TGSI_OPCODE_RCP:
2538 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2539 break;
2540 case TGSI_OPCODE_RET:
2541 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2542 nv50_fp_move_results(pc);
2543 emit_ret(pc, -1, 0);
2544 break;
2545 case TGSI_OPCODE_RSQ:
2546 src[0][0]->mod |= NV50_MOD_ABS;
2547 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2548 break;
2549 case TGSI_OPCODE_SCS:
2550 temp = temp_temp(pc);
2551 if (mask & 3)
2552 emit_precossin(pc, temp, src[0][0]);
2553 if (mask & (1 << 0))
2554 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
2555 if (mask & (1 << 1))
2556 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
2557 if (mask & (1 << 2))
2558 emit_mov_immdval(pc, dst[2], 0.0);
2559 if (mask & (1 << 3))
2560 emit_mov_immdval(pc, dst[3], 1.0);
2561 break;
2562 case TGSI_OPCODE_SIN:
2563 if (mask & 8) {
2564 emit_precossin(pc, temp, src[0][3]);
2565 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
2566 if (!(mask &= 7))
2567 break;
2568 if (temp == dst[3])
2569 temp = brdc = temp_temp(pc);
2570 }
2571 emit_precossin(pc, temp, src[0][0]);
2572 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
2573 break;
2574 case TGSI_OPCODE_SLT:
2575 case TGSI_OPCODE_SGE:
2576 case TGSI_OPCODE_SEQ:
2577 case TGSI_OPCODE_SGT:
2578 case TGSI_OPCODE_SLE:
2579 case TGSI_OPCODE_SNE:
2580 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
2581 for (c = 0; c < 4; c++) {
2582 if (!(mask & (1 << c)))
2583 continue;
2584 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
2585 }
2586 break;
2587 case TGSI_OPCODE_SUB:
2588 for (c = 0; c < 4; c++) {
2589 if (!(mask & (1 << c)))
2590 continue;
2591 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2592 }
2593 break;
2594 case TGSI_OPCODE_TEX:
2595 emit_tex(pc, dst, mask, src[0], unit,
2596 inst->Texture.Texture, FALSE, 0);
2597 break;
2598 case TGSI_OPCODE_TXB:
2599 emit_tex(pc, dst, mask, src[0], unit,
2600 inst->Texture.Texture, FALSE, -1);
2601 break;
2602 case TGSI_OPCODE_TXL:
2603 emit_tex(pc, dst, mask, src[0], unit,
2604 inst->Texture.Texture, FALSE, 1);
2605 break;
2606 case TGSI_OPCODE_TXP:
2607 emit_tex(pc, dst, mask, src[0], unit,
2608 inst->Texture.Texture, TRUE, 0);
2609 break;
2610 case TGSI_OPCODE_TRUNC:
2611 for (c = 0; c < 4; c++) {
2612 if (!(mask & (1 << c)))
2613 continue;
2614 emit_cvt(pc, dst[c], src[0][c], -1,
2615 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
2616 }
2617 break;
2618 case TGSI_OPCODE_XPD:
2619 temp = temp_temp(pc);
2620 if (mask & (1 << 0)) {
2621 emit_mul(pc, temp, src[0][2], src[1][1]);
2622 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2623 }
2624 if (mask & (1 << 1)) {
2625 emit_mul(pc, temp, src[0][0], src[1][2]);
2626 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2627 }
2628 if (mask & (1 << 2)) {
2629 emit_mul(pc, temp, src[0][1], src[1][0]);
2630 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2631 }
2632 if (mask & (1 << 3))
2633 emit_mov_immdval(pc, dst[3], 1.0);
2634 break;
2635 case TGSI_OPCODE_END:
2636 if (pc->p->type == PIPE_SHADER_FRAGMENT)
2637 nv50_fp_move_results(pc);
2638
2639 /* last insn must be long so it can have the exit bit set */
2640 if (!is_long(pc->p->exec_tail))
2641 convert_to_long(pc, pc->p->exec_tail);
2642 else
2643 if (is_immd(pc->p->exec_tail) || is_join(pc->p->exec_tail))
2644 emit_nop(pc);
2645
2646 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
2647 break;
2648 default:
2649 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2650 return FALSE;
2651 }
2652
2653 if (brdc) {
2654 if (sat)
2655 emit_sat(pc, brdc, brdc);
2656 for (c = 0; c < 4; c++)
2657 if ((mask & (1 << c)) && dst[c] != brdc)
2658 emit_mov(pc, dst[c], brdc);
2659 } else
2660 if (sat) {
2661 for (c = 0; c < 4; c++) {
2662 if (!(mask & (1 << c)))
2663 continue;
2664 /* In this case we saturate later, and dst[c] won't
2665 * be another temp_temp (and thus lost), since rdst
2666 * already is TEMP (see above). */
2667 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2668 continue;
2669 emit_sat(pc, rdst[c], dst[c]);
2670 }
2671 }
2672
2673 kill_temp_temp(pc);
2674 pc->reg_instance_nr = 0;
2675
2676 return TRUE;
2677 }
2678
2679 static void
2680 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2681 {
2682 struct nv50_reg *reg = NULL;
2683 const struct tgsi_full_src_register *src;
2684 const struct tgsi_dst_register *dst;
2685 unsigned i, c, k, mask;
2686
2687 dst = &insn->Dst[0].Register;
2688 mask = dst->WriteMask;
2689
2690 if (dst->File == TGSI_FILE_TEMPORARY)
2691 reg = pc->temp;
2692 else
2693 if (dst->File == TGSI_FILE_OUTPUT) {
2694 reg = pc->result;
2695
2696 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
2697 dst->Index == pc->edgeflag_out &&
2698 insn->Src[0].Register.File == TGSI_FILE_INPUT)
2699 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
2700 }
2701
2702 if (reg) {
2703 for (c = 0; c < 4; c++) {
2704 if (!(mask & (1 << c)))
2705 continue;
2706 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2707 }
2708 }
2709
2710 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2711 src = &insn->Src[i];
2712
2713 if (src->Register.File == TGSI_FILE_TEMPORARY)
2714 reg = pc->temp;
2715 else
2716 if (src->Register.File == TGSI_FILE_INPUT)
2717 reg = pc->attr;
2718 else
2719 continue;
2720
2721 mask = nv50_tgsi_src_mask(insn, i);
2722
2723 for (c = 0; c < 4; c++) {
2724 if (!(mask & (1 << c)))
2725 continue;
2726 k = tgsi_util_get_full_src_register_swizzle(src, c);
2727
2728 reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
2729 }
2730 }
2731 }
2732
2733 /* Returns a bitmask indicating which dst components need to be
2734 * written to temporaries first to avoid 'corrupting' sources.
2735 *
2736 * m[i] (out) indicate component to write in the i-th position
2737 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2738 */
2739 static unsigned
2740 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2741 {
2742 unsigned i, c, x, unsafe;
2743
2744 for (c = 0; c < 4; c++)
2745 m[c] = c;
2746
2747 /* Swap as long as a dst component written earlier is depended on
2748 * by one written later, but the next one isn't depended on by it.
2749 */
2750 for (c = 0; c < 3; c++) {
2751 if (rdep[m[c + 1]] & (1 << m[c]))
2752 continue; /* if next one is depended on by us */
2753 for (i = c + 1; i < 4; i++)
2754 /* if we are depended on by a later one */
2755 if (rdep[m[c]] & (1 << m[i]))
2756 break;
2757 if (i == 4)
2758 continue;
2759 /* now, swap */
2760 x = m[c];
2761 m[c] = m[c + 1];
2762 m[c + 1] = x;
2763
2764 /* restart */
2765 c = 0;
2766 }
2767
2768 /* mark dependencies that could not be resolved by reordering */
2769 for (i = 0; i < 3; ++i)
2770 for (c = i + 1; c < 4; ++c)
2771 if (rdep[m[i]] & (1 << m[c]))
2772 unsafe |= (1 << i);
2773
2774 /* NOTE: $unsafe is with respect to order, not component */
2775 return unsafe;
2776 }
2777
2778 /* Select a suitable dst register for broadcasting scalar results,
2779 * or return NULL if we have to allocate an extra TEMP.
2780 *
2781 * If e.g. only 1 component is written, we may also emit the final
2782 * result to a write-only register.
2783 */
2784 static struct nv50_reg *
2785 tgsi_broadcast_dst(struct nv50_pc *pc,
2786 const struct tgsi_full_dst_register *fd, unsigned mask)
2787 {
2788 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
2789 int c = ffs(~mask & fd->Register.WriteMask);
2790 if (c)
2791 return tgsi_dst(pc, c - 1, fd);
2792 } else {
2793 int c = ffs(fd->Register.WriteMask) - 1;
2794 if ((1 << c) == fd->Register.WriteMask)
2795 return tgsi_dst(pc, c, fd);
2796 }
2797
2798 return NULL;
2799 }
2800
2801 /* Scan source swizzles and return a bitmask indicating dst regs that
2802 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2803 */
2804 static unsigned
2805 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2806 unsigned rdep[4])
2807 {
2808 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
2809 const struct tgsi_full_src_register *fs;
2810 unsigned i, deqs = 0;
2811
2812 for (i = 0; i < 4; ++i)
2813 rdep[i] = 0;
2814
2815 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2816 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2817 boolean neg_supp = negate_supported(insn, i);
2818
2819 fs = &insn->Src[i];
2820 if (fs->Register.File != fd->Register.File ||
2821 fs->Register.Index != fd->Register.Index)
2822 continue;
2823
2824 for (chn = 0; chn < 4; ++chn) {
2825 unsigned s, c;
2826
2827 if (!(mask & (1 << chn))) /* src is not read */
2828 continue;
2829 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2830 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2831
2832 if (!(fd->Register.WriteMask & (1 << c)))
2833 continue;
2834
2835 /* no danger if src is copied to TEMP first */
2836 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2837 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2838 continue;
2839
2840 rdep[c] |= nv50_tgsi_dst_revdep(
2841 insn->Instruction.Opcode, i, chn);
2842 deqs |= (1 << c);
2843 }
2844 }
2845
2846 return deqs;
2847 }
2848
2849 static boolean
2850 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2851 {
2852 struct tgsi_full_instruction insn = tok->FullInstruction;
2853 const struct tgsi_full_dst_register *fd;
2854 unsigned i, deqs, rdep[4], m[4];
2855
2856 fd = &tok->FullInstruction.Dst[0];
2857 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2858
2859 if (is_scalar_op(insn.Instruction.Opcode)) {
2860 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2861 if (!pc->r_brdc)
2862 pc->r_brdc = temp_temp(pc);
2863 return nv50_program_tx_insn(pc, &insn);
2864 }
2865 pc->r_brdc = NULL;
2866
2867 if (!deqs || (!rdep[0] && !rdep[1] && !rdep[2] && !rdep[3]))
2868 return nv50_program_tx_insn(pc, &insn);
2869
2870 deqs = nv50_revdep_reorder(m, rdep);
2871
2872 for (i = 0; i < 4; ++i) {
2873 assert(pc->r_dst[m[i]] == NULL);
2874
2875 insn.Dst[0].Register.WriteMask =
2876 fd->Register.WriteMask & (1 << m[i]);
2877
2878 if (!insn.Dst[0].Register.WriteMask)
2879 continue;
2880
2881 if (deqs & (1 << i))
2882 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2883
2884 if (!nv50_program_tx_insn(pc, &insn))
2885 return FALSE;
2886 }
2887
2888 for (i = 0; i < 4; i++) {
2889 struct nv50_reg *reg = pc->r_dst[i];
2890 if (!reg)
2891 continue;
2892 pc->r_dst[i] = NULL;
2893
2894 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2895 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2896 else
2897 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2898 free_temp(pc, reg);
2899 }
2900
2901 return TRUE;
2902 }
2903
2904 static void
2905 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2906 {
2907 struct nv50_reg *iv, **ppiv;
2908 unsigned mode = pc->interp_mode[reg->index];
2909
2910 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2911 iv = *ppiv;
2912
2913 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2914 iv = *ppiv = alloc_temp(pc, NULL);
2915 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2916
2917 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2918 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
2919
2920 /* XXX: when loading interpolants dynamically, move these
2921 * to the program head, or make sure it can't be skipped.
2922 */
2923 }
2924
2925 emit_interp(pc, reg, iv, mode);
2926 }
2927
2928 /* The face input is always at v[255] (varying space), with a
2929 * value of 0 for back-facing, and 0xffffffff for front-facing.
2930 */
2931 static void
2932 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
2933 {
2934 struct nv50_reg *one = alloc_immd(pc, 1.0f);
2935
2936 assert(a->rhw == -1);
2937 alloc_reg(pc, a); /* do this before rhw is set */
2938 a->rhw = 255;
2939 load_interpolant(pc, a);
2940 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
2941
2942 FREE(one);
2943 }
2944
2945 static boolean
2946 nv50_program_tx_prep(struct nv50_pc *pc)
2947 {
2948 struct tgsi_parse_context tp;
2949 struct nv50_program *p = pc->p;
2950 boolean ret = FALSE;
2951 unsigned i, c, flat_nr = 0;
2952
2953 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2954 while (!tgsi_parse_end_of_tokens(&tp)) {
2955 const union tgsi_full_token *tok = &tp.FullToken;
2956
2957 tgsi_parse_token(&tp);
2958 switch (tok->Token.Type) {
2959 case TGSI_TOKEN_TYPE_IMMEDIATE:
2960 {
2961 const struct tgsi_full_immediate *imm =
2962 &tp.FullToken.FullImmediate;
2963
2964 ctor_immd_4f32(pc, imm->u[0].Float,
2965 imm->u[1].Float,
2966 imm->u[2].Float,
2967 imm->u[3].Float);
2968 }
2969 break;
2970 case TGSI_TOKEN_TYPE_DECLARATION:
2971 {
2972 const struct tgsi_full_declaration *d;
2973 unsigned si, last, first, mode;
2974
2975 d = &tp.FullToken.FullDeclaration;
2976 first = d->Range.First;
2977 last = d->Range.Last;
2978
2979 switch (d->Declaration.File) {
2980 case TGSI_FILE_TEMPORARY:
2981 break;
2982 case TGSI_FILE_OUTPUT:
2983 if (!d->Declaration.Semantic ||
2984 p->type == PIPE_SHADER_FRAGMENT)
2985 break;
2986
2987 si = d->Semantic.Index;
2988 switch (d->Semantic.Name) {
2989 case TGSI_SEMANTIC_BCOLOR:
2990 p->cfg.two_side[si].hw = first;
2991 if (p->cfg.io_nr > first)
2992 p->cfg.io_nr = first;
2993 break;
2994 case TGSI_SEMANTIC_PSIZE:
2995 p->cfg.psiz = first;
2996 if (p->cfg.io_nr > first)
2997 p->cfg.io_nr = first;
2998 break;
2999 case TGSI_SEMANTIC_EDGEFLAG:
3000 pc->edgeflag_out = first;
3001 break;
3002 /*
3003 case TGSI_SEMANTIC_CLIP_DISTANCE:
3004 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3005 break;
3006 */
3007 default:
3008 break;
3009 }
3010 break;
3011 case TGSI_FILE_INPUT:
3012 {
3013 if (p->type != PIPE_SHADER_FRAGMENT)
3014 break;
3015
3016 switch (d->Declaration.Interpolate) {
3017 case TGSI_INTERPOLATE_CONSTANT:
3018 mode = INTERP_FLAT;
3019 flat_nr++;
3020 break;
3021 case TGSI_INTERPOLATE_PERSPECTIVE:
3022 mode = INTERP_PERSPECTIVE;
3023 p->cfg.regs[1] |= 0x08 << 24;
3024 break;
3025 default:
3026 mode = INTERP_LINEAR;
3027 break;
3028 }
3029 if (d->Declaration.Centroid)
3030 mode |= INTERP_CENTROID;
3031
3032 assert(last < 32);
3033 for (i = first; i <= last; i++)
3034 pc->interp_mode[i] = mode;
3035 }
3036 break;
3037 case TGSI_FILE_ADDRESS:
3038 case TGSI_FILE_CONSTANT:
3039 case TGSI_FILE_SAMPLER:
3040 break;
3041 default:
3042 NOUVEAU_ERR("bad decl file %d\n",
3043 d->Declaration.File);
3044 goto out_err;
3045 }
3046 }
3047 break;
3048 case TGSI_TOKEN_TYPE_INSTRUCTION:
3049 pc->insn_nr++;
3050 prep_inspect_insn(pc, &tok->FullInstruction);
3051 break;
3052 default:
3053 break;
3054 }
3055 }
3056
3057 if (p->type == PIPE_SHADER_VERTEX) {
3058 int rid = 0;
3059
3060 for (i = 0; i < pc->attr_nr * 4; ++i) {
3061 if (pc->attr[i].acc) {
3062 pc->attr[i].hw = rid++;
3063 p->cfg.attr[i / 32] |= 1 << (i % 32);
3064 }
3065 }
3066
3067 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3068 p->cfg.io[i].hw = rid;
3069 p->cfg.io[i].id = i;
3070
3071 for (c = 0; c < 4; ++c) {
3072 int n = i * 4 + c;
3073 if (!pc->result[n].acc)
3074 continue;
3075 pc->result[n].hw = rid++;
3076 p->cfg.io[i].mask |= 1 << c;
3077 }
3078 }
3079
3080 for (c = 0; c < 2; ++c)
3081 if (p->cfg.two_side[c].hw < 0x40)
3082 p->cfg.two_side[c] = p->cfg.io[
3083 p->cfg.two_side[c].hw];
3084
3085 if (p->cfg.psiz < 0x40)
3086 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
3087 } else
3088 if (p->type == PIPE_SHADER_FRAGMENT) {
3089 int rid, aid;
3090 unsigned n = 0, m = pc->attr_nr - flat_nr;
3091
3092 pc->allow32 = TRUE;
3093
3094 int base = (TGSI_SEMANTIC_POSITION ==
3095 p->info.input_semantic_name[0]) ? 0 : 1;
3096
3097 /* non-flat interpolants have to be mapped to
3098 * the lower hardware IDs, so sort them:
3099 */
3100 for (i = 0; i < pc->attr_nr; i++) {
3101 if (pc->interp_mode[i] == INTERP_FLAT)
3102 p->cfg.io[m++].id = i;
3103 else {
3104 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3105 p->cfg.io[n].linear = TRUE;
3106 p->cfg.io[n++].id = i;
3107 }
3108 }
3109
3110 if (!base) /* set w-coordinate mask from perspective interp */
3111 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
3112
3113 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
3114 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
3115
3116 for (n = 0; n < pc->attr_nr; ++n) {
3117 p->cfg.io[n].hw = rid = aid;
3118 i = p->cfg.io[n].id;
3119
3120 if (p->info.input_semantic_name[n] ==
3121 TGSI_SEMANTIC_FACE) {
3122 load_frontfacing(pc, &pc->attr[i * 4]);
3123 continue;
3124 }
3125
3126 for (c = 0; c < 4; ++c) {
3127 if (!pc->attr[i * 4 + c].acc)
3128 continue;
3129 pc->attr[i * 4 + c].rhw = rid++;
3130 p->cfg.io[n].mask |= 1 << c;
3131
3132 load_interpolant(pc, &pc->attr[i * 4 + c]);
3133 }
3134 aid += popcnt4(p->cfg.io[n].mask);
3135 }
3136
3137 if (!base)
3138 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
3139
3140 m = popcnt4(p->cfg.regs[1] >> 24);
3141
3142 /* set count of non-position inputs and of non-flat
3143 * non-position inputs for FP_INTERPOLANT_CTRL
3144 */
3145 p->cfg.regs[1] |= aid - m;
3146
3147 if (flat_nr) {
3148 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
3149 p->cfg.regs[1] |= (i - m) << 16;
3150 } else
3151 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3152
3153 /* mark color semantic for light-twoside */
3154 n = 0x40;
3155 for (i = 0; i < pc->attr_nr; i++) {
3156 ubyte si, sn;
3157
3158 sn = p->info.input_semantic_name[p->cfg.io[i].id];
3159 si = p->info.input_semantic_index[p->cfg.io[i].id];
3160
3161 if (sn == TGSI_SEMANTIC_COLOR) {
3162 p->cfg.two_side[si] = p->cfg.io[i];
3163
3164 /* increase colour count */
3165 p->cfg.regs[0] += popcnt4(
3166 p->cfg.two_side[si].mask) << 16;
3167
3168 n = MIN2(n, p->cfg.io[i].hw - m);
3169 }
3170 }
3171 if (n < 0x40)
3172 p->cfg.regs[0] += n;
3173
3174 /* Initialize FP results:
3175 * FragDepth is always first TGSI and last hw output
3176 */
3177 i = p->info.writes_z ? 4 : 0;
3178 for (rid = 0; i < pc->result_nr * 4; i++)
3179 pc->result[i].rhw = rid++;
3180 if (p->info.writes_z)
3181 pc->result[2].rhw = rid;
3182
3183 p->cfg.high_result = rid;
3184
3185 /* separate/different colour results for MRTs ? */
3186 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3187 p->cfg.regs[2] |= 1;
3188 }
3189
3190 if (pc->immd_nr) {
3191 int rid = 0;
3192
3193 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3194 if (!pc->immd)
3195 goto out_err;
3196
3197 for (i = 0; i < pc->immd_nr; i++) {
3198 for (c = 0; c < 4; c++, rid++)
3199 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3200 }
3201 }
3202
3203 ret = TRUE;
3204 out_err:
3205 if (pc->iv_p)
3206 free_temp(pc, pc->iv_p);
3207 if (pc->iv_c)
3208 free_temp(pc, pc->iv_c);
3209
3210 tgsi_parse_free(&tp);
3211 return ret;
3212 }
3213
3214 static void
3215 free_nv50_pc(struct nv50_pc *pc)
3216 {
3217 if (pc->immd)
3218 FREE(pc->immd);
3219 if (pc->param)
3220 FREE(pc->param);
3221 if (pc->result)
3222 FREE(pc->result);
3223 if (pc->attr)
3224 FREE(pc->attr);
3225 if (pc->temp)
3226 FREE(pc->temp);
3227
3228 FREE(pc);
3229 }
3230
3231 static boolean
3232 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3233 {
3234 int i, c;
3235 unsigned rtype[2] = { P_ATTR, P_RESULT };
3236
3237 pc->p = p;
3238 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3239 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3240 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3241 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3242 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3243 assert(pc->addr_nr <= 2);
3244
3245 p->cfg.high_temp = 4;
3246
3247 p->cfg.two_side[0].hw = 0x40;
3248 p->cfg.two_side[1].hw = 0x40;
3249
3250 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3251
3252 switch (p->type) {
3253 case PIPE_SHADER_VERTEX:
3254 p->cfg.psiz = 0x40;
3255 p->cfg.clpd = 0x40;
3256 p->cfg.io_nr = pc->result_nr;
3257 break;
3258 case PIPE_SHADER_FRAGMENT:
3259 rtype[0] = rtype[1] = P_TEMP;
3260
3261 p->cfg.regs[0] = 0x01000004;
3262 p->cfg.io_nr = pc->attr_nr;
3263
3264 if (p->info.writes_z) {
3265 p->cfg.regs[2] |= 0x00000100;
3266 p->cfg.regs[3] |= 0x00000011;
3267 }
3268 if (p->info.uses_kill)
3269 p->cfg.regs[2] |= 0x00100000;
3270 break;
3271 }
3272
3273 if (pc->temp_nr) {
3274 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3275 if (!pc->temp)
3276 return FALSE;
3277
3278 for (i = 0; i < pc->temp_nr * 4; ++i)
3279 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3280 }
3281
3282 if (pc->attr_nr) {
3283 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3284 if (!pc->attr)
3285 return FALSE;
3286
3287 for (i = 0; i < pc->attr_nr * 4; ++i)
3288 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3289 }
3290
3291 if (pc->result_nr) {
3292 unsigned nr = pc->result_nr * 4;
3293
3294 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3295 if (!pc->result)
3296 return FALSE;
3297
3298 for (i = 0; i < nr; ++i)
3299 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3300 }
3301
3302 if (pc->param_nr) {
3303 int rid = 0;
3304
3305 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3306 if (!pc->param)
3307 return FALSE;
3308
3309 for (i = 0; i < pc->param_nr; ++i)
3310 for (c = 0; c < 4; ++c, ++rid)
3311 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3312 }
3313
3314 if (pc->addr_nr) {
3315 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3316 if (!pc->addr)
3317 return FALSE;
3318 }
3319 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3320 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
3321
3322 return TRUE;
3323 }
3324
3325 static void
3326 nv50_program_fixup_insns(struct nv50_pc *pc)
3327 {
3328 struct nv50_program_exec *e, **bra_list;
3329 unsigned i, n, pos;
3330
3331 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3332
3333 /* Collect branch instructions, we need to adjust their offsets
3334 * when converting 32 bit instructions to 64 bit ones
3335 */
3336 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3337 if (e->param.index >= 0 && !e->param.mask)
3338 bra_list[n++] = e;
3339
3340 /* Make sure we don't have any single 32 bit instructions. */
3341 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3342 pos += is_long(e) ? 2 : 1;
3343
3344 if ((pos & 1) && (!e->next || is_long(e->next))) {
3345 for (i = 0; i < n; ++i)
3346 if (bra_list[i]->param.index >= pos)
3347 bra_list[i]->param.index += 1;
3348 for (i = 0; i < pc->insn_nr; ++i)
3349 if (pc->insn_pos[i] >= pos)
3350 pc->insn_pos[i] += 1;
3351 convert_to_long(pc, e);
3352 ++pos;
3353 }
3354 }
3355
3356 FREE(bra_list);
3357
3358 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
3359 return;
3360
3361 /* fill in CALL offsets */
3362 for (e = pc->p->exec_head; e; e = e->next) {
3363 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
3364 e->param.index = pc->insn_pos[e->param.index];
3365 }
3366 }
3367
3368 static boolean
3369 nv50_program_tx(struct nv50_program *p)
3370 {
3371 struct tgsi_parse_context parse;
3372 struct nv50_pc *pc;
3373 boolean ret;
3374
3375 pc = CALLOC_STRUCT(nv50_pc);
3376 if (!pc)
3377 return FALSE;
3378
3379 ret = ctor_nv50_pc(pc, p);
3380 if (ret == FALSE)
3381 goto out_cleanup;
3382
3383 ret = nv50_program_tx_prep(pc);
3384 if (ret == FALSE)
3385 goto out_cleanup;
3386
3387 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
3388
3389 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3390 while (!tgsi_parse_end_of_tokens(&parse)) {
3391 const union tgsi_full_token *tok = &parse.FullToken;
3392
3393 /* previously allow32 was FALSE for first & last instruction */
3394 pc->allow32 = TRUE;
3395
3396 tgsi_parse_token(&parse);
3397
3398 switch (tok->Token.Type) {
3399 case TGSI_TOKEN_TYPE_INSTRUCTION:
3400 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
3401 ++pc->insn_cur;
3402 ret = nv50_tgsi_insn(pc, tok);
3403 if (ret == FALSE)
3404 goto out_err;
3405 break;
3406 default:
3407 break;
3408 }
3409 }
3410
3411 nv50_program_fixup_insns(pc);
3412
3413 p->param_nr = pc->param_nr * 4;
3414 p->immd_nr = pc->immd_nr * 4;
3415 p->immd = pc->immd_buf;
3416
3417 out_err:
3418 tgsi_parse_free(&parse);
3419
3420 out_cleanup:
3421 free_nv50_pc(pc);
3422 return ret;
3423 }
3424
3425 static void
3426 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3427 {
3428 if (nv50_program_tx(p) == FALSE)
3429 assert(0);
3430 p->translated = TRUE;
3431 }
3432
3433 static void
3434 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
3435 unsigned start, unsigned count, unsigned cbuf)
3436 {
3437 struct nouveau_channel *chan = nv50->screen->base.channel;
3438 struct nouveau_grobj *tesla = nv50->screen->tesla;
3439
3440 while (count) {
3441 unsigned nr = count > 2047 ? 2047 : count;
3442
3443 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3444 OUT_RING (chan, (cbuf << 0) | (start << 8));
3445 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3446 OUT_RINGp (chan, map, nr);
3447
3448 map += nr;
3449 start += nr;
3450 count -= nr;
3451 }
3452 }
3453
3454 static void
3455 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3456 {
3457 struct pipe_screen *pscreen = nv50->pipe.screen;
3458
3459 if (!p->data[0] && p->immd_nr) {
3460 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3461
3462 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3463 while (heap->next && heap->size < p->immd_nr) {
3464 struct nv50_program *evict = heap->next->priv;
3465 nouveau_resource_free(&evict->data[0]);
3466 }
3467
3468 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3469 &p->data[0]))
3470 assert(0);
3471 }
3472
3473 /* immediates only need to be uploaded again when freed */
3474 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3475 p->immd_nr, NV50_CB_PMISC);
3476 }
3477
3478 assert(p->param_nr <= 512);
3479
3480 if (p->param_nr) {
3481 unsigned cb;
3482 uint32_t *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3483 PIPE_BUFFER_USAGE_CPU_READ);
3484
3485 if (p->type == PIPE_SHADER_VERTEX)
3486 cb = NV50_CB_PVP;
3487 else
3488 cb = NV50_CB_PFP;
3489
3490 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3491 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3492 }
3493 }
3494
3495 static void
3496 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3497 {
3498 struct nouveau_channel *chan = nv50->screen->base.channel;
3499 struct nv50_program_exec *e;
3500 uint32_t *up, i;
3501 boolean upload = FALSE;
3502
3503 if (!p->bo) {
3504 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3505 p->exec_size * 4, &p->bo);
3506 upload = TRUE;
3507 }
3508
3509 if (p->data[0] && p->data[0]->start != p->data_start[0])
3510 upload = TRUE;
3511
3512 if (!upload)
3513 return;
3514
3515 up = MALLOC(p->exec_size * 4);
3516
3517 for (i = 0, e = p->exec_head; e; e = e->next) {
3518 unsigned ei, ci, bs;
3519
3520 if (e->param.index >= 0 && e->param.mask) {
3521 bs = (e->inst[1] >> 22) & 0x07;
3522 assert(bs < 2);
3523 ei = e->param.shift >> 5;
3524 ci = e->param.index;
3525 if (bs == 0)
3526 ci += p->data[bs]->start;
3527
3528 e->inst[ei] &= ~e->param.mask;
3529 e->inst[ei] |= (ci << e->param.shift);
3530 } else
3531 if (e->param.index >= 0) {
3532 /* zero mask means param is a jump/branch offset */
3533 assert(!(e->param.index & 1));
3534 /* seem to be 8 byte steps */
3535 ei = (e->param.index >> 1) + 0 /* START_ID */;
3536
3537 e->inst[0] &= 0xf0000fff;
3538 e->inst[0] |= ei << 12;
3539 }
3540
3541 up[i++] = e->inst[0];
3542 if (is_long(e))
3543 up[i++] = e->inst[1];
3544 }
3545 assert(i == p->exec_size);
3546
3547 if (p->data[0])
3548 p->data_start[0] = p->data[0]->start;
3549
3550 #ifdef NV50_PROGRAM_DUMP
3551 NOUVEAU_ERR("-------\n");
3552 for (e = p->exec_head; e; e = e->next) {
3553 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3554 if (is_long(e))
3555 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3556 }
3557 #endif
3558 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3559 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3560 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3561 0, 0, p->exec_size * 4, 1, 1);
3562
3563 FREE(up);
3564 }
3565
3566 void
3567 nv50_vertprog_validate(struct nv50_context *nv50)
3568 {
3569 struct nouveau_grobj *tesla = nv50->screen->tesla;
3570 struct nv50_program *p = nv50->vertprog;
3571 struct nouveau_stateobj *so;
3572
3573 if (!p->translated) {
3574 nv50_program_validate(nv50, p);
3575 if (!p->translated)
3576 assert(0);
3577 }
3578
3579 nv50_program_validate_data(nv50, p);
3580 nv50_program_validate_code(nv50, p);
3581
3582 so = so_new(13, 2);
3583 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3584 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3585 NOUVEAU_BO_HIGH, 0, 0);
3586 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3587 NOUVEAU_BO_LOW, 0, 0);
3588 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3589 so_data (so, p->cfg.attr[0]);
3590 so_data (so, p->cfg.attr[1]);
3591 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3592 so_data (so, p->cfg.high_result);
3593 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3594 so_data (so, p->cfg.high_result); //8);
3595 so_data (so, p->cfg.high_temp);
3596 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3597 so_data (so, 0); /* program start offset */
3598 so_ref(so, &nv50->state.vertprog);
3599 so_ref(NULL, &so);
3600 }
3601
3602 void
3603 nv50_fragprog_validate(struct nv50_context *nv50)
3604 {
3605 struct nouveau_grobj *tesla = nv50->screen->tesla;
3606 struct nv50_program *p = nv50->fragprog;
3607 struct nouveau_stateobj *so;
3608
3609 if (!p->translated) {
3610 nv50_program_validate(nv50, p);
3611 if (!p->translated)
3612 assert(0);
3613 }
3614
3615 nv50_program_validate_data(nv50, p);
3616 nv50_program_validate_code(nv50, p);
3617
3618 so = so_new(64, 2);
3619 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3620 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3621 NOUVEAU_BO_HIGH, 0, 0);
3622 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3623 NOUVEAU_BO_LOW, 0, 0);
3624 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3625 so_data (so, p->cfg.high_temp);
3626 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3627 so_data (so, p->cfg.high_result);
3628 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
3629 so_data (so, p->cfg.regs[2]);
3630 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3631 so_data (so, p->cfg.regs[3]);
3632 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3633 so_data (so, 0); /* program start offset */
3634 so_ref(so, &nv50->state.fragprog);
3635 so_ref(NULL, &so);
3636 }
3637
3638 static void
3639 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3640 {
3641 struct nv50_program *fp = nv50->fragprog;
3642 struct nv50_program *vp = nv50->vertprog;
3643 unsigned i, c, m = base;
3644
3645 /* XXX: this might not work correctly in all cases yet - we'll
3646 * just assume that an FP generic input that is not written in
3647 * the VP is PointCoord.
3648 */
3649 memset(pntc, 0, 8 * sizeof(uint32_t));
3650
3651 for (i = 0; i < fp->cfg.io_nr; i++) {
3652 uint8_t sn, si;
3653 uint8_t j, k = fp->cfg.io[i].id;
3654 unsigned n = popcnt4(fp->cfg.io[i].mask);
3655
3656 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3657 m += n;
3658 continue;
3659 }
3660
3661 for (j = 0; j < vp->info.num_outputs; ++j) {
3662 sn = vp->info.output_semantic_name[j];
3663 si = vp->info.output_semantic_index[j];
3664
3665 if (sn == fp->info.input_semantic_name[k] &&
3666 si == fp->info.input_semantic_index[k])
3667 break;
3668 }
3669
3670 if (j < vp->info.num_outputs) {
3671 ubyte mode =
3672 nv50->rasterizer->pipe.sprite_coord_mode[si];
3673
3674 if (mode == PIPE_SPRITE_COORD_NONE) {
3675 m += n;
3676 continue;
3677 }
3678 }
3679
3680 /* this is either PointCoord or replaced by sprite coords */
3681 for (c = 0; c < 4; c++) {
3682 if (!(fp->cfg.io[i].mask & (1 << c)))
3683 continue;
3684 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3685 ++m;
3686 }
3687 }
3688 }
3689
3690 static int
3691 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3692 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3693 {
3694 int c;
3695 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3696 uint8_t *map = (uint8_t *)p_map;
3697
3698 for (c = 0; c < 4; ++c) {
3699 if (mf & 1) {
3700 if (fpi->linear == TRUE)
3701 lin[mid / 32] |= 1 << (mid % 32);
3702 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3703 }
3704
3705 oid += mv & 1;
3706 mf >>= 1;
3707 mv >>= 1;
3708 }
3709
3710 return mid;
3711 }
3712
3713 void
3714 nv50_linkage_validate(struct nv50_context *nv50)
3715 {
3716 struct nouveau_grobj *tesla = nv50->screen->tesla;
3717 struct nv50_program *vp = nv50->vertprog;
3718 struct nv50_program *fp = nv50->fragprog;
3719 struct nouveau_stateobj *so;
3720 struct nv50_sreg4 dummy, *vpo;
3721 int i, n, c, m = 0;
3722 uint32_t map[16], lin[4], reg[5], pcrd[8];
3723
3724 memset(map, 0, sizeof(map));
3725 memset(lin, 0, sizeof(lin));
3726
3727 reg[1] = 0x00000004; /* low and high clip distance map ids */
3728 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3729 reg[3] = 0x00000000; /* point size map id & enable */
3730 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3731 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3732
3733 dummy.linear = FALSE;
3734 dummy.mask = 0xf; /* map all components of HPOS */
3735 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3736
3737 dummy.mask = 0x0;
3738
3739 if (vp->cfg.clpd < 0x40) {
3740 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3741 map[m++] = vp->cfg.clpd + c;
3742 reg[1] = (m << 8);
3743 }
3744
3745 reg[0] |= m << 8; /* adjust BFC0 id */
3746
3747 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3748 if (nv50->rasterizer->pipe.light_twoside) {
3749 vpo = &vp->cfg.two_side[0];
3750
3751 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3752 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3753 }
3754
3755 reg[0] += m - 4; /* adjust FFC0 id */
3756 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3757
3758 for (i = 0; i < fp->cfg.io_nr; i++) {
3759 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
3760 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
3761
3762 /* position must be mapped first */
3763 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
3764
3765 /* maybe even remove these from cfg.io */
3766 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
3767 continue;
3768
3769 /* VP outputs and vp->cfg.io are in the same order */
3770 for (n = 0; n < vp->info.num_outputs; ++n) {
3771 if (vp->info.output_semantic_name[n] == sn &&
3772 vp->info.output_semantic_index[n] == si)
3773 break;
3774 }
3775 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
3776
3777 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3778 }
3779
3780 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3781 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3782 reg[3] = (m++ << 4) | 1;
3783 }
3784
3785 /* now fill the stateobj */
3786 so = so_new(64, 0);
3787
3788 n = (m + 3) / 4;
3789 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3790 so_data (so, m);
3791 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3792 so_datap (so, map, n);
3793
3794 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3795 so_datap (so, reg, 4);
3796
3797 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3798 so_data (so, reg[4]);
3799
3800 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
3801 so_datap (so, lin, 4);
3802
3803 if (nv50->rasterizer->pipe.point_sprite) {
3804 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3805
3806 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3807 so_datap (so, pcrd, 8);
3808 }
3809
3810 so_ref(so, &nv50->state.programs);
3811 so_ref(NULL, &so);
3812 }
3813
3814 void
3815 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3816 {
3817 while (p->exec_head) {
3818 struct nv50_program_exec *e = p->exec_head;
3819
3820 p->exec_head = e->next;
3821 FREE(e);
3822 }
3823 p->exec_tail = NULL;
3824 p->exec_size = 0;
3825
3826 nouveau_bo_ref(NULL, &p->bo);
3827
3828 nouveau_resource_free(&p->data[0]);
3829
3830 p->translated = 0;
3831 }