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nv50: fix memory leak on nv50_pc free
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
100 #define NV50_MOD_SAT 4
101 #define NV50_MOD_I32 8
102
103 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
104
105 /* STACK: Conditionals and loops have to use the (per warp) stack.
106 * Stack entries consist of an entry type (divergent path, join at),
107 * a mask indicating the active threads of the warp, and an address.
108 * MPs can store 12 stack entries internally, if we need more (and
109 * we probably do), we have to create a stack buffer in VRAM.
110 */
111 /* impose low limits for now */
112 #define NV50_MAX_COND_NESTING 4
113 #define NV50_MAX_LOOP_NESTING 3
114
115 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
116
117 struct nv50_pc {
118 struct nv50_program *p;
119
120 /* hw resources */
121 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
122 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
123
124 /* tgsi resources */
125 struct nv50_reg *temp;
126 int temp_nr;
127 struct nv50_reg *attr;
128 int attr_nr;
129 struct nv50_reg *result;
130 int result_nr;
131 struct nv50_reg *param;
132 int param_nr;
133 struct nv50_reg *immd;
134 uint32_t *immd_buf;
135 int immd_nr;
136 struct nv50_reg **addr;
137 int addr_nr;
138 uint8_t addr_alloc; /* set bit indicates used for TGSI_FILE_ADDRESS */
139
140 struct nv50_reg *temp_temp[16];
141 struct nv50_program_exec *temp_temp_exec[16];
142 unsigned temp_temp_nr;
143
144 /* broadcast and destination replacement regs */
145 struct nv50_reg *r_brdc;
146 struct nv50_reg *r_dst[4];
147
148 struct nv50_reg reg_instances[16];
149 unsigned reg_instance_nr;
150
151 unsigned interp_mode[32];
152 /* perspective interpolation registers */
153 struct nv50_reg *iv_p;
154 struct nv50_reg *iv_c;
155
156 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
157 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
158 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
159 int if_lvl, loop_lvl;
160 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
161
162 unsigned *insn_pos; /* actual program offset of each TGSI insn */
163 boolean in_subroutine;
164
165 /* current instruction and total number of insns */
166 unsigned insn_cur;
167 unsigned insn_nr;
168
169 boolean allow32;
170
171 uint8_t edgeflag_out;
172 };
173
174 static INLINE void
175 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
176 {
177 reg->type = type;
178 reg->index = index;
179 reg->hw = hw;
180 reg->mod = 0;
181 reg->rhw = -1;
182 reg->acc = 0;
183 }
184
185 static INLINE unsigned
186 popcnt4(uint32_t val)
187 {
188 static const unsigned cnt[16]
189 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
190 return cnt[val & 0xf];
191 }
192
193 static void
194 terminate_mbb(struct nv50_pc *pc)
195 {
196 int i;
197
198 /* remove records of temporary address register values */
199 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
200 pc->r_addr[i].rhw = -1;
201 }
202
203 static void
204 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
205 {
206 int i = 0;
207
208 if (reg->type == P_RESULT) {
209 if (pc->p->cfg.high_result < (reg->hw + 1))
210 pc->p->cfg.high_result = reg->hw + 1;
211 }
212
213 if (reg->type != P_TEMP)
214 return;
215
216 if (reg->hw >= 0) {
217 /*XXX: do this here too to catch FP temp-as-attr usage..
218 * not clean, but works */
219 if (pc->p->cfg.high_temp < (reg->hw + 1))
220 pc->p->cfg.high_temp = reg->hw + 1;
221 return;
222 }
223
224 if (reg->rhw != -1) {
225 /* try to allocate temporary with index rhw first */
226 if (!(pc->r_temp[reg->rhw])) {
227 pc->r_temp[reg->rhw] = reg;
228 reg->hw = reg->rhw;
229 if (pc->p->cfg.high_temp < (reg->rhw + 1))
230 pc->p->cfg.high_temp = reg->rhw + 1;
231 return;
232 }
233 /* make sure we don't get things like $r0 needs to go
234 * in $r1 and $r1 in $r0
235 */
236 i = pc->result_nr * 4;
237 }
238
239 for (; i < NV50_SU_MAX_TEMP; i++) {
240 if (!(pc->r_temp[i])) {
241 pc->r_temp[i] = reg;
242 reg->hw = i;
243 if (pc->p->cfg.high_temp < (i + 1))
244 pc->p->cfg.high_temp = i + 1;
245 return;
246 }
247 }
248
249 NOUVEAU_ERR("out of registers\n");
250 abort();
251 }
252
253 static INLINE struct nv50_reg *
254 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
255 {
256 struct nv50_reg *ri;
257
258 assert(pc->reg_instance_nr < 16);
259 ri = &pc->reg_instances[pc->reg_instance_nr++];
260 if (reg) {
261 alloc_reg(pc, reg);
262 *ri = *reg;
263 reg->mod = 0;
264 }
265 return ri;
266 }
267
268 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
269 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
270 * lest we risk temp_temps overwriting regs alloc'd "later".
271 */
272 static struct nv50_reg *
273 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
274 {
275 struct nv50_reg *r;
276 int i;
277
278 if (dst && dst->type == P_TEMP && dst->hw == -1)
279 return dst;
280
281 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
282 if (!pc->r_temp[i]) {
283 r = MALLOC_STRUCT(nv50_reg);
284 ctor_reg(r, P_TEMP, -1, i);
285 pc->r_temp[i] = r;
286 return r;
287 }
288 }
289
290 NOUVEAU_ERR("out of registers\n");
291 abort();
292 return NULL;
293 }
294
295 /* release the hardware resource held by r */
296 static void
297 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
298 {
299 assert(r->type == P_TEMP);
300 if (r->hw == -1)
301 return;
302
303 assert(pc->r_temp[r->hw] == r);
304 pc->r_temp[r->hw] = NULL;
305
306 r->acc = 0;
307 if (r->index == -1)
308 FREE(r);
309 }
310
311 static void
312 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
313 {
314 if (r->index == -1) {
315 unsigned hw = r->hw;
316
317 FREE(pc->r_temp[hw]);
318 pc->r_temp[hw] = NULL;
319 }
320 }
321
322 static int
323 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
324 {
325 int i;
326
327 if ((idx + 4) >= NV50_SU_MAX_TEMP)
328 return 1;
329
330 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
331 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
332 return alloc_temp4(pc, dst, idx + 4);
333
334 for (i = 0; i < 4; i++) {
335 dst[i] = MALLOC_STRUCT(nv50_reg);
336 ctor_reg(dst[i], P_TEMP, -1, idx + i);
337 pc->r_temp[idx + i] = dst[i];
338 }
339
340 return 0;
341 }
342
343 static void
344 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
345 {
346 int i;
347
348 for (i = 0; i < 4; i++)
349 free_temp(pc, reg[i]);
350 }
351
352 static struct nv50_reg *
353 temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
354 {
355 if (pc->temp_temp_nr >= 16)
356 assert(0);
357
358 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
359 pc->temp_temp_exec[pc->temp_temp_nr] = e;
360 return pc->temp_temp[pc->temp_temp_nr++];
361 }
362
363 /* This *must* be called for all nv50_program_exec that have been
364 * given as argument to temp_temp, or the temps will be leaked !
365 */
366 static void
367 kill_temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
368 {
369 int i;
370
371 for (i = 0; i < pc->temp_temp_nr; i++)
372 if (pc->temp_temp_exec[i] == e)
373 free_temp(pc, pc->temp_temp[i]);
374 if (!e)
375 pc->temp_temp_nr = 0;
376 }
377
378 static int
379 ctor_immd_4u32(struct nv50_pc *pc,
380 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
381 {
382 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
383
384 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
385
386 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
387 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
388 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
389 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
390
391 return pc->immd_nr++;
392 }
393
394 static INLINE int
395 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
396 {
397 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
398 }
399
400 static struct nv50_reg *
401 alloc_immd(struct nv50_pc *pc, float f)
402 {
403 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
404 unsigned hw;
405
406 for (hw = 0; hw < pc->immd_nr * 4; hw++)
407 if (pc->immd_buf[hw] == fui(f))
408 break;
409
410 if (hw == pc->immd_nr * 4)
411 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
412
413 ctor_reg(r, P_IMMD, -1, hw);
414 return r;
415 }
416
417 static struct nv50_program_exec *
418 exec(struct nv50_pc *pc)
419 {
420 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
421
422 e->param.index = -1;
423 return e;
424 }
425
426 static void
427 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
428 {
429 struct nv50_program *p = pc->p;
430
431 if (p->exec_tail)
432 p->exec_tail->next = e;
433 if (!p->exec_head)
434 p->exec_head = e;
435 p->exec_tail = e;
436 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
437
438 kill_temp_temp(pc, e);
439 }
440
441 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
442
443 static boolean
444 is_long(struct nv50_program_exec *e)
445 {
446 if (e->inst[0] & 1)
447 return TRUE;
448 return FALSE;
449 }
450
451 static boolean
452 is_immd(struct nv50_program_exec *e)
453 {
454 if (is_long(e) && (e->inst[1] & 3) == 3)
455 return TRUE;
456 return FALSE;
457 }
458
459 static boolean
460 is_join(struct nv50_program_exec *e)
461 {
462 if (is_long(e) && (e->inst[1] & 3) == 2)
463 return TRUE;
464 return FALSE;
465 }
466
467 static INLINE void
468 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
469 struct nv50_program_exec *e)
470 {
471 assert(!is_immd(e));
472 set_long(pc, e);
473 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
474 e->inst[1] |= (pred << 7) | (idx << 12);
475 }
476
477 static INLINE void
478 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
479 struct nv50_program_exec *e)
480 {
481 set_long(pc, e);
482 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
483 e->inst[1] |= (idx << 4) | (on << 6);
484 }
485
486 static INLINE void
487 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
488 {
489 if (is_long(e))
490 return;
491
492 e->inst[0] |= 1;
493 set_pred(pc, 0xf, 0, e);
494 set_pred_wr(pc, 0, 0, e);
495 }
496
497 static INLINE void
498 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
499 {
500 if (dst->type == P_RESULT) {
501 set_long(pc, e);
502 e->inst[1] |= 0x00000008;
503 }
504
505 alloc_reg(pc, dst);
506 if (dst->hw > 63)
507 set_long(pc, e);
508 e->inst[0] |= (dst->hw << 2);
509 }
510
511 static INLINE void
512 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
513 {
514 set_long(pc, e);
515 /* XXX: can't be predicated - bits overlap; cases where both
516 * are required should be avoided by using pc->allow32 */
517 set_pred(pc, 0, 0, e);
518 set_pred_wr(pc, 0, 0, e);
519
520 e->inst[1] |= 0x00000002 | 0x00000001;
521 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
522 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
523 }
524
525 static INLINE void
526 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
527 {
528 assert(!(e->inst[0] & 0x0c000000));
529 assert(!(e->inst[1] & 0x00000004));
530
531 e->inst[0] |= (a->hw & 3) << 26;
532 e->inst[1] |= (a->hw >> 2) << 2;
533 }
534
535 static void
536 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
537 struct nv50_reg *src0, uint16_t src1_val)
538 {
539 struct nv50_program_exec *e = exec(pc);
540
541 e->inst[0] = 0xd0000000 | (src1_val << 9);
542 e->inst[1] = 0x20000000;
543 set_long(pc, e);
544 e->inst[0] |= dst->hw << 2;
545 if (src0) /* otherwise will add to $a0, which is always 0 */
546 set_addr(e, src0);
547
548 emit(pc, e);
549 }
550
551 static struct nv50_reg *
552 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
553 {
554 struct nv50_reg *a_tgsi = NULL, *a = NULL;
555 int i;
556 uint8_t avail = ~pc->addr_alloc;
557
558 if (!ref) {
559 /* allocate for TGSI_FILE_ADDRESS */
560 while (avail) {
561 i = ffs(avail) - 1;
562
563 if (pc->r_addr[i].rhw < 0 ||
564 pc->r_addr[i].acc != pc->insn_cur) {
565 pc->addr_alloc |= (1 << i);
566
567 pc->r_addr[i].rhw = -1;
568 pc->r_addr[i].index = i;
569 return &pc->r_addr[i];
570 }
571 avail &= ~(1 << i);
572 }
573 assert(0);
574 return NULL;
575 }
576
577 /* Allocate and set an address reg so we can access 'ref'.
578 *
579 * If and r_addr->index will be -1 or the hw index the value
580 * value in rhw is relative to. If rhw < 0, the reg has not
581 * been initialized or is in use for TGSI_FILE_ADDRESS.
582 */
583 while (avail) { /* only consider regs that are not TGSI */
584 i = ffs(avail) - 1;
585 avail &= ~(1 << i);
586
587 if ((!a || a->rhw >= 0) && pc->r_addr[i].rhw < 0) {
588 /* prefer an usused reg with low hw index */
589 a = &pc->r_addr[i];
590 continue;
591 }
592 if (!a && pc->r_addr[i].acc != pc->insn_cur)
593 a = &pc->r_addr[i];
594
595 if (ref->hw - pc->r_addr[i].rhw >= 128)
596 continue;
597
598 if ((ref->acc >= 0 && pc->r_addr[i].index < 0) ||
599 (ref->acc < 0 && pc->r_addr[i].index == ref->index)) {
600 pc->r_addr[i].acc = pc->insn_cur;
601 return &pc->r_addr[i];
602 }
603 }
604 assert(a);
605
606 if (ref->acc < 0)
607 a_tgsi = pc->addr[ref->index];
608
609 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
610
611 a->rhw = ref->hw & ~0x7f;
612 a->acc = pc->insn_cur;
613 a->index = a_tgsi ? ref->index : -1;
614 return a;
615 }
616
617 #define INTERP_LINEAR 0
618 #define INTERP_FLAT 1
619 #define INTERP_PERSPECTIVE 2
620 #define INTERP_CENTROID 4
621
622 /* interpolant index has been stored in dst->rhw */
623 static void
624 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
625 unsigned mode)
626 {
627 assert(dst->rhw != -1);
628 struct nv50_program_exec *e = exec(pc);
629
630 e->inst[0] |= 0x80000000;
631 set_dst(pc, dst, e);
632 e->inst[0] |= (dst->rhw << 16);
633
634 if (mode & INTERP_FLAT) {
635 e->inst[0] |= (1 << 8);
636 } else {
637 if (mode & INTERP_PERSPECTIVE) {
638 e->inst[0] |= (1 << 25);
639 alloc_reg(pc, iv);
640 e->inst[0] |= (iv->hw << 9);
641 }
642
643 if (mode & INTERP_CENTROID)
644 e->inst[0] |= (1 << 24);
645 }
646
647 emit(pc, e);
648 }
649
650 static void
651 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
652 struct nv50_program_exec *e)
653 {
654 set_long(pc, e);
655
656 e->param.index = src->hw & 127;
657 e->param.shift = s;
658 e->param.mask = m << (s % 32);
659
660 if (src->hw > 127)
661 set_addr(e, alloc_addr(pc, src));
662 else
663 if (src->acc < 0) {
664 assert(src->type == P_CONST);
665 set_addr(e, pc->addr[src->index]);
666 }
667
668 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
669 }
670
671 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
672 static void
673 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
674 {
675 struct nv50_program_exec *e = exec(pc);
676
677 e->inst[0] = 0x10000000;
678 if (!pc->allow32)
679 set_long(pc, e);
680
681 set_dst(pc, dst, e);
682
683 if (!is_long(e) && src->type == P_IMMD) {
684 set_immd(pc, src, e);
685 /*XXX: 32-bit, but steals part of "half" reg space - need to
686 * catch and handle this case if/when we do half-regs
687 */
688 } else
689 if (src->type == P_IMMD || src->type == P_CONST) {
690 set_long(pc, e);
691 set_data(pc, src, 0x7f, 9, e);
692 e->inst[1] |= 0x20000000; /* mov from c[] */
693 } else {
694 if (src->type == P_ATTR) {
695 set_long(pc, e);
696 e->inst[1] |= 0x00200000;
697 }
698
699 alloc_reg(pc, src);
700 if (src->hw > 63)
701 set_long(pc, e);
702 e->inst[0] |= (src->hw << 9);
703 }
704
705 if (is_long(e) && !is_immd(e)) {
706 e->inst[1] |= 0x04000000; /* 32-bit */
707 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
708 if (!(e->inst[1] & 0x20000000))
709 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
710 } else
711 e->inst[0] |= 0x00008000;
712
713 emit(pc, e);
714 }
715
716 static INLINE void
717 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
718 {
719 struct nv50_reg *imm = alloc_immd(pc, f);
720 emit_mov(pc, dst, imm);
721 FREE(imm);
722 }
723
724 /* Assign the hw of the discarded temporary register src
725 * to the tgsi register dst and free src.
726 */
727 static void
728 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
729 {
730 assert(src->index == -1 && src->hw != -1);
731
732 if (pc->if_lvl || pc->loop_lvl ||
733 (dst->type != P_TEMP) ||
734 (src->hw < pc->result_nr * 4 &&
735 pc->p->type == PIPE_SHADER_FRAGMENT) ||
736 pc->p->info.opcode_count[TGSI_OPCODE_CAL] ||
737 pc->p->info.opcode_count[TGSI_OPCODE_BRA]) {
738
739 emit_mov(pc, dst, src);
740 free_temp(pc, src);
741 return;
742 }
743
744 if (dst->hw != -1)
745 pc->r_temp[dst->hw] = NULL;
746 pc->r_temp[src->hw] = dst;
747 dst->hw = src->hw;
748
749 FREE(src);
750 }
751
752 static void
753 emit_nop(struct nv50_pc *pc)
754 {
755 struct nv50_program_exec *e = exec(pc);
756
757 e->inst[0] = 0xf0000000;
758 set_long(pc, e);
759 e->inst[1] = 0xe0000000;
760 emit(pc, e);
761 }
762
763 static boolean
764 check_swap_src_0_1(struct nv50_pc *pc,
765 struct nv50_reg **s0, struct nv50_reg **s1)
766 {
767 struct nv50_reg *src0 = *s0, *src1 = *s1;
768
769 if (src0->type == P_CONST) {
770 if (src1->type != P_CONST) {
771 *s0 = src1;
772 *s1 = src0;
773 return TRUE;
774 }
775 } else
776 if (src1->type == P_ATTR) {
777 if (src0->type != P_ATTR) {
778 *s0 = src1;
779 *s1 = src0;
780 return TRUE;
781 }
782 }
783
784 return FALSE;
785 }
786
787 static void
788 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
789 struct nv50_program_exec *e)
790 {
791 struct nv50_reg *temp;
792
793 if (src->type != P_TEMP) {
794 temp = temp_temp(pc, e);
795 emit_mov(pc, temp, src);
796 src = temp;
797 }
798
799 alloc_reg(pc, src);
800 if (src->hw > 63)
801 set_long(pc, e);
802 e->inst[0] |= (src->hw << 9);
803 }
804
805 static void
806 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
807 {
808 if (src->type == P_ATTR) {
809 set_long(pc, e);
810 e->inst[1] |= 0x00200000;
811 } else
812 if (src->type == P_CONST || src->type == P_IMMD) {
813 struct nv50_reg *temp = temp_temp(pc, e);
814
815 emit_mov(pc, temp, src);
816 src = temp;
817 }
818
819 alloc_reg(pc, src);
820 if (src->hw > 63)
821 set_long(pc, e);
822 e->inst[0] |= (src->hw << 9);
823 }
824
825 static void
826 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
827 {
828 if (src->type == P_ATTR) {
829 struct nv50_reg *temp = temp_temp(pc, e);
830
831 emit_mov(pc, temp, src);
832 src = temp;
833 } else
834 if (src->type == P_CONST || src->type == P_IMMD) {
835 assert(!(e->inst[0] & 0x00800000));
836 if (e->inst[0] & 0x01000000) {
837 struct nv50_reg *temp = temp_temp(pc, e);
838
839 emit_mov(pc, temp, src);
840 src = temp;
841 } else {
842 set_data(pc, src, 0x7f, 16, e);
843 e->inst[0] |= 0x00800000;
844 }
845 }
846
847 alloc_reg(pc, src);
848 if (src->hw > 63)
849 set_long(pc, e);
850 e->inst[0] |= ((src->hw & 127) << 16);
851 }
852
853 static void
854 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
855 {
856 set_long(pc, e);
857
858 if (src->type == P_ATTR) {
859 struct nv50_reg *temp = temp_temp(pc, e);
860
861 emit_mov(pc, temp, src);
862 src = temp;
863 } else
864 if (src->type == P_CONST || src->type == P_IMMD) {
865 assert(!(e->inst[0] & 0x01000000));
866 if (e->inst[0] & 0x00800000) {
867 struct nv50_reg *temp = temp_temp(pc, e);
868
869 emit_mov(pc, temp, src);
870 src = temp;
871 } else {
872 set_data(pc, src, 0x7f, 32+14, e);
873 e->inst[0] |= 0x01000000;
874 }
875 }
876
877 alloc_reg(pc, src);
878 e->inst[1] |= ((src->hw & 127) << 14);
879 }
880
881 static void
882 set_half_src(struct nv50_pc *pc, struct nv50_reg *src, int lh,
883 struct nv50_program_exec *e, int pos)
884 {
885 struct nv50_reg *r = src;
886
887 alloc_reg(pc, r);
888 if (r->type != P_TEMP) {
889 r = temp_temp(pc, e);
890 emit_mov(pc, r, src);
891 }
892
893 if (r->hw > (NV50_SU_MAX_TEMP / 2)) {
894 NOUVEAU_ERR("out of low GPRs\n");
895 abort();
896 }
897
898 e->inst[pos / 32] |= ((src->hw * 2) + lh) << (pos % 32);
899 }
900
901 static void
902 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
903 {
904 struct nv50_program_exec *e = exec(pc);
905
906 assert(dst->type == P_TEMP);
907 e->inst[1] = 0x20000000 | (pred << 12);
908 set_long(pc, e);
909 set_dst(pc, dst, e);
910
911 emit(pc, e);
912 }
913
914 static void
915 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
916 {
917 struct nv50_program_exec *e = exec(pc);
918
919 e->inst[0] = 0x000001fc;
920 e->inst[1] = 0xa0000008;
921 set_long(pc, e);
922 set_pred_wr(pc, 1, pred, e);
923 set_src_0_restricted(pc, src, e);
924
925 emit(pc, e);
926 }
927
928 static void
929 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
930 struct nv50_reg *src1)
931 {
932 struct nv50_program_exec *e = exec(pc);
933
934 e->inst[0] |= 0xc0000000;
935
936 if (!pc->allow32)
937 set_long(pc, e);
938
939 check_swap_src_0_1(pc, &src0, &src1);
940 set_dst(pc, dst, e);
941 set_src_0(pc, src0, e);
942 if (src1->type == P_IMMD && !is_long(e)) {
943 if (src0->mod ^ src1->mod)
944 e->inst[0] |= 0x00008000;
945 set_immd(pc, src1, e);
946 } else {
947 set_src_1(pc, src1, e);
948 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
949 if (is_long(e))
950 e->inst[1] |= 0x08000000;
951 else
952 e->inst[0] |= 0x00008000;
953 }
954 }
955
956 emit(pc, e);
957 }
958
959 static void
960 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
961 struct nv50_reg *src0, struct nv50_reg *src1)
962 {
963 struct nv50_program_exec *e = exec(pc);
964
965 e->inst[0] = 0xb0000000;
966
967 alloc_reg(pc, src1);
968 check_swap_src_0_1(pc, &src0, &src1);
969
970 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
971 set_long(pc, e);
972 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
973 ((src1->mod & NV50_MOD_NEG) << 27);
974 }
975
976 set_dst(pc, dst, e);
977 set_src_0(pc, src0, e);
978 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
979 set_src_2(pc, src1, e);
980 else
981 if (src1->type == P_IMMD)
982 set_immd(pc, src1, e);
983 else
984 set_src_1(pc, src1, e);
985
986 emit(pc, e);
987 }
988
989 static void
990 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
991 uint8_t s)
992 {
993 struct nv50_program_exec *e = exec(pc);
994
995 set_long(pc, e);
996 e->inst[1] |= 0xc0000000;
997
998 e->inst[0] |= dst->hw << 2;
999 e->inst[0] |= s << 16; /* shift left */
1000 set_src_0_restricted(pc, src, e);
1001
1002 emit(pc, e);
1003 }
1004
1005 #define NV50_MAX_F32 0x880
1006 #define NV50_MAX_S32 0x08c
1007 #define NV50_MAX_U32 0x084
1008 #define NV50_MIN_F32 0x8a0
1009 #define NV50_MIN_S32 0x0ac
1010 #define NV50_MIN_U32 0x0a4
1011
1012 static void
1013 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
1014 struct nv50_reg *src0, struct nv50_reg *src1)
1015 {
1016 struct nv50_program_exec *e = exec(pc);
1017
1018 set_long(pc, e);
1019 e->inst[0] |= 0x30000000 | ((sub & 0x800) << 20);
1020 e->inst[1] |= (sub << 24);
1021
1022 check_swap_src_0_1(pc, &src0, &src1);
1023 set_dst(pc, dst, e);
1024 set_src_0(pc, src0, e);
1025 set_src_1(pc, src1, e);
1026
1027 if (src0->mod & NV50_MOD_ABS)
1028 e->inst[1] |= 0x00100000;
1029 if (src1->mod & NV50_MOD_ABS)
1030 e->inst[1] |= 0x00080000;
1031
1032 emit(pc, e);
1033 }
1034
1035 static INLINE void
1036 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1037 struct nv50_reg *src1)
1038 {
1039 src1->mod ^= NV50_MOD_NEG;
1040 emit_add(pc, dst, src0, src1);
1041 src1->mod ^= NV50_MOD_NEG;
1042 }
1043
1044 static void
1045 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1046 struct nv50_reg *src1, unsigned op)
1047 {
1048 struct nv50_program_exec *e = exec(pc);
1049
1050 e->inst[0] = 0xd0000000;
1051 set_long(pc, e);
1052
1053 check_swap_src_0_1(pc, &src0, &src1);
1054 set_dst(pc, dst, e);
1055 set_src_0(pc, src0, e);
1056
1057 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1058 op != TGSI_OPCODE_XOR)
1059 assert(!"invalid bit op");
1060
1061 assert(!(src0->mod | src1->mod));
1062
1063 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1064 set_immd(pc, src1, e);
1065 if (op == TGSI_OPCODE_OR)
1066 e->inst[0] |= 0x0100;
1067 else
1068 if (op == TGSI_OPCODE_XOR)
1069 e->inst[0] |= 0x8000;
1070 } else {
1071 set_src_1(pc, src1, e);
1072 e->inst[1] |= 0x04000000; /* 32 bit */
1073 if (op == TGSI_OPCODE_OR)
1074 e->inst[1] |= 0x4000;
1075 else
1076 if (op == TGSI_OPCODE_XOR)
1077 e->inst[1] |= 0x8000;
1078 }
1079
1080 emit(pc, e);
1081 }
1082
1083 static void
1084 emit_not(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1085 {
1086 struct nv50_program_exec *e = exec(pc);
1087
1088 e->inst[0] = 0xd0000000;
1089 e->inst[1] = 0x0402c000;
1090 set_long(pc, e);
1091 set_dst(pc, dst, e);
1092 set_src_1(pc, src, e);
1093
1094 emit(pc, e);
1095 }
1096
1097 static void
1098 emit_shift(struct nv50_pc *pc, struct nv50_reg *dst,
1099 struct nv50_reg *src0, struct nv50_reg *src1, unsigned dir)
1100 {
1101 struct nv50_program_exec *e = exec(pc);
1102
1103 e->inst[0] = 0x30000000;
1104 e->inst[1] = 0xc4000000;
1105
1106 set_long(pc, e);
1107 set_dst(pc, dst, e);
1108 set_src_0(pc, src0, e);
1109
1110 if (src1->type == P_IMMD) {
1111 e->inst[1] |= (1 << 20);
1112 e->inst[0] |= (pc->immd_buf[src1->hw] & 0x7f) << 16;
1113 } else
1114 set_src_1(pc, src1, e);
1115
1116 if (dir != TGSI_OPCODE_SHL)
1117 e->inst[1] |= (1 << 29);
1118
1119 if (dir == TGSI_OPCODE_ISHR)
1120 e->inst[1] |= (1 << 27);
1121
1122 emit(pc, e);
1123 }
1124
1125 static void
1126 emit_shl_imm(struct nv50_pc *pc, struct nv50_reg *dst,
1127 struct nv50_reg *src, int s)
1128 {
1129 struct nv50_program_exec *e = exec(pc);
1130
1131 e->inst[0] = 0x30000000;
1132 e->inst[1] = 0xc4100000;
1133 if (s < 0) {
1134 e->inst[1] |= 1 << 29;
1135 s = -s;
1136 }
1137 e->inst[1] |= ((s & 0x7f) << 16);
1138
1139 set_long(pc, e);
1140 set_dst(pc, dst, e);
1141 set_src_0(pc, src, e);
1142
1143 emit(pc, e);
1144 }
1145
1146 static void
1147 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1148 struct nv50_reg *src1, struct nv50_reg *src2)
1149 {
1150 struct nv50_program_exec *e = exec(pc);
1151
1152 e->inst[0] |= 0xe0000000;
1153
1154 check_swap_src_0_1(pc, &src0, &src1);
1155 set_dst(pc, dst, e);
1156 set_src_0(pc, src0, e);
1157 set_src_1(pc, src1, e);
1158 set_src_2(pc, src2, e);
1159
1160 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1161 e->inst[1] |= 0x04000000;
1162 if (src2->mod & NV50_MOD_NEG)
1163 e->inst[1] |= 0x08000000;
1164
1165 emit(pc, e);
1166 }
1167
1168 static INLINE void
1169 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1170 struct nv50_reg *src1, struct nv50_reg *src2)
1171 {
1172 src2->mod ^= NV50_MOD_NEG;
1173 emit_mad(pc, dst, src0, src1, src2);
1174 src2->mod ^= NV50_MOD_NEG;
1175 }
1176
1177 #define NV50_FLOP_RCP 0
1178 #define NV50_FLOP_RSQ 2
1179 #define NV50_FLOP_LG2 3
1180 #define NV50_FLOP_SIN 4
1181 #define NV50_FLOP_COS 5
1182 #define NV50_FLOP_EX2 6
1183
1184 /* rcp, rsqrt, lg2 support neg and abs */
1185 static void
1186 emit_flop(struct nv50_pc *pc, unsigned sub,
1187 struct nv50_reg *dst, struct nv50_reg *src)
1188 {
1189 struct nv50_program_exec *e = exec(pc);
1190
1191 e->inst[0] |= 0x90000000;
1192 if (sub || src->mod) {
1193 set_long(pc, e);
1194 e->inst[1] |= (sub << 29);
1195 }
1196
1197 set_dst(pc, dst, e);
1198 set_src_0_restricted(pc, src, e);
1199
1200 assert(!src->mod || sub < 4);
1201
1202 if (src->mod & NV50_MOD_NEG)
1203 e->inst[1] |= 0x04000000;
1204 if (src->mod & NV50_MOD_ABS)
1205 e->inst[1] |= 0x00100000;
1206
1207 emit(pc, e);
1208 }
1209
1210 static void
1211 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1212 {
1213 struct nv50_program_exec *e = exec(pc);
1214
1215 e->inst[0] |= 0xb0000000;
1216
1217 set_dst(pc, dst, e);
1218 set_src_0(pc, src, e);
1219 set_long(pc, e);
1220 e->inst[1] |= (6 << 29) | 0x00004000;
1221
1222 if (src->mod & NV50_MOD_NEG)
1223 e->inst[1] |= 0x04000000;
1224 if (src->mod & NV50_MOD_ABS)
1225 e->inst[1] |= 0x00100000;
1226
1227 emit(pc, e);
1228 }
1229
1230 static void
1231 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1232 {
1233 struct nv50_program_exec *e = exec(pc);
1234
1235 e->inst[0] |= 0xb0000000;
1236
1237 set_dst(pc, dst, e);
1238 set_src_0(pc, src, e);
1239 set_long(pc, e);
1240 e->inst[1] |= (6 << 29);
1241
1242 if (src->mod & NV50_MOD_NEG)
1243 e->inst[1] |= 0x04000000;
1244 if (src->mod & NV50_MOD_ABS)
1245 e->inst[1] |= 0x00100000;
1246
1247 emit(pc, e);
1248 }
1249
1250 #define CVT_RN (0x00 << 16)
1251 #define CVT_FLOOR (0x02 << 16)
1252 #define CVT_CEIL (0x04 << 16)
1253 #define CVT_TRUNC (0x06 << 16)
1254 #define CVT_SAT (0x08 << 16)
1255 #define CVT_ABS (0x10 << 16)
1256
1257 #define CVT_X32_X32 0x04004000
1258 #define CVT_X32_S32 0x04014000
1259 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1260 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1261 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1262 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1263 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1264 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1265 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1266 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1267
1268 #define CVT_NEG 0x20000000
1269 #define CVT_RI 0x08000000
1270
1271 static void
1272 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1273 int wp, uint32_t cvn)
1274 {
1275 struct nv50_program_exec *e;
1276
1277 e = exec(pc);
1278
1279 if (src->mod & NV50_MOD_NEG) cvn |= CVT_NEG;
1280 if (src->mod & NV50_MOD_ABS) cvn |= CVT_ABS;
1281
1282 e->inst[0] = 0xa0000000;
1283 e->inst[1] = cvn;
1284 set_long(pc, e);
1285 set_src_0(pc, src, e);
1286
1287 if (wp >= 0)
1288 set_pred_wr(pc, 1, wp, e);
1289
1290 if (dst)
1291 set_dst(pc, dst, e);
1292 else {
1293 e->inst[0] |= 0x000001fc;
1294 e->inst[1] |= 0x00000008;
1295 }
1296
1297 emit(pc, e);
1298 }
1299
1300 /* nv50 Condition codes:
1301 * 0x1 = LT
1302 * 0x2 = EQ
1303 * 0x3 = LE
1304 * 0x4 = GT
1305 * 0x5 = NE
1306 * 0x6 = GE
1307 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1308 * 0x8 = unordered bit (allows NaN)
1309 *
1310 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1311 */
1312 static void
1313 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1314 struct nv50_reg *src0, struct nv50_reg *src1, uint8_t mode)
1315 {
1316 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1317
1318 struct nv50_program_exec *e = exec(pc);
1319 struct nv50_reg *rdst;
1320
1321 assert(ccode < 16);
1322 if (check_swap_src_0_1(pc, &src0, &src1))
1323 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1324
1325 rdst = dst;
1326 if (dst && dst->type != P_TEMP)
1327 dst = alloc_temp(pc, NULL);
1328
1329 set_long(pc, e);
1330 e->inst[0] |= 0x30000000 | (mode << 24);
1331 e->inst[1] |= 0x60000000 | (ccode << 14);
1332
1333 if (wp >= 0)
1334 set_pred_wr(pc, 1, wp, e);
1335 if (dst)
1336 set_dst(pc, dst, e);
1337 else {
1338 e->inst[0] |= 0x000001fc;
1339 e->inst[1] |= 0x00000008;
1340 }
1341
1342 set_src_0(pc, src0, e);
1343 set_src_1(pc, src1, e);
1344
1345 emit(pc, e);
1346
1347 if (rdst && mode == 0x80) /* convert to float ? */
1348 emit_cvt(pc, rdst, dst, -1, CVT_ABS | CVT_F32_S32);
1349 if (rdst && rdst != dst)
1350 free_temp(pc, dst);
1351 }
1352
1353 static INLINE void
1354 map_tgsi_setop_hw(unsigned op, uint8_t *cc, uint8_t *ty)
1355 {
1356 switch (op) {
1357 case TGSI_OPCODE_SLT: *cc = 0x1; *ty = 0x80; break;
1358 case TGSI_OPCODE_SGE: *cc = 0x6; *ty = 0x80; break;
1359 case TGSI_OPCODE_SEQ: *cc = 0x2; *ty = 0x80; break;
1360 case TGSI_OPCODE_SGT: *cc = 0x4; *ty = 0x80; break;
1361 case TGSI_OPCODE_SLE: *cc = 0x3; *ty = 0x80; break;
1362 case TGSI_OPCODE_SNE: *cc = 0xd; *ty = 0x80; break;
1363
1364 case TGSI_OPCODE_ISLT: *cc = 0x1; *ty = 0x0c; break;
1365 case TGSI_OPCODE_ISGE: *cc = 0x6; *ty = 0x0c; break;
1366 case TGSI_OPCODE_USEQ: *cc = 0x2; *ty = 0x04; break;
1367 case TGSI_OPCODE_USGE: *cc = 0x6; *ty = 0x04; break;
1368 case TGSI_OPCODE_USLT: *cc = 0x1; *ty = 0x04; break;
1369 case TGSI_OPCODE_USNE: *cc = 0x5; *ty = 0x04; break;
1370 default:
1371 assert(0);
1372 return;
1373 }
1374 }
1375
1376 static void
1377 emit_add_b32(struct nv50_pc *pc, struct nv50_reg *dst,
1378 struct nv50_reg *src0, struct nv50_reg *rsrc1)
1379 {
1380 struct nv50_program_exec *e = exec(pc);
1381 struct nv50_reg *src1;
1382
1383 e->inst[0] = 0x20000000;
1384
1385 alloc_reg(pc, rsrc1);
1386 check_swap_src_0_1(pc, &src0, &rsrc1);
1387
1388 src1 = rsrc1;
1389 if (src0->mod & rsrc1->mod & NV50_MOD_NEG) {
1390 src1 = temp_temp(pc, e);
1391 emit_cvt(pc, src1, rsrc1, -1, CVT_S32_S32);
1392 }
1393
1394 if (!pc->allow32 || src1->hw > 63 ||
1395 (src1->type != P_TEMP && src1->type != P_IMMD))
1396 set_long(pc, e);
1397
1398 set_dst(pc, dst, e);
1399 set_src_0(pc, src0, e);
1400
1401 if (is_long(e)) {
1402 e->inst[1] |= 1 << 26;
1403 set_src_2(pc, src1, e);
1404 } else {
1405 e->inst[0] |= 0x8000;
1406 if (src1->type == P_IMMD)
1407 set_immd(pc, src1, e);
1408 else
1409 set_src_1(pc, src1, e);
1410 }
1411
1412 if (src0->mod & NV50_MOD_NEG)
1413 e->inst[0] |= 1 << 28;
1414 else
1415 if (src1->mod & NV50_MOD_NEG)
1416 e->inst[0] |= 1 << 22;
1417
1418 emit(pc, e);
1419 }
1420
1421 static void
1422 emit_mad_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1423 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1,
1424 struct nv50_reg *src2)
1425 {
1426 struct nv50_program_exec *e = exec(pc);
1427
1428 e->inst[0] = 0x60000000;
1429 if (!pc->allow32)
1430 set_long(pc, e);
1431 set_dst(pc, dst, e);
1432
1433 set_half_src(pc, src0, lh_0, e, 9);
1434 set_half_src(pc, src1, lh_1, e, 16);
1435 alloc_reg(pc, src2);
1436 if (is_long(e) || (src2->type != P_TEMP) || (src2->hw != dst->hw))
1437 set_src_2(pc, src2, e);
1438
1439 emit(pc, e);
1440 }
1441
1442 static void
1443 emit_mul_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1444 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1)
1445 {
1446 struct nv50_program_exec *e = exec(pc);
1447
1448 e->inst[0] = 0x40000000;
1449 set_long(pc, e);
1450 set_dst(pc, dst, e);
1451
1452 set_half_src(pc, src0, lh_0, e, 9);
1453 set_half_src(pc, src1, lh_1, e, 16);
1454
1455 emit(pc, e);
1456 }
1457
1458 static void
1459 emit_sad(struct nv50_pc *pc, struct nv50_reg *dst,
1460 struct nv50_reg *src0, struct nv50_reg *src1, struct nv50_reg *src2)
1461 {
1462 struct nv50_program_exec *e = exec(pc);
1463
1464 e->inst[0] = 0x50000000;
1465 if (!pc->allow32)
1466 set_long(pc, e);
1467 check_swap_src_0_1(pc, &src0, &src1);
1468 set_dst(pc, dst, e);
1469 set_src_0(pc, src0, e);
1470 set_src_1(pc, src1, e);
1471 alloc_reg(pc, src2);
1472 if (is_long(e) || (src2->type != dst->type) || (src2->hw != dst->hw))
1473 set_src_2(pc, src2, e);
1474
1475 if (is_long(e))
1476 e->inst[1] |= 0x0c << 24;
1477 else
1478 e->inst[0] |= 0x81 << 8;
1479
1480 emit(pc, e);
1481 }
1482
1483 static INLINE void
1484 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1485 {
1486 emit_cvt(pc, dst, src, -1, CVT_FLOOR | CVT_F32_F32 | CVT_RI);
1487 }
1488
1489 static void
1490 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1491 struct nv50_reg *v, struct nv50_reg *e)
1492 {
1493 struct nv50_reg *temp = alloc_temp(pc, NULL);
1494
1495 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1496 emit_mul(pc, temp, temp, e);
1497 emit_preex2(pc, temp, temp);
1498 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1499
1500 free_temp(pc, temp);
1501 }
1502
1503 static INLINE void
1504 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1505 {
1506 emit_cvt(pc, dst, src, -1, CVT_SAT | CVT_F32_F32);
1507 }
1508
1509 static void
1510 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1511 struct nv50_reg **src)
1512 {
1513 struct nv50_reg *one = alloc_immd(pc, 1.0);
1514 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1515 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1516 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1517 struct nv50_reg *tmp[4];
1518 boolean allow32 = pc->allow32;
1519
1520 pc->allow32 = FALSE;
1521
1522 if (mask & (3 << 1)) {
1523 tmp[0] = alloc_temp(pc, NULL);
1524 emit_minmax(pc, NV50_MAX_F32, tmp[0], src[0], zero);
1525 }
1526
1527 if (mask & (1 << 2)) {
1528 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1529
1530 tmp[1] = temp_temp(pc, NULL);
1531 emit_minmax(pc, NV50_MAX_F32, tmp[1], src[1], zero);
1532
1533 tmp[3] = temp_temp(pc, NULL);
1534 emit_minmax(pc, NV50_MAX_F32, tmp[3], src[3], neg128);
1535 emit_minmax(pc, NV50_MIN_F32, tmp[3], tmp[3], pos128);
1536
1537 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1538 emit_mov(pc, dst[2], zero);
1539 set_pred(pc, 3, 0, pc->p->exec_tail);
1540 }
1541
1542 if (mask & (1 << 1))
1543 assimilate_temp(pc, dst[1], tmp[0]);
1544 else
1545 if (mask & (1 << 2))
1546 free_temp(pc, tmp[0]);
1547
1548 pc->allow32 = allow32;
1549
1550 /* do this last, in case src[i,j] == dst[0,3] */
1551 if (mask & (1 << 0))
1552 emit_mov(pc, dst[0], one);
1553
1554 if (mask & (1 << 3))
1555 emit_mov(pc, dst[3], one);
1556
1557 FREE(pos128);
1558 FREE(neg128);
1559 FREE(zero);
1560 FREE(one);
1561 }
1562
1563 static void
1564 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1565 {
1566 struct nv50_program_exec *e;
1567 const int r_pred = 1;
1568
1569 e = exec(pc);
1570 e->inst[0] = 0x00000002; /* discard */
1571 set_long(pc, e); /* sets cond code to ALWAYS */
1572
1573 if (src) {
1574 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1575 /* write to predicate reg */
1576 emit_cvt(pc, NULL, src, r_pred, CVT_F32_F32);
1577 }
1578
1579 emit(pc, e);
1580 }
1581
1582 static struct nv50_program_exec *
1583 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1584 {
1585 struct nv50_program_exec *e = exec(pc);
1586
1587 e->inst[0] = (op << 28) | 2;
1588 set_long(pc, e);
1589 if (pred >= 0)
1590 set_pred(pc, cc, pred, e);
1591
1592 emit(pc, e);
1593 return e;
1594 }
1595
1596 static INLINE struct nv50_program_exec *
1597 emit_breakaddr(struct nv50_pc *pc)
1598 {
1599 return emit_control_flow(pc, 0x4, -1, 0);
1600 }
1601
1602 static INLINE void
1603 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1604 {
1605 emit_control_flow(pc, 0x5, pred, cc);
1606 }
1607
1608 static INLINE struct nv50_program_exec *
1609 emit_joinat(struct nv50_pc *pc)
1610 {
1611 return emit_control_flow(pc, 0xa, -1, 0);
1612 }
1613
1614 static INLINE struct nv50_program_exec *
1615 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1616 {
1617 return emit_control_flow(pc, 0x1, pred, cc);
1618 }
1619
1620 static INLINE struct nv50_program_exec *
1621 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1622 {
1623 return emit_control_flow(pc, 0x2, pred, cc);
1624 }
1625
1626 static INLINE void
1627 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1628 {
1629 emit_control_flow(pc, 0x3, pred, cc);
1630 }
1631
1632 #define QOP_ADD 0
1633 #define QOP_SUBR 1
1634 #define QOP_SUB 2
1635 #define QOP_MOV_SRC1 3
1636
1637 /* For a quad of threads / top left, top right, bottom left, bottom right
1638 * pixels, do a different operation, and take src0 from a specific thread.
1639 */
1640 static void
1641 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1642 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1643 {
1644 struct nv50_program_exec *e = exec(pc);
1645
1646 e->inst[0] = 0xc0000000;
1647 e->inst[1] = 0x80000000;
1648 set_long(pc, e);
1649 e->inst[0] |= lane_src0 << 16;
1650 set_src_0(pc, src0, e);
1651 set_src_2(pc, src1, e);
1652
1653 if (wp >= 0)
1654 set_pred_wr(pc, 1, wp, e);
1655
1656 if (dst)
1657 set_dst(pc, dst, e);
1658 else {
1659 e->inst[0] |= 0x000001fc;
1660 e->inst[1] |= 0x00000008;
1661 }
1662
1663 e->inst[0] |= (qop & 3) << 20;
1664 e->inst[1] |= (qop >> 2) << 22;
1665
1666 emit(pc, e);
1667 }
1668
1669 static void
1670 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1671 struct nv50_reg **src, unsigned arg, boolean proj)
1672 {
1673 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1674
1675 src[0]->mod |= NV50_MOD_ABS;
1676 src[1]->mod |= NV50_MOD_ABS;
1677 src[2]->mod |= NV50_MOD_ABS;
1678
1679 emit_minmax(pc, NV50_MAX_F32, t[2], src[0], src[1]);
1680 emit_minmax(pc, NV50_MAX_F32, t[2], src[2], t[2]);
1681
1682 src[0]->mod = mod[0];
1683 src[1]->mod = mod[1];
1684 src[2]->mod = mod[2];
1685
1686 if (proj && 0 /* looks more correct without this */)
1687 emit_mul(pc, t[2], t[2], src[3]);
1688 else
1689 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1690 emit_mov(pc, t[3], src[3]);
1691
1692 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1693
1694 emit_mul(pc, t[0], src[0], t[2]);
1695 emit_mul(pc, t[1], src[1], t[2]);
1696 emit_mul(pc, t[2], src[2], t[2]);
1697 }
1698
1699 static void
1700 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1701 struct nv50_reg **src, unsigned dim, unsigned arg)
1702 {
1703 unsigned c, mode;
1704
1705 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1706 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1707
1708 t[3]->rhw = src[3]->rhw;
1709 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1710 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1711
1712 for (c = 0; c < dim; ++c) {
1713 t[c]->rhw = src[c]->rhw;
1714 emit_interp(pc, t[c], t[3], mode);
1715 }
1716 if (arg != dim) { /* depth reference value */
1717 t[dim]->rhw = src[2]->rhw;
1718 emit_interp(pc, t[dim], t[3], mode);
1719 }
1720 } else {
1721 /* XXX: for some reason the blob sometimes uses MAD
1722 * (mad f32 $rX $rY $rZ neg $r63)
1723 */
1724 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1725 for (c = 0; c < dim; ++c)
1726 emit_mul(pc, t[c], src[c], t[3]);
1727 if (arg != dim) /* depth reference value */
1728 emit_mul(pc, t[dim], src[2], t[3]);
1729 }
1730 }
1731
1732 static INLINE void
1733 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1734 {
1735 switch (type) {
1736 case TGSI_TEXTURE_1D:
1737 *arg = *dim = 1;
1738 break;
1739 case TGSI_TEXTURE_SHADOW1D:
1740 *dim = 1;
1741 *arg = 2;
1742 break;
1743 case TGSI_TEXTURE_UNKNOWN:
1744 case TGSI_TEXTURE_2D:
1745 case TGSI_TEXTURE_RECT:
1746 *arg = *dim = 2;
1747 break;
1748 case TGSI_TEXTURE_SHADOW2D:
1749 case TGSI_TEXTURE_SHADOWRECT:
1750 *dim = 2;
1751 *arg = 3;
1752 break;
1753 case TGSI_TEXTURE_3D:
1754 case TGSI_TEXTURE_CUBE:
1755 *dim = *arg = 3;
1756 break;
1757 default:
1758 assert(0);
1759 break;
1760 }
1761 }
1762
1763 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1764 * different LOD values, so branch off groups of equal LOD.
1765 */
1766 static void
1767 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1768 struct nv50_reg *src, struct nv50_program_exec *tex)
1769 {
1770 struct nv50_program_exec *join_at;
1771 unsigned i, target = pc->p->exec_size + 9 * 2;
1772
1773 if (pc->p->type != PIPE_SHADER_FRAGMENT) {
1774 emit(pc, tex);
1775 return;
1776 }
1777 pc->allow32 = FALSE;
1778
1779 /* Subtract lod of each pixel from lod of top left pixel, jump
1780 * texlod insn if result is 0, then repeat for 2 other pixels.
1781 */
1782 join_at = emit_joinat(pc);
1783 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1784 emit_branch(pc, 0, 2)->param.index = target;
1785
1786 for (i = 1; i < 4; ++i) {
1787 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1788 emit_branch(pc, 0, 2)->param.index = target;
1789 }
1790
1791 emit_mov(pc, tlod, src); /* target */
1792 emit(pc, tex); /* texlod */
1793
1794 join_at->param.index = target + 2 * 2;
1795 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1796 }
1797
1798 static void
1799 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1800 struct nv50_program_exec *tex)
1801 {
1802 struct nv50_program_exec *e;
1803 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1804 int r_pred = 0;
1805 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1806
1807 pc->allow32 = FALSE;
1808 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1809
1810 /* Subtract bias value of thread i from bias values of each thread,
1811 * store result in r_pred, and set bit i in r_bits if result was 0.
1812 */
1813 assert(arg < 4);
1814 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1815 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1816 emit_mov(pc, r_bits, &imm_1248);
1817 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1818 }
1819 emit_mov_to_pred(pc, r_pred, r_bits);
1820
1821 /* The lanes of a quad are now grouped by the bit in r_pred they have
1822 * set. Put the input values for TEX into a new register set for each
1823 * group and execute TEX only for a specific group.
1824 * We cannot use the same register set for each group because we need
1825 * the derivatives, which are implicitly calculated, to be correct.
1826 */
1827 for (i = 1; i < 4; ++i) {
1828 alloc_temp4(pc, t123[i], 0);
1829
1830 for (c = 0; c <= arg; ++c)
1831 emit_mov(pc, t123[i][c], t[c]);
1832
1833 *(e = exec(pc)) = *(tex);
1834 e->inst[0] &= ~0x01fc;
1835 set_dst(pc, t123[i][0], e);
1836 set_pred(pc, cc[i], r_pred, e);
1837 emit(pc, e);
1838 }
1839 /* finally TEX on the original regs (where we kept the input) */
1840 set_pred(pc, cc[0], r_pred, tex);
1841 emit(pc, tex);
1842
1843 /* put the 3 * n other results into regs for lane 0 */
1844 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1845 for (i = 1; i < 4; ++i) {
1846 for (c = 0; c < n; ++c) {
1847 emit_mov(pc, t[c], t123[i][c]);
1848 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1849 }
1850 free_temp4(pc, t123[i]);
1851 }
1852
1853 emit_nop(pc);
1854 free_temp(pc, r_bits);
1855 }
1856
1857 static void
1858 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1859 struct nv50_reg **src, unsigned unit, unsigned type,
1860 boolean proj, int bias_lod)
1861 {
1862 struct nv50_reg *t[4];
1863 struct nv50_program_exec *e;
1864 unsigned c, dim, arg;
1865
1866 /* t[i] must be within a single 128 bit super-reg */
1867 alloc_temp4(pc, t, 0);
1868
1869 e = exec(pc);
1870 e->inst[0] = 0xf0000000;
1871 set_long(pc, e);
1872 set_dst(pc, t[0], e);
1873
1874 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1875 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1876
1877 /* live flag (don't set if TEX results affect input to another TEX): */
1878 /* e->inst[0] |= 0x00000004; */
1879
1880 get_tex_dim(type, &dim, &arg);
1881
1882 if (type == TGSI_TEXTURE_CUBE) {
1883 e->inst[0] |= 0x08000000;
1884 load_cube_tex_coords(pc, t, src, arg, proj);
1885 } else
1886 if (proj)
1887 load_proj_tex_coords(pc, t, src, dim, arg);
1888 else {
1889 for (c = 0; c < dim; c++)
1890 emit_mov(pc, t[c], src[c]);
1891 if (arg != dim) /* depth reference value (always src.z here) */
1892 emit_mov(pc, t[dim], src[2]);
1893 }
1894
1895 e->inst[0] |= (mask & 0x3) << 25;
1896 e->inst[1] |= (mask & 0xc) << 12;
1897
1898 if (!bias_lod) {
1899 e->inst[0] |= (arg - 1) << 22;
1900 emit(pc, e);
1901 } else
1902 if (bias_lod < 0) {
1903 assert(pc->p->type == PIPE_SHADER_FRAGMENT);
1904 e->inst[0] |= arg << 22;
1905 e->inst[1] |= 0x20000000; /* texbias */
1906 emit_mov(pc, t[arg], src[3]);
1907 emit_texbias_sequence(pc, t, arg, e);
1908 } else {
1909 e->inst[0] |= arg << 22;
1910 e->inst[1] |= 0x40000000; /* texlod */
1911 emit_mov(pc, t[arg], src[3]);
1912 emit_texlod_sequence(pc, t[arg], src[3], e);
1913 }
1914
1915 #if 1
1916 c = 0;
1917 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1918 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1919 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1920 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1921
1922 free_temp4(pc, t);
1923 #else
1924 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1925 * the texture coordinates, not the fetched values: latency ? */
1926
1927 for (c = 0; c < 4; c++) {
1928 if (mask & (1 << c))
1929 assimilate_temp(pc, dst[c], t[c]);
1930 else
1931 free_temp(pc, t[c]);
1932 }
1933 #endif
1934 }
1935
1936 static void
1937 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1938 {
1939 struct nv50_program_exec *e = exec(pc);
1940
1941 assert(src->type == P_TEMP);
1942
1943 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
1944 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
1945 set_long(pc, e);
1946 set_dst(pc, dst, e);
1947 set_src_0(pc, src, e);
1948 set_src_2(pc, src, e);
1949
1950 emit(pc, e);
1951 }
1952
1953 static void
1954 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1955 {
1956 struct nv50_program_exec *e = exec(pc);
1957
1958 assert(src->type == P_TEMP);
1959
1960 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
1961 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
1962 set_long(pc, e);
1963 set_dst(pc, dst, e);
1964 set_src_0(pc, src, e);
1965 set_src_2(pc, src, e);
1966
1967 emit(pc, e);
1968 }
1969
1970 static void
1971 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1972 {
1973 unsigned q = 0, m = ~0;
1974
1975 assert(!is_long(e));
1976
1977 switch (e->inst[0] >> 28) {
1978 case 0x1:
1979 /* MOV */
1980 q = 0x0403c000;
1981 m = 0xffff7fff;
1982 break;
1983 case 0x2:
1984 case 0x3:
1985 /* ADD, SUB, SUBR b32 */
1986 m = ~(0x8000 | (127 << 16));
1987 q = ((e->inst[0] & (~m)) >> 2) | (1 << 26);
1988 break;
1989 case 0x5:
1990 /* SAD */
1991 m = ~(0x81 << 8);
1992 q = (0x0c << 24) | ((e->inst[0] & (0x7f << 2)) << 12);
1993 break;
1994 case 0x6:
1995 /* MAD u16 */
1996 q = (e->inst[0] & (0x7f << 2)) << 12;
1997 break;
1998 case 0x8:
1999 /* INTERP (move centroid, perspective and flat bits) */
2000 m = ~0x03000100;
2001 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
2002 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
2003 break;
2004 case 0x9:
2005 /* RCP */
2006 break;
2007 case 0xB:
2008 /* ADD */
2009 m = ~(127 << 16);
2010 q = ((e->inst[0] & (~m)) >> 2);
2011 break;
2012 case 0xC:
2013 /* MUL */
2014 m = ~0x00008000;
2015 q = ((e->inst[0] & (~m)) << 12);
2016 break;
2017 case 0xE:
2018 /* MAD (if src2 == dst) */
2019 q = ((e->inst[0] & 0x1fc) << 12);
2020 break;
2021 default:
2022 assert(0);
2023 break;
2024 }
2025
2026 set_long(pc, e);
2027 pc->p->exec_size++;
2028
2029 e->inst[0] &= m;
2030 e->inst[1] |= q;
2031 }
2032
2033 /* Some operations support an optional negation flag. */
2034 static int
2035 get_supported_mods(const struct tgsi_full_instruction *insn, int i)
2036 {
2037 switch (insn->Instruction.Opcode) {
2038 case TGSI_OPCODE_ADD:
2039 case TGSI_OPCODE_COS:
2040 case TGSI_OPCODE_DDX:
2041 case TGSI_OPCODE_DDY:
2042 case TGSI_OPCODE_DP3:
2043 case TGSI_OPCODE_DP4:
2044 case TGSI_OPCODE_EX2:
2045 case TGSI_OPCODE_KIL:
2046 case TGSI_OPCODE_LG2:
2047 case TGSI_OPCODE_MAD:
2048 case TGSI_OPCODE_MUL:
2049 case TGSI_OPCODE_POW:
2050 case TGSI_OPCODE_RCP:
2051 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
2052 case TGSI_OPCODE_SCS:
2053 case TGSI_OPCODE_SIN:
2054 case TGSI_OPCODE_SUB:
2055 return NV50_MOD_NEG;
2056 case TGSI_OPCODE_MAX:
2057 case TGSI_OPCODE_MIN:
2058 case TGSI_OPCODE_INEG: /* tgsi src sign toggle/set would be stupid */
2059 return NV50_MOD_ABS;
2060 case TGSI_OPCODE_CEIL:
2061 case TGSI_OPCODE_FLR:
2062 case TGSI_OPCODE_TRUNC:
2063 return NV50_MOD_NEG | NV50_MOD_ABS;
2064 case TGSI_OPCODE_F2I:
2065 case TGSI_OPCODE_F2U:
2066 case TGSI_OPCODE_I2F:
2067 case TGSI_OPCODE_U2F:
2068 return NV50_MOD_NEG | NV50_MOD_ABS | NV50_MOD_I32;
2069 case TGSI_OPCODE_UADD:
2070 return NV50_MOD_NEG | NV50_MOD_I32;
2071 case TGSI_OPCODE_SAD:
2072 case TGSI_OPCODE_SHL:
2073 case TGSI_OPCODE_IMAX:
2074 case TGSI_OPCODE_IMIN:
2075 case TGSI_OPCODE_ISHR:
2076 case TGSI_OPCODE_NOT:
2077 case TGSI_OPCODE_UMAD:
2078 case TGSI_OPCODE_UMAX:
2079 case TGSI_OPCODE_UMIN:
2080 case TGSI_OPCODE_UMUL:
2081 case TGSI_OPCODE_USHR:
2082 return NV50_MOD_I32;
2083 default:
2084 return 0;
2085 }
2086 }
2087
2088 /* Return a read mask for source registers deduced from opcode & write mask. */
2089 static unsigned
2090 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
2091 {
2092 unsigned x, mask = insn->Dst[0].Register.WriteMask;
2093
2094 switch (insn->Instruction.Opcode) {
2095 case TGSI_OPCODE_COS:
2096 case TGSI_OPCODE_SIN:
2097 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
2098 case TGSI_OPCODE_DP3:
2099 return 0x7;
2100 case TGSI_OPCODE_DP4:
2101 case TGSI_OPCODE_DPH:
2102 case TGSI_OPCODE_KIL: /* WriteMask ignored */
2103 return 0xf;
2104 case TGSI_OPCODE_DST:
2105 return mask & (c ? 0xa : 0x6);
2106 case TGSI_OPCODE_EX2:
2107 case TGSI_OPCODE_EXP:
2108 case TGSI_OPCODE_LG2:
2109 case TGSI_OPCODE_LOG:
2110 case TGSI_OPCODE_POW:
2111 case TGSI_OPCODE_RCP:
2112 case TGSI_OPCODE_RSQ:
2113 case TGSI_OPCODE_SCS:
2114 return 0x1;
2115 case TGSI_OPCODE_IF:
2116 return 0x1;
2117 case TGSI_OPCODE_LIT:
2118 return 0xb;
2119 case TGSI_OPCODE_TEX:
2120 case TGSI_OPCODE_TXB:
2121 case TGSI_OPCODE_TXL:
2122 case TGSI_OPCODE_TXP:
2123 {
2124 const struct tgsi_instruction_texture *tex;
2125
2126 assert(insn->Instruction.Texture);
2127 tex = &insn->Texture;
2128
2129 mask = 0x7;
2130 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
2131 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
2132 mask |= 0x8; /* bias, lod or proj */
2133
2134 switch (tex->Texture) {
2135 case TGSI_TEXTURE_1D:
2136 mask &= 0x9;
2137 break;
2138 case TGSI_TEXTURE_SHADOW1D:
2139 mask &= 0x5;
2140 break;
2141 case TGSI_TEXTURE_2D:
2142 mask &= 0xb;
2143 break;
2144 default:
2145 break;
2146 }
2147 }
2148 return mask;
2149 case TGSI_OPCODE_XPD:
2150 x = 0;
2151 if (mask & 1) x |= 0x6;
2152 if (mask & 2) x |= 0x5;
2153 if (mask & 4) x |= 0x3;
2154 return x;
2155 default:
2156 break;
2157 }
2158
2159 return mask;
2160 }
2161
2162 static struct nv50_reg *
2163 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
2164 {
2165 switch (dst->Register.File) {
2166 case TGSI_FILE_TEMPORARY:
2167 return &pc->temp[dst->Register.Index * 4 + c];
2168 case TGSI_FILE_OUTPUT:
2169 return &pc->result[dst->Register.Index * 4 + c];
2170 case TGSI_FILE_ADDRESS:
2171 {
2172 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
2173 if (!r) {
2174 r = alloc_addr(pc, NULL);
2175 pc->addr[dst->Register.Index * 4 + c] = r;
2176 }
2177 assert(r);
2178 return r;
2179 }
2180 case TGSI_FILE_NULL:
2181 return NULL;
2182 default:
2183 break;
2184 }
2185
2186 return NULL;
2187 }
2188
2189 static struct nv50_reg *
2190 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
2191 int mod)
2192 {
2193 struct nv50_reg *r = NULL;
2194 struct nv50_reg *temp = NULL;
2195 unsigned sgn, c, swz, cvn;
2196
2197 if (src->Register.File != TGSI_FILE_CONSTANT)
2198 assert(!src->Register.Indirect);
2199
2200 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
2201
2202 c = tgsi_util_get_full_src_register_swizzle(src, chan);
2203 switch (c) {
2204 case TGSI_SWIZZLE_X:
2205 case TGSI_SWIZZLE_Y:
2206 case TGSI_SWIZZLE_Z:
2207 case TGSI_SWIZZLE_W:
2208 switch (src->Register.File) {
2209 case TGSI_FILE_INPUT:
2210 r = &pc->attr[src->Register.Index * 4 + c];
2211 break;
2212 case TGSI_FILE_TEMPORARY:
2213 r = &pc->temp[src->Register.Index * 4 + c];
2214 break;
2215 case TGSI_FILE_CONSTANT:
2216 if (!src->Register.Indirect) {
2217 r = &pc->param[src->Register.Index * 4 + c];
2218 break;
2219 }
2220 /* Indicate indirection by setting r->acc < 0 and
2221 * use the index field to select the address reg.
2222 */
2223 r = reg_instance(pc, NULL);
2224 swz = tgsi_util_get_src_register_swizzle(
2225 &src->Indirect, 0);
2226 ctor_reg(r, P_CONST,
2227 src->Indirect.Index * 4 + swz,
2228 src->Register.Index * 4 + c);
2229 r->acc = -1;
2230 break;
2231 case TGSI_FILE_IMMEDIATE:
2232 r = &pc->immd[src->Register.Index * 4 + c];
2233 break;
2234 case TGSI_FILE_SAMPLER:
2235 return NULL;
2236 case TGSI_FILE_ADDRESS:
2237 r = pc->addr[src->Register.Index * 4 + c];
2238 assert(r);
2239 break;
2240 default:
2241 assert(0);
2242 break;
2243 }
2244 break;
2245 default:
2246 assert(0);
2247 break;
2248 }
2249
2250 cvn = (mod & NV50_MOD_I32) ? CVT_S32_S32 : CVT_F32_F32;
2251
2252 switch (sgn) {
2253 case TGSI_UTIL_SIGN_CLEAR:
2254 r->mod = NV50_MOD_ABS;
2255 break;
2256 case TGSI_UTIL_SIGN_SET:
2257 r->mod = NV50_MOD_NEG_ABS;
2258 break;
2259 case TGSI_UTIL_SIGN_TOGGLE:
2260 r->mod = NV50_MOD_NEG;
2261 break;
2262 default:
2263 assert(!r->mod && sgn == TGSI_UTIL_SIGN_KEEP);
2264 break;
2265 }
2266
2267 if ((r->mod & mod) != r->mod) {
2268 temp = temp_temp(pc, NULL);
2269 emit_cvt(pc, temp, r, -1, cvn);
2270 r->mod = 0;
2271 r = temp;
2272 } else
2273 r->mod |= mod & NV50_MOD_I32;
2274
2275 assert(r);
2276 if (r->acc >= 0 && r != temp)
2277 return reg_instance(pc, r); /* will clear r->mod */
2278 return r;
2279 }
2280
2281 /* return TRUE for ops that produce only a single result */
2282 static boolean
2283 is_scalar_op(unsigned op)
2284 {
2285 switch (op) {
2286 case TGSI_OPCODE_COS:
2287 case TGSI_OPCODE_DP2:
2288 case TGSI_OPCODE_DP3:
2289 case TGSI_OPCODE_DP4:
2290 case TGSI_OPCODE_DPH:
2291 case TGSI_OPCODE_EX2:
2292 case TGSI_OPCODE_LG2:
2293 case TGSI_OPCODE_POW:
2294 case TGSI_OPCODE_RCP:
2295 case TGSI_OPCODE_RSQ:
2296 case TGSI_OPCODE_SIN:
2297 /*
2298 case TGSI_OPCODE_KIL:
2299 case TGSI_OPCODE_LIT:
2300 case TGSI_OPCODE_SCS:
2301 */
2302 return TRUE;
2303 default:
2304 return FALSE;
2305 }
2306 }
2307
2308 /* Returns a bitmask indicating which dst components depend
2309 * on source s, component c (reverse of nv50_tgsi_src_mask).
2310 */
2311 static unsigned
2312 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2313 {
2314 if (is_scalar_op(op))
2315 return 0x1;
2316
2317 switch (op) {
2318 case TGSI_OPCODE_DST:
2319 return (1 << c) & (s ? 0xa : 0x6);
2320 case TGSI_OPCODE_XPD:
2321 switch (c) {
2322 case 0: return 0x6;
2323 case 1: return 0x5;
2324 case 2: return 0x3;
2325 case 3: return 0x0;
2326 default:
2327 assert(0);
2328 return 0x0;
2329 }
2330 case TGSI_OPCODE_EXP:
2331 case TGSI_OPCODE_LOG:
2332 case TGSI_OPCODE_LIT:
2333 case TGSI_OPCODE_SCS:
2334 case TGSI_OPCODE_TEX:
2335 case TGSI_OPCODE_TXB:
2336 case TGSI_OPCODE_TXL:
2337 case TGSI_OPCODE_TXP:
2338 /* these take care of dangerous swizzles themselves */
2339 return 0x0;
2340 case TGSI_OPCODE_IF:
2341 case TGSI_OPCODE_KIL:
2342 /* don't call this function for these ops */
2343 assert(0);
2344 return 0;
2345 default:
2346 /* linear vector instruction */
2347 return (1 << c);
2348 }
2349 }
2350
2351 static INLINE boolean
2352 has_pred(struct nv50_program_exec *e, unsigned cc)
2353 {
2354 if (!is_long(e) || is_immd(e))
2355 return FALSE;
2356 return ((e->inst[1] & 0x780) == (cc << 7));
2357 }
2358
2359 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2360 * join_at ENDIF
2361 * @p0.eq bra ENDIF
2362 * single_op
2363 * ENDIF: nop.join
2364 */
2365 static boolean
2366 nv50_kill_branch(struct nv50_pc *pc)
2367 {
2368 int lvl = pc->if_lvl;
2369
2370 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2371 return FALSE;
2372 if (is_immd(pc->p->exec_tail))
2373 return FALSE;
2374
2375 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2376 * reg may no longer be valid, since we currently always use $p0
2377 */
2378 if (has_pred(pc->if_insn[lvl], 0xf))
2379 return FALSE;
2380 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2381
2382 /* We'll use the exec allocated for JOIN_AT (we can't easily
2383 * access nv50_program_exec's prev).
2384 */
2385 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2386
2387 *pc->if_join[lvl] = *pc->p->exec_tail;
2388
2389 FREE(pc->if_insn[lvl]);
2390 FREE(pc->p->exec_tail);
2391
2392 pc->p->exec_tail = pc->if_join[lvl];
2393 pc->p->exec_tail->next = NULL;
2394 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2395
2396 return TRUE;
2397 }
2398
2399 static void
2400 nv50_fp_move_results(struct nv50_pc *pc)
2401 {
2402 struct nv50_reg reg;
2403 unsigned i;
2404
2405 ctor_reg(&reg, P_TEMP, -1, -1);
2406
2407 for (i = 0; i < pc->result_nr * 4; ++i) {
2408 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2409 continue;
2410 if (pc->result[i].rhw != pc->result[i].hw) {
2411 reg.hw = pc->result[i].rhw;
2412 emit_mov(pc, &reg, &pc->result[i]);
2413 }
2414 }
2415 }
2416
2417 static boolean
2418 nv50_program_tx_insn(struct nv50_pc *pc,
2419 const struct tgsi_full_instruction *inst)
2420 {
2421 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2422 unsigned mask, sat, unit;
2423 int i, c;
2424
2425 mask = inst->Dst[0].Register.WriteMask;
2426 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2427
2428 memset(src, 0, sizeof(src));
2429
2430 for (c = 0; c < 4; c++) {
2431 if ((mask & (1 << c)) && !pc->r_dst[c])
2432 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2433 else
2434 dst[c] = pc->r_dst[c];
2435 rdst[c] = dst[c];
2436 }
2437
2438 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2439 const struct tgsi_full_src_register *fs = &inst->Src[i];
2440 unsigned src_mask;
2441 int mod_supp;
2442
2443 src_mask = nv50_tgsi_src_mask(inst, i);
2444 mod_supp = get_supported_mods(inst, i);
2445
2446 if (fs->Register.File == TGSI_FILE_SAMPLER)
2447 unit = fs->Register.Index;
2448
2449 for (c = 0; c < 4; c++)
2450 if (src_mask & (1 << c))
2451 src[i][c] = tgsi_src(pc, c, fs, mod_supp);
2452 }
2453
2454 brdc = temp = pc->r_brdc;
2455 if (brdc && brdc->type != P_TEMP) {
2456 temp = temp_temp(pc, NULL);
2457 if (sat)
2458 brdc = temp;
2459 } else
2460 if (sat) {
2461 for (c = 0; c < 4; c++) {
2462 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2463 continue;
2464 /* rdst[c] = dst[c]; */ /* done above */
2465 dst[c] = temp_temp(pc, NULL);
2466 }
2467 }
2468
2469 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2470
2471 switch (inst->Instruction.Opcode) {
2472 case TGSI_OPCODE_ABS:
2473 for (c = 0; c < 4; c++) {
2474 if (!(mask & (1 << c)))
2475 continue;
2476 emit_cvt(pc, dst[c], src[0][c], -1,
2477 CVT_ABS | CVT_F32_F32);
2478 }
2479 break;
2480 case TGSI_OPCODE_ADD:
2481 for (c = 0; c < 4; c++) {
2482 if (!(mask & (1 << c)))
2483 continue;
2484 emit_add(pc, dst[c], src[0][c], src[1][c]);
2485 }
2486 break;
2487 case TGSI_OPCODE_AND:
2488 case TGSI_OPCODE_XOR:
2489 case TGSI_OPCODE_OR:
2490 for (c = 0; c < 4; c++) {
2491 if (!(mask & (1 << c)))
2492 continue;
2493 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2494 inst->Instruction.Opcode);
2495 }
2496 break;
2497 case TGSI_OPCODE_ARL:
2498 assert(src[0][0]);
2499 temp = temp_temp(pc, NULL);
2500 emit_cvt(pc, temp, src[0][0], -1, CVT_FLOOR | CVT_S32_F32);
2501 emit_arl(pc, dst[0], temp, 4);
2502 break;
2503 case TGSI_OPCODE_BGNLOOP:
2504 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2505 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2506 terminate_mbb(pc);
2507 break;
2508 case TGSI_OPCODE_BGNSUB:
2509 assert(!pc->in_subroutine);
2510 pc->in_subroutine = TRUE;
2511 /* probably not necessary, but align to 8 byte boundary */
2512 if (!is_long(pc->p->exec_tail))
2513 convert_to_long(pc, pc->p->exec_tail);
2514 break;
2515 case TGSI_OPCODE_BRK:
2516 assert(pc->loop_lvl > 0);
2517 emit_break(pc, -1, 0);
2518 break;
2519 case TGSI_OPCODE_CAL:
2520 assert(inst->Label.Label < pc->insn_nr);
2521 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2522 /* replaced by actual offset in nv50_program_fixup_insns */
2523 break;
2524 case TGSI_OPCODE_CEIL:
2525 for (c = 0; c < 4; c++) {
2526 if (!(mask & (1 << c)))
2527 continue;
2528 emit_cvt(pc, dst[c], src[0][c], -1,
2529 CVT_CEIL | CVT_F32_F32 | CVT_RI);
2530 }
2531 break;
2532 case TGSI_OPCODE_CMP:
2533 pc->allow32 = FALSE;
2534 for (c = 0; c < 4; c++) {
2535 if (!(mask & (1 << c)))
2536 continue;
2537 emit_cvt(pc, NULL, src[0][c], 1, CVT_F32_F32);
2538 emit_mov(pc, dst[c], src[1][c]);
2539 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2540 emit_mov(pc, dst[c], src[2][c]);
2541 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2542 }
2543 break;
2544 case TGSI_OPCODE_CONT:
2545 assert(pc->loop_lvl > 0);
2546 emit_branch(pc, -1, 0)->param.index =
2547 pc->loop_pos[pc->loop_lvl - 1];
2548 break;
2549 case TGSI_OPCODE_COS:
2550 if (mask & 8) {
2551 emit_precossin(pc, temp, src[0][3]);
2552 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2553 if (!(mask &= 7))
2554 break;
2555 if (temp == dst[3])
2556 temp = brdc = temp_temp(pc, NULL);
2557 }
2558 emit_precossin(pc, temp, src[0][0]);
2559 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2560 break;
2561 case TGSI_OPCODE_DDX:
2562 for (c = 0; c < 4; c++) {
2563 if (!(mask & (1 << c)))
2564 continue;
2565 emit_ddx(pc, dst[c], src[0][c]);
2566 }
2567 break;
2568 case TGSI_OPCODE_DDY:
2569 for (c = 0; c < 4; c++) {
2570 if (!(mask & (1 << c)))
2571 continue;
2572 emit_ddy(pc, dst[c], src[0][c]);
2573 }
2574 break;
2575 case TGSI_OPCODE_DP3:
2576 emit_mul(pc, temp, src[0][0], src[1][0]);
2577 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2578 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2579 break;
2580 case TGSI_OPCODE_DP4:
2581 emit_mul(pc, temp, src[0][0], src[1][0]);
2582 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2583 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2584 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2585 break;
2586 case TGSI_OPCODE_DPH:
2587 emit_mul(pc, temp, src[0][0], src[1][0]);
2588 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2589 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2590 emit_add(pc, brdc, src[1][3], temp);
2591 break;
2592 case TGSI_OPCODE_DST:
2593 if (mask & (1 << 1))
2594 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2595 if (mask & (1 << 2))
2596 emit_mov(pc, dst[2], src[0][2]);
2597 if (mask & (1 << 3))
2598 emit_mov(pc, dst[3], src[1][3]);
2599 if (mask & (1 << 0))
2600 emit_mov_immdval(pc, dst[0], 1.0f);
2601 break;
2602 case TGSI_OPCODE_ELSE:
2603 emit_branch(pc, -1, 0);
2604 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2605 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2606 terminate_mbb(pc);
2607 break;
2608 case TGSI_OPCODE_ENDIF:
2609 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2610
2611 /* try to replace branch over 1 insn with a predicated insn */
2612 if (nv50_kill_branch(pc) == TRUE)
2613 break;
2614
2615 if (pc->if_join[pc->if_lvl]) {
2616 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2617 pc->if_join[pc->if_lvl] = NULL;
2618 }
2619 terminate_mbb(pc);
2620 /* emit a NOP as join point, we could set it on the next
2621 * one, but would have to make sure it is long and !immd
2622 */
2623 JOIN_ON(emit_nop(pc));
2624 break;
2625 case TGSI_OPCODE_ENDLOOP:
2626 emit_branch(pc, -1, 0)->param.index =
2627 pc->loop_pos[--pc->loop_lvl];
2628 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2629 terminate_mbb(pc);
2630 break;
2631 case TGSI_OPCODE_ENDSUB:
2632 assert(pc->in_subroutine);
2633 pc->in_subroutine = FALSE;
2634 break;
2635 case TGSI_OPCODE_EX2:
2636 emit_preex2(pc, temp, src[0][0]);
2637 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2638 break;
2639 case TGSI_OPCODE_EXP:
2640 {
2641 struct nv50_reg *t[2];
2642
2643 assert(!temp);
2644 t[0] = temp_temp(pc, NULL);
2645 t[1] = temp_temp(pc, NULL);
2646
2647 if (mask & 0x6)
2648 emit_mov(pc, t[0], src[0][0]);
2649 if (mask & 0x3)
2650 emit_flr(pc, t[1], src[0][0]);
2651
2652 if (mask & (1 << 1))
2653 emit_sub(pc, dst[1], t[0], t[1]);
2654 if (mask & (1 << 0)) {
2655 emit_preex2(pc, t[1], t[1]);
2656 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2657 }
2658 if (mask & (1 << 2)) {
2659 emit_preex2(pc, t[0], t[0]);
2660 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2661 }
2662 if (mask & (1 << 3))
2663 emit_mov_immdval(pc, dst[3], 1.0f);
2664 }
2665 break;
2666 case TGSI_OPCODE_F2I:
2667 for (c = 0; c < 4; c++) {
2668 if (!(mask & (1 << c)))
2669 continue;
2670 emit_cvt(pc, dst[c], src[0][c], -1,
2671 CVT_TRUNC | CVT_S32_F32);
2672 }
2673 break;
2674 case TGSI_OPCODE_F2U:
2675 for (c = 0; c < 4; c++) {
2676 if (!(mask & (1 << c)))
2677 continue;
2678 emit_cvt(pc, dst[c], src[0][c], -1,
2679 CVT_TRUNC | CVT_U32_F32);
2680 }
2681 break;
2682 case TGSI_OPCODE_FLR:
2683 for (c = 0; c < 4; c++) {
2684 if (!(mask & (1 << c)))
2685 continue;
2686 emit_flr(pc, dst[c], src[0][c]);
2687 }
2688 break;
2689 case TGSI_OPCODE_FRC:
2690 temp = temp_temp(pc, NULL);
2691 for (c = 0; c < 4; c++) {
2692 if (!(mask & (1 << c)))
2693 continue;
2694 emit_flr(pc, temp, src[0][c]);
2695 emit_sub(pc, dst[c], src[0][c], temp);
2696 }
2697 break;
2698 case TGSI_OPCODE_I2F:
2699 for (c = 0; c < 4; c++) {
2700 if (!(mask & (1 << c)))
2701 continue;
2702 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_S32);
2703 }
2704 break;
2705 case TGSI_OPCODE_IF:
2706 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2707 emit_cvt(pc, NULL, src[0][0], 0, CVT_ABS | CVT_F32_F32);
2708 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2709 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2710 terminate_mbb(pc);
2711 break;
2712 case TGSI_OPCODE_IMAX:
2713 for (c = 0; c < 4; c++) {
2714 if (!(mask & (1 << c)))
2715 continue;
2716 emit_minmax(pc, 0x08c, dst[c], src[0][c], src[1][c]);
2717 }
2718 break;
2719 case TGSI_OPCODE_IMIN:
2720 for (c = 0; c < 4; c++) {
2721 if (!(mask & (1 << c)))
2722 continue;
2723 emit_minmax(pc, 0x0ac, dst[c], src[0][c], src[1][c]);
2724 }
2725 break;
2726 case TGSI_OPCODE_INEG:
2727 for (c = 0; c < 4; c++) {
2728 if (!(mask & (1 << c)))
2729 continue;
2730 emit_cvt(pc, dst[c], src[0][c], -1,
2731 CVT_S32_S32 | CVT_NEG);
2732 }
2733 break;
2734 case TGSI_OPCODE_KIL:
2735 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2736 emit_kil(pc, src[0][0]);
2737 emit_kil(pc, src[0][1]);
2738 emit_kil(pc, src[0][2]);
2739 emit_kil(pc, src[0][3]);
2740 break;
2741 case TGSI_OPCODE_KILP:
2742 emit_kil(pc, NULL);
2743 break;
2744 case TGSI_OPCODE_LIT:
2745 emit_lit(pc, &dst[0], mask, &src[0][0]);
2746 break;
2747 case TGSI_OPCODE_LG2:
2748 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2749 break;
2750 case TGSI_OPCODE_LOG:
2751 {
2752 struct nv50_reg *t[2];
2753
2754 t[0] = temp_temp(pc, NULL);
2755 if (mask & (1 << 1))
2756 t[1] = temp_temp(pc, NULL);
2757 else
2758 t[1] = t[0];
2759
2760 emit_cvt(pc, t[0], src[0][0], -1, CVT_ABS | CVT_F32_F32);
2761 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2762 if (mask & (1 << 2))
2763 emit_mov(pc, dst[2], t[1]);
2764 emit_flr(pc, t[1], t[1]);
2765 if (mask & (1 << 0))
2766 emit_mov(pc, dst[0], t[1]);
2767 if (mask & (1 << 1)) {
2768 t[1]->mod = NV50_MOD_NEG;
2769 emit_preex2(pc, t[1], t[1]);
2770 t[1]->mod = 0;
2771 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2772 emit_mul(pc, dst[1], t[0], t[1]);
2773 }
2774 if (mask & (1 << 3))
2775 emit_mov_immdval(pc, dst[3], 1.0f);
2776 }
2777 break;
2778 case TGSI_OPCODE_LRP:
2779 temp = temp_temp(pc, NULL);
2780 for (c = 0; c < 4; c++) {
2781 if (!(mask & (1 << c)))
2782 continue;
2783 emit_sub(pc, temp, src[1][c], src[2][c]);
2784 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2785 }
2786 break;
2787 case TGSI_OPCODE_MAD:
2788 for (c = 0; c < 4; c++) {
2789 if (!(mask & (1 << c)))
2790 continue;
2791 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2792 }
2793 break;
2794 case TGSI_OPCODE_MAX:
2795 for (c = 0; c < 4; c++) {
2796 if (!(mask & (1 << c)))
2797 continue;
2798 emit_minmax(pc, 0x880, dst[c], src[0][c], src[1][c]);
2799 }
2800 break;
2801 case TGSI_OPCODE_MIN:
2802 for (c = 0; c < 4; c++) {
2803 if (!(mask & (1 << c)))
2804 continue;
2805 emit_minmax(pc, 0x8a0, dst[c], src[0][c], src[1][c]);
2806 }
2807 break;
2808 case TGSI_OPCODE_MOV:
2809 for (c = 0; c < 4; c++) {
2810 if (!(mask & (1 << c)))
2811 continue;
2812 emit_mov(pc, dst[c], src[0][c]);
2813 }
2814 break;
2815 case TGSI_OPCODE_MUL:
2816 for (c = 0; c < 4; c++) {
2817 if (!(mask & (1 << c)))
2818 continue;
2819 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2820 }
2821 break;
2822 case TGSI_OPCODE_NOT:
2823 for (c = 0; c < 4; c++) {
2824 if (!(mask & (1 << c)))
2825 continue;
2826 emit_not(pc, dst[c], src[0][c]);
2827 }
2828 break;
2829 case TGSI_OPCODE_POW:
2830 emit_pow(pc, brdc, src[0][0], src[1][0]);
2831 break;
2832 case TGSI_OPCODE_RCP:
2833 if (!sat && popcnt4(mask) == 1)
2834 brdc = dst[ffs(mask) - 1];
2835 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2836 break;
2837 case TGSI_OPCODE_RET:
2838 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2839 nv50_fp_move_results(pc);
2840 emit_ret(pc, -1, 0);
2841 break;
2842 case TGSI_OPCODE_RSQ:
2843 if (!sat && popcnt4(mask) == 1)
2844 brdc = dst[ffs(mask) - 1];
2845 src[0][0]->mod |= NV50_MOD_ABS;
2846 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2847 break;
2848 case TGSI_OPCODE_SAD:
2849 for (c = 0; c < 4; c++) {
2850 if (!(mask & (1 << c)))
2851 continue;
2852 emit_sad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2853 }
2854 break;
2855 case TGSI_OPCODE_SCS:
2856 temp = temp_temp(pc, NULL);
2857 if (mask & 3)
2858 emit_precossin(pc, temp, src[0][0]);
2859 if (mask & (1 << 0))
2860 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
2861 if (mask & (1 << 1))
2862 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
2863 if (mask & (1 << 2))
2864 emit_mov_immdval(pc, dst[2], 0.0);
2865 if (mask & (1 << 3))
2866 emit_mov_immdval(pc, dst[3], 1.0);
2867 break;
2868 case TGSI_OPCODE_SHL:
2869 case TGSI_OPCODE_ISHR:
2870 case TGSI_OPCODE_USHR:
2871 for (c = 0; c < 4; c++) {
2872 if (!(mask & (1 << c)))
2873 continue;
2874 emit_shift(pc, dst[c], src[0][c], src[1][c],
2875 inst->Instruction.Opcode);
2876 }
2877 break;
2878 case TGSI_OPCODE_SIN:
2879 if (mask & 8) {
2880 emit_precossin(pc, temp, src[0][3]);
2881 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
2882 if (!(mask &= 7))
2883 break;
2884 if (temp == dst[3])
2885 temp = brdc = temp_temp(pc, NULL);
2886 }
2887 emit_precossin(pc, temp, src[0][0]);
2888 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
2889 break;
2890 case TGSI_OPCODE_SLT:
2891 case TGSI_OPCODE_SGE:
2892 case TGSI_OPCODE_SEQ:
2893 case TGSI_OPCODE_SGT:
2894 case TGSI_OPCODE_SLE:
2895 case TGSI_OPCODE_SNE:
2896 case TGSI_OPCODE_ISLT:
2897 case TGSI_OPCODE_ISGE:
2898 case TGSI_OPCODE_USEQ:
2899 case TGSI_OPCODE_USGE:
2900 case TGSI_OPCODE_USLT:
2901 case TGSI_OPCODE_USNE:
2902 {
2903 uint8_t cc, ty;
2904
2905 map_tgsi_setop_hw(inst->Instruction.Opcode, &cc, &ty);
2906
2907 for (c = 0; c < 4; c++) {
2908 if (!(mask & (1 << c)))
2909 continue;
2910 emit_set(pc, cc, dst[c], -1, src[0][c], src[1][c], ty);
2911 }
2912 }
2913 break;
2914 case TGSI_OPCODE_SUB:
2915 for (c = 0; c < 4; c++) {
2916 if (!(mask & (1 << c)))
2917 continue;
2918 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2919 }
2920 break;
2921 case TGSI_OPCODE_TEX:
2922 emit_tex(pc, dst, mask, src[0], unit,
2923 inst->Texture.Texture, FALSE, 0);
2924 break;
2925 case TGSI_OPCODE_TXB:
2926 emit_tex(pc, dst, mask, src[0], unit,
2927 inst->Texture.Texture, FALSE, -1);
2928 break;
2929 case TGSI_OPCODE_TXL:
2930 emit_tex(pc, dst, mask, src[0], unit,
2931 inst->Texture.Texture, FALSE, 1);
2932 break;
2933 case TGSI_OPCODE_TXP:
2934 emit_tex(pc, dst, mask, src[0], unit,
2935 inst->Texture.Texture, TRUE, 0);
2936 break;
2937 case TGSI_OPCODE_TRUNC:
2938 for (c = 0; c < 4; c++) {
2939 if (!(mask & (1 << c)))
2940 continue;
2941 emit_cvt(pc, dst[c], src[0][c], -1,
2942 CVT_TRUNC | CVT_F32_F32 | CVT_RI);
2943 }
2944 break;
2945 case TGSI_OPCODE_U2F:
2946 for (c = 0; c < 4; c++) {
2947 if (!(mask & (1 << c)))
2948 continue;
2949 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_U32);
2950 }
2951 break;
2952 case TGSI_OPCODE_UADD:
2953 for (c = 0; c < 4; c++) {
2954 if (!(mask & (1 << c)))
2955 continue;
2956 emit_add_b32(pc, dst[c], src[0][c], src[1][c]);
2957 }
2958 break;
2959 case TGSI_OPCODE_UMAX:
2960 for (c = 0; c < 4; c++) {
2961 if (!(mask & (1 << c)))
2962 continue;
2963 emit_minmax(pc, 0x084, dst[c], src[0][c], src[1][c]);
2964 }
2965 break;
2966 case TGSI_OPCODE_UMIN:
2967 for (c = 0; c < 4; c++) {
2968 if (!(mask & (1 << c)))
2969 continue;
2970 emit_minmax(pc, 0x0a4, dst[c], src[0][c], src[1][c]);
2971 }
2972 break;
2973 case TGSI_OPCODE_UMAD:
2974 {
2975 assert(!temp);
2976 temp = temp_temp(pc, NULL);
2977 for (c = 0; c < 4; c++) {
2978 if (!(mask & (1 << c)))
2979 continue;
2980 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
2981 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
2982 temp);
2983 emit_shl_imm(pc, temp, temp, 16);
2984 emit_mad_u16(pc, temp, src[0][c], 0, src[1][c], 0,
2985 temp);
2986 emit_add_b32(pc, dst[c], temp, src[2][c]);
2987 }
2988 }
2989 break;
2990 case TGSI_OPCODE_UMUL:
2991 {
2992 assert(!temp);
2993 temp = temp_temp(pc, NULL);
2994 for (c = 0; c < 4; c++) {
2995 if (!(mask & (1 << c)))
2996 continue;
2997 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
2998 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
2999 temp);
3000 emit_shl_imm(pc, temp, temp, 16);
3001 emit_mad_u16(pc, dst[c], src[0][c], 0, src[1][c], 0,
3002 temp);
3003 }
3004 }
3005 break;
3006 case TGSI_OPCODE_XPD:
3007 temp = temp_temp(pc, NULL);
3008 if (mask & (1 << 0)) {
3009 emit_mul(pc, temp, src[0][2], src[1][1]);
3010 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
3011 }
3012 if (mask & (1 << 1)) {
3013 emit_mul(pc, temp, src[0][0], src[1][2]);
3014 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
3015 }
3016 if (mask & (1 << 2)) {
3017 emit_mul(pc, temp, src[0][1], src[1][0]);
3018 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
3019 }
3020 if (mask & (1 << 3))
3021 emit_mov_immdval(pc, dst[3], 1.0);
3022 break;
3023 case TGSI_OPCODE_END:
3024 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3025 nv50_fp_move_results(pc);
3026
3027 /* last insn must be long so it can have the exit bit set */
3028 if (!is_long(pc->p->exec_tail))
3029 convert_to_long(pc, pc->p->exec_tail);
3030 else
3031 if (is_immd(pc->p->exec_tail) || is_join(pc->p->exec_tail))
3032 emit_nop(pc);
3033
3034 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
3035 break;
3036 default:
3037 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
3038 return FALSE;
3039 }
3040
3041 if (brdc) {
3042 if (sat)
3043 emit_sat(pc, brdc, brdc);
3044 for (c = 0; c < 4; c++)
3045 if ((mask & (1 << c)) && dst[c] != brdc)
3046 emit_mov(pc, dst[c], brdc);
3047 } else
3048 if (sat) {
3049 for (c = 0; c < 4; c++) {
3050 if (!(mask & (1 << c)))
3051 continue;
3052 /* In this case we saturate later, and dst[c] won't
3053 * be another temp_temp (and thus lost), since rdst
3054 * already is TEMP (see above). */
3055 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
3056 continue;
3057 emit_sat(pc, rdst[c], dst[c]);
3058 }
3059 }
3060
3061 kill_temp_temp(pc, NULL);
3062 pc->reg_instance_nr = 0;
3063
3064 return TRUE;
3065 }
3066
3067 static void
3068 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
3069 {
3070 struct nv50_reg *r, *reg = NULL;
3071 const struct tgsi_full_src_register *src;
3072 const struct tgsi_dst_register *dst;
3073 unsigned i, c, k, mask;
3074
3075 dst = &insn->Dst[0].Register;
3076 mask = dst->WriteMask;
3077
3078 if (dst->File == TGSI_FILE_TEMPORARY)
3079 reg = pc->temp;
3080 else
3081 if (dst->File == TGSI_FILE_OUTPUT) {
3082 reg = pc->result;
3083
3084 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
3085 dst->Index == pc->edgeflag_out &&
3086 insn->Src[0].Register.File == TGSI_FILE_INPUT)
3087 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
3088 }
3089
3090 if (reg) {
3091 for (c = 0; c < 4; c++) {
3092 if (!(mask & (1 << c)))
3093 continue;
3094 reg[dst->Index * 4 + c].acc = pc->insn_nr;
3095 }
3096 }
3097
3098 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3099 src = &insn->Src[i];
3100
3101 if (src->Register.File == TGSI_FILE_TEMPORARY)
3102 reg = pc->temp;
3103 else
3104 if (src->Register.File == TGSI_FILE_INPUT)
3105 reg = pc->attr;
3106 else
3107 continue;
3108
3109 mask = nv50_tgsi_src_mask(insn, i);
3110
3111 for (c = 0; c < 4; c++) {
3112 if (!(mask & (1 << c)))
3113 continue;
3114 k = tgsi_util_get_full_src_register_swizzle(src, c);
3115
3116 r = &reg[src->Register.Index * 4 + k];
3117
3118 /* If used before written, pre-allocate the reg,
3119 * lest we overwrite results from a subroutine.
3120 */
3121 if (!r->acc && r->type == P_TEMP)
3122 alloc_reg(pc, r);
3123
3124 r->acc = pc->insn_nr;
3125 }
3126 }
3127 }
3128
3129 /* Returns a bitmask indicating which dst components need to be
3130 * written to temporaries first to avoid 'corrupting' sources.
3131 *
3132 * m[i] (out) indicate component to write in the i-th position
3133 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
3134 */
3135 static unsigned
3136 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
3137 {
3138 unsigned i, c, x, unsafe;
3139
3140 for (c = 0; c < 4; c++)
3141 m[c] = c;
3142
3143 /* Swap as long as a dst component written earlier is depended on
3144 * by one written later, but the next one isn't depended on by it.
3145 */
3146 for (c = 0; c < 3; c++) {
3147 if (rdep[m[c + 1]] & (1 << m[c]))
3148 continue; /* if next one is depended on by us */
3149 for (i = c + 1; i < 4; i++)
3150 /* if we are depended on by a later one */
3151 if (rdep[m[c]] & (1 << m[i]))
3152 break;
3153 if (i == 4)
3154 continue;
3155 /* now, swap */
3156 x = m[c];
3157 m[c] = m[c + 1];
3158 m[c + 1] = x;
3159
3160 /* restart */
3161 c = 0;
3162 }
3163
3164 /* mark dependencies that could not be resolved by reordering */
3165 for (i = 0; i < 3; ++i)
3166 for (c = i + 1; c < 4; ++c)
3167 if (rdep[m[i]] & (1 << m[c]))
3168 unsafe |= (1 << i);
3169
3170 /* NOTE: $unsafe is with respect to order, not component */
3171 return unsafe;
3172 }
3173
3174 /* Select a suitable dst register for broadcasting scalar results,
3175 * or return NULL if we have to allocate an extra TEMP.
3176 *
3177 * If e.g. only 1 component is written, we may also emit the final
3178 * result to a write-only register.
3179 */
3180 static struct nv50_reg *
3181 tgsi_broadcast_dst(struct nv50_pc *pc,
3182 const struct tgsi_full_dst_register *fd, unsigned mask)
3183 {
3184 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
3185 int c = ffs(~mask & fd->Register.WriteMask);
3186 if (c)
3187 return tgsi_dst(pc, c - 1, fd);
3188 } else {
3189 int c = ffs(fd->Register.WriteMask) - 1;
3190 if ((1 << c) == fd->Register.WriteMask)
3191 return tgsi_dst(pc, c, fd);
3192 }
3193
3194 return NULL;
3195 }
3196
3197 /* Scan source swizzles and return a bitmask indicating dst regs that
3198 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
3199 */
3200 static unsigned
3201 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
3202 unsigned rdep[4])
3203 {
3204 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
3205 const struct tgsi_full_src_register *fs;
3206 unsigned i, deqs = 0;
3207
3208 for (i = 0; i < 4; ++i)
3209 rdep[i] = 0;
3210
3211 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3212 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
3213 int ms = get_supported_mods(insn, i);
3214
3215 fs = &insn->Src[i];
3216 if (fs->Register.File != fd->Register.File ||
3217 fs->Register.Index != fd->Register.Index)
3218 continue;
3219
3220 for (chn = 0; chn < 4; ++chn) {
3221 unsigned s, c;
3222
3223 if (!(mask & (1 << chn))) /* src is not read */
3224 continue;
3225 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
3226 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
3227
3228 if (!(fd->Register.WriteMask & (1 << c)))
3229 continue;
3230
3231 if (s == TGSI_UTIL_SIGN_TOGGLE && !(ms & NV50_MOD_NEG))
3232 continue;
3233 if (s == TGSI_UTIL_SIGN_CLEAR && !(ms & NV50_MOD_ABS))
3234 continue;
3235 if ((s == TGSI_UTIL_SIGN_SET) && ((ms & 3) != 3))
3236 continue;
3237
3238 rdep[c] |= nv50_tgsi_dst_revdep(
3239 insn->Instruction.Opcode, i, chn);
3240 deqs |= (1 << c);
3241 }
3242 }
3243
3244 return deqs;
3245 }
3246
3247 static boolean
3248 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
3249 {
3250 struct tgsi_full_instruction insn = tok->FullInstruction;
3251 const struct tgsi_full_dst_register *fd;
3252 unsigned i, deqs, rdep[4], m[4];
3253
3254 fd = &tok->FullInstruction.Dst[0];
3255 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
3256
3257 if (is_scalar_op(insn.Instruction.Opcode)) {
3258 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
3259 if (!pc->r_brdc)
3260 pc->r_brdc = temp_temp(pc, NULL);
3261 return nv50_program_tx_insn(pc, &insn);
3262 }
3263 pc->r_brdc = NULL;
3264
3265 if (!deqs || (!rdep[0] && !rdep[1] && !rdep[2] && !rdep[3]))
3266 return nv50_program_tx_insn(pc, &insn);
3267
3268 deqs = nv50_revdep_reorder(m, rdep);
3269
3270 for (i = 0; i < 4; ++i) {
3271 assert(pc->r_dst[m[i]] == NULL);
3272
3273 insn.Dst[0].Register.WriteMask =
3274 fd->Register.WriteMask & (1 << m[i]);
3275
3276 if (!insn.Dst[0].Register.WriteMask)
3277 continue;
3278
3279 if (deqs & (1 << i))
3280 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
3281
3282 if (!nv50_program_tx_insn(pc, &insn))
3283 return FALSE;
3284 }
3285
3286 for (i = 0; i < 4; i++) {
3287 struct nv50_reg *reg = pc->r_dst[i];
3288 if (!reg)
3289 continue;
3290 pc->r_dst[i] = NULL;
3291
3292 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
3293 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
3294 else
3295 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
3296 free_temp(pc, reg);
3297 }
3298
3299 return TRUE;
3300 }
3301
3302 static void
3303 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
3304 {
3305 struct nv50_reg *iv, **ppiv;
3306 unsigned mode = pc->interp_mode[reg->index];
3307
3308 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
3309 iv = *ppiv;
3310
3311 if ((mode & INTERP_PERSPECTIVE) && !iv) {
3312 iv = *ppiv = alloc_temp(pc, NULL);
3313 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
3314
3315 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
3316 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
3317
3318 /* XXX: when loading interpolants dynamically, move these
3319 * to the program head, or make sure it can't be skipped.
3320 */
3321 }
3322
3323 emit_interp(pc, reg, iv, mode);
3324 }
3325
3326 /* The face input is always at v[255] (varying space), with a
3327 * value of 0 for back-facing, and 0xffffffff for front-facing.
3328 */
3329 static void
3330 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
3331 {
3332 struct nv50_reg *one = alloc_immd(pc, 1.0f);
3333
3334 assert(a->rhw == -1);
3335 alloc_reg(pc, a); /* do this before rhw is set */
3336 a->rhw = 255;
3337 load_interpolant(pc, a);
3338 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
3339
3340 FREE(one);
3341 }
3342
3343 static boolean
3344 nv50_program_tx_prep(struct nv50_pc *pc)
3345 {
3346 struct tgsi_parse_context tp;
3347 struct nv50_program *p = pc->p;
3348 boolean ret = FALSE;
3349 unsigned i, c, flat_nr = 0;
3350
3351 tgsi_parse_init(&tp, pc->p->pipe.tokens);
3352 while (!tgsi_parse_end_of_tokens(&tp)) {
3353 const union tgsi_full_token *tok = &tp.FullToken;
3354
3355 tgsi_parse_token(&tp);
3356 switch (tok->Token.Type) {
3357 case TGSI_TOKEN_TYPE_IMMEDIATE:
3358 {
3359 const struct tgsi_full_immediate *imm =
3360 &tp.FullToken.FullImmediate;
3361
3362 ctor_immd_4f32(pc, imm->u[0].Float,
3363 imm->u[1].Float,
3364 imm->u[2].Float,
3365 imm->u[3].Float);
3366 }
3367 break;
3368 case TGSI_TOKEN_TYPE_DECLARATION:
3369 {
3370 const struct tgsi_full_declaration *d;
3371 unsigned si, last, first, mode;
3372
3373 d = &tp.FullToken.FullDeclaration;
3374 first = d->Range.First;
3375 last = d->Range.Last;
3376
3377 switch (d->Declaration.File) {
3378 case TGSI_FILE_TEMPORARY:
3379 break;
3380 case TGSI_FILE_OUTPUT:
3381 if (!d->Declaration.Semantic ||
3382 p->type == PIPE_SHADER_FRAGMENT)
3383 break;
3384
3385 si = d->Semantic.Index;
3386 switch (d->Semantic.Name) {
3387 case TGSI_SEMANTIC_BCOLOR:
3388 p->cfg.two_side[si].hw = first;
3389 if (p->cfg.io_nr > first)
3390 p->cfg.io_nr = first;
3391 break;
3392 case TGSI_SEMANTIC_PSIZE:
3393 p->cfg.psiz = first;
3394 if (p->cfg.io_nr > first)
3395 p->cfg.io_nr = first;
3396 break;
3397 case TGSI_SEMANTIC_EDGEFLAG:
3398 pc->edgeflag_out = first;
3399 break;
3400 /*
3401 case TGSI_SEMANTIC_CLIP_DISTANCE:
3402 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3403 break;
3404 */
3405 default:
3406 break;
3407 }
3408 break;
3409 case TGSI_FILE_INPUT:
3410 {
3411 if (p->type != PIPE_SHADER_FRAGMENT)
3412 break;
3413
3414 switch (d->Declaration.Interpolate) {
3415 case TGSI_INTERPOLATE_CONSTANT:
3416 mode = INTERP_FLAT;
3417 flat_nr++;
3418 break;
3419 case TGSI_INTERPOLATE_PERSPECTIVE:
3420 mode = INTERP_PERSPECTIVE;
3421 p->cfg.regs[1] |= 0x08 << 24;
3422 break;
3423 default:
3424 mode = INTERP_LINEAR;
3425 break;
3426 }
3427 if (d->Declaration.Centroid)
3428 mode |= INTERP_CENTROID;
3429
3430 assert(last < 32);
3431 for (i = first; i <= last; i++)
3432 pc->interp_mode[i] = mode;
3433 }
3434 break;
3435 case TGSI_FILE_ADDRESS:
3436 case TGSI_FILE_CONSTANT:
3437 case TGSI_FILE_SAMPLER:
3438 break;
3439 default:
3440 NOUVEAU_ERR("bad decl file %d\n",
3441 d->Declaration.File);
3442 goto out_err;
3443 }
3444 }
3445 break;
3446 case TGSI_TOKEN_TYPE_INSTRUCTION:
3447 pc->insn_nr++;
3448 prep_inspect_insn(pc, &tok->FullInstruction);
3449 break;
3450 default:
3451 break;
3452 }
3453 }
3454
3455 if (p->type == PIPE_SHADER_VERTEX) {
3456 int rid = 0;
3457
3458 for (i = 0; i < pc->attr_nr * 4; ++i) {
3459 if (pc->attr[i].acc) {
3460 pc->attr[i].hw = rid++;
3461 p->cfg.attr[i / 32] |= 1 << (i % 32);
3462 }
3463 }
3464
3465 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3466 p->cfg.io[i].hw = rid;
3467 p->cfg.io[i].id = i;
3468
3469 for (c = 0; c < 4; ++c) {
3470 int n = i * 4 + c;
3471 if (!pc->result[n].acc)
3472 continue;
3473 pc->result[n].hw = rid++;
3474 p->cfg.io[i].mask |= 1 << c;
3475 }
3476 }
3477
3478 for (c = 0; c < 2; ++c)
3479 if (p->cfg.two_side[c].hw < 0x40)
3480 p->cfg.two_side[c] = p->cfg.io[
3481 p->cfg.two_side[c].hw];
3482
3483 if (p->cfg.psiz < 0x40)
3484 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
3485 } else
3486 if (p->type == PIPE_SHADER_FRAGMENT) {
3487 int rid, aid;
3488 unsigned n = 0, m = pc->attr_nr - flat_nr;
3489
3490 pc->allow32 = TRUE;
3491
3492 int base = (TGSI_SEMANTIC_POSITION ==
3493 p->info.input_semantic_name[0]) ? 0 : 1;
3494
3495 /* non-flat interpolants have to be mapped to
3496 * the lower hardware IDs, so sort them:
3497 */
3498 for (i = 0; i < pc->attr_nr; i++) {
3499 if (pc->interp_mode[i] == INTERP_FLAT)
3500 p->cfg.io[m++].id = i;
3501 else {
3502 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3503 p->cfg.io[n].linear = TRUE;
3504 p->cfg.io[n++].id = i;
3505 }
3506 }
3507
3508 if (!base) /* set w-coordinate mask from perspective interp */
3509 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
3510
3511 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
3512 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
3513
3514 for (n = 0; n < pc->attr_nr; ++n) {
3515 p->cfg.io[n].hw = rid = aid;
3516 i = p->cfg.io[n].id;
3517
3518 if (p->info.input_semantic_name[n] ==
3519 TGSI_SEMANTIC_FACE) {
3520 load_frontfacing(pc, &pc->attr[i * 4]);
3521 continue;
3522 }
3523
3524 for (c = 0; c < 4; ++c) {
3525 if (!pc->attr[i * 4 + c].acc)
3526 continue;
3527 pc->attr[i * 4 + c].rhw = rid++;
3528 p->cfg.io[n].mask |= 1 << c;
3529
3530 load_interpolant(pc, &pc->attr[i * 4 + c]);
3531 }
3532 aid += popcnt4(p->cfg.io[n].mask);
3533 }
3534
3535 if (!base)
3536 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
3537
3538 m = popcnt4(p->cfg.regs[1] >> 24);
3539
3540 /* set count of non-position inputs and of non-flat
3541 * non-position inputs for FP_INTERPOLANT_CTRL
3542 */
3543 p->cfg.regs[1] |= aid - m;
3544
3545 if (flat_nr) {
3546 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
3547 p->cfg.regs[1] |= (i - m) << 16;
3548 } else
3549 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3550
3551 /* mark color semantic for light-twoside */
3552 n = 0x40;
3553 for (i = 0; i < pc->attr_nr; i++) {
3554 ubyte si, sn;
3555
3556 sn = p->info.input_semantic_name[p->cfg.io[i].id];
3557 si = p->info.input_semantic_index[p->cfg.io[i].id];
3558
3559 if (sn == TGSI_SEMANTIC_COLOR) {
3560 p->cfg.two_side[si] = p->cfg.io[i];
3561
3562 /* increase colour count */
3563 p->cfg.regs[0] += popcnt4(
3564 p->cfg.two_side[si].mask) << 16;
3565
3566 n = MIN2(n, p->cfg.io[i].hw - m);
3567 }
3568 }
3569 if (n < 0x40)
3570 p->cfg.regs[0] += n;
3571
3572 /* Initialize FP results:
3573 * FragDepth is always first TGSI and last hw output
3574 */
3575 i = p->info.writes_z ? 4 : 0;
3576 for (rid = 0; i < pc->result_nr * 4; i++)
3577 pc->result[i].rhw = rid++;
3578 if (p->info.writes_z)
3579 pc->result[2].rhw = rid;
3580
3581 p->cfg.high_result = rid;
3582
3583 /* separate/different colour results for MRTs ? */
3584 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3585 p->cfg.regs[2] |= 1;
3586 }
3587
3588 if (pc->immd_nr) {
3589 int rid = 0;
3590
3591 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3592 if (!pc->immd)
3593 goto out_err;
3594
3595 for (i = 0; i < pc->immd_nr; i++) {
3596 for (c = 0; c < 4; c++, rid++)
3597 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3598 }
3599 }
3600
3601 ret = TRUE;
3602 out_err:
3603 if (pc->iv_p)
3604 free_temp(pc, pc->iv_p);
3605 if (pc->iv_c)
3606 free_temp(pc, pc->iv_c);
3607
3608 tgsi_parse_free(&tp);
3609 return ret;
3610 }
3611
3612 static void
3613 free_nv50_pc(struct nv50_pc *pc)
3614 {
3615 if (pc->immd)
3616 FREE(pc->immd);
3617 if (pc->param)
3618 FREE(pc->param);
3619 if (pc->result)
3620 FREE(pc->result);
3621 if (pc->attr)
3622 FREE(pc->attr);
3623 if (pc->temp)
3624 FREE(pc->temp);
3625 if (pc->insn_pos)
3626 FREE(pc->insn_pos);
3627
3628 FREE(pc);
3629 }
3630
3631 static boolean
3632 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3633 {
3634 int i, c;
3635 unsigned rtype[2] = { P_ATTR, P_RESULT };
3636
3637 pc->p = p;
3638 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3639 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3640 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3641 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3642 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3643 assert(pc->addr_nr <= 2);
3644
3645 p->cfg.high_temp = 4;
3646
3647 p->cfg.two_side[0].hw = 0x40;
3648 p->cfg.two_side[1].hw = 0x40;
3649
3650 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3651
3652 switch (p->type) {
3653 case PIPE_SHADER_VERTEX:
3654 p->cfg.psiz = 0x40;
3655 p->cfg.clpd = 0x40;
3656 p->cfg.io_nr = pc->result_nr;
3657 break;
3658 case PIPE_SHADER_FRAGMENT:
3659 rtype[0] = rtype[1] = P_TEMP;
3660
3661 p->cfg.regs[0] = 0x01000004;
3662 p->cfg.io_nr = pc->attr_nr;
3663
3664 if (p->info.writes_z) {
3665 p->cfg.regs[2] |= 0x00000100;
3666 p->cfg.regs[3] |= 0x00000011;
3667 }
3668 if (p->info.uses_kill)
3669 p->cfg.regs[2] |= 0x00100000;
3670 break;
3671 }
3672
3673 if (pc->temp_nr) {
3674 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3675 if (!pc->temp)
3676 return FALSE;
3677
3678 for (i = 0; i < pc->temp_nr * 4; ++i)
3679 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3680 }
3681
3682 if (pc->attr_nr) {
3683 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3684 if (!pc->attr)
3685 return FALSE;
3686
3687 for (i = 0; i < pc->attr_nr * 4; ++i)
3688 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3689 }
3690
3691 if (pc->result_nr) {
3692 unsigned nr = pc->result_nr * 4;
3693
3694 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3695 if (!pc->result)
3696 return FALSE;
3697
3698 for (i = 0; i < nr; ++i)
3699 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3700 }
3701
3702 if (pc->param_nr) {
3703 int rid = 0;
3704
3705 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3706 if (!pc->param)
3707 return FALSE;
3708
3709 for (i = 0; i < pc->param_nr; ++i)
3710 for (c = 0; c < 4; ++c, ++rid)
3711 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3712 }
3713
3714 if (pc->addr_nr) {
3715 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3716 if (!pc->addr)
3717 return FALSE;
3718 }
3719 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3720 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
3721
3722 return TRUE;
3723 }
3724
3725 static void
3726 nv50_program_fixup_insns(struct nv50_pc *pc)
3727 {
3728 struct nv50_program_exec *e, **bra_list;
3729 unsigned i, n, pos;
3730
3731 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3732
3733 /* Collect branch instructions, we need to adjust their offsets
3734 * when converting 32 bit instructions to 64 bit ones
3735 */
3736 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3737 if (e->param.index >= 0 && !e->param.mask)
3738 bra_list[n++] = e;
3739
3740 /* Make sure we don't have any single 32 bit instructions. */
3741 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3742 pos += is_long(e) ? 2 : 1;
3743
3744 if ((pos & 1) && (!e->next || is_long(e->next))) {
3745 for (i = 0; i < n; ++i)
3746 if (bra_list[i]->param.index >= pos)
3747 bra_list[i]->param.index += 1;
3748 for (i = 0; i < pc->insn_nr; ++i)
3749 if (pc->insn_pos[i] >= pos)
3750 pc->insn_pos[i] += 1;
3751 convert_to_long(pc, e);
3752 ++pos;
3753 }
3754 }
3755
3756 FREE(bra_list);
3757
3758 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
3759 return;
3760
3761 /* fill in CALL offsets */
3762 for (e = pc->p->exec_head; e; e = e->next) {
3763 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
3764 e->param.index = pc->insn_pos[e->param.index];
3765 }
3766 }
3767
3768 static boolean
3769 nv50_program_tx(struct nv50_program *p)
3770 {
3771 struct tgsi_parse_context parse;
3772 struct nv50_pc *pc;
3773 boolean ret;
3774
3775 pc = CALLOC_STRUCT(nv50_pc);
3776 if (!pc)
3777 return FALSE;
3778
3779 ret = ctor_nv50_pc(pc, p);
3780 if (ret == FALSE)
3781 goto out_cleanup;
3782
3783 ret = nv50_program_tx_prep(pc);
3784 if (ret == FALSE)
3785 goto out_cleanup;
3786
3787 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
3788
3789 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3790 while (!tgsi_parse_end_of_tokens(&parse)) {
3791 const union tgsi_full_token *tok = &parse.FullToken;
3792
3793 /* previously allow32 was FALSE for first & last instruction */
3794 pc->allow32 = TRUE;
3795
3796 tgsi_parse_token(&parse);
3797
3798 switch (tok->Token.Type) {
3799 case TGSI_TOKEN_TYPE_INSTRUCTION:
3800 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
3801 ++pc->insn_cur;
3802 ret = nv50_tgsi_insn(pc, tok);
3803 if (ret == FALSE)
3804 goto out_err;
3805 break;
3806 default:
3807 break;
3808 }
3809 }
3810
3811 nv50_program_fixup_insns(pc);
3812
3813 p->param_nr = pc->param_nr * 4;
3814 p->immd_nr = pc->immd_nr * 4;
3815 p->immd = pc->immd_buf;
3816
3817 out_err:
3818 tgsi_parse_free(&parse);
3819
3820 out_cleanup:
3821 free_nv50_pc(pc);
3822 return ret;
3823 }
3824
3825 static void
3826 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3827 {
3828 if (nv50_program_tx(p) == FALSE)
3829 assert(0);
3830 p->translated = TRUE;
3831 }
3832
3833 static void
3834 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
3835 unsigned start, unsigned count, unsigned cbuf)
3836 {
3837 struct nouveau_channel *chan = nv50->screen->base.channel;
3838 struct nouveau_grobj *tesla = nv50->screen->tesla;
3839
3840 while (count) {
3841 unsigned nr = count > 2047 ? 2047 : count;
3842
3843 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3844 OUT_RING (chan, (cbuf << 0) | (start << 8));
3845 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3846 OUT_RINGp (chan, map, nr);
3847
3848 map += nr;
3849 start += nr;
3850 count -= nr;
3851 }
3852 }
3853
3854 static void
3855 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3856 {
3857 struct pipe_screen *pscreen = nv50->pipe.screen;
3858
3859 if (!p->data[0] && p->immd_nr) {
3860 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3861
3862 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3863 while (heap->next && heap->size < p->immd_nr) {
3864 struct nv50_program *evict = heap->next->priv;
3865 nouveau_resource_free(&evict->data[0]);
3866 }
3867
3868 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3869 &p->data[0]))
3870 assert(0);
3871 }
3872
3873 /* immediates only need to be uploaded again when freed */
3874 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3875 p->immd_nr, NV50_CB_PMISC);
3876 }
3877
3878 assert(p->param_nr <= 512);
3879
3880 if (p->param_nr) {
3881 unsigned cb;
3882 uint32_t *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3883 PIPE_BUFFER_USAGE_CPU_READ);
3884
3885 if (p->type == PIPE_SHADER_VERTEX)
3886 cb = NV50_CB_PVP;
3887 else
3888 cb = NV50_CB_PFP;
3889
3890 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3891 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3892 }
3893 }
3894
3895 static void
3896 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3897 {
3898 struct nouveau_channel *chan = nv50->screen->base.channel;
3899 struct nv50_program_exec *e;
3900 uint32_t *up, i;
3901 boolean upload = FALSE;
3902
3903 if (!p->bo) {
3904 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3905 p->exec_size * 4, &p->bo);
3906 upload = TRUE;
3907 }
3908
3909 if (p->data[0] && p->data[0]->start != p->data_start[0])
3910 upload = TRUE;
3911
3912 if (!upload)
3913 return;
3914
3915 up = MALLOC(p->exec_size * 4);
3916
3917 for (i = 0, e = p->exec_head; e; e = e->next) {
3918 unsigned ei, ci, bs;
3919
3920 if (e->param.index >= 0 && e->param.mask) {
3921 bs = (e->inst[1] >> 22) & 0x07;
3922 assert(bs < 2);
3923 ei = e->param.shift >> 5;
3924 ci = e->param.index;
3925 if (bs == 0)
3926 ci += p->data[bs]->start;
3927
3928 e->inst[ei] &= ~e->param.mask;
3929 e->inst[ei] |= (ci << e->param.shift);
3930 } else
3931 if (e->param.index >= 0) {
3932 /* zero mask means param is a jump/branch offset */
3933 assert(!(e->param.index & 1));
3934 /* seem to be 8 byte steps */
3935 ei = (e->param.index >> 1) + 0 /* START_ID */;
3936
3937 e->inst[0] &= 0xf0000fff;
3938 e->inst[0] |= ei << 12;
3939 }
3940
3941 up[i++] = e->inst[0];
3942 if (is_long(e))
3943 up[i++] = e->inst[1];
3944 }
3945 assert(i == p->exec_size);
3946
3947 if (p->data[0])
3948 p->data_start[0] = p->data[0]->start;
3949
3950 #ifdef NV50_PROGRAM_DUMP
3951 NOUVEAU_ERR("-------\n");
3952 for (e = p->exec_head; e; e = e->next) {
3953 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3954 if (is_long(e))
3955 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3956 }
3957 #endif
3958 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3959 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3960 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3961 0, 0, p->exec_size * 4, 1, 1);
3962
3963 FREE(up);
3964 }
3965
3966 void
3967 nv50_vertprog_validate(struct nv50_context *nv50)
3968 {
3969 struct nouveau_grobj *tesla = nv50->screen->tesla;
3970 struct nv50_program *p = nv50->vertprog;
3971 struct nouveau_stateobj *so;
3972
3973 if (!p->translated) {
3974 nv50_program_validate(nv50, p);
3975 if (!p->translated)
3976 assert(0);
3977 }
3978
3979 nv50_program_validate_data(nv50, p);
3980 nv50_program_validate_code(nv50, p);
3981
3982 so = so_new(5, 8, 2);
3983 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3984 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3985 NOUVEAU_BO_HIGH, 0, 0);
3986 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3987 NOUVEAU_BO_LOW, 0, 0);
3988 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3989 so_data (so, p->cfg.attr[0]);
3990 so_data (so, p->cfg.attr[1]);
3991 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3992 so_data (so, p->cfg.high_result);
3993 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3994 so_data (so, p->cfg.high_result); //8);
3995 so_data (so, p->cfg.high_temp);
3996 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3997 so_data (so, 0); /* program start offset */
3998 so_ref(so, &nv50->state.vertprog);
3999 so_ref(NULL, &so);
4000 }
4001
4002 void
4003 nv50_fragprog_validate(struct nv50_context *nv50)
4004 {
4005 struct nouveau_grobj *tesla = nv50->screen->tesla;
4006 struct nv50_program *p = nv50->fragprog;
4007 struct nouveau_stateobj *so;
4008
4009 if (!p->translated) {
4010 nv50_program_validate(nv50, p);
4011 if (!p->translated)
4012 assert(0);
4013 }
4014
4015 nv50_program_validate_data(nv50, p);
4016 nv50_program_validate_code(nv50, p);
4017
4018 so = so_new(6, 7, 2);
4019 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
4020 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4021 NOUVEAU_BO_HIGH, 0, 0);
4022 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4023 NOUVEAU_BO_LOW, 0, 0);
4024 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
4025 so_data (so, p->cfg.high_temp);
4026 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
4027 so_data (so, p->cfg.high_result);
4028 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
4029 so_data (so, p->cfg.regs[2]);
4030 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
4031 so_data (so, p->cfg.regs[3]);
4032 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
4033 so_data (so, 0); /* program start offset */
4034 so_ref(so, &nv50->state.fragprog);
4035 so_ref(NULL, &so);
4036 }
4037
4038 static uint32_t
4039 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
4040 {
4041 struct nv50_program *fp = nv50->fragprog;
4042 struct nv50_program *vp = nv50->vertprog;
4043 unsigned i, c, m = base;
4044 uint32_t origin = 0x00000010;
4045
4046 /* XXX: this might not work correctly in all cases yet - we'll
4047 * just assume that an FP generic input that is not written in
4048 * the VP is PointCoord.
4049 */
4050 memset(pntc, 0, 8 * sizeof(uint32_t));
4051
4052 for (i = 0; i < fp->cfg.io_nr; i++) {
4053 uint8_t sn, si;
4054 uint8_t j, k = fp->cfg.io[i].id;
4055 unsigned n = popcnt4(fp->cfg.io[i].mask);
4056
4057 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
4058 m += n;
4059 continue;
4060 }
4061
4062 for (j = 0; j < vp->info.num_outputs; ++j) {
4063 sn = vp->info.output_semantic_name[j];
4064 si = vp->info.output_semantic_index[j];
4065
4066 if (sn == fp->info.input_semantic_name[k] &&
4067 si == fp->info.input_semantic_index[k])
4068 break;
4069 }
4070
4071 if (j < vp->info.num_outputs) {
4072 ubyte mode =
4073 nv50->rasterizer->pipe.sprite_coord_mode[si];
4074
4075 if (mode == PIPE_SPRITE_COORD_NONE) {
4076 m += n;
4077 continue;
4078 } else
4079 if (mode == PIPE_SPRITE_COORD_LOWER_LEFT)
4080 origin = 0;
4081 }
4082
4083 /* this is either PointCoord or replaced by sprite coords */
4084 for (c = 0; c < 4; c++) {
4085 if (!(fp->cfg.io[i].mask & (1 << c)))
4086 continue;
4087 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
4088 ++m;
4089 }
4090 }
4091 return origin;
4092 }
4093
4094 static int
4095 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
4096 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
4097 {
4098 int c;
4099 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
4100 uint8_t *map = (uint8_t *)p_map;
4101
4102 for (c = 0; c < 4; ++c) {
4103 if (mf & 1) {
4104 if (fpi->linear == TRUE)
4105 lin[mid / 32] |= 1 << (mid % 32);
4106 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
4107 }
4108
4109 oid += mv & 1;
4110 mf >>= 1;
4111 mv >>= 1;
4112 }
4113
4114 return mid;
4115 }
4116
4117 void
4118 nv50_linkage_validate(struct nv50_context *nv50)
4119 {
4120 struct nouveau_grobj *tesla = nv50->screen->tesla;
4121 struct nv50_program *vp = nv50->vertprog;
4122 struct nv50_program *fp = nv50->fragprog;
4123 struct nouveau_stateobj *so;
4124 struct nv50_sreg4 dummy, *vpo;
4125 int i, n, c, m = 0;
4126 uint32_t map[16], lin[4], reg[5], pcrd[8];
4127
4128 memset(map, 0, sizeof(map));
4129 memset(lin, 0, sizeof(lin));
4130
4131 reg[1] = 0x00000004; /* low and high clip distance map ids */
4132 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
4133 reg[3] = 0x00000000; /* point size map id & enable */
4134 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
4135 reg[4] = fp->cfg.regs[1]; /* interpolant info */
4136
4137 dummy.linear = FALSE;
4138 dummy.mask = 0xf; /* map all components of HPOS */
4139 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
4140
4141 dummy.mask = 0x0;
4142
4143 if (vp->cfg.clpd < 0x40) {
4144 for (c = 0; c < vp->cfg.clpd_nr; ++c)
4145 map[m++] = vp->cfg.clpd + c;
4146 reg[1] = (m << 8);
4147 }
4148
4149 reg[0] |= m << 8; /* adjust BFC0 id */
4150
4151 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
4152 if (nv50->rasterizer->pipe.light_twoside) {
4153 vpo = &vp->cfg.two_side[0];
4154
4155 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
4156 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
4157 }
4158
4159 reg[0] += m - 4; /* adjust FFC0 id */
4160 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
4161
4162 for (i = 0; i < fp->cfg.io_nr; i++) {
4163 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
4164 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
4165
4166 /* position must be mapped first */
4167 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
4168
4169 /* maybe even remove these from cfg.io */
4170 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
4171 continue;
4172
4173 /* VP outputs and vp->cfg.io are in the same order */
4174 for (n = 0; n < vp->info.num_outputs; ++n) {
4175 if (vp->info.output_semantic_name[n] == sn &&
4176 vp->info.output_semantic_index[n] == si)
4177 break;
4178 }
4179 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
4180
4181 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
4182 }
4183
4184 if (nv50->rasterizer->pipe.point_size_per_vertex) {
4185 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
4186 reg[3] = (m++ << 4) | 1;
4187 }
4188
4189 /* now fill the stateobj */
4190 so = so_new(7, 57, 0);
4191
4192 n = (m + 3) / 4;
4193 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4194 so_data (so, m);
4195 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
4196 so_datap (so, map, n);
4197
4198 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
4199 so_datap (so, reg, 4);
4200
4201 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
4202 so_data (so, reg[4]);
4203
4204 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
4205 so_datap (so, lin, 4);
4206
4207 if (nv50->rasterizer->pipe.point_sprite) {
4208 so_method(so, tesla, NV50TCL_POINT_SPRITE_CTRL, 1);
4209 so_data (so,
4210 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff));
4211
4212 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
4213 so_datap (so, pcrd, 8);
4214 }
4215
4216 so_ref(so, &nv50->state.programs);
4217 so_ref(NULL, &so);
4218 }
4219
4220 void
4221 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
4222 {
4223 while (p->exec_head) {
4224 struct nv50_program_exec *e = p->exec_head;
4225
4226 p->exec_head = e->next;
4227 FREE(e);
4228 }
4229 p->exec_tail = NULL;
4230 p->exec_size = 0;
4231
4232 nouveau_bo_ref(NULL, &p->bo);
4233
4234 nouveau_resource_free(&p->data[0]);
4235
4236 p->translated = 0;
4237 }