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nv50: Dehexify and bring up to date with new method defines.
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_SAT 4
100
101 /* STACK: Conditionals and loops have to use the (per warp) stack.
102 * Stack entries consist of an entry type (divergent path, join at),
103 * a mask indicating the active threads of the warp, and an address.
104 * MPs can store 12 stack entries internally, if we need more (and
105 * we probably do), we have to create a stack buffer in VRAM.
106 */
107 /* impose low limits for now */
108 #define NV50_MAX_COND_NESTING 4
109 #define NV50_MAX_LOOP_NESTING 3
110
111 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
112
113 struct nv50_pc {
114 struct nv50_program *p;
115
116 /* hw resources */
117 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
118 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
119
120 /* tgsi resources */
121 struct nv50_reg *temp;
122 int temp_nr;
123 struct nv50_reg *attr;
124 int attr_nr;
125 struct nv50_reg *result;
126 int result_nr;
127 struct nv50_reg *param;
128 int param_nr;
129 struct nv50_reg *immd;
130 uint32_t *immd_buf;
131 int immd_nr;
132 struct nv50_reg **addr;
133 int addr_nr;
134 uint8_t addr_alloc; /* set bit indicates used for TGSI_FILE_ADDRESS */
135
136 struct nv50_reg *temp_temp[16];
137 unsigned temp_temp_nr;
138
139 /* broadcast and destination replacement regs */
140 struct nv50_reg *r_brdc;
141 struct nv50_reg *r_dst[4];
142
143 struct nv50_reg reg_instances[16];
144 unsigned reg_instance_nr;
145
146 unsigned interp_mode[32];
147 /* perspective interpolation registers */
148 struct nv50_reg *iv_p;
149 struct nv50_reg *iv_c;
150
151 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
152 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
153 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
154 int if_lvl, loop_lvl;
155 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
156
157 /* current instruction and total number of insns */
158 unsigned insn_cur;
159 unsigned insn_nr;
160
161 boolean allow32;
162
163 uint8_t edgeflag_out;
164 };
165
166 static INLINE struct nv50_reg *
167 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
168 {
169 struct nv50_reg *ri;
170
171 assert(pc->reg_instance_nr < 16);
172 ri = &pc->reg_instances[pc->reg_instance_nr++];
173 if (reg) {
174 *ri = *reg;
175 reg->mod = 0;
176 }
177 return ri;
178 }
179
180 static INLINE void
181 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
182 {
183 reg->type = type;
184 reg->index = index;
185 reg->hw = hw;
186 reg->mod = 0;
187 reg->rhw = -1;
188 reg->acc = 0;
189 }
190
191 static INLINE unsigned
192 popcnt4(uint32_t val)
193 {
194 static const unsigned cnt[16]
195 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
196 return cnt[val & 0xf];
197 }
198
199 static void
200 terminate_mbb(struct nv50_pc *pc)
201 {
202 int i;
203
204 /* remove records of temporary address register values */
205 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
206 pc->r_addr[i].rhw = -1;
207 }
208
209 static void
210 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
211 {
212 int i = 0;
213
214 if (reg->type == P_RESULT) {
215 if (pc->p->cfg.high_result < (reg->hw + 1))
216 pc->p->cfg.high_result = reg->hw + 1;
217 }
218
219 if (reg->type != P_TEMP)
220 return;
221
222 if (reg->hw >= 0) {
223 /*XXX: do this here too to catch FP temp-as-attr usage..
224 * not clean, but works */
225 if (pc->p->cfg.high_temp < (reg->hw + 1))
226 pc->p->cfg.high_temp = reg->hw + 1;
227 return;
228 }
229
230 if (reg->rhw != -1) {
231 /* try to allocate temporary with index rhw first */
232 if (!(pc->r_temp[reg->rhw])) {
233 pc->r_temp[reg->rhw] = reg;
234 reg->hw = reg->rhw;
235 if (pc->p->cfg.high_temp < (reg->rhw + 1))
236 pc->p->cfg.high_temp = reg->rhw + 1;
237 return;
238 }
239 /* make sure we don't get things like $r0 needs to go
240 * in $r1 and $r1 in $r0
241 */
242 i = pc->result_nr * 4;
243 }
244
245 for (; i < NV50_SU_MAX_TEMP; i++) {
246 if (!(pc->r_temp[i])) {
247 pc->r_temp[i] = reg;
248 reg->hw = i;
249 if (pc->p->cfg.high_temp < (i + 1))
250 pc->p->cfg.high_temp = i + 1;
251 return;
252 }
253 }
254
255 assert(0);
256 }
257
258 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
259 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
260 * lest we risk temp_temps overwriting regs alloc'd "later".
261 */
262 static struct nv50_reg *
263 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
264 {
265 struct nv50_reg *r;
266 int i;
267
268 if (dst && dst->type == P_TEMP && dst->hw == -1)
269 return dst;
270
271 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
272 if (!pc->r_temp[i]) {
273 r = MALLOC_STRUCT(nv50_reg);
274 ctor_reg(r, P_TEMP, -1, i);
275 pc->r_temp[i] = r;
276 return r;
277 }
278 }
279
280 assert(0);
281 return NULL;
282 }
283
284 /* Assign the hw of the discarded temporary register src
285 * to the tgsi register dst and free src.
286 */
287 static void
288 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
289 {
290 assert(src->index == -1 && src->hw != -1);
291
292 if (dst->hw != -1)
293 pc->r_temp[dst->hw] = NULL;
294 pc->r_temp[src->hw] = dst;
295 dst->hw = src->hw;
296
297 FREE(src);
298 }
299
300 /* release the hardware resource held by r */
301 static void
302 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
303 {
304 assert(r->type == P_TEMP);
305 if (r->hw == -1)
306 return;
307
308 assert(pc->r_temp[r->hw] == r);
309 pc->r_temp[r->hw] = NULL;
310
311 r->acc = 0;
312 if (r->index == -1)
313 FREE(r);
314 }
315
316 static void
317 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
318 {
319 if (r->index == -1) {
320 unsigned hw = r->hw;
321
322 FREE(pc->r_temp[hw]);
323 pc->r_temp[hw] = NULL;
324 }
325 }
326
327 static int
328 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
329 {
330 int i;
331
332 if ((idx + 4) >= NV50_SU_MAX_TEMP)
333 return 1;
334
335 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
336 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
337 return alloc_temp4(pc, dst, idx + 4);
338
339 for (i = 0; i < 4; i++) {
340 dst[i] = MALLOC_STRUCT(nv50_reg);
341 ctor_reg(dst[i], P_TEMP, -1, idx + i);
342 pc->r_temp[idx + i] = dst[i];
343 }
344
345 return 0;
346 }
347
348 static void
349 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
350 {
351 int i;
352
353 for (i = 0; i < 4; i++)
354 free_temp(pc, reg[i]);
355 }
356
357 static struct nv50_reg *
358 temp_temp(struct nv50_pc *pc)
359 {
360 if (pc->temp_temp_nr >= 16)
361 assert(0);
362
363 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
364 return pc->temp_temp[pc->temp_temp_nr++];
365 }
366
367 static void
368 kill_temp_temp(struct nv50_pc *pc)
369 {
370 int i;
371
372 for (i = 0; i < pc->temp_temp_nr; i++)
373 free_temp(pc, pc->temp_temp[i]);
374 pc->temp_temp_nr = 0;
375 }
376
377 static int
378 ctor_immd_4u32(struct nv50_pc *pc,
379 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
380 {
381 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
382
383 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
384
385 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
386 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
387 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
388 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
389
390 return pc->immd_nr++;
391 }
392
393 static INLINE int
394 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
395 {
396 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
397 }
398
399 static struct nv50_reg *
400 alloc_immd(struct nv50_pc *pc, float f)
401 {
402 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
403 unsigned hw;
404
405 for (hw = 0; hw < pc->immd_nr * 4; hw++)
406 if (pc->immd_buf[hw] == fui(f))
407 break;
408
409 if (hw == pc->immd_nr * 4)
410 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
411
412 ctor_reg(r, P_IMMD, -1, hw);
413 return r;
414 }
415
416 static struct nv50_program_exec *
417 exec(struct nv50_pc *pc)
418 {
419 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
420
421 e->param.index = -1;
422 return e;
423 }
424
425 static void
426 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
427 {
428 struct nv50_program *p = pc->p;
429
430 if (p->exec_tail)
431 p->exec_tail->next = e;
432 if (!p->exec_head)
433 p->exec_head = e;
434 p->exec_tail = e;
435 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
436 }
437
438 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
439
440 static boolean
441 is_long(struct nv50_program_exec *e)
442 {
443 if (e->inst[0] & 1)
444 return TRUE;
445 return FALSE;
446 }
447
448 static boolean
449 is_immd(struct nv50_program_exec *e)
450 {
451 if (is_long(e) && (e->inst[1] & 3) == 3)
452 return TRUE;
453 return FALSE;
454 }
455
456 static INLINE void
457 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
458 struct nv50_program_exec *e)
459 {
460 set_long(pc, e);
461 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
462 e->inst[1] |= (pred << 7) | (idx << 12);
463 }
464
465 static INLINE void
466 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
467 struct nv50_program_exec *e)
468 {
469 set_long(pc, e);
470 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
471 e->inst[1] |= (idx << 4) | (on << 6);
472 }
473
474 static INLINE void
475 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
476 {
477 if (is_long(e))
478 return;
479
480 e->inst[0] |= 1;
481 set_pred(pc, 0xf, 0, e);
482 set_pred_wr(pc, 0, 0, e);
483 }
484
485 static INLINE void
486 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
487 {
488 if (dst->type == P_RESULT) {
489 set_long(pc, e);
490 e->inst[1] |= 0x00000008;
491 }
492
493 alloc_reg(pc, dst);
494 if (dst->hw > 63)
495 set_long(pc, e);
496 e->inst[0] |= (dst->hw << 2);
497 }
498
499 static INLINE void
500 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
501 {
502 union {
503 float f;
504 uint32_t ui;
505 } u;
506 u.ui = pc->immd_buf[imm->hw];
507
508 u.f = (imm->mod & NV50_MOD_ABS) ? fabsf(u.f) : u.f;
509 u.f = (imm->mod & NV50_MOD_NEG) ? -u.f : u.f;
510
511 set_long(pc, e);
512 /* XXX: can't be predicated - bits overlap; cases where both
513 * are required should be avoided by using pc->allow32 */
514 set_pred(pc, 0, 0, e);
515 set_pred_wr(pc, 0, 0, e);
516
517 e->inst[1] |= 0x00000002 | 0x00000001;
518 e->inst[0] |= (u.ui & 0x3f) << 16;
519 e->inst[1] |= (u.ui >> 6) << 2;
520 }
521
522 static INLINE void
523 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
524 {
525 assert(!(e->inst[0] & 0x0c000000));
526 assert(!(e->inst[1] & 0x00000004));
527
528 e->inst[0] |= (a->hw & 3) << 26;
529 e->inst[1] |= (a->hw >> 2) << 2;
530 }
531
532 static void
533 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
534 struct nv50_reg *src0, uint16_t src1_val)
535 {
536 struct nv50_program_exec *e = exec(pc);
537
538 e->inst[0] = 0xd0000000 | (src1_val << 9);
539 e->inst[1] = 0x20000000;
540 set_long(pc, e);
541 e->inst[0] |= dst->hw << 2;
542 if (src0) /* otherwise will add to $a0, which is always 0 */
543 set_addr(e, src0);
544
545 emit(pc, e);
546 }
547
548 static struct nv50_reg *
549 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
550 {
551 struct nv50_reg *a_tgsi = NULL, *a = NULL;
552 int i;
553 uint8_t avail = ~pc->addr_alloc;
554
555 if (!ref) {
556 /* allocate for TGSI_FILE_ADDRESS */
557 while (avail) {
558 i = ffs(avail) - 1;
559
560 if (pc->r_addr[i].rhw < 0 ||
561 pc->r_addr[i].acc != pc->insn_cur) {
562 pc->addr_alloc |= (1 << i);
563
564 pc->r_addr[i].rhw = -1;
565 pc->r_addr[i].index = i;
566 return &pc->r_addr[i];
567 }
568 avail &= ~(1 << i);
569 }
570 assert(0);
571 return NULL;
572 }
573
574 /* Allocate and set an address reg so we can access 'ref'.
575 *
576 * If and r_addr->index will be -1 or the hw index the value
577 * value in rhw is relative to. If rhw < 0, the reg has not
578 * been initialized or is in use for TGSI_FILE_ADDRESS.
579 */
580 while (avail) { /* only consider regs that are not TGSI */
581 i = ffs(avail) - 1;
582 avail &= ~(1 << i);
583
584 if ((!a || a->rhw >= 0) && pc->r_addr[i].rhw < 0) {
585 /* prefer an usused reg with low hw index */
586 a = &pc->r_addr[i];
587 continue;
588 }
589 if (!a && pc->r_addr[i].acc != pc->insn_cur)
590 a = &pc->r_addr[i];
591
592 if (ref->hw - pc->r_addr[i].rhw >= 128)
593 continue;
594
595 if ((ref->acc >= 0 && pc->r_addr[i].index < 0) ||
596 (ref->acc < 0 && pc->r_addr[i].index == ref->index)) {
597 pc->r_addr[i].acc = pc->insn_cur;
598 return &pc->r_addr[i];
599 }
600 }
601 assert(a);
602
603 if (ref->acc < 0)
604 a_tgsi = pc->addr[ref->index];
605
606 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
607
608 a->rhw = ref->hw & ~0x7f;
609 a->acc = pc->insn_cur;
610 a->index = a_tgsi ? ref->index : -1;
611 return a;
612 }
613
614 #define INTERP_LINEAR 0
615 #define INTERP_FLAT 1
616 #define INTERP_PERSPECTIVE 2
617 #define INTERP_CENTROID 4
618
619 /* interpolant index has been stored in dst->rhw */
620 static void
621 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
622 unsigned mode)
623 {
624 assert(dst->rhw != -1);
625 struct nv50_program_exec *e = exec(pc);
626
627 e->inst[0] |= 0x80000000;
628 set_dst(pc, dst, e);
629 e->inst[0] |= (dst->rhw << 16);
630
631 if (mode & INTERP_FLAT) {
632 e->inst[0] |= (1 << 8);
633 } else {
634 if (mode & INTERP_PERSPECTIVE) {
635 e->inst[0] |= (1 << 25);
636 alloc_reg(pc, iv);
637 e->inst[0] |= (iv->hw << 9);
638 }
639
640 if (mode & INTERP_CENTROID)
641 e->inst[0] |= (1 << 24);
642 }
643
644 emit(pc, e);
645 }
646
647 static void
648 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
649 struct nv50_program_exec *e)
650 {
651 set_long(pc, e);
652
653 e->param.index = src->hw & 127;
654 e->param.shift = s;
655 e->param.mask = m << (s % 32);
656
657 if (src->hw > 127)
658 set_addr(e, alloc_addr(pc, src));
659 else
660 if (src->acc < 0) {
661 assert(src->type == P_CONST);
662 set_addr(e, pc->addr[src->index]);
663 }
664
665 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
666 }
667
668 static void
669 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
670 {
671 struct nv50_program_exec *e = exec(pc);
672
673 e->inst[0] = 0x10000000;
674 if (!pc->allow32)
675 set_long(pc, e);
676
677 set_dst(pc, dst, e);
678
679 if (!is_long(e) && src->type == P_IMMD) {
680 set_immd(pc, src, e);
681 /*XXX: 32-bit, but steals part of "half" reg space - need to
682 * catch and handle this case if/when we do half-regs
683 */
684 } else
685 if (src->type == P_IMMD || src->type == P_CONST) {
686 set_long(pc, e);
687 set_data(pc, src, 0x7f, 9, e);
688 e->inst[1] |= 0x20000000; /* mov from c[] */
689 } else {
690 if (src->type == P_ATTR) {
691 set_long(pc, e);
692 e->inst[1] |= 0x00200000;
693 }
694
695 alloc_reg(pc, src);
696 if (src->hw > 63)
697 set_long(pc, e);
698 e->inst[0] |= (src->hw << 9);
699 }
700
701 if (is_long(e) && !is_immd(e)) {
702 e->inst[1] |= 0x04000000; /* 32-bit */
703 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
704 if (!(e->inst[1] & 0x20000000))
705 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
706 } else
707 e->inst[0] |= 0x00008000;
708
709 emit(pc, e);
710 }
711
712 static INLINE void
713 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
714 {
715 struct nv50_reg *imm = alloc_immd(pc, f);
716 emit_mov(pc, dst, imm);
717 FREE(imm);
718 }
719
720 static void
721 emit_nop(struct nv50_pc *pc)
722 {
723 struct nv50_program_exec *e = exec(pc);
724
725 e->inst[0] = 0xf0000000;
726 set_long(pc, e);
727 e->inst[1] = 0xe0000000;
728 emit(pc, e);
729 }
730
731 static boolean
732 check_swap_src_0_1(struct nv50_pc *pc,
733 struct nv50_reg **s0, struct nv50_reg **s1)
734 {
735 struct nv50_reg *src0 = *s0, *src1 = *s1;
736
737 if (src0->type == P_CONST) {
738 if (src1->type != P_CONST) {
739 *s0 = src1;
740 *s1 = src0;
741 return TRUE;
742 }
743 } else
744 if (src1->type == P_ATTR) {
745 if (src0->type != P_ATTR) {
746 *s0 = src1;
747 *s1 = src0;
748 return TRUE;
749 }
750 }
751
752 return FALSE;
753 }
754
755 static void
756 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
757 struct nv50_program_exec *e)
758 {
759 struct nv50_reg *temp;
760
761 if (src->type != P_TEMP) {
762 temp = temp_temp(pc);
763 emit_mov(pc, temp, src);
764 src = temp;
765 }
766
767 alloc_reg(pc, src);
768 if (src->hw > 63)
769 set_long(pc, e);
770 e->inst[0] |= (src->hw << 9);
771 }
772
773 static void
774 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
775 {
776 if (src->type == P_ATTR) {
777 set_long(pc, e);
778 e->inst[1] |= 0x00200000;
779 } else
780 if (src->type == P_CONST || src->type == P_IMMD) {
781 struct nv50_reg *temp = temp_temp(pc);
782
783 emit_mov(pc, temp, src);
784 src = temp;
785 }
786
787 alloc_reg(pc, src);
788 if (src->hw > 63)
789 set_long(pc, e);
790 e->inst[0] |= (src->hw << 9);
791 }
792
793 static void
794 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
795 {
796 if (src->type == P_ATTR) {
797 struct nv50_reg *temp = temp_temp(pc);
798
799 emit_mov(pc, temp, src);
800 src = temp;
801 } else
802 if (src->type == P_CONST || src->type == P_IMMD) {
803 assert(!(e->inst[0] & 0x00800000));
804 if (e->inst[0] & 0x01000000) {
805 struct nv50_reg *temp = temp_temp(pc);
806
807 emit_mov(pc, temp, src);
808 src = temp;
809 } else {
810 set_data(pc, src, 0x7f, 16, e);
811 e->inst[0] |= 0x00800000;
812 }
813 }
814
815 alloc_reg(pc, src);
816 if (src->hw > 63)
817 set_long(pc, e);
818 e->inst[0] |= ((src->hw & 127) << 16);
819 }
820
821 static void
822 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
823 {
824 set_long(pc, e);
825
826 if (src->type == P_ATTR) {
827 struct nv50_reg *temp = temp_temp(pc);
828
829 emit_mov(pc, temp, src);
830 src = temp;
831 } else
832 if (src->type == P_CONST || src->type == P_IMMD) {
833 assert(!(e->inst[0] & 0x01000000));
834 if (e->inst[0] & 0x00800000) {
835 struct nv50_reg *temp = temp_temp(pc);
836
837 emit_mov(pc, temp, src);
838 src = temp;
839 } else {
840 set_data(pc, src, 0x7f, 32+14, e);
841 e->inst[0] |= 0x01000000;
842 }
843 }
844
845 alloc_reg(pc, src);
846 e->inst[1] |= ((src->hw & 127) << 14);
847 }
848
849 static void
850 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
851 {
852 struct nv50_program_exec *e = exec(pc);
853
854 assert(dst->type == P_TEMP);
855 e->inst[1] = 0x20000000 | (pred << 12);
856 set_long(pc, e);
857 set_dst(pc, dst, e);
858
859 emit(pc, e);
860 }
861
862 static void
863 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
864 {
865 struct nv50_program_exec *e = exec(pc);
866
867 e->inst[0] = 0x000001fc;
868 e->inst[1] = 0xa0000008;
869 set_long(pc, e);
870 set_pred_wr(pc, 1, pred, e);
871 set_src_0_restricted(pc, src, e);
872
873 emit(pc, e);
874 }
875
876 static void
877 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
878 struct nv50_reg *src1)
879 {
880 struct nv50_program_exec *e = exec(pc);
881
882 e->inst[0] |= 0xc0000000;
883
884 if (!pc->allow32)
885 set_long(pc, e);
886
887 check_swap_src_0_1(pc, &src0, &src1);
888 set_dst(pc, dst, e);
889 set_src_0(pc, src0, e);
890 if (src1->type == P_IMMD && !is_long(e)) {
891 if (src0->mod & NV50_MOD_NEG)
892 e->inst[0] |= 0x00008000;
893 set_immd(pc, src1, e);
894 } else {
895 set_src_1(pc, src1, e);
896 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
897 if (is_long(e))
898 e->inst[1] |= 0x08000000;
899 else
900 e->inst[0] |= 0x00008000;
901 }
902 }
903
904 emit(pc, e);
905 }
906
907 static void
908 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
909 struct nv50_reg *src0, struct nv50_reg *src1)
910 {
911 struct nv50_program_exec *e = exec(pc);
912
913 e->inst[0] = 0xb0000000;
914
915 alloc_reg(pc, src1);
916 check_swap_src_0_1(pc, &src0, &src1);
917
918 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
919 set_long(pc, e);
920 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
921 ((src1->mod & NV50_MOD_NEG) << 27);
922 }
923
924 set_dst(pc, dst, e);
925 set_src_0(pc, src0, e);
926 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
927 set_src_2(pc, src1, e);
928 else
929 if (src1->type == P_IMMD)
930 set_immd(pc, src1, e);
931 else
932 set_src_1(pc, src1, e);
933
934 emit(pc, e);
935 }
936
937 static void
938 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
939 uint8_t s)
940 {
941 struct nv50_program_exec *e = exec(pc);
942
943 set_long(pc, e);
944 e->inst[1] |= 0xc0000000;
945
946 e->inst[0] |= dst->hw << 2;
947 e->inst[0] |= s << 16; /* shift left */
948 set_src_0_restricted(pc, src, e);
949
950 emit(pc, e);
951 }
952
953 static void
954 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
955 struct nv50_reg *src0, struct nv50_reg *src1)
956 {
957 struct nv50_program_exec *e = exec(pc);
958
959 set_long(pc, e);
960 e->inst[0] |= 0xb0000000;
961 e->inst[1] |= (sub << 29);
962
963 check_swap_src_0_1(pc, &src0, &src1);
964 set_dst(pc, dst, e);
965 set_src_0(pc, src0, e);
966 set_src_1(pc, src1, e);
967
968 if (src0->mod & NV50_MOD_ABS)
969 e->inst[1] |= 0x00100000;
970 if (src1->mod & NV50_MOD_ABS)
971 e->inst[1] |= 0x00080000;
972
973 emit(pc, e);
974 }
975
976 static INLINE void
977 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
978 struct nv50_reg *src1)
979 {
980 src1->mod ^= NV50_MOD_NEG;
981 emit_add(pc, dst, src0, src1);
982 src1->mod ^= NV50_MOD_NEG;
983 }
984
985 static void
986 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
987 struct nv50_reg *src1, unsigned op)
988 {
989 struct nv50_program_exec *e = exec(pc);
990
991 e->inst[0] = 0xd0000000;
992 set_long(pc, e);
993
994 check_swap_src_0_1(pc, &src0, &src1);
995 set_dst(pc, dst, e);
996 set_src_0(pc, src0, e);
997
998 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
999 op != TGSI_OPCODE_XOR)
1000 assert(!"invalid bit op");
1001
1002 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1003 set_immd(pc, src1, e);
1004 if (op == TGSI_OPCODE_OR)
1005 e->inst[0] |= 0x0100;
1006 else
1007 if (op == TGSI_OPCODE_XOR)
1008 e->inst[0] |= 0x8000;
1009 } else {
1010 set_src_1(pc, src1, e);
1011 e->inst[1] |= 0x04000000; /* 32 bit */
1012 if (op == TGSI_OPCODE_OR)
1013 e->inst[1] |= 0x4000;
1014 else
1015 if (op == TGSI_OPCODE_XOR)
1016 e->inst[1] |= 0x8000;
1017 }
1018
1019 emit(pc, e);
1020 }
1021
1022 static void
1023 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1024 struct nv50_reg *src1, struct nv50_reg *src2)
1025 {
1026 struct nv50_program_exec *e = exec(pc);
1027
1028 e->inst[0] |= 0xe0000000;
1029
1030 check_swap_src_0_1(pc, &src0, &src1);
1031 set_dst(pc, dst, e);
1032 set_src_0(pc, src0, e);
1033 set_src_1(pc, src1, e);
1034 set_src_2(pc, src2, e);
1035
1036 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1037 e->inst[1] |= 0x04000000;
1038 if (src2->mod & NV50_MOD_NEG)
1039 e->inst[1] |= 0x08000000;
1040
1041 emit(pc, e);
1042 }
1043
1044 static INLINE void
1045 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1046 struct nv50_reg *src1, struct nv50_reg *src2)
1047 {
1048 src2->mod ^= NV50_MOD_NEG;
1049 emit_mad(pc, dst, src0, src1, src2);
1050 src2->mod ^= NV50_MOD_NEG;
1051 }
1052
1053 static void
1054 emit_flop(struct nv50_pc *pc, unsigned sub,
1055 struct nv50_reg *dst, struct nv50_reg *src)
1056 {
1057 struct nv50_program_exec *e = exec(pc);
1058
1059 e->inst[0] |= 0x90000000;
1060 if (sub) {
1061 set_long(pc, e);
1062 e->inst[1] |= (sub << 29);
1063 }
1064
1065 set_dst(pc, dst, e);
1066
1067 if (sub == 0 || sub == 2)
1068 set_src_0_restricted(pc, src, e);
1069 else
1070 set_src_0(pc, src, e);
1071
1072 emit(pc, e);
1073 }
1074
1075 static void
1076 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1077 {
1078 struct nv50_program_exec *e = exec(pc);
1079
1080 e->inst[0] |= 0xb0000000;
1081
1082 set_dst(pc, dst, e);
1083 set_src_0(pc, src, e);
1084 set_long(pc, e);
1085 e->inst[1] |= (6 << 29) | 0x00004000;
1086
1087 emit(pc, e);
1088 }
1089
1090 static void
1091 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1092 {
1093 struct nv50_program_exec *e = exec(pc);
1094
1095 e->inst[0] |= 0xb0000000;
1096
1097 set_dst(pc, dst, e);
1098 set_src_0(pc, src, e);
1099 set_long(pc, e);
1100 e->inst[1] |= (6 << 29);
1101
1102 emit(pc, e);
1103 }
1104
1105 #define CVTOP_RN 0x01
1106 #define CVTOP_FLOOR 0x03
1107 #define CVTOP_CEIL 0x05
1108 #define CVTOP_TRUNC 0x07
1109 #define CVTOP_SAT 0x08
1110 #define CVTOP_ABS 0x10
1111
1112 /* 0x04 == 32 bit dst */
1113 /* 0x40 == dst is float */
1114 /* 0x80 == src is float */
1115 #define CVT_F32_F32 0xc4
1116 #define CVT_F32_S32 0x44
1117 #define CVT_S32_F32 0x8c
1118 #define CVT_S32_S32 0x0c
1119 #define CVT_NEG 0x20
1120 #define CVT_RI 0x08
1121
1122 static void
1123 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1124 int wp, unsigned cvn, unsigned fmt)
1125 {
1126 struct nv50_program_exec *e;
1127
1128 e = exec(pc);
1129 set_long(pc, e);
1130
1131 e->inst[0] |= 0xa0000000;
1132 e->inst[1] |= 0x00004000; /* 32 bit src */
1133 e->inst[1] |= (cvn << 16);
1134 e->inst[1] |= (fmt << 24);
1135 set_src_0(pc, src, e);
1136
1137 if (wp >= 0)
1138 set_pred_wr(pc, 1, wp, e);
1139
1140 if (dst)
1141 set_dst(pc, dst, e);
1142 else {
1143 e->inst[0] |= 0x000001fc;
1144 e->inst[1] |= 0x00000008;
1145 }
1146
1147 emit(pc, e);
1148 }
1149
1150 /* nv50 Condition codes:
1151 * 0x1 = LT
1152 * 0x2 = EQ
1153 * 0x3 = LE
1154 * 0x4 = GT
1155 * 0x5 = NE
1156 * 0x6 = GE
1157 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1158 * 0x8 = unordered bit (allows NaN)
1159 */
1160 static void
1161 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1162 struct nv50_reg *src0, struct nv50_reg *src1)
1163 {
1164 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1165
1166 struct nv50_program_exec *e = exec(pc);
1167 struct nv50_reg *rdst;
1168
1169 assert(ccode < 16);
1170 if (check_swap_src_0_1(pc, &src0, &src1))
1171 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1172
1173 rdst = dst;
1174 if (dst && dst->type != P_TEMP)
1175 dst = alloc_temp(pc, NULL);
1176
1177 /* set.u32 */
1178 set_long(pc, e);
1179 e->inst[0] |= 0xb0000000;
1180 e->inst[1] |= 0x60000000 | (ccode << 14);
1181
1182 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1183 * that doesn't seem to match what the hw actually does
1184 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1185 */
1186
1187 if (wp >= 0)
1188 set_pred_wr(pc, 1, wp, e);
1189 if (dst)
1190 set_dst(pc, dst, e);
1191 else {
1192 e->inst[0] |= 0x000001fc;
1193 e->inst[1] |= 0x00000008;
1194 }
1195
1196 set_src_0(pc, src0, e);
1197 set_src_1(pc, src1, e);
1198
1199 emit(pc, e);
1200
1201 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1202 if (rdst)
1203 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
1204 if (rdst && rdst != dst)
1205 free_temp(pc, dst);
1206 }
1207
1208 static INLINE unsigned
1209 map_tgsi_setop_cc(unsigned op)
1210 {
1211 switch (op) {
1212 case TGSI_OPCODE_SLT: return 0x1;
1213 case TGSI_OPCODE_SGE: return 0x6;
1214 case TGSI_OPCODE_SEQ: return 0x2;
1215 case TGSI_OPCODE_SGT: return 0x4;
1216 case TGSI_OPCODE_SLE: return 0x3;
1217 case TGSI_OPCODE_SNE: return 0xd;
1218 default:
1219 assert(0);
1220 return 0;
1221 }
1222 }
1223
1224 static INLINE void
1225 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1226 {
1227 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
1228 }
1229
1230 static void
1231 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1232 struct nv50_reg *v, struct nv50_reg *e)
1233 {
1234 struct nv50_reg *temp = alloc_temp(pc, NULL);
1235
1236 emit_flop(pc, 3, temp, v);
1237 emit_mul(pc, temp, temp, e);
1238 emit_preex2(pc, temp, temp);
1239 emit_flop(pc, 6, dst, temp);
1240
1241 free_temp(pc, temp);
1242 }
1243
1244 static INLINE void
1245 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1246 {
1247 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
1248 }
1249
1250 static INLINE void
1251 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1252 {
1253 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
1254 }
1255
1256 static void
1257 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1258 struct nv50_reg **src)
1259 {
1260 struct nv50_reg *one = alloc_immd(pc, 1.0);
1261 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1262 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1263 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1264 struct nv50_reg *tmp[4];
1265 boolean allow32 = pc->allow32;
1266
1267 pc->allow32 = FALSE;
1268
1269 if (mask & (3 << 1)) {
1270 tmp[0] = alloc_temp(pc, NULL);
1271 emit_minmax(pc, 4, tmp[0], src[0], zero);
1272 }
1273
1274 if (mask & (1 << 2)) {
1275 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1276
1277 tmp[1] = temp_temp(pc);
1278 emit_minmax(pc, 4, tmp[1], src[1], zero);
1279
1280 tmp[3] = temp_temp(pc);
1281 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1282 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1283
1284 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1285 emit_mov(pc, dst[2], zero);
1286 set_pred(pc, 3, 0, pc->p->exec_tail);
1287 }
1288
1289 if (mask & (1 << 1))
1290 assimilate_temp(pc, dst[1], tmp[0]);
1291 else
1292 if (mask & (1 << 2))
1293 free_temp(pc, tmp[0]);
1294
1295 pc->allow32 = allow32;
1296
1297 /* do this last, in case src[i,j] == dst[0,3] */
1298 if (mask & (1 << 0))
1299 emit_mov(pc, dst[0], one);
1300
1301 if (mask & (1 << 3))
1302 emit_mov(pc, dst[3], one);
1303
1304 FREE(pos128);
1305 FREE(neg128);
1306 FREE(zero);
1307 FREE(one);
1308 }
1309
1310 static INLINE void
1311 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1312 {
1313 emit_cvt(pc, dst, src, -1, CVTOP_RN, CVT_F32_F32 | CVT_NEG);
1314 }
1315
1316 static void
1317 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1318 {
1319 struct nv50_program_exec *e;
1320 const int r_pred = 1;
1321
1322 e = exec(pc);
1323 e->inst[0] = 0x00000002; /* discard */
1324 set_long(pc, e); /* sets cond code to ALWAYS */
1325
1326 if (src) {
1327 unsigned cvn = CVT_F32_F32;
1328
1329 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1330
1331 if (src->mod & NV50_MOD_NEG)
1332 cvn |= CVT_NEG;
1333 /* write predicate reg */
1334 emit_cvt(pc, NULL, src, r_pred, CVTOP_RN, cvn);
1335 }
1336
1337 emit(pc, e);
1338 }
1339
1340 static struct nv50_program_exec *
1341 emit_breakaddr(struct nv50_pc *pc)
1342 {
1343 struct nv50_program_exec *e = exec(pc);
1344
1345 e->inst[0] = 0x40000002;
1346 set_long(pc, e);
1347
1348 emit(pc, e);
1349 return e;
1350 }
1351
1352 static void
1353 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1354 {
1355 struct nv50_program_exec *e = exec(pc);
1356
1357 e->inst[0] = 0x50000002;
1358 set_long(pc, e);
1359 if (pred >= 0)
1360 set_pred(pc, cc, pred, e);
1361
1362 emit(pc, e);
1363 }
1364
1365 static struct nv50_program_exec *
1366 emit_joinat(struct nv50_pc *pc)
1367 {
1368 struct nv50_program_exec *e = exec(pc);
1369
1370 e->inst[0] = 0xa0000002;
1371 set_long(pc, e);
1372
1373 emit(pc, e);
1374 return e;
1375 }
1376
1377 static struct nv50_program_exec *
1378 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1379 {
1380 struct nv50_program_exec *e = exec(pc);
1381
1382 e->inst[0] = 0x10000002;
1383 set_long(pc, e);
1384 if (pred >= 0)
1385 set_pred(pc, cc, pred, e);
1386 emit(pc, e);
1387 return pc->p->exec_tail;
1388 }
1389
1390 static void
1391 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1392 {
1393 struct nv50_program_exec *e = exec(pc);
1394
1395 e->inst[0] = 0x30000002;
1396 set_long(pc, e);
1397 if (pred >= 0)
1398 set_pred(pc, cc, pred, e);
1399
1400 emit(pc, e);
1401 }
1402
1403 #define QOP_ADD 0
1404 #define QOP_SUBR 1
1405 #define QOP_SUB 2
1406 #define QOP_MOV_SRC1 3
1407
1408 /* For a quad of threads / top left, top right, bottom left, bottom right
1409 * pixels, do a different operation, and take src0 from a specific thread.
1410 */
1411 static void
1412 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1413 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1414 {
1415 struct nv50_program_exec *e = exec(pc);
1416
1417 e->inst[0] = 0xc0000000;
1418 e->inst[1] = 0x80000000;
1419 set_long(pc, e);
1420 e->inst[0] |= lane_src0 << 16;
1421 set_src_0(pc, src0, e);
1422 set_src_2(pc, src1, e);
1423
1424 if (wp >= 0)
1425 set_pred_wr(pc, 1, wp, e);
1426
1427 if (dst)
1428 set_dst(pc, dst, e);
1429 else {
1430 e->inst[0] |= 0x000001fc;
1431 e->inst[1] |= 0x00000008;
1432 }
1433
1434 e->inst[0] |= (qop & 3) << 20;
1435 e->inst[1] |= (qop >> 2) << 22;
1436
1437 emit(pc, e);
1438 }
1439
1440 static void
1441 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1442 struct nv50_reg **src, unsigned arg, boolean proj)
1443 {
1444 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1445
1446 src[0]->mod |= NV50_MOD_ABS;
1447 src[1]->mod |= NV50_MOD_ABS;
1448 src[2]->mod |= NV50_MOD_ABS;
1449
1450 emit_minmax(pc, 4, t[2], src[0], src[1]);
1451 emit_minmax(pc, 4, t[2], src[2], t[2]);
1452
1453 src[0]->mod = mod[0];
1454 src[1]->mod = mod[1];
1455 src[2]->mod = mod[2];
1456
1457 if (proj && 0 /* looks more correct without this */)
1458 emit_mul(pc, t[2], t[2], src[3]);
1459 else
1460 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1461 emit_mov(pc, t[3], src[3]);
1462
1463 emit_flop(pc, 0, t[2], t[2]);
1464
1465 emit_mul(pc, t[0], src[0], t[2]);
1466 emit_mul(pc, t[1], src[1], t[2]);
1467 emit_mul(pc, t[2], src[2], t[2]);
1468 }
1469
1470 static void
1471 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1472 struct nv50_reg **src, unsigned dim, unsigned arg)
1473 {
1474 unsigned c, mode;
1475
1476 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1477 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1478
1479 t[3]->rhw = src[3]->rhw;
1480 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1481 emit_flop(pc, 0, t[3], t[3]);
1482
1483 for (c = 0; c < dim; ++c) {
1484 t[c]->rhw = src[c]->rhw;
1485 emit_interp(pc, t[c], t[3], mode);
1486 }
1487 if (arg != dim) { /* depth reference value */
1488 t[dim]->rhw = src[2]->rhw;
1489 emit_interp(pc, t[dim], t[3], mode);
1490 }
1491 } else {
1492 /* XXX: for some reason the blob sometimes uses MAD
1493 * (mad f32 $rX $rY $rZ neg $r63)
1494 */
1495 emit_flop(pc, 0, t[3], src[3]);
1496 for (c = 0; c < dim; ++c)
1497 emit_mul(pc, t[c], src[c], t[3]);
1498 if (arg != dim) /* depth reference value */
1499 emit_mul(pc, t[dim], src[2], t[3]);
1500 }
1501 }
1502
1503 static INLINE void
1504 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1505 {
1506 switch (type) {
1507 case TGSI_TEXTURE_1D:
1508 *arg = *dim = 1;
1509 break;
1510 case TGSI_TEXTURE_SHADOW1D:
1511 *dim = 1;
1512 *arg = 2;
1513 break;
1514 case TGSI_TEXTURE_UNKNOWN:
1515 case TGSI_TEXTURE_2D:
1516 case TGSI_TEXTURE_RECT:
1517 *arg = *dim = 2;
1518 break;
1519 case TGSI_TEXTURE_SHADOW2D:
1520 case TGSI_TEXTURE_SHADOWRECT:
1521 *dim = 2;
1522 *arg = 3;
1523 break;
1524 case TGSI_TEXTURE_3D:
1525 case TGSI_TEXTURE_CUBE:
1526 *dim = *arg = 3;
1527 break;
1528 default:
1529 assert(0);
1530 break;
1531 }
1532 }
1533
1534 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1535 * different LOD values, so branch off groups of equal LOD.
1536 */
1537 static void
1538 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1539 struct nv50_reg *src, struct nv50_program_exec *tex)
1540 {
1541 struct nv50_program_exec *join_at;
1542 unsigned i, target = pc->p->exec_size + 7 * 2;
1543
1544 /* Subtract lod of each pixel from lod of top left pixel, jump
1545 * texlod insn if result is 0, then repeat for 2 other pixels.
1546 */
1547 join_at = emit_joinat(pc);
1548 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1549 emit_branch(pc, 0, 2)->param.index = target;
1550
1551 for (i = 1; i < 4; ++i) {
1552 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1553 emit_branch(pc, 0, 2)->param.index = target;
1554 }
1555
1556 emit_mov(pc, tlod, src); /* target */
1557 emit(pc, tex); /* texlod */
1558
1559 join_at->param.index = target + 2 * 2;
1560 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1561 }
1562
1563 static void
1564 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1565 struct nv50_program_exec *tex)
1566 {
1567 struct nv50_program_exec *e;
1568 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1569 int r_pred = 0;
1570 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1571
1572 pc->allow32 = FALSE;
1573 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1574
1575 /* Subtract bias value of thread i from bias values of each thread,
1576 * store result in r_pred, and set bit i in r_bits if result was 0.
1577 */
1578 assert(arg < 4);
1579 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1580 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1581 emit_mov(pc, r_bits, &imm_1248);
1582 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1583 }
1584 emit_mov_to_pred(pc, r_pred, r_bits);
1585
1586 /* The lanes of a quad are now grouped by the bit in r_pred they have
1587 * set. Put the input values for TEX into a new register set for each
1588 * group and execute TEX only for a specific group.
1589 * We cannot use the same register set for each group because we need
1590 * the derivatives, which are implicitly calculated, to be correct.
1591 */
1592 for (i = 1; i < 4; ++i) {
1593 alloc_temp4(pc, t123[i], 0);
1594
1595 for (c = 0; c <= arg; ++c)
1596 emit_mov(pc, t123[i][c], t[c]);
1597
1598 *(e = exec(pc)) = *(tex);
1599 e->inst[0] &= ~0x01fc;
1600 set_dst(pc, t123[i][0], e);
1601 set_pred(pc, cc[i], r_pred, e);
1602 emit(pc, e);
1603 }
1604 /* finally TEX on the original regs (where we kept the input) */
1605 set_pred(pc, cc[0], r_pred, tex);
1606 emit(pc, tex);
1607
1608 /* put the 3 * n other results into regs for lane 0 */
1609 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1610 for (i = 1; i < 4; ++i) {
1611 for (c = 0; c < n; ++c) {
1612 emit_mov(pc, t[c], t123[i][c]);
1613 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1614 }
1615 free_temp4(pc, t123[i]);
1616 }
1617
1618 emit_nop(pc);
1619 free_temp(pc, r_bits);
1620 }
1621
1622 static void
1623 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1624 struct nv50_reg **src, unsigned unit, unsigned type,
1625 boolean proj, int bias_lod)
1626 {
1627 struct nv50_reg *t[4];
1628 struct nv50_program_exec *e;
1629 unsigned c, dim, arg;
1630
1631 /* t[i] must be within a single 128 bit super-reg */
1632 alloc_temp4(pc, t, 0);
1633
1634 e = exec(pc);
1635 e->inst[0] = 0xf0000000;
1636 set_long(pc, e);
1637 set_dst(pc, t[0], e);
1638
1639 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1640 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1641
1642 /* live flag (don't set if TEX results affect input to another TEX): */
1643 /* e->inst[0] |= 0x00000004; */
1644
1645 get_tex_dim(type, &dim, &arg);
1646
1647 if (type == TGSI_TEXTURE_CUBE) {
1648 e->inst[0] |= 0x08000000;
1649 load_cube_tex_coords(pc, t, src, arg, proj);
1650 } else
1651 if (proj)
1652 load_proj_tex_coords(pc, t, src, dim, arg);
1653 else {
1654 for (c = 0; c < dim; c++)
1655 emit_mov(pc, t[c], src[c]);
1656 if (arg != dim) /* depth reference value (always src.z here) */
1657 emit_mov(pc, t[dim], src[2]);
1658 }
1659
1660 e->inst[0] |= (mask & 0x3) << 25;
1661 e->inst[1] |= (mask & 0xc) << 12;
1662
1663 if (!bias_lod) {
1664 e->inst[0] |= (arg - 1) << 22;
1665 emit(pc, e);
1666 } else
1667 if (bias_lod < 0) {
1668 e->inst[0] |= arg << 22;
1669 e->inst[1] |= 0x20000000; /* texbias */
1670 emit_mov(pc, t[arg], src[3]);
1671 emit_texbias_sequence(pc, t, arg, e);
1672 } else {
1673 e->inst[0] |= arg << 22;
1674 e->inst[1] |= 0x40000000; /* texlod */
1675 emit_mov(pc, t[arg], src[3]);
1676 emit_texlod_sequence(pc, t[arg], src[3], e);
1677 }
1678
1679 #if 1
1680 c = 0;
1681 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1682 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1683 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1684 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1685
1686 free_temp4(pc, t);
1687 #else
1688 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1689 * the texture coordinates, not the fetched values: latency ? */
1690
1691 for (c = 0; c < 4; c++) {
1692 if (mask & (1 << c))
1693 assimilate_temp(pc, dst[c], t[c]);
1694 else
1695 free_temp(pc, t[c]);
1696 }
1697 #endif
1698 }
1699
1700 static void
1701 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1702 {
1703 struct nv50_program_exec *e = exec(pc);
1704
1705 assert(src->type == P_TEMP);
1706
1707 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
1708 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
1709 set_long(pc, e);
1710 set_dst(pc, dst, e);
1711 set_src_0(pc, src, e);
1712 set_src_2(pc, src, e);
1713
1714 emit(pc, e);
1715 }
1716
1717 static void
1718 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1719 {
1720 struct nv50_program_exec *e = exec(pc);
1721
1722 assert(src->type == P_TEMP);
1723
1724 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
1725 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
1726 set_long(pc, e);
1727 set_dst(pc, dst, e);
1728 set_src_0(pc, src, e);
1729 set_src_2(pc, src, e);
1730
1731 emit(pc, e);
1732 }
1733
1734 static void
1735 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1736 {
1737 unsigned q = 0, m = ~0;
1738
1739 assert(!is_long(e));
1740
1741 switch (e->inst[0] >> 28) {
1742 case 0x1:
1743 /* MOV */
1744 q = 0x0403c000;
1745 m = 0xffff7fff;
1746 break;
1747 case 0x8:
1748 /* INTERP (move centroid, perspective and flat bits) */
1749 m = ~0x03000100;
1750 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1751 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1752 break;
1753 case 0x9:
1754 /* RCP */
1755 break;
1756 case 0xB:
1757 /* ADD */
1758 m = ~(127 << 16);
1759 q = ((e->inst[0] & (~m)) >> 2);
1760 break;
1761 case 0xC:
1762 /* MUL */
1763 m = ~0x00008000;
1764 q = ((e->inst[0] & (~m)) << 12);
1765 break;
1766 case 0xE:
1767 /* MAD (if src2 == dst) */
1768 q = ((e->inst[0] & 0x1fc) << 12);
1769 break;
1770 default:
1771 assert(0);
1772 break;
1773 }
1774
1775 set_long(pc, e);
1776 pc->p->exec_size++;
1777
1778 e->inst[0] &= m;
1779 e->inst[1] |= q;
1780 }
1781
1782 /* Some operations support an optional negation flag. */
1783 static boolean
1784 negate_supported(const struct tgsi_full_instruction *insn, int i)
1785 {
1786 switch (insn->Instruction.Opcode) {
1787 case TGSI_OPCODE_DDX:
1788 case TGSI_OPCODE_DDY:
1789 case TGSI_OPCODE_DP3:
1790 case TGSI_OPCODE_DP4:
1791 case TGSI_OPCODE_MUL:
1792 case TGSI_OPCODE_KIL:
1793 case TGSI_OPCODE_ADD:
1794 case TGSI_OPCODE_SUB:
1795 case TGSI_OPCODE_MAD:
1796 return TRUE;
1797 case TGSI_OPCODE_POW:
1798 if (i == 1)
1799 return TRUE;
1800 return FALSE;
1801 default:
1802 return FALSE;
1803 }
1804 }
1805
1806 /* Return a read mask for source registers deduced from opcode & write mask. */
1807 static unsigned
1808 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1809 {
1810 unsigned x, mask = insn->Dst[0].Register.WriteMask;
1811
1812 switch (insn->Instruction.Opcode) {
1813 case TGSI_OPCODE_COS:
1814 case TGSI_OPCODE_SIN:
1815 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1816 case TGSI_OPCODE_DP3:
1817 return 0x7;
1818 case TGSI_OPCODE_DP4:
1819 case TGSI_OPCODE_DPH:
1820 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1821 return 0xf;
1822 case TGSI_OPCODE_DST:
1823 return mask & (c ? 0xa : 0x6);
1824 case TGSI_OPCODE_EX2:
1825 case TGSI_OPCODE_LG2:
1826 case TGSI_OPCODE_POW:
1827 case TGSI_OPCODE_RCP:
1828 case TGSI_OPCODE_RSQ:
1829 case TGSI_OPCODE_SCS:
1830 return 0x1;
1831 case TGSI_OPCODE_IF:
1832 return 0x1;
1833 case TGSI_OPCODE_LIT:
1834 return 0xb;
1835 case TGSI_OPCODE_TEX:
1836 case TGSI_OPCODE_TXB:
1837 case TGSI_OPCODE_TXL:
1838 case TGSI_OPCODE_TXP:
1839 {
1840 const struct tgsi_instruction_texture *tex;
1841
1842 assert(insn->Instruction.Texture);
1843 tex = &insn->Texture;
1844
1845 mask = 0x7;
1846 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
1847 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
1848 mask |= 0x8; /* bias, lod or proj */
1849
1850 switch (tex->Texture) {
1851 case TGSI_TEXTURE_1D:
1852 mask &= 0x9;
1853 break;
1854 case TGSI_TEXTURE_SHADOW1D:
1855 mask &= 0x5;
1856 break;
1857 case TGSI_TEXTURE_2D:
1858 mask &= 0xb;
1859 break;
1860 default:
1861 break;
1862 }
1863 }
1864 return mask;
1865 case TGSI_OPCODE_XPD:
1866 x = 0;
1867 if (mask & 1) x |= 0x6;
1868 if (mask & 2) x |= 0x5;
1869 if (mask & 4) x |= 0x3;
1870 return x;
1871 default:
1872 break;
1873 }
1874
1875 return mask;
1876 }
1877
1878 static struct nv50_reg *
1879 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1880 {
1881 switch (dst->Register.File) {
1882 case TGSI_FILE_TEMPORARY:
1883 return &pc->temp[dst->Register.Index * 4 + c];
1884 case TGSI_FILE_OUTPUT:
1885 return &pc->result[dst->Register.Index * 4 + c];
1886 case TGSI_FILE_ADDRESS:
1887 {
1888 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
1889 if (!r) {
1890 r = alloc_addr(pc, NULL);
1891 pc->addr[dst->Register.Index * 4 + c] = r;
1892 }
1893 assert(r);
1894 return r;
1895 }
1896 case TGSI_FILE_NULL:
1897 return NULL;
1898 default:
1899 break;
1900 }
1901
1902 return NULL;
1903 }
1904
1905 static struct nv50_reg *
1906 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1907 boolean neg)
1908 {
1909 struct nv50_reg *r = NULL;
1910 struct nv50_reg *temp;
1911 unsigned sgn, c, swz;
1912
1913 if (src->Register.File != TGSI_FILE_CONSTANT)
1914 assert(!src->Register.Indirect);
1915
1916 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1917
1918 c = tgsi_util_get_full_src_register_swizzle(src, chan);
1919 switch (c) {
1920 case TGSI_SWIZZLE_X:
1921 case TGSI_SWIZZLE_Y:
1922 case TGSI_SWIZZLE_Z:
1923 case TGSI_SWIZZLE_W:
1924 switch (src->Register.File) {
1925 case TGSI_FILE_INPUT:
1926 r = &pc->attr[src->Register.Index * 4 + c];
1927 break;
1928 case TGSI_FILE_TEMPORARY:
1929 r = &pc->temp[src->Register.Index * 4 + c];
1930 break;
1931 case TGSI_FILE_CONSTANT:
1932 if (!src->Register.Indirect) {
1933 r = &pc->param[src->Register.Index * 4 + c];
1934 break;
1935 }
1936 /* Indicate indirection by setting r->acc < 0 and
1937 * use the index field to select the address reg.
1938 */
1939 r = reg_instance(pc, NULL);
1940 swz = tgsi_util_get_src_register_swizzle(
1941 &src->Indirect, 0);
1942 ctor_reg(r, P_CONST,
1943 src->Indirect.Index * 4 + swz,
1944 src->Register.Index * 4 + c);
1945 r->acc = -1;
1946 break;
1947 case TGSI_FILE_IMMEDIATE:
1948 r = &pc->immd[src->Register.Index * 4 + c];
1949 break;
1950 case TGSI_FILE_SAMPLER:
1951 break;
1952 case TGSI_FILE_ADDRESS:
1953 r = pc->addr[src->Register.Index * 4 + c];
1954 assert(r);
1955 break;
1956 default:
1957 assert(0);
1958 break;
1959 }
1960 break;
1961 default:
1962 assert(0);
1963 break;
1964 }
1965
1966 switch (sgn) {
1967 case TGSI_UTIL_SIGN_KEEP:
1968 break;
1969 case TGSI_UTIL_SIGN_CLEAR:
1970 temp = temp_temp(pc);
1971 emit_abs(pc, temp, r);
1972 r = temp;
1973 break;
1974 case TGSI_UTIL_SIGN_TOGGLE:
1975 if (neg)
1976 r->mod = NV50_MOD_NEG;
1977 else {
1978 temp = temp_temp(pc);
1979 emit_neg(pc, temp, r);
1980 r = temp;
1981 }
1982 break;
1983 case TGSI_UTIL_SIGN_SET:
1984 temp = temp_temp(pc);
1985 emit_cvt(pc, temp, r, -1, CVTOP_ABS, CVT_F32_F32 | CVT_NEG);
1986 r = temp;
1987 break;
1988 default:
1989 assert(0);
1990 break;
1991 }
1992
1993 if (r && r->acc >= 0 && r != temp)
1994 return reg_instance(pc, r);
1995 return r;
1996 }
1997
1998 /* return TRUE for ops that produce only a single result */
1999 static boolean
2000 is_scalar_op(unsigned op)
2001 {
2002 switch (op) {
2003 case TGSI_OPCODE_COS:
2004 case TGSI_OPCODE_DP2:
2005 case TGSI_OPCODE_DP3:
2006 case TGSI_OPCODE_DP4:
2007 case TGSI_OPCODE_DPH:
2008 case TGSI_OPCODE_EX2:
2009 case TGSI_OPCODE_LG2:
2010 case TGSI_OPCODE_POW:
2011 case TGSI_OPCODE_RCP:
2012 case TGSI_OPCODE_RSQ:
2013 case TGSI_OPCODE_SIN:
2014 /*
2015 case TGSI_OPCODE_KIL:
2016 case TGSI_OPCODE_LIT:
2017 case TGSI_OPCODE_SCS:
2018 */
2019 return TRUE;
2020 default:
2021 return FALSE;
2022 }
2023 }
2024
2025 /* Returns a bitmask indicating which dst components depend
2026 * on source s, component c (reverse of nv50_tgsi_src_mask).
2027 */
2028 static unsigned
2029 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2030 {
2031 if (is_scalar_op(op))
2032 return 0x1;
2033
2034 switch (op) {
2035 case TGSI_OPCODE_DST:
2036 return (1 << c) & (s ? 0xa : 0x6);
2037 case TGSI_OPCODE_XPD:
2038 switch (c) {
2039 case 0: return 0x6;
2040 case 1: return 0x5;
2041 case 2: return 0x3;
2042 case 3: return 0x0;
2043 default:
2044 assert(0);
2045 return 0x0;
2046 }
2047 case TGSI_OPCODE_LIT:
2048 case TGSI_OPCODE_SCS:
2049 case TGSI_OPCODE_TEX:
2050 case TGSI_OPCODE_TXB:
2051 case TGSI_OPCODE_TXL:
2052 case TGSI_OPCODE_TXP:
2053 /* these take care of dangerous swizzles themselves */
2054 return 0x0;
2055 case TGSI_OPCODE_IF:
2056 case TGSI_OPCODE_KIL:
2057 /* don't call this function for these ops */
2058 assert(0);
2059 return 0;
2060 default:
2061 /* linear vector instruction */
2062 return (1 << c);
2063 }
2064 }
2065
2066 static INLINE boolean
2067 has_pred(struct nv50_program_exec *e, unsigned cc)
2068 {
2069 if (!is_long(e) || is_immd(e))
2070 return FALSE;
2071 return ((e->inst[1] & 0x780) == (cc << 7));
2072 }
2073
2074 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2075 * join_at ENDIF
2076 * @p0.eq bra ENDIF
2077 * single_op
2078 * ENDIF: nop.join
2079 */
2080 static boolean
2081 nv50_kill_branch(struct nv50_pc *pc)
2082 {
2083 int lvl = pc->if_lvl;
2084
2085 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2086 return FALSE;
2087
2088 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2089 * reg may no longer be valid, since we currently always use $p0
2090 */
2091 if (has_pred(pc->if_insn[lvl], 0xf))
2092 return FALSE;
2093 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2094
2095 /* We'll use the exec allocated for JOIN_AT (we can't easily
2096 * access nv50_program_exec's prev).
2097 */
2098 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2099
2100 *pc->if_join[lvl] = *pc->p->exec_tail;
2101
2102 FREE(pc->if_insn[lvl]);
2103 FREE(pc->p->exec_tail);
2104
2105 pc->p->exec_tail = pc->if_join[lvl];
2106 pc->p->exec_tail->next = NULL;
2107 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2108
2109 return TRUE;
2110 }
2111
2112 static void
2113 nv50_fp_move_results(struct nv50_pc *pc)
2114 {
2115 struct nv50_reg reg;
2116 unsigned i;
2117
2118 ctor_reg(&reg, P_TEMP, -1, -1);
2119
2120 for (i = 0; i < pc->result_nr * 4; ++i) {
2121 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2122 continue;
2123 if (pc->result[i].rhw != pc->result[i].hw) {
2124 reg.hw = pc->result[i].rhw;
2125 emit_mov(pc, &reg, &pc->result[i]);
2126 }
2127 }
2128 }
2129
2130 static boolean
2131 nv50_program_tx_insn(struct nv50_pc *pc,
2132 const struct tgsi_full_instruction *inst)
2133 {
2134 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2135 unsigned mask, sat, unit;
2136 int i, c;
2137
2138 mask = inst->Dst[0].Register.WriteMask;
2139 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2140
2141 memset(src, 0, sizeof(src));
2142
2143 for (c = 0; c < 4; c++) {
2144 if ((mask & (1 << c)) && !pc->r_dst[c])
2145 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2146 else
2147 dst[c] = pc->r_dst[c];
2148 rdst[c] = dst[c];
2149 }
2150
2151 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2152 const struct tgsi_full_src_register *fs = &inst->Src[i];
2153 unsigned src_mask;
2154 boolean neg_supp;
2155
2156 src_mask = nv50_tgsi_src_mask(inst, i);
2157 neg_supp = negate_supported(inst, i);
2158
2159 if (fs->Register.File == TGSI_FILE_SAMPLER)
2160 unit = fs->Register.Index;
2161
2162 for (c = 0; c < 4; c++)
2163 if (src_mask & (1 << c))
2164 src[i][c] = tgsi_src(pc, c, fs, neg_supp);
2165 }
2166
2167 brdc = temp = pc->r_brdc;
2168 if (brdc && brdc->type != P_TEMP) {
2169 temp = temp_temp(pc);
2170 if (sat)
2171 brdc = temp;
2172 } else
2173 if (sat) {
2174 for (c = 0; c < 4; c++) {
2175 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2176 continue;
2177 /* rdst[c] = dst[c]; */ /* done above */
2178 dst[c] = temp_temp(pc);
2179 }
2180 }
2181
2182 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2183
2184 switch (inst->Instruction.Opcode) {
2185 case TGSI_OPCODE_ABS:
2186 for (c = 0; c < 4; c++) {
2187 if (!(mask & (1 << c)))
2188 continue;
2189 emit_abs(pc, dst[c], src[0][c]);
2190 }
2191 break;
2192 case TGSI_OPCODE_ADD:
2193 for (c = 0; c < 4; c++) {
2194 if (!(mask & (1 << c)))
2195 continue;
2196 emit_add(pc, dst[c], src[0][c], src[1][c]);
2197 }
2198 break;
2199 case TGSI_OPCODE_AND:
2200 case TGSI_OPCODE_XOR:
2201 case TGSI_OPCODE_OR:
2202 for (c = 0; c < 4; c++) {
2203 if (!(mask & (1 << c)))
2204 continue;
2205 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2206 inst->Instruction.Opcode);
2207 }
2208 break;
2209 case TGSI_OPCODE_ARL:
2210 assert(src[0][0]);
2211 temp = temp_temp(pc);
2212 emit_cvt(pc, temp, src[0][0], -1, CVTOP_FLOOR, CVT_S32_F32);
2213 emit_arl(pc, dst[0], temp, 4);
2214 break;
2215 case TGSI_OPCODE_BGNLOOP:
2216 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2217 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2218 terminate_mbb(pc);
2219 break;
2220 case TGSI_OPCODE_BRK:
2221 assert(pc->loop_lvl > 0);
2222 emit_break(pc, -1, 0);
2223 break;
2224 case TGSI_OPCODE_CEIL:
2225 for (c = 0; c < 4; c++) {
2226 if (!(mask & (1 << c)))
2227 continue;
2228 emit_cvt(pc, dst[c], src[0][c], -1,
2229 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
2230 }
2231 break;
2232 case TGSI_OPCODE_CMP:
2233 pc->allow32 = FALSE;
2234 for (c = 0; c < 4; c++) {
2235 if (!(mask & (1 << c)))
2236 continue;
2237 emit_cvt(pc, NULL, src[0][c], 1, CVTOP_RN, CVT_F32_F32);
2238 emit_mov(pc, dst[c], src[1][c]);
2239 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2240 emit_mov(pc, dst[c], src[2][c]);
2241 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2242 }
2243 break;
2244 case TGSI_OPCODE_CONT:
2245 assert(pc->loop_lvl > 0);
2246 emit_branch(pc, -1, 0)->param.index =
2247 pc->loop_pos[pc->loop_lvl - 1];
2248 break;
2249 case TGSI_OPCODE_COS:
2250 if (mask & 8) {
2251 emit_precossin(pc, temp, src[0][3]);
2252 emit_flop(pc, 5, dst[3], temp);
2253 if (!(mask &= 7))
2254 break;
2255 if (temp == dst[3])
2256 temp = brdc = temp_temp(pc);
2257 }
2258 emit_precossin(pc, temp, src[0][0]);
2259 emit_flop(pc, 5, brdc, temp);
2260 break;
2261 case TGSI_OPCODE_DDX:
2262 for (c = 0; c < 4; c++) {
2263 if (!(mask & (1 << c)))
2264 continue;
2265 emit_ddx(pc, dst[c], src[0][c]);
2266 }
2267 break;
2268 case TGSI_OPCODE_DDY:
2269 for (c = 0; c < 4; c++) {
2270 if (!(mask & (1 << c)))
2271 continue;
2272 emit_ddy(pc, dst[c], src[0][c]);
2273 }
2274 break;
2275 case TGSI_OPCODE_DP3:
2276 emit_mul(pc, temp, src[0][0], src[1][0]);
2277 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2278 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2279 break;
2280 case TGSI_OPCODE_DP4:
2281 emit_mul(pc, temp, src[0][0], src[1][0]);
2282 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2283 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2284 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2285 break;
2286 case TGSI_OPCODE_DPH:
2287 emit_mul(pc, temp, src[0][0], src[1][0]);
2288 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2289 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2290 emit_add(pc, brdc, src[1][3], temp);
2291 break;
2292 case TGSI_OPCODE_DST:
2293 if (mask & (1 << 1))
2294 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2295 if (mask & (1 << 2))
2296 emit_mov(pc, dst[2], src[0][2]);
2297 if (mask & (1 << 3))
2298 emit_mov(pc, dst[3], src[1][3]);
2299 if (mask & (1 << 0))
2300 emit_mov_immdval(pc, dst[0], 1.0f);
2301 break;
2302 case TGSI_OPCODE_ELSE:
2303 emit_branch(pc, -1, 0);
2304 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2305 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2306 terminate_mbb(pc);
2307 break;
2308 case TGSI_OPCODE_ENDIF:
2309 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2310
2311 /* try to replace branch over 1 insn with a predicated insn */
2312 if (nv50_kill_branch(pc) == TRUE)
2313 break;
2314
2315 if (pc->if_join[pc->if_lvl]) {
2316 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2317 pc->if_join[pc->if_lvl] = NULL;
2318 }
2319 terminate_mbb(pc);
2320 /* emit a NOP as join point, we could set it on the next
2321 * one, but would have to make sure it is long and !immd
2322 */
2323 JOIN_ON(emit_nop(pc));
2324 break;
2325 case TGSI_OPCODE_ENDLOOP:
2326 emit_branch(pc, -1, 0)->param.index =
2327 pc->loop_pos[--pc->loop_lvl];
2328 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2329 terminate_mbb(pc);
2330 break;
2331 case TGSI_OPCODE_EX2:
2332 emit_preex2(pc, temp, src[0][0]);
2333 emit_flop(pc, 6, brdc, temp);
2334 break;
2335 case TGSI_OPCODE_FLR:
2336 for (c = 0; c < 4; c++) {
2337 if (!(mask & (1 << c)))
2338 continue;
2339 emit_flr(pc, dst[c], src[0][c]);
2340 }
2341 break;
2342 case TGSI_OPCODE_FRC:
2343 temp = temp_temp(pc);
2344 for (c = 0; c < 4; c++) {
2345 if (!(mask & (1 << c)))
2346 continue;
2347 emit_flr(pc, temp, src[0][c]);
2348 emit_sub(pc, dst[c], src[0][c], temp);
2349 }
2350 break;
2351 case TGSI_OPCODE_IF:
2352 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2353 emit_cvt(pc, NULL, src[0][0], 0, CVTOP_ABS | CVTOP_RN,
2354 CVT_F32_F32);
2355 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2356 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2357 terminate_mbb(pc);
2358 break;
2359 case TGSI_OPCODE_KIL:
2360 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2361 emit_kil(pc, src[0][0]);
2362 emit_kil(pc, src[0][1]);
2363 emit_kil(pc, src[0][2]);
2364 emit_kil(pc, src[0][3]);
2365 break;
2366 case TGSI_OPCODE_KILP:
2367 emit_kil(pc, NULL);
2368 break;
2369 case TGSI_OPCODE_LIT:
2370 emit_lit(pc, &dst[0], mask, &src[0][0]);
2371 break;
2372 case TGSI_OPCODE_LG2:
2373 emit_flop(pc, 3, brdc, src[0][0]);
2374 break;
2375 case TGSI_OPCODE_LRP:
2376 temp = temp_temp(pc);
2377 for (c = 0; c < 4; c++) {
2378 if (!(mask & (1 << c)))
2379 continue;
2380 emit_sub(pc, temp, src[1][c], src[2][c]);
2381 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2382 }
2383 break;
2384 case TGSI_OPCODE_MAD:
2385 for (c = 0; c < 4; c++) {
2386 if (!(mask & (1 << c)))
2387 continue;
2388 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2389 }
2390 break;
2391 case TGSI_OPCODE_MAX:
2392 for (c = 0; c < 4; c++) {
2393 if (!(mask & (1 << c)))
2394 continue;
2395 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
2396 }
2397 break;
2398 case TGSI_OPCODE_MIN:
2399 for (c = 0; c < 4; c++) {
2400 if (!(mask & (1 << c)))
2401 continue;
2402 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
2403 }
2404 break;
2405 case TGSI_OPCODE_MOV:
2406 for (c = 0; c < 4; c++) {
2407 if (!(mask & (1 << c)))
2408 continue;
2409 emit_mov(pc, dst[c], src[0][c]);
2410 }
2411 break;
2412 case TGSI_OPCODE_MUL:
2413 for (c = 0; c < 4; c++) {
2414 if (!(mask & (1 << c)))
2415 continue;
2416 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2417 }
2418 break;
2419 case TGSI_OPCODE_POW:
2420 emit_pow(pc, brdc, src[0][0], src[1][0]);
2421 break;
2422 case TGSI_OPCODE_RCP:
2423 emit_flop(pc, 0, brdc, src[0][0]);
2424 break;
2425 case TGSI_OPCODE_RET:
2426 if (pc->p->type == PIPE_SHADER_FRAGMENT)
2427 nv50_fp_move_results(pc);
2428 emit_ret(pc, -1, 0);
2429 break;
2430 case TGSI_OPCODE_RSQ:
2431 emit_flop(pc, 2, brdc, src[0][0]);
2432 break;
2433 case TGSI_OPCODE_SCS:
2434 temp = temp_temp(pc);
2435 if (mask & 3)
2436 emit_precossin(pc, temp, src[0][0]);
2437 if (mask & (1 << 0))
2438 emit_flop(pc, 5, dst[0], temp);
2439 if (mask & (1 << 1))
2440 emit_flop(pc, 4, dst[1], temp);
2441 if (mask & (1 << 2))
2442 emit_mov_immdval(pc, dst[2], 0.0);
2443 if (mask & (1 << 3))
2444 emit_mov_immdval(pc, dst[3], 1.0);
2445 break;
2446 case TGSI_OPCODE_SIN:
2447 if (mask & 8) {
2448 emit_precossin(pc, temp, src[0][3]);
2449 emit_flop(pc, 4, dst[3], temp);
2450 if (!(mask &= 7))
2451 break;
2452 if (temp == dst[3])
2453 temp = brdc = temp_temp(pc);
2454 }
2455 emit_precossin(pc, temp, src[0][0]);
2456 emit_flop(pc, 4, brdc, temp);
2457 break;
2458 case TGSI_OPCODE_SLT:
2459 case TGSI_OPCODE_SGE:
2460 case TGSI_OPCODE_SEQ:
2461 case TGSI_OPCODE_SGT:
2462 case TGSI_OPCODE_SLE:
2463 case TGSI_OPCODE_SNE:
2464 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
2465 for (c = 0; c < 4; c++) {
2466 if (!(mask & (1 << c)))
2467 continue;
2468 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
2469 }
2470 break;
2471 case TGSI_OPCODE_SUB:
2472 for (c = 0; c < 4; c++) {
2473 if (!(mask & (1 << c)))
2474 continue;
2475 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2476 }
2477 break;
2478 case TGSI_OPCODE_TEX:
2479 emit_tex(pc, dst, mask, src[0], unit,
2480 inst->Texture.Texture, FALSE, 0);
2481 break;
2482 case TGSI_OPCODE_TXB:
2483 emit_tex(pc, dst, mask, src[0], unit,
2484 inst->Texture.Texture, FALSE, -1);
2485 break;
2486 case TGSI_OPCODE_TXL:
2487 emit_tex(pc, dst, mask, src[0], unit,
2488 inst->Texture.Texture, FALSE, 1);
2489 break;
2490 case TGSI_OPCODE_TXP:
2491 emit_tex(pc, dst, mask, src[0], unit,
2492 inst->Texture.Texture, TRUE, 0);
2493 break;
2494 case TGSI_OPCODE_TRUNC:
2495 for (c = 0; c < 4; c++) {
2496 if (!(mask & (1 << c)))
2497 continue;
2498 emit_cvt(pc, dst[c], src[0][c], -1,
2499 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
2500 }
2501 break;
2502 case TGSI_OPCODE_XPD:
2503 temp = temp_temp(pc);
2504 if (mask & (1 << 0)) {
2505 emit_mul(pc, temp, src[0][2], src[1][1]);
2506 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2507 }
2508 if (mask & (1 << 1)) {
2509 emit_mul(pc, temp, src[0][0], src[1][2]);
2510 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2511 }
2512 if (mask & (1 << 2)) {
2513 emit_mul(pc, temp, src[0][1], src[1][0]);
2514 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2515 }
2516 if (mask & (1 << 3))
2517 emit_mov_immdval(pc, dst[3], 1.0);
2518 break;
2519 case TGSI_OPCODE_END:
2520 break;
2521 default:
2522 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2523 return FALSE;
2524 }
2525
2526 if (brdc) {
2527 if (sat)
2528 emit_sat(pc, brdc, brdc);
2529 for (c = 0; c < 4; c++)
2530 if ((mask & (1 << c)) && dst[c] != brdc)
2531 emit_mov(pc, dst[c], brdc);
2532 } else
2533 if (sat) {
2534 for (c = 0; c < 4; c++) {
2535 if (!(mask & (1 << c)))
2536 continue;
2537 /* In this case we saturate later, and dst[c] won't
2538 * be another temp_temp (and thus lost), since rdst
2539 * already is TEMP (see above). */
2540 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2541 continue;
2542 emit_sat(pc, rdst[c], dst[c]);
2543 }
2544 }
2545
2546 kill_temp_temp(pc);
2547 pc->reg_instance_nr = 0;
2548
2549 return TRUE;
2550 }
2551
2552 static void
2553 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2554 {
2555 struct nv50_reg *reg = NULL;
2556 const struct tgsi_full_src_register *src;
2557 const struct tgsi_dst_register *dst;
2558 unsigned i, c, k, mask;
2559
2560 dst = &insn->Dst[0].Register;
2561 mask = dst->WriteMask;
2562
2563 if (dst->File == TGSI_FILE_TEMPORARY)
2564 reg = pc->temp;
2565 else
2566 if (dst->File == TGSI_FILE_OUTPUT) {
2567 reg = pc->result;
2568
2569 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
2570 dst->Index == pc->edgeflag_out &&
2571 insn->Src[0].Register.File == TGSI_FILE_INPUT)
2572 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
2573 }
2574
2575 if (reg) {
2576 for (c = 0; c < 4; c++) {
2577 if (!(mask & (1 << c)))
2578 continue;
2579 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2580 }
2581 }
2582
2583 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2584 src = &insn->Src[i];
2585
2586 if (src->Register.File == TGSI_FILE_TEMPORARY)
2587 reg = pc->temp;
2588 else
2589 if (src->Register.File == TGSI_FILE_INPUT)
2590 reg = pc->attr;
2591 else
2592 continue;
2593
2594 mask = nv50_tgsi_src_mask(insn, i);
2595
2596 for (c = 0; c < 4; c++) {
2597 if (!(mask & (1 << c)))
2598 continue;
2599 k = tgsi_util_get_full_src_register_swizzle(src, c);
2600
2601 reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
2602 }
2603 }
2604 }
2605
2606 /* Returns a bitmask indicating which dst components need to be
2607 * written to temporaries first to avoid 'corrupting' sources.
2608 *
2609 * m[i] (out) indicate component to write in the i-th position
2610 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2611 */
2612 static unsigned
2613 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2614 {
2615 unsigned i, c, x, unsafe;
2616
2617 for (c = 0; c < 4; c++)
2618 m[c] = c;
2619
2620 /* Swap as long as a dst component written earlier is depended on
2621 * by one written later, but the next one isn't depended on by it.
2622 */
2623 for (c = 0; c < 3; c++) {
2624 if (rdep[m[c + 1]] & (1 << m[c]))
2625 continue; /* if next one is depended on by us */
2626 for (i = c + 1; i < 4; i++)
2627 /* if we are depended on by a later one */
2628 if (rdep[m[c]] & (1 << m[i]))
2629 break;
2630 if (i == 4)
2631 continue;
2632 /* now, swap */
2633 x = m[c];
2634 m[c] = m[c + 1];
2635 m[c + 1] = x;
2636
2637 /* restart */
2638 c = 0;
2639 }
2640
2641 /* mark dependencies that could not be resolved by reordering */
2642 for (i = 0; i < 3; ++i)
2643 for (c = i + 1; c < 4; ++c)
2644 if (rdep[m[i]] & (1 << m[c]))
2645 unsafe |= (1 << i);
2646
2647 /* NOTE: $unsafe is with respect to order, not component */
2648 return unsafe;
2649 }
2650
2651 /* Select a suitable dst register for broadcasting scalar results,
2652 * or return NULL if we have to allocate an extra TEMP.
2653 *
2654 * If e.g. only 1 component is written, we may also emit the final
2655 * result to a write-only register.
2656 */
2657 static struct nv50_reg *
2658 tgsi_broadcast_dst(struct nv50_pc *pc,
2659 const struct tgsi_full_dst_register *fd, unsigned mask)
2660 {
2661 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
2662 int c = ffs(~mask & fd->Register.WriteMask);
2663 if (c)
2664 return tgsi_dst(pc, c - 1, fd);
2665 } else {
2666 int c = ffs(fd->Register.WriteMask) - 1;
2667 if ((1 << c) == fd->Register.WriteMask)
2668 return tgsi_dst(pc, c, fd);
2669 }
2670
2671 return NULL;
2672 }
2673
2674 /* Scan source swizzles and return a bitmask indicating dst regs that
2675 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2676 */
2677 static unsigned
2678 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2679 unsigned rdep[4])
2680 {
2681 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
2682 const struct tgsi_full_src_register *fs;
2683 unsigned i, deqs = 0;
2684
2685 for (i = 0; i < 4; ++i)
2686 rdep[i] = 0;
2687
2688 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2689 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2690 boolean neg_supp = negate_supported(insn, i);
2691
2692 fs = &insn->Src[i];
2693 if (fs->Register.File != fd->Register.File ||
2694 fs->Register.Index != fd->Register.Index)
2695 continue;
2696
2697 for (chn = 0; chn < 4; ++chn) {
2698 unsigned s, c;
2699
2700 if (!(mask & (1 << chn))) /* src is not read */
2701 continue;
2702 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2703 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2704
2705 if (!(fd->Register.WriteMask & (1 << c)))
2706 continue;
2707
2708 /* no danger if src is copied to TEMP first */
2709 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2710 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2711 continue;
2712
2713 rdep[c] |= nv50_tgsi_dst_revdep(
2714 insn->Instruction.Opcode, i, chn);
2715 deqs |= (1 << c);
2716 }
2717 }
2718
2719 return deqs;
2720 }
2721
2722 static boolean
2723 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2724 {
2725 struct tgsi_full_instruction insn = tok->FullInstruction;
2726 const struct tgsi_full_dst_register *fd;
2727 unsigned i, deqs, rdep[4], m[4];
2728
2729 fd = &tok->FullInstruction.Dst[0];
2730 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2731
2732 if (is_scalar_op(insn.Instruction.Opcode)) {
2733 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2734 if (!pc->r_brdc)
2735 pc->r_brdc = temp_temp(pc);
2736 return nv50_program_tx_insn(pc, &insn);
2737 }
2738 pc->r_brdc = NULL;
2739
2740 if (!deqs)
2741 return nv50_program_tx_insn(pc, &insn);
2742
2743 deqs = nv50_revdep_reorder(m, rdep);
2744
2745 for (i = 0; i < 4; ++i) {
2746 assert(pc->r_dst[m[i]] == NULL);
2747
2748 insn.Dst[0].Register.WriteMask =
2749 fd->Register.WriteMask & (1 << m[i]);
2750
2751 if (!insn.Dst[0].Register.WriteMask)
2752 continue;
2753
2754 if (deqs & (1 << i))
2755 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2756
2757 if (!nv50_program_tx_insn(pc, &insn))
2758 return FALSE;
2759 }
2760
2761 for (i = 0; i < 4; i++) {
2762 struct nv50_reg *reg = pc->r_dst[i];
2763 if (!reg)
2764 continue;
2765 pc->r_dst[i] = NULL;
2766
2767 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2768 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2769 else
2770 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2771 free_temp(pc, reg);
2772 }
2773
2774 return TRUE;
2775 }
2776
2777 static void
2778 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2779 {
2780 struct nv50_reg *iv, **ppiv;
2781 unsigned mode = pc->interp_mode[reg->index];
2782
2783 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2784 iv = *ppiv;
2785
2786 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2787 iv = *ppiv = alloc_temp(pc, NULL);
2788 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2789
2790 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2791 emit_flop(pc, 0, iv, iv);
2792
2793 /* XXX: when loading interpolants dynamically, move these
2794 * to the program head, or make sure it can't be skipped.
2795 */
2796 }
2797
2798 emit_interp(pc, reg, iv, mode);
2799 }
2800
2801 /* The face input is always at v[255] (varying space), with a
2802 * value of 0 for back-facing, and 0xffffffff for front-facing.
2803 */
2804 static void
2805 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
2806 {
2807 struct nv50_reg *one = alloc_immd(pc, 1.0f);
2808
2809 assert(a->rhw == -1);
2810 alloc_reg(pc, a); /* do this before rhw is set */
2811 a->rhw = 255;
2812 load_interpolant(pc, a);
2813 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
2814
2815 FREE(one);
2816 }
2817
2818 static boolean
2819 nv50_program_tx_prep(struct nv50_pc *pc)
2820 {
2821 struct tgsi_parse_context tp;
2822 struct nv50_program *p = pc->p;
2823 boolean ret = FALSE;
2824 unsigned i, c, flat_nr = 0;
2825
2826 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2827 while (!tgsi_parse_end_of_tokens(&tp)) {
2828 const union tgsi_full_token *tok = &tp.FullToken;
2829
2830 tgsi_parse_token(&tp);
2831 switch (tok->Token.Type) {
2832 case TGSI_TOKEN_TYPE_IMMEDIATE:
2833 {
2834 const struct tgsi_full_immediate *imm =
2835 &tp.FullToken.FullImmediate;
2836
2837 ctor_immd_4f32(pc, imm->u[0].Float,
2838 imm->u[1].Float,
2839 imm->u[2].Float,
2840 imm->u[3].Float);
2841 }
2842 break;
2843 case TGSI_TOKEN_TYPE_DECLARATION:
2844 {
2845 const struct tgsi_full_declaration *d;
2846 unsigned si, last, first, mode;
2847
2848 d = &tp.FullToken.FullDeclaration;
2849 first = d->Range.First;
2850 last = d->Range.Last;
2851
2852 switch (d->Declaration.File) {
2853 case TGSI_FILE_TEMPORARY:
2854 break;
2855 case TGSI_FILE_OUTPUT:
2856 if (!d->Declaration.Semantic ||
2857 p->type == PIPE_SHADER_FRAGMENT)
2858 break;
2859
2860 si = d->Semantic.Index;
2861 switch (d->Semantic.Name) {
2862 case TGSI_SEMANTIC_BCOLOR:
2863 p->cfg.two_side[si].hw = first;
2864 if (p->cfg.io_nr > first)
2865 p->cfg.io_nr = first;
2866 break;
2867 case TGSI_SEMANTIC_PSIZE:
2868 p->cfg.psiz = first;
2869 if (p->cfg.io_nr > first)
2870 p->cfg.io_nr = first;
2871 break;
2872 case TGSI_SEMANTIC_EDGEFLAG:
2873 pc->edgeflag_out = first;
2874 break;
2875 /*
2876 case TGSI_SEMANTIC_CLIP_DISTANCE:
2877 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2878 break;
2879 */
2880 default:
2881 break;
2882 }
2883 break;
2884 case TGSI_FILE_INPUT:
2885 {
2886 if (p->type != PIPE_SHADER_FRAGMENT)
2887 break;
2888
2889 switch (d->Declaration.Interpolate) {
2890 case TGSI_INTERPOLATE_CONSTANT:
2891 mode = INTERP_FLAT;
2892 flat_nr++;
2893 break;
2894 case TGSI_INTERPOLATE_PERSPECTIVE:
2895 mode = INTERP_PERSPECTIVE;
2896 p->cfg.regs[1] |= 0x08 << 24;
2897 break;
2898 default:
2899 mode = INTERP_LINEAR;
2900 break;
2901 }
2902 if (d->Declaration.Centroid)
2903 mode |= INTERP_CENTROID;
2904
2905 assert(last < 32);
2906 for (i = first; i <= last; i++)
2907 pc->interp_mode[i] = mode;
2908 }
2909 break;
2910 case TGSI_FILE_ADDRESS:
2911 case TGSI_FILE_CONSTANT:
2912 case TGSI_FILE_SAMPLER:
2913 break;
2914 default:
2915 NOUVEAU_ERR("bad decl file %d\n",
2916 d->Declaration.File);
2917 goto out_err;
2918 }
2919 }
2920 break;
2921 case TGSI_TOKEN_TYPE_INSTRUCTION:
2922 pc->insn_nr++;
2923 prep_inspect_insn(pc, &tok->FullInstruction);
2924 break;
2925 default:
2926 break;
2927 }
2928 }
2929
2930 if (p->type == PIPE_SHADER_VERTEX) {
2931 int rid = 0;
2932
2933 for (i = 0; i < pc->attr_nr * 4; ++i) {
2934 if (pc->attr[i].acc) {
2935 pc->attr[i].hw = rid++;
2936 p->cfg.attr[i / 32] |= 1 << (i % 32);
2937 }
2938 }
2939
2940 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
2941 p->cfg.io[i].hw = rid;
2942 p->cfg.io[i].id = i;
2943
2944 for (c = 0; c < 4; ++c) {
2945 int n = i * 4 + c;
2946 if (!pc->result[n].acc)
2947 continue;
2948 pc->result[n].hw = rid++;
2949 p->cfg.io[i].mask |= 1 << c;
2950 }
2951 }
2952
2953 for (c = 0; c < 2; ++c)
2954 if (p->cfg.two_side[c].hw < 0x40)
2955 p->cfg.two_side[c] = p->cfg.io[
2956 p->cfg.two_side[c].hw];
2957
2958 if (p->cfg.psiz < 0x40)
2959 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
2960 } else
2961 if (p->type == PIPE_SHADER_FRAGMENT) {
2962 int rid, aid;
2963 unsigned n = 0, m = pc->attr_nr - flat_nr;
2964
2965 pc->allow32 = TRUE;
2966
2967 int base = (TGSI_SEMANTIC_POSITION ==
2968 p->info.input_semantic_name[0]) ? 0 : 1;
2969
2970 /* non-flat interpolants have to be mapped to
2971 * the lower hardware IDs, so sort them:
2972 */
2973 for (i = 0; i < pc->attr_nr; i++) {
2974 if (pc->interp_mode[i] == INTERP_FLAT)
2975 p->cfg.io[m++].id = i;
2976 else {
2977 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
2978 p->cfg.io[n].linear = TRUE;
2979 p->cfg.io[n++].id = i;
2980 }
2981 }
2982
2983 if (!base) /* set w-coordinate mask from perspective interp */
2984 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
2985
2986 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
2987 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
2988
2989 for (n = 0; n < pc->attr_nr; ++n) {
2990 p->cfg.io[n].hw = rid = aid;
2991 i = p->cfg.io[n].id;
2992
2993 if (p->info.input_semantic_name[n] ==
2994 TGSI_SEMANTIC_FACE) {
2995 load_frontfacing(pc, &pc->attr[i * 4]);
2996 continue;
2997 }
2998
2999 for (c = 0; c < 4; ++c) {
3000 if (!pc->attr[i * 4 + c].acc)
3001 continue;
3002 pc->attr[i * 4 + c].rhw = rid++;
3003 p->cfg.io[n].mask |= 1 << c;
3004
3005 load_interpolant(pc, &pc->attr[i * 4 + c]);
3006 }
3007 aid += popcnt4(p->cfg.io[n].mask);
3008 }
3009
3010 if (!base)
3011 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
3012
3013 m = popcnt4(p->cfg.regs[1] >> 24);
3014
3015 /* set count of non-position inputs and of non-flat
3016 * non-position inputs for FP_INTERPOLANT_CTRL
3017 */
3018 p->cfg.regs[1] |= aid - m;
3019
3020 if (flat_nr) {
3021 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
3022 p->cfg.regs[1] |= (i - m) << 16;
3023 } else
3024 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3025
3026 /* mark color semantic for light-twoside */
3027 n = 0x40;
3028 for (i = 0; i < pc->attr_nr; i++) {
3029 ubyte si, sn;
3030
3031 sn = p->info.input_semantic_name[p->cfg.io[i].id];
3032 si = p->info.input_semantic_index[p->cfg.io[i].id];
3033
3034 if (sn == TGSI_SEMANTIC_COLOR) {
3035 p->cfg.two_side[si] = p->cfg.io[i];
3036
3037 /* increase colour count */
3038 p->cfg.regs[0] += popcnt4(
3039 p->cfg.two_side[si].mask) << 16;
3040
3041 n = MIN2(n, p->cfg.io[i].hw - m);
3042 }
3043 }
3044 if (n < 0x40)
3045 p->cfg.regs[0] += n;
3046
3047 /* Initialize FP results:
3048 * FragDepth is always first TGSI and last hw output
3049 */
3050 i = p->info.writes_z ? 4 : 0;
3051 for (rid = 0; i < pc->result_nr * 4; i++)
3052 pc->result[i].rhw = rid++;
3053 if (p->info.writes_z)
3054 pc->result[2].rhw = rid;
3055
3056 p->cfg.high_result = rid;
3057
3058 /* separate/different colour results for MRTs ? */
3059 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3060 p->cfg.regs[2] |= 1;
3061 }
3062
3063 if (pc->immd_nr) {
3064 int rid = 0;
3065
3066 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3067 if (!pc->immd)
3068 goto out_err;
3069
3070 for (i = 0; i < pc->immd_nr; i++) {
3071 for (c = 0; c < 4; c++, rid++)
3072 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3073 }
3074 }
3075
3076 ret = TRUE;
3077 out_err:
3078 if (pc->iv_p)
3079 free_temp(pc, pc->iv_p);
3080 if (pc->iv_c)
3081 free_temp(pc, pc->iv_c);
3082
3083 tgsi_parse_free(&tp);
3084 return ret;
3085 }
3086
3087 static void
3088 free_nv50_pc(struct nv50_pc *pc)
3089 {
3090 if (pc->immd)
3091 FREE(pc->immd);
3092 if (pc->param)
3093 FREE(pc->param);
3094 if (pc->result)
3095 FREE(pc->result);
3096 if (pc->attr)
3097 FREE(pc->attr);
3098 if (pc->temp)
3099 FREE(pc->temp);
3100
3101 FREE(pc);
3102 }
3103
3104 static boolean
3105 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3106 {
3107 int i, c;
3108 unsigned rtype[2] = { P_ATTR, P_RESULT };
3109
3110 pc->p = p;
3111 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3112 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3113 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3114 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3115 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3116 assert(pc->addr_nr <= 2);
3117
3118 p->cfg.high_temp = 4;
3119
3120 p->cfg.two_side[0].hw = 0x40;
3121 p->cfg.two_side[1].hw = 0x40;
3122
3123 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3124
3125 switch (p->type) {
3126 case PIPE_SHADER_VERTEX:
3127 p->cfg.psiz = 0x40;
3128 p->cfg.clpd = 0x40;
3129 p->cfg.io_nr = pc->result_nr;
3130 break;
3131 case PIPE_SHADER_FRAGMENT:
3132 rtype[0] = rtype[1] = P_TEMP;
3133
3134 p->cfg.regs[0] = 0x01000004;
3135 p->cfg.io_nr = pc->attr_nr;
3136
3137 if (p->info.writes_z) {
3138 p->cfg.regs[2] |= 0x00000100;
3139 p->cfg.regs[3] |= 0x00000011;
3140 }
3141 if (p->info.uses_kill)
3142 p->cfg.regs[2] |= 0x00100000;
3143 break;
3144 }
3145
3146 if (pc->temp_nr) {
3147 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3148 if (!pc->temp)
3149 return FALSE;
3150
3151 for (i = 0; i < pc->temp_nr * 4; ++i)
3152 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3153 }
3154
3155 if (pc->attr_nr) {
3156 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3157 if (!pc->attr)
3158 return FALSE;
3159
3160 for (i = 0; i < pc->attr_nr * 4; ++i)
3161 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3162 }
3163
3164 if (pc->result_nr) {
3165 unsigned nr = pc->result_nr * 4;
3166
3167 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3168 if (!pc->result)
3169 return FALSE;
3170
3171 for (i = 0; i < nr; ++i)
3172 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3173 }
3174
3175 if (pc->param_nr) {
3176 int rid = 0;
3177
3178 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3179 if (!pc->param)
3180 return FALSE;
3181
3182 for (i = 0; i < pc->param_nr; ++i)
3183 for (c = 0; c < 4; ++c, ++rid)
3184 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3185 }
3186
3187 if (pc->addr_nr) {
3188 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3189 if (!pc->addr)
3190 return FALSE;
3191 }
3192 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3193 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
3194
3195 return TRUE;
3196 }
3197
3198 static void
3199 nv50_program_fixup_insns(struct nv50_pc *pc)
3200 {
3201 struct nv50_program_exec *e, **bra_list;
3202 unsigned i, n, pos;
3203
3204 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3205
3206 /* Collect branch instructions, we need to adjust their offsets
3207 * when converting 32 bit instructions to 64 bit ones
3208 */
3209 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3210 if (e->param.index >= 0 && !e->param.mask)
3211 bra_list[n++] = e;
3212
3213 /* last instruction must be long so it can have the exit bit set */
3214 if (!is_long(pc->p->exec_tail))
3215 convert_to_long(pc, pc->p->exec_tail);
3216 /* set exit bit */
3217 pc->p->exec_tail->inst[1] |= 1;
3218
3219 /* !immd on exit insn simultaneously means !join */
3220 assert(!is_immd(pc->p->exec_head));
3221 assert(!is_immd(pc->p->exec_tail));
3222
3223 /* Make sure we don't have any single 32 bit instructions. */
3224 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3225 pos += is_long(e) ? 2 : 1;
3226
3227 if ((pos & 1) && (!e->next || is_long(e->next))) {
3228 for (i = 0; i < n; ++i)
3229 if (bra_list[i]->param.index >= pos)
3230 bra_list[i]->param.index += 1;
3231 convert_to_long(pc, e);
3232 ++pos;
3233 }
3234 }
3235
3236 FREE(bra_list);
3237 }
3238
3239 static boolean
3240 nv50_program_tx(struct nv50_program *p)
3241 {
3242 struct tgsi_parse_context parse;
3243 struct nv50_pc *pc;
3244 boolean ret;
3245
3246 pc = CALLOC_STRUCT(nv50_pc);
3247 if (!pc)
3248 return FALSE;
3249
3250 ret = ctor_nv50_pc(pc, p);
3251 if (ret == FALSE)
3252 goto out_cleanup;
3253
3254 ret = nv50_program_tx_prep(pc);
3255 if (ret == FALSE)
3256 goto out_cleanup;
3257
3258 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3259 while (!tgsi_parse_end_of_tokens(&parse)) {
3260 const union tgsi_full_token *tok = &parse.FullToken;
3261
3262 /* don't allow half insn/immd on first and last instruction */
3263 pc->allow32 = TRUE;
3264 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr)
3265 pc->allow32 = FALSE;
3266
3267 tgsi_parse_token(&parse);
3268
3269 switch (tok->Token.Type) {
3270 case TGSI_TOKEN_TYPE_INSTRUCTION:
3271 ++pc->insn_cur;
3272 ret = nv50_tgsi_insn(pc, tok);
3273 if (ret == FALSE)
3274 goto out_err;
3275 break;
3276 default:
3277 break;
3278 }
3279 }
3280
3281 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3282 nv50_fp_move_results(pc);
3283
3284 nv50_program_fixup_insns(pc);
3285
3286 p->param_nr = pc->param_nr * 4;
3287 p->immd_nr = pc->immd_nr * 4;
3288 p->immd = pc->immd_buf;
3289
3290 out_err:
3291 tgsi_parse_free(&parse);
3292
3293 out_cleanup:
3294 free_nv50_pc(pc);
3295 return ret;
3296 }
3297
3298 static void
3299 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3300 {
3301 if (nv50_program_tx(p) == FALSE)
3302 assert(0);
3303 p->translated = TRUE;
3304 }
3305
3306 static void
3307 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
3308 unsigned start, unsigned count, unsigned cbuf)
3309 {
3310 struct nouveau_channel *chan = nv50->screen->base.channel;
3311 struct nouveau_grobj *tesla = nv50->screen->tesla;
3312
3313 while (count) {
3314 unsigned nr = count > 2047 ? 2047 : count;
3315
3316 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3317 OUT_RING (chan, (cbuf << 0) | (start << 8));
3318 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3319 OUT_RINGp (chan, map, nr);
3320
3321 map += nr;
3322 start += nr;
3323 count -= nr;
3324 }
3325 }
3326
3327 static void
3328 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3329 {
3330 struct pipe_screen *pscreen = nv50->pipe.screen;
3331
3332 if (!p->data[0] && p->immd_nr) {
3333 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3334
3335 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3336 while (heap->next && heap->size < p->immd_nr) {
3337 struct nv50_program *evict = heap->next->priv;
3338 nouveau_resource_free(&evict->data[0]);
3339 }
3340
3341 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3342 &p->data[0]))
3343 assert(0);
3344 }
3345
3346 /* immediates only need to be uploaded again when freed */
3347 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3348 p->immd_nr, NV50_CB_PMISC);
3349 }
3350
3351 assert(p->param_nr <= 512);
3352
3353 if (p->param_nr) {
3354 unsigned cb;
3355 uint32_t *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3356 PIPE_BUFFER_USAGE_CPU_READ);
3357
3358 if (p->type == PIPE_SHADER_VERTEX)
3359 cb = NV50_CB_PVP;
3360 else
3361 cb = NV50_CB_PFP;
3362
3363 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3364 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3365 }
3366 }
3367
3368 static void
3369 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3370 {
3371 struct nouveau_channel *chan = nv50->screen->base.channel;
3372 struct nv50_program_exec *e;
3373 uint32_t *up, i;
3374 boolean upload = FALSE;
3375
3376 if (!p->bo) {
3377 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3378 p->exec_size * 4, &p->bo);
3379 upload = TRUE;
3380 }
3381
3382 if (p->data[0] && p->data[0]->start != p->data_start[0])
3383 upload = TRUE;
3384
3385 if (!upload)
3386 return;
3387
3388 up = MALLOC(p->exec_size * 4);
3389
3390 for (i = 0, e = p->exec_head; e; e = e->next) {
3391 unsigned ei, ci, bs;
3392
3393 if (e->param.index >= 0 && e->param.mask) {
3394 bs = (e->inst[1] >> 22) & 0x07;
3395 assert(bs < 2);
3396 ei = e->param.shift >> 5;
3397 ci = e->param.index;
3398 if (bs == 0)
3399 ci += p->data[bs]->start;
3400
3401 e->inst[ei] &= ~e->param.mask;
3402 e->inst[ei] |= (ci << e->param.shift);
3403 } else
3404 if (e->param.index >= 0) {
3405 /* zero mask means param is a jump/branch offset */
3406 assert(!(e->param.index & 1));
3407 /* seem to be 8 byte steps */
3408 ei = (e->param.index >> 1) + 0 /* START_ID */;
3409
3410 e->inst[0] &= 0xf0000fff;
3411 e->inst[0] |= ei << 12;
3412 }
3413
3414 up[i++] = e->inst[0];
3415 if (is_long(e))
3416 up[i++] = e->inst[1];
3417 }
3418 assert(i == p->exec_size);
3419
3420 if (p->data[0])
3421 p->data_start[0] = p->data[0]->start;
3422
3423 #ifdef NV50_PROGRAM_DUMP
3424 NOUVEAU_ERR("-------\n");
3425 for (e = p->exec_head; e; e = e->next) {
3426 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3427 if (is_long(e))
3428 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3429 }
3430 #endif
3431 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3432 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3433 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3434 0, 0, p->exec_size * 4, 1, 1);
3435
3436 FREE(up);
3437 }
3438
3439 void
3440 nv50_vertprog_validate(struct nv50_context *nv50)
3441 {
3442 struct nouveau_grobj *tesla = nv50->screen->tesla;
3443 struct nv50_program *p = nv50->vertprog;
3444 struct nouveau_stateobj *so;
3445
3446 if (!p->translated) {
3447 nv50_program_validate(nv50, p);
3448 if (!p->translated)
3449 assert(0);
3450 }
3451
3452 nv50_program_validate_data(nv50, p);
3453 nv50_program_validate_code(nv50, p);
3454
3455 so = so_new(13, 2);
3456 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3457 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3458 NOUVEAU_BO_HIGH, 0, 0);
3459 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3460 NOUVEAU_BO_LOW, 0, 0);
3461 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3462 so_data (so, p->cfg.attr[0]);
3463 so_data (so, p->cfg.attr[1]);
3464 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3465 so_data (so, p->cfg.high_result);
3466 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3467 so_data (so, p->cfg.high_result); //8);
3468 so_data (so, p->cfg.high_temp);
3469 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3470 so_data (so, 0); /* program start offset */
3471 so_ref(so, &nv50->state.vertprog);
3472 so_ref(NULL, &so);
3473 }
3474
3475 void
3476 nv50_fragprog_validate(struct nv50_context *nv50)
3477 {
3478 struct nouveau_grobj *tesla = nv50->screen->tesla;
3479 struct nv50_program *p = nv50->fragprog;
3480 struct nouveau_stateobj *so;
3481
3482 if (!p->translated) {
3483 nv50_program_validate(nv50, p);
3484 if (!p->translated)
3485 assert(0);
3486 }
3487
3488 nv50_program_validate_data(nv50, p);
3489 nv50_program_validate_code(nv50, p);
3490
3491 so = so_new(64, 2);
3492 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3493 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3494 NOUVEAU_BO_HIGH, 0, 0);
3495 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3496 NOUVEAU_BO_LOW, 0, 0);
3497 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3498 so_data (so, p->cfg.high_temp);
3499 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3500 so_data (so, p->cfg.high_result);
3501 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
3502 so_data (so, p->cfg.regs[2]);
3503 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3504 so_data (so, p->cfg.regs[3]);
3505 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3506 so_data (so, 0); /* program start offset */
3507 so_ref(so, &nv50->state.fragprog);
3508 so_ref(NULL, &so);
3509 }
3510
3511 static void
3512 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3513 {
3514 struct nv50_program *fp = nv50->fragprog;
3515 struct nv50_program *vp = nv50->vertprog;
3516 unsigned i, c, m = base;
3517
3518 /* XXX: this might not work correctly in all cases yet - we'll
3519 * just assume that an FP generic input that is not written in
3520 * the VP is PointCoord.
3521 */
3522 memset(pntc, 0, 8 * sizeof(uint32_t));
3523
3524 for (i = 0; i < fp->cfg.io_nr; i++) {
3525 uint8_t sn, si;
3526 uint8_t j, k = fp->cfg.io[i].id;
3527 unsigned n = popcnt4(fp->cfg.io[i].mask);
3528
3529 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3530 m += n;
3531 continue;
3532 }
3533
3534 for (j = 0; j < vp->info.num_outputs; ++j) {
3535 sn = vp->info.output_semantic_name[j];
3536 si = vp->info.output_semantic_index[j];
3537
3538 if (sn == fp->info.input_semantic_name[k] &&
3539 si == fp->info.input_semantic_index[k])
3540 break;
3541 }
3542
3543 if (j < vp->info.num_outputs) {
3544 ubyte mode =
3545 nv50->rasterizer->pipe.sprite_coord_mode[si];
3546
3547 if (mode == PIPE_SPRITE_COORD_NONE) {
3548 m += n;
3549 continue;
3550 }
3551 }
3552
3553 /* this is either PointCoord or replaced by sprite coords */
3554 for (c = 0; c < 4; c++) {
3555 if (!(fp->cfg.io[i].mask & (1 << c)))
3556 continue;
3557 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3558 ++m;
3559 }
3560 }
3561 }
3562
3563 static int
3564 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3565 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3566 {
3567 int c;
3568 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3569 uint8_t *map = (uint8_t *)p_map;
3570
3571 for (c = 0; c < 4; ++c) {
3572 if (mf & 1) {
3573 if (fpi->linear == TRUE)
3574 lin[mid / 32] |= 1 << (mid % 32);
3575 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3576 }
3577
3578 oid += mv & 1;
3579 mf >>= 1;
3580 mv >>= 1;
3581 }
3582
3583 return mid;
3584 }
3585
3586 void
3587 nv50_linkage_validate(struct nv50_context *nv50)
3588 {
3589 struct nouveau_grobj *tesla = nv50->screen->tesla;
3590 struct nv50_program *vp = nv50->vertprog;
3591 struct nv50_program *fp = nv50->fragprog;
3592 struct nouveau_stateobj *so;
3593 struct nv50_sreg4 dummy, *vpo;
3594 int i, n, c, m = 0;
3595 uint32_t map[16], lin[4], reg[5], pcrd[8];
3596
3597 memset(map, 0, sizeof(map));
3598 memset(lin, 0, sizeof(lin));
3599
3600 reg[1] = 0x00000004; /* low and high clip distance map ids */
3601 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3602 reg[3] = 0x00000000; /* point size map id & enable */
3603 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3604 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3605
3606 dummy.linear = FALSE;
3607 dummy.mask = 0xf; /* map all components of HPOS */
3608 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3609
3610 dummy.mask = 0x0;
3611
3612 if (vp->cfg.clpd < 0x40) {
3613 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3614 map[m++] = vp->cfg.clpd + c;
3615 reg[1] = (m << 8);
3616 }
3617
3618 reg[0] |= m << 8; /* adjust BFC0 id */
3619
3620 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3621 if (nv50->rasterizer->pipe.light_twoside) {
3622 vpo = &vp->cfg.two_side[0];
3623
3624 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3625 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3626 }
3627
3628 reg[0] += m - 4; /* adjust FFC0 id */
3629 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3630
3631 for (i = 0; i < fp->cfg.io_nr; i++) {
3632 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
3633 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
3634
3635 /* position must be mapped first */
3636 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
3637
3638 /* maybe even remove these from cfg.io */
3639 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
3640 continue;
3641
3642 /* VP outputs and vp->cfg.io are in the same order */
3643 for (n = 0; n < vp->info.num_outputs; ++n) {
3644 if (vp->info.output_semantic_name[n] == sn &&
3645 vp->info.output_semantic_index[n] == si)
3646 break;
3647 }
3648 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
3649
3650 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3651 }
3652
3653 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3654 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3655 reg[3] = (m++ << 4) | 1;
3656 }
3657
3658 /* now fill the stateobj */
3659 so = so_new(64, 0);
3660
3661 n = (m + 3) / 4;
3662 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3663 so_data (so, m);
3664 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3665 so_datap (so, map, n);
3666
3667 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3668 so_datap (so, reg, 4);
3669
3670 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3671 so_data (so, reg[4]);
3672
3673 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
3674 so_datap (so, lin, 4);
3675
3676 if (nv50->rasterizer->pipe.point_sprite) {
3677 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3678
3679 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3680 so_datap (so, pcrd, 8);
3681 }
3682
3683 so_ref(so, &nv50->state.programs);
3684 so_ref(NULL, &so);
3685 }
3686
3687 void
3688 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3689 {
3690 while (p->exec_head) {
3691 struct nv50_program_exec *e = p->exec_head;
3692
3693 p->exec_head = e->next;
3694 FREE(e);
3695 }
3696 p->exec_tail = NULL;
3697 p->exec_size = 0;
3698
3699 nouveau_bo_ref(NULL, &p->bo);
3700
3701 nouveau_resource_free(&p->data[0]);
3702
3703 p->translated = 0;
3704 }