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nouveau: nv50: Add missing ctor_immd_4u32 function
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_SAT 4
100
101 /* arbitrary limits */
102 #define MAX_IF_DEPTH 4
103 #define MAX_LOOP_DEPTH 4
104
105 struct nv50_pc {
106 struct nv50_program *p;
107
108 /* hw resources */
109 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
110 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
111
112 /* tgsi resources */
113 struct nv50_reg *temp;
114 int temp_nr;
115 struct nv50_reg *attr;
116 int attr_nr;
117 struct nv50_reg *result;
118 int result_nr;
119 struct nv50_reg *param;
120 int param_nr;
121 struct nv50_reg *immd;
122 float *immd_buf;
123 int immd_nr;
124 struct nv50_reg **addr;
125 int addr_nr;
126
127 struct nv50_reg *temp_temp[16];
128 unsigned temp_temp_nr;
129
130 /* broadcast and destination replacement regs */
131 struct nv50_reg *r_brdc;
132 struct nv50_reg *r_dst[4];
133
134 struct nv50_reg reg_instances[16];
135 unsigned reg_instance_nr;
136
137 unsigned interp_mode[32];
138 /* perspective interpolation registers */
139 struct nv50_reg *iv_p;
140 struct nv50_reg *iv_c;
141
142 struct nv50_program_exec *if_cond;
143 struct nv50_program_exec *if_insn[MAX_IF_DEPTH];
144 struct nv50_program_exec *br_join[MAX_IF_DEPTH];
145 struct nv50_program_exec *br_loop[MAX_LOOP_DEPTH]; /* for BRK branch */
146 int if_lvl, loop_lvl;
147 unsigned loop_pos[MAX_LOOP_DEPTH];
148
149 /* current instruction and total number of insns */
150 unsigned insn_cur;
151 unsigned insn_nr;
152
153 boolean allow32;
154 };
155
156 static INLINE struct nv50_reg *
157 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
158 {
159 struct nv50_reg *dup = NULL;
160 if (reg) {
161 assert(pc->reg_instance_nr < 16);
162 dup = &pc->reg_instances[pc->reg_instance_nr++];
163 *dup = *reg;
164 reg->mod = 0;
165 }
166 return dup;
167 }
168
169 static INLINE void
170 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
171 {
172 reg->type = type;
173 reg->index = index;
174 reg->hw = hw;
175 reg->mod = 0;
176 reg->rhw = -1;
177 reg->acc = 0;
178 }
179
180 static INLINE unsigned
181 popcnt4(uint32_t val)
182 {
183 static const unsigned cnt[16]
184 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
185 return cnt[val & 0xf];
186 }
187
188 static void
189 terminate_mbb(struct nv50_pc *pc)
190 {
191 int i;
192
193 /* remove records of temporary address register values */
194 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
195 if (pc->r_addr[i].index < 0)
196 pc->r_addr[i].rhw = -1;
197 }
198
199 static void
200 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
201 {
202 int i = 0;
203
204 if (reg->type == P_RESULT) {
205 if (pc->p->cfg.high_result < (reg->hw + 1))
206 pc->p->cfg.high_result = reg->hw + 1;
207 }
208
209 if (reg->type != P_TEMP)
210 return;
211
212 if (reg->hw >= 0) {
213 /*XXX: do this here too to catch FP temp-as-attr usage..
214 * not clean, but works */
215 if (pc->p->cfg.high_temp < (reg->hw + 1))
216 pc->p->cfg.high_temp = reg->hw + 1;
217 return;
218 }
219
220 if (reg->rhw != -1) {
221 /* try to allocate temporary with index rhw first */
222 if (!(pc->r_temp[reg->rhw])) {
223 pc->r_temp[reg->rhw] = reg;
224 reg->hw = reg->rhw;
225 if (pc->p->cfg.high_temp < (reg->rhw + 1))
226 pc->p->cfg.high_temp = reg->rhw + 1;
227 return;
228 }
229 /* make sure we don't get things like $r0 needs to go
230 * in $r1 and $r1 in $r0
231 */
232 i = pc->result_nr * 4;
233 }
234
235 for (; i < NV50_SU_MAX_TEMP; i++) {
236 if (!(pc->r_temp[i])) {
237 pc->r_temp[i] = reg;
238 reg->hw = i;
239 if (pc->p->cfg.high_temp < (i + 1))
240 pc->p->cfg.high_temp = i + 1;
241 return;
242 }
243 }
244
245 assert(0);
246 }
247
248 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
249 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
250 * lest we risk temp_temps overwriting regs alloc'd "later".
251 */
252 static struct nv50_reg *
253 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
254 {
255 struct nv50_reg *r;
256 int i;
257
258 if (dst && dst->type == P_TEMP && dst->hw == -1)
259 return dst;
260
261 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
262 if (!pc->r_temp[i]) {
263 r = MALLOC_STRUCT(nv50_reg);
264 ctor_reg(r, P_TEMP, -1, i);
265 pc->r_temp[i] = r;
266 return r;
267 }
268 }
269
270 assert(0);
271 return NULL;
272 }
273
274 /* Assign the hw of the discarded temporary register src
275 * to the tgsi register dst and free src.
276 */
277 static void
278 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
279 {
280 assert(src->index == -1 && src->hw != -1);
281
282 if (dst->hw != -1)
283 pc->r_temp[dst->hw] = NULL;
284 pc->r_temp[src->hw] = dst;
285 dst->hw = src->hw;
286
287 FREE(src);
288 }
289
290 /* release the hardware resource held by r */
291 static void
292 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
293 {
294 assert(r->type == P_TEMP);
295 if (r->hw == -1)
296 return;
297
298 assert(pc->r_temp[r->hw] == r);
299 pc->r_temp[r->hw] = NULL;
300
301 r->acc = 0;
302 if (r->index == -1)
303 FREE(r);
304 }
305
306 static void
307 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
308 {
309 if (r->index == -1) {
310 unsigned hw = r->hw;
311
312 FREE(pc->r_temp[hw]);
313 pc->r_temp[hw] = NULL;
314 }
315 }
316
317 static int
318 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
319 {
320 int i;
321
322 if ((idx + 4) >= NV50_SU_MAX_TEMP)
323 return 1;
324
325 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
326 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
327 return alloc_temp4(pc, dst, idx + 4);
328
329 for (i = 0; i < 4; i++) {
330 dst[i] = MALLOC_STRUCT(nv50_reg);
331 ctor_reg(dst[i], P_TEMP, -1, idx + i);
332 pc->r_temp[idx + i] = dst[i];
333 }
334
335 return 0;
336 }
337
338 static void
339 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
340 {
341 int i;
342
343 for (i = 0; i < 4; i++)
344 free_temp(pc, reg[i]);
345 }
346
347 static struct nv50_reg *
348 temp_temp(struct nv50_pc *pc)
349 {
350 if (pc->temp_temp_nr >= 16)
351 assert(0);
352
353 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
354 return pc->temp_temp[pc->temp_temp_nr++];
355 }
356
357 static void
358 kill_temp_temp(struct nv50_pc *pc)
359 {
360 int i;
361
362 for (i = 0; i < pc->temp_temp_nr; i++)
363 free_temp(pc, pc->temp_temp[i]);
364 pc->temp_temp_nr = 0;
365 }
366
367 static int
368 ctor_immd(struct nv50_pc *pc, float x, float y, float z, float w)
369 {
370 pc->immd_buf = REALLOC(pc->immd_buf, (pc->immd_nr * 4 * sizeof(float)),
371 (pc->immd_nr + 1) * 4 * sizeof(float));
372 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
373 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
374 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
375 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
376
377 return pc->immd_nr++;
378 }
379
380 static int
381 ctor_immd_4u32(struct nv50_pc *pc, uint32_t x, uint32_t y, uint32_t z, uint32_t w)
382 {
383 pc->immd_buf = REALLOC(pc->immd_buf, (pc->immd_nr * 4 * sizeof(uint32_t)),
384 (pc->immd_nr + 1) * 4 * sizeof(uint32_t));
385 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
386 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
387 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
388 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
389
390 return pc->immd_nr++;
391 }
392
393 static struct nv50_reg *
394 alloc_immd(struct nv50_pc *pc, float f)
395 {
396 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
397 unsigned hw;
398
399 for (hw = 0; hw < pc->immd_nr * 4; hw++)
400 if (pc->immd_buf[hw] == f)
401 break;
402
403 if (hw == pc->immd_nr * 4)
404 hw = ctor_immd(pc, f, -f, 0.5 * f, 0) * 4;
405
406 ctor_reg(r, P_IMMD, -1, hw);
407 return r;
408 }
409
410 static struct nv50_program_exec *
411 exec(struct nv50_pc *pc)
412 {
413 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
414
415 e->param.index = -1;
416 return e;
417 }
418
419 static void
420 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
421 {
422 struct nv50_program *p = pc->p;
423
424 if (p->exec_tail)
425 p->exec_tail->next = e;
426 if (!p->exec_head)
427 p->exec_head = e;
428 p->exec_tail = e;
429 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
430 }
431
432 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
433
434 static boolean
435 is_long(struct nv50_program_exec *e)
436 {
437 if (e->inst[0] & 1)
438 return TRUE;
439 return FALSE;
440 }
441
442 static boolean
443 is_immd(struct nv50_program_exec *e)
444 {
445 if (is_long(e) && (e->inst[1] & 3) == 3)
446 return TRUE;
447 return FALSE;
448 }
449
450 static INLINE void
451 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
452 struct nv50_program_exec *e)
453 {
454 set_long(pc, e);
455 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
456 e->inst[1] |= (pred << 7) | (idx << 12);
457 }
458
459 static INLINE void
460 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
461 struct nv50_program_exec *e)
462 {
463 set_long(pc, e);
464 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
465 e->inst[1] |= (idx << 4) | (on << 6);
466 }
467
468 static INLINE void
469 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
470 {
471 if (is_long(e))
472 return;
473
474 e->inst[0] |= 1;
475 set_pred(pc, 0xf, 0, e);
476 set_pred_wr(pc, 0, 0, e);
477 }
478
479 static INLINE void
480 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
481 {
482 if (dst->type == P_RESULT) {
483 set_long(pc, e);
484 e->inst[1] |= 0x00000008;
485 }
486
487 alloc_reg(pc, dst);
488 if (dst->hw > 63)
489 set_long(pc, e);
490 e->inst[0] |= (dst->hw << 2);
491 }
492
493 static INLINE void
494 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
495 {
496 unsigned val;
497 float f = pc->immd_buf[imm->hw];
498
499 if (imm->mod & NV50_MOD_ABS)
500 f = fabsf(f);
501 val = fui((imm->mod & NV50_MOD_NEG) ? -f : f);
502
503 set_long(pc, e);
504 /*XXX: can't be predicated - bits overlap.. catch cases where both
505 * are required and avoid them. */
506 set_pred(pc, 0, 0, e);
507 set_pred_wr(pc, 0, 0, e);
508
509 e->inst[1] |= 0x00000002 | 0x00000001;
510 e->inst[0] |= (val & 0x3f) << 16;
511 e->inst[1] |= (val >> 6) << 2;
512 }
513
514 static INLINE void
515 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
516 {
517 assert(!(e->inst[0] & 0x0c000000));
518 assert(!(e->inst[1] & 0x00000004));
519
520 e->inst[0] |= (a->hw & 3) << 26;
521 e->inst[1] |= (a->hw >> 2) << 2;
522 }
523
524 static void
525 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
526 struct nv50_reg *src0, uint16_t src1_val)
527 {
528 struct nv50_program_exec *e = exec(pc);
529
530 e->inst[0] = 0xd0000000 | (src1_val << 9);
531 e->inst[1] = 0x20000000;
532 set_long(pc, e);
533 e->inst[0] |= dst->hw << 2;
534 if (src0) /* otherwise will add to $a0, which is always 0 */
535 set_addr(e, src0);
536
537 emit(pc, e);
538 }
539
540 static struct nv50_reg *
541 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
542 {
543 int i;
544 struct nv50_reg *a_tgsi = NULL, *a = NULL;
545
546 if (!ref) {
547 /* allocate for TGSI address reg */
548 for (i = 0; i < NV50_SU_MAX_ADDR; ++i) {
549 if (pc->r_addr[i].index >= 0)
550 continue;
551 if (pc->r_addr[i].rhw >= 0 &&
552 pc->r_addr[i].acc == pc->insn_cur)
553 continue;
554
555 pc->r_addr[i].rhw = -1;
556 pc->r_addr[i].index = i;
557 return &pc->r_addr[i];
558 }
559 assert(0);
560 return NULL;
561 }
562
563 /* Allocate and set an address reg so we can access 'ref'.
564 *
565 * If and r_addr has index < 0, it is not reserved for TGSI,
566 * and index will be the negative of the TGSI addr index the
567 * value in rhw is relative to, or -256 if rhw is an offset
568 * from 0. If rhw < 0, the reg has not been initialized.
569 */
570 for (i = NV50_SU_MAX_ADDR - 1; i >= 0; --i) {
571 if (pc->r_addr[i].index >= 0) /* occupied for TGSI */
572 continue;
573 if (pc->r_addr[i].rhw < 0) { /* unused */
574 a = &pc->r_addr[i];
575 continue;
576 }
577 if (!a && pc->r_addr[i].acc != pc->insn_cur)
578 a = &pc->r_addr[i];
579
580 if (ref->hw - pc->r_addr[i].rhw >= 128)
581 continue;
582
583 if ((ref->acc >= 0 && pc->r_addr[i].index == -256) ||
584 (ref->acc < 0 && -pc->r_addr[i].index == ref->index)) {
585 pc->r_addr[i].acc = pc->insn_cur;
586 return &pc->r_addr[i];
587 }
588 }
589 assert(a);
590
591 if (ref->acc < 0)
592 a_tgsi = pc->addr[ref->index];
593
594 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
595
596 a->rhw = ref->hw & ~0x7f;
597 a->acc = pc->insn_cur;
598 a->index = a_tgsi ? -ref->index : -256;
599 return a;
600 }
601
602 #define INTERP_LINEAR 0
603 #define INTERP_FLAT 1
604 #define INTERP_PERSPECTIVE 2
605 #define INTERP_CENTROID 4
606
607 /* interpolant index has been stored in dst->rhw */
608 static void
609 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
610 unsigned mode)
611 {
612 assert(dst->rhw != -1);
613 struct nv50_program_exec *e = exec(pc);
614
615 e->inst[0] |= 0x80000000;
616 set_dst(pc, dst, e);
617 e->inst[0] |= (dst->rhw << 16);
618
619 if (mode & INTERP_FLAT) {
620 e->inst[0] |= (1 << 8);
621 } else {
622 if (mode & INTERP_PERSPECTIVE) {
623 e->inst[0] |= (1 << 25);
624 alloc_reg(pc, iv);
625 e->inst[0] |= (iv->hw << 9);
626 }
627
628 if (mode & INTERP_CENTROID)
629 e->inst[0] |= (1 << 24);
630 }
631
632 emit(pc, e);
633 }
634
635 static void
636 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
637 struct nv50_program_exec *e)
638 {
639 set_long(pc, e);
640
641 e->param.index = src->hw & 127;
642 e->param.shift = s;
643 e->param.mask = m << (s % 32);
644
645 if (src->hw > 127)
646 set_addr(e, alloc_addr(pc, src));
647 else
648 if (src->acc < 0) {
649 assert(src->type == P_CONST);
650 set_addr(e, pc->addr[src->index]);
651 }
652
653 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
654 }
655
656 static void
657 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
658 {
659 struct nv50_program_exec *e = exec(pc);
660
661 e->inst[0] = 0x10000000;
662 if (!pc->allow32)
663 set_long(pc, e);
664
665 set_dst(pc, dst, e);
666
667 if (!is_long(e) && src->type == P_IMMD) {
668 set_immd(pc, src, e);
669 /*XXX: 32-bit, but steals part of "half" reg space - need to
670 * catch and handle this case if/when we do half-regs
671 */
672 } else
673 if (src->type == P_IMMD || src->type == P_CONST) {
674 set_long(pc, e);
675 set_data(pc, src, 0x7f, 9, e);
676 e->inst[1] |= 0x20000000; /* mov from c[] */
677 } else {
678 if (src->type == P_ATTR) {
679 set_long(pc, e);
680 e->inst[1] |= 0x00200000;
681 }
682
683 alloc_reg(pc, src);
684 if (src->hw > 63)
685 set_long(pc, e);
686 e->inst[0] |= (src->hw << 9);
687 }
688
689 if (is_long(e) && !is_immd(e)) {
690 e->inst[1] |= 0x04000000; /* 32-bit */
691 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
692 if (!(e->inst[1] & 0x20000000))
693 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
694 } else
695 e->inst[0] |= 0x00008000;
696
697 emit(pc, e);
698 }
699
700 static INLINE void
701 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
702 {
703 struct nv50_reg *imm = alloc_immd(pc, f);
704 emit_mov(pc, dst, imm);
705 FREE(imm);
706 }
707
708 static void
709 emit_nop(struct nv50_pc *pc)
710 {
711 struct nv50_program_exec *e = exec(pc);
712
713 e->inst[0] = 0xf0000000;
714 set_long(pc, e);
715 e->inst[1] = 0xe0000000;
716 emit(pc, e);
717 }
718
719 static boolean
720 check_swap_src_0_1(struct nv50_pc *pc,
721 struct nv50_reg **s0, struct nv50_reg **s1)
722 {
723 struct nv50_reg *src0 = *s0, *src1 = *s1;
724
725 if (src0->type == P_CONST) {
726 if (src1->type != P_CONST) {
727 *s0 = src1;
728 *s1 = src0;
729 return TRUE;
730 }
731 } else
732 if (src1->type == P_ATTR) {
733 if (src0->type != P_ATTR) {
734 *s0 = src1;
735 *s1 = src0;
736 return TRUE;
737 }
738 }
739
740 return FALSE;
741 }
742
743 static void
744 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
745 struct nv50_program_exec *e)
746 {
747 struct nv50_reg *temp;
748
749 if (src->type != P_TEMP) {
750 temp = temp_temp(pc);
751 emit_mov(pc, temp, src);
752 src = temp;
753 }
754
755 alloc_reg(pc, src);
756 if (src->hw > 63)
757 set_long(pc, e);
758 e->inst[0] |= (src->hw << 9);
759 }
760
761 static void
762 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
763 {
764 if (src->type == P_ATTR) {
765 set_long(pc, e);
766 e->inst[1] |= 0x00200000;
767 } else
768 if (src->type == P_CONST || src->type == P_IMMD) {
769 struct nv50_reg *temp = temp_temp(pc);
770
771 emit_mov(pc, temp, src);
772 src = temp;
773 }
774
775 alloc_reg(pc, src);
776 if (src->hw > 63)
777 set_long(pc, e);
778 e->inst[0] |= (src->hw << 9);
779 }
780
781 static void
782 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
783 {
784 if (src->type == P_ATTR) {
785 struct nv50_reg *temp = temp_temp(pc);
786
787 emit_mov(pc, temp, src);
788 src = temp;
789 } else
790 if (src->type == P_CONST || src->type == P_IMMD) {
791 assert(!(e->inst[0] & 0x00800000));
792 if (e->inst[0] & 0x01000000) {
793 struct nv50_reg *temp = temp_temp(pc);
794
795 emit_mov(pc, temp, src);
796 src = temp;
797 } else {
798 set_data(pc, src, 0x7f, 16, e);
799 e->inst[0] |= 0x00800000;
800 }
801 }
802
803 alloc_reg(pc, src);
804 if (src->hw > 63)
805 set_long(pc, e);
806 e->inst[0] |= ((src->hw & 127) << 16);
807 }
808
809 static void
810 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
811 {
812 set_long(pc, e);
813
814 if (src->type == P_ATTR) {
815 struct nv50_reg *temp = temp_temp(pc);
816
817 emit_mov(pc, temp, src);
818 src = temp;
819 } else
820 if (src->type == P_CONST || src->type == P_IMMD) {
821 assert(!(e->inst[0] & 0x01000000));
822 if (e->inst[0] & 0x00800000) {
823 struct nv50_reg *temp = temp_temp(pc);
824
825 emit_mov(pc, temp, src);
826 src = temp;
827 } else {
828 set_data(pc, src, 0x7f, 32+14, e);
829 e->inst[0] |= 0x01000000;
830 }
831 }
832
833 alloc_reg(pc, src);
834 e->inst[1] |= ((src->hw & 127) << 14);
835 }
836
837 static void
838 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
839 {
840 struct nv50_program_exec *e = exec(pc);
841
842 assert(dst->type == P_TEMP);
843 e->inst[1] = 0x20000000 | (pred << 12);
844 set_long(pc, e);
845 set_dst(pc, dst, e);
846
847 emit(pc, e);
848 }
849
850 static void
851 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
852 {
853 struct nv50_program_exec *e = exec(pc);
854
855 e->inst[0] = 0x000001fc;
856 e->inst[1] = 0xa0000008;
857 set_long(pc, e);
858 set_pred_wr(pc, 1, pred, e);
859 set_src_0_restricted(pc, src, e);
860
861 emit(pc, e);
862 }
863
864 static void
865 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
866 struct nv50_reg *src1)
867 {
868 struct nv50_program_exec *e = exec(pc);
869
870 e->inst[0] |= 0xc0000000;
871
872 if (!pc->allow32)
873 set_long(pc, e);
874
875 check_swap_src_0_1(pc, &src0, &src1);
876 set_dst(pc, dst, e);
877 set_src_0(pc, src0, e);
878 if (src1->type == P_IMMD && !is_long(e)) {
879 if (src0->mod & NV50_MOD_NEG)
880 e->inst[0] |= 0x00008000;
881 set_immd(pc, src1, e);
882 } else {
883 set_src_1(pc, src1, e);
884 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
885 if (is_long(e))
886 e->inst[1] |= 0x08000000;
887 else
888 e->inst[0] |= 0x00008000;
889 }
890 }
891
892 emit(pc, e);
893 }
894
895 static void
896 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
897 struct nv50_reg *src0, struct nv50_reg *src1)
898 {
899 struct nv50_program_exec *e = exec(pc);
900
901 e->inst[0] = 0xb0000000;
902
903 alloc_reg(pc, src1);
904 check_swap_src_0_1(pc, &src0, &src1);
905
906 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
907 set_long(pc, e);
908 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
909 ((src1->mod & NV50_MOD_NEG) << 27);
910 }
911
912 set_dst(pc, dst, e);
913 set_src_0(pc, src0, e);
914 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
915 set_src_2(pc, src1, e);
916 else
917 if (src1->type == P_IMMD)
918 set_immd(pc, src1, e);
919 else
920 set_src_1(pc, src1, e);
921
922 emit(pc, e);
923 }
924
925 static void
926 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
927 uint8_t s)
928 {
929 struct nv50_program_exec *e = exec(pc);
930
931 set_long(pc, e);
932 e->inst[1] |= 0xc0000000;
933
934 e->inst[0] |= dst->hw << 2;
935 e->inst[0] |= s << 16; /* shift left */
936 set_src_0_restricted(pc, src, e);
937
938 emit(pc, e);
939 }
940
941 static void
942 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
943 struct nv50_reg *src0, struct nv50_reg *src1)
944 {
945 struct nv50_program_exec *e = exec(pc);
946
947 set_long(pc, e);
948 e->inst[0] |= 0xb0000000;
949 e->inst[1] |= (sub << 29);
950
951 check_swap_src_0_1(pc, &src0, &src1);
952 set_dst(pc, dst, e);
953 set_src_0(pc, src0, e);
954 set_src_1(pc, src1, e);
955
956 if (src0->mod & NV50_MOD_ABS)
957 e->inst[1] |= 0x00100000;
958 if (src1->mod & NV50_MOD_ABS)
959 e->inst[1] |= 0x00080000;
960
961 emit(pc, e);
962 }
963
964 static INLINE void
965 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
966 struct nv50_reg *src1)
967 {
968 src1->mod ^= NV50_MOD_NEG;
969 emit_add(pc, dst, src0, src1);
970 src1->mod ^= NV50_MOD_NEG;
971 }
972
973 static void
974 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
975 struct nv50_reg *src1, unsigned op)
976 {
977 struct nv50_program_exec *e = exec(pc);
978
979 e->inst[0] = 0xd0000000;
980 set_long(pc, e);
981
982 check_swap_src_0_1(pc, &src0, &src1);
983 set_dst(pc, dst, e);
984 set_src_0(pc, src0, e);
985
986 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
987 op != TGSI_OPCODE_XOR)
988 assert(!"invalid bit op");
989
990 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
991 set_immd(pc, src1, e);
992 if (op == TGSI_OPCODE_OR)
993 e->inst[0] |= 0x0100;
994 else
995 if (op == TGSI_OPCODE_XOR)
996 e->inst[0] |= 0x8000;
997 } else {
998 set_src_1(pc, src1, e);
999 e->inst[1] |= 0x04000000; /* 32 bit */
1000 if (op == TGSI_OPCODE_OR)
1001 e->inst[1] |= 0x4000;
1002 else
1003 if (op == TGSI_OPCODE_XOR)
1004 e->inst[1] |= 0x8000;
1005 }
1006
1007 emit(pc, e);
1008 }
1009
1010 static void
1011 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1012 struct nv50_reg *src1, struct nv50_reg *src2)
1013 {
1014 struct nv50_program_exec *e = exec(pc);
1015
1016 e->inst[0] |= 0xe0000000;
1017
1018 check_swap_src_0_1(pc, &src0, &src1);
1019 set_dst(pc, dst, e);
1020 set_src_0(pc, src0, e);
1021 set_src_1(pc, src1, e);
1022 set_src_2(pc, src2, e);
1023
1024 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1025 e->inst[1] |= 0x04000000;
1026 if (src2->mod & NV50_MOD_NEG)
1027 e->inst[1] |= 0x08000000;
1028
1029 emit(pc, e);
1030 }
1031
1032 static INLINE void
1033 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1034 struct nv50_reg *src1, struct nv50_reg *src2)
1035 {
1036 src2->mod ^= NV50_MOD_NEG;
1037 emit_mad(pc, dst, src0, src1, src2);
1038 src2->mod ^= NV50_MOD_NEG;
1039 }
1040
1041 static void
1042 emit_flop(struct nv50_pc *pc, unsigned sub,
1043 struct nv50_reg *dst, struct nv50_reg *src)
1044 {
1045 struct nv50_program_exec *e = exec(pc);
1046
1047 e->inst[0] |= 0x90000000;
1048 if (sub) {
1049 set_long(pc, e);
1050 e->inst[1] |= (sub << 29);
1051 }
1052
1053 set_dst(pc, dst, e);
1054
1055 if (sub == 0 || sub == 2)
1056 set_src_0_restricted(pc, src, e);
1057 else
1058 set_src_0(pc, src, e);
1059
1060 emit(pc, e);
1061 }
1062
1063 static void
1064 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1065 {
1066 struct nv50_program_exec *e = exec(pc);
1067
1068 e->inst[0] |= 0xb0000000;
1069
1070 set_dst(pc, dst, e);
1071 set_src_0(pc, src, e);
1072 set_long(pc, e);
1073 e->inst[1] |= (6 << 29) | 0x00004000;
1074
1075 emit(pc, e);
1076 }
1077
1078 static void
1079 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1080 {
1081 struct nv50_program_exec *e = exec(pc);
1082
1083 e->inst[0] |= 0xb0000000;
1084
1085 set_dst(pc, dst, e);
1086 set_src_0(pc, src, e);
1087 set_long(pc, e);
1088 e->inst[1] |= (6 << 29);
1089
1090 emit(pc, e);
1091 }
1092
1093 #define CVTOP_RN 0x01
1094 #define CVTOP_FLOOR 0x03
1095 #define CVTOP_CEIL 0x05
1096 #define CVTOP_TRUNC 0x07
1097 #define CVTOP_SAT 0x08
1098 #define CVTOP_ABS 0x10
1099
1100 /* 0x04 == 32 bit dst */
1101 /* 0x40 == dst is float */
1102 /* 0x80 == src is float */
1103 #define CVT_F32_F32 0xc4
1104 #define CVT_F32_S32 0x44
1105 #define CVT_S32_F32 0x8c
1106 #define CVT_S32_S32 0x0c
1107 #define CVT_NEG 0x20
1108 #define CVT_RI 0x08
1109
1110 static void
1111 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1112 int wp, unsigned cvn, unsigned fmt)
1113 {
1114 struct nv50_program_exec *e;
1115
1116 e = exec(pc);
1117 set_long(pc, e);
1118
1119 e->inst[0] |= 0xa0000000;
1120 e->inst[1] |= 0x00004000; /* 32 bit src */
1121 e->inst[1] |= (cvn << 16);
1122 e->inst[1] |= (fmt << 24);
1123 set_src_0(pc, src, e);
1124
1125 if (wp >= 0)
1126 set_pred_wr(pc, 1, wp, e);
1127
1128 if (dst)
1129 set_dst(pc, dst, e);
1130 else {
1131 e->inst[0] |= 0x000001fc;
1132 e->inst[1] |= 0x00000008;
1133 }
1134
1135 emit(pc, e);
1136 }
1137
1138 /* nv50 Condition codes:
1139 * 0x1 = LT
1140 * 0x2 = EQ
1141 * 0x3 = LE
1142 * 0x4 = GT
1143 * 0x5 = NE
1144 * 0x6 = GE
1145 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1146 * 0x8 = unordered bit (allows NaN)
1147 */
1148 static void
1149 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1150 struct nv50_reg *src0, struct nv50_reg *src1)
1151 {
1152 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1153
1154 struct nv50_program_exec *e = exec(pc);
1155 struct nv50_reg *rdst;
1156
1157 assert(ccode < 16);
1158 if (check_swap_src_0_1(pc, &src0, &src1))
1159 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1160
1161 rdst = dst;
1162 if (dst && dst->type != P_TEMP)
1163 dst = alloc_temp(pc, NULL);
1164
1165 /* set.u32 */
1166 set_long(pc, e);
1167 e->inst[0] |= 0xb0000000;
1168 e->inst[1] |= 0x60000000 | (ccode << 14);
1169
1170 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1171 * that doesn't seem to match what the hw actually does
1172 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1173 */
1174
1175 if (wp >= 0)
1176 set_pred_wr(pc, 1, wp, e);
1177 if (dst)
1178 set_dst(pc, dst, e);
1179 else {
1180 e->inst[0] |= 0x000001fc;
1181 e->inst[1] |= 0x00000008;
1182 }
1183
1184 set_src_0(pc, src0, e);
1185 set_src_1(pc, src1, e);
1186
1187 emit(pc, e);
1188 pc->if_cond = pc->p->exec_tail; /* record for OPCODE_IF */
1189
1190 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1191 if (rdst)
1192 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
1193 if (rdst && rdst != dst)
1194 free_temp(pc, dst);
1195 }
1196
1197 static INLINE unsigned
1198 map_tgsi_setop_cc(unsigned op)
1199 {
1200 switch (op) {
1201 case TGSI_OPCODE_SLT: return 0x1;
1202 case TGSI_OPCODE_SGE: return 0x6;
1203 case TGSI_OPCODE_SEQ: return 0x2;
1204 case TGSI_OPCODE_SGT: return 0x4;
1205 case TGSI_OPCODE_SLE: return 0x3;
1206 case TGSI_OPCODE_SNE: return 0xd;
1207 default:
1208 assert(0);
1209 return 0;
1210 }
1211 }
1212
1213 static INLINE void
1214 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1215 {
1216 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
1217 }
1218
1219 static void
1220 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1221 struct nv50_reg *v, struct nv50_reg *e)
1222 {
1223 struct nv50_reg *temp = alloc_temp(pc, NULL);
1224
1225 emit_flop(pc, 3, temp, v);
1226 emit_mul(pc, temp, temp, e);
1227 emit_preex2(pc, temp, temp);
1228 emit_flop(pc, 6, dst, temp);
1229
1230 free_temp(pc, temp);
1231 }
1232
1233 static INLINE void
1234 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1235 {
1236 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
1237 }
1238
1239 static INLINE void
1240 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1241 {
1242 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
1243 }
1244
1245 static void
1246 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1247 struct nv50_reg **src)
1248 {
1249 struct nv50_reg *one = alloc_immd(pc, 1.0);
1250 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1251 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1252 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1253 struct nv50_reg *tmp[4];
1254 boolean allow32 = pc->allow32;
1255
1256 pc->allow32 = FALSE;
1257
1258 if (mask & (3 << 1)) {
1259 tmp[0] = alloc_temp(pc, NULL);
1260 emit_minmax(pc, 4, tmp[0], src[0], zero);
1261 }
1262
1263 if (mask & (1 << 2)) {
1264 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1265
1266 tmp[1] = temp_temp(pc);
1267 emit_minmax(pc, 4, tmp[1], src[1], zero);
1268
1269 tmp[3] = temp_temp(pc);
1270 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1271 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1272
1273 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1274 emit_mov(pc, dst[2], zero);
1275 set_pred(pc, 3, 0, pc->p->exec_tail);
1276 }
1277
1278 if (mask & (1 << 1))
1279 assimilate_temp(pc, dst[1], tmp[0]);
1280 else
1281 if (mask & (1 << 2))
1282 free_temp(pc, tmp[0]);
1283
1284 pc->allow32 = allow32;
1285
1286 /* do this last, in case src[i,j] == dst[0,3] */
1287 if (mask & (1 << 0))
1288 emit_mov(pc, dst[0], one);
1289
1290 if (mask & (1 << 3))
1291 emit_mov(pc, dst[3], one);
1292
1293 FREE(pos128);
1294 FREE(neg128);
1295 FREE(zero);
1296 FREE(one);
1297 }
1298
1299 static INLINE void
1300 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1301 {
1302 emit_cvt(pc, dst, src, -1, CVTOP_RN, CVT_F32_F32 | CVT_NEG);
1303 }
1304
1305 static void
1306 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1307 {
1308 struct nv50_program_exec *e;
1309 const int r_pred = 1;
1310 unsigned cvn = CVT_F32_F32;
1311
1312 if (src->mod & NV50_MOD_NEG)
1313 cvn |= CVT_NEG;
1314 /* write predicate reg */
1315 emit_cvt(pc, NULL, src, r_pred, CVTOP_RN, cvn);
1316
1317 /* conditional discard */
1318 e = exec(pc);
1319 e->inst[0] = 0x00000002;
1320 set_long(pc, e);
1321 set_pred(pc, 0x1 /* LT */, r_pred, e);
1322 emit(pc, e);
1323 }
1324
1325 static struct nv50_program_exec *
1326 emit_branch(struct nv50_pc *pc, int pred, unsigned cc,
1327 struct nv50_program_exec **join)
1328 {
1329 struct nv50_program_exec *e = exec(pc);
1330
1331 if (join) {
1332 set_long(pc, e);
1333 e->inst[0] |= 0xa0000002;
1334 emit(pc, e);
1335 *join = e;
1336 e = exec(pc);
1337 }
1338
1339 set_long(pc, e);
1340 e->inst[0] |= 0x10000002;
1341 if (pred >= 0)
1342 set_pred(pc, cc, pred, e);
1343 emit(pc, e);
1344 return pc->p->exec_tail;
1345 }
1346
1347 #define QOP_ADD 0
1348 #define QOP_SUBR 1
1349 #define QOP_SUB 2
1350 #define QOP_MOV_SRC1 3
1351
1352 /* For a quad of threads / top left, top right, bottom left, bottom right
1353 * pixels, do a different operation, and take src0 from a specific thread.
1354 */
1355 static void
1356 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1357 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1358 {
1359 struct nv50_program_exec *e = exec(pc);
1360
1361 e->inst[0] = 0xc0000000;
1362 e->inst[1] = 0x80000000;
1363 set_long(pc, e);
1364 e->inst[0] |= lane_src0 << 16;
1365 set_src_0(pc, src0, e);
1366 set_src_2(pc, src1, e);
1367
1368 if (wp >= 0)
1369 set_pred_wr(pc, 1, wp, e);
1370
1371 if (dst)
1372 set_dst(pc, dst, e);
1373 else {
1374 e->inst[0] |= 0x000001fc;
1375 e->inst[1] |= 0x00000008;
1376 }
1377
1378 e->inst[0] |= (qop & 3) << 20;
1379 e->inst[1] |= (qop >> 2) << 22;
1380
1381 emit(pc, e);
1382 }
1383
1384 static void
1385 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1386 struct nv50_reg **src, unsigned arg, boolean proj)
1387 {
1388 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1389
1390 src[0]->mod |= NV50_MOD_ABS;
1391 src[1]->mod |= NV50_MOD_ABS;
1392 src[2]->mod |= NV50_MOD_ABS;
1393
1394 emit_minmax(pc, 4, t[2], src[0], src[1]);
1395 emit_minmax(pc, 4, t[2], src[2], t[2]);
1396
1397 src[0]->mod = mod[0];
1398 src[1]->mod = mod[1];
1399 src[2]->mod = mod[2];
1400
1401 if (proj && 0 /* looks more correct without this */)
1402 emit_mul(pc, t[2], t[2], src[3]);
1403 else
1404 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1405 emit_mov(pc, t[3], src[3]);
1406
1407 emit_flop(pc, 0, t[2], t[2]);
1408
1409 emit_mul(pc, t[0], src[0], t[2]);
1410 emit_mul(pc, t[1], src[1], t[2]);
1411 emit_mul(pc, t[2], src[2], t[2]);
1412 }
1413
1414 static void
1415 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1416 struct nv50_reg **src, unsigned dim, unsigned arg)
1417 {
1418 unsigned c, mode;
1419
1420 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1421 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1422
1423 t[3]->rhw = src[3]->rhw;
1424 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1425 emit_flop(pc, 0, t[3], t[3]);
1426
1427 for (c = 0; c < dim; ++c) {
1428 t[c]->rhw = src[c]->rhw;
1429 emit_interp(pc, t[c], t[3], mode);
1430 }
1431 if (arg != dim) { /* depth reference value */
1432 t[dim]->rhw = src[2]->rhw;
1433 emit_interp(pc, t[dim], t[3], mode);
1434 }
1435 } else {
1436 /* XXX: for some reason the blob sometimes uses MAD
1437 * (mad f32 $rX $rY $rZ neg $r63)
1438 */
1439 emit_flop(pc, 0, t[3], src[3]);
1440 for (c = 0; c < dim; ++c)
1441 emit_mul(pc, t[c], src[c], t[3]);
1442 if (arg != dim) /* depth reference value */
1443 emit_mul(pc, t[dim], src[2], t[3]);
1444 }
1445 }
1446
1447 static INLINE void
1448 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1449 {
1450 switch (type) {
1451 case TGSI_TEXTURE_1D:
1452 *arg = *dim = 1;
1453 break;
1454 case TGSI_TEXTURE_SHADOW1D:
1455 *dim = 1;
1456 *arg = 2;
1457 break;
1458 case TGSI_TEXTURE_UNKNOWN:
1459 case TGSI_TEXTURE_2D:
1460 case TGSI_TEXTURE_RECT:
1461 *arg = *dim = 2;
1462 break;
1463 case TGSI_TEXTURE_SHADOW2D:
1464 case TGSI_TEXTURE_SHADOWRECT:
1465 *dim = 2;
1466 *arg = 3;
1467 break;
1468 case TGSI_TEXTURE_3D:
1469 case TGSI_TEXTURE_CUBE:
1470 *dim = *arg = 3;
1471 break;
1472 default:
1473 assert(0);
1474 break;
1475 }
1476 }
1477
1478 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1479 * different LOD values, so branch off groups of equal LOD.
1480 */
1481 static void
1482 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1483 struct nv50_reg *src, struct nv50_program_exec *tex)
1484 {
1485 struct nv50_program_exec *join_at;
1486 unsigned i, target = pc->p->exec_size + 7 * 2;
1487
1488 /* Subtract lod of each pixel from lod of top left pixel, jump
1489 * texlod insn if result is 0, then repeat for 2 other pixels.
1490 */
1491 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1492 emit_branch(pc, 0, 2, &join_at)->param.index = target;
1493
1494 for (i = 1; i < 4; ++i) {
1495 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1496 emit_branch(pc, 0, 2, NULL)->param.index = target;
1497 }
1498
1499 emit_mov(pc, tlod, src); /* target */
1500 emit(pc, tex); /* texlod */
1501
1502 join_at->param.index = target + 2 * 2;
1503 emit_nop(pc);
1504 pc->p->exec_tail->inst[1] |= 2; /* join _after_ tex */
1505 }
1506
1507 static void
1508 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1509 struct nv50_program_exec *tex)
1510 {
1511 struct nv50_program_exec *e;
1512 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1513 int r_pred = 0;
1514 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1515
1516 pc->allow32 = FALSE;
1517 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1518
1519 /* Subtract bias value of thread i from bias values of each thread,
1520 * store result in r_pred, and set bit i in r_bits if result was 0.
1521 */
1522 assert(arg < 4);
1523 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1524 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1525 emit_mov(pc, r_bits, &imm_1248);
1526 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1527 }
1528 emit_mov_to_pred(pc, r_pred, r_bits);
1529
1530 /* The lanes of a quad are now grouped by the bit in r_pred they have
1531 * set. Put the input values for TEX into a new register set for each
1532 * group and execute TEX only for a specific group.
1533 * We cannot use the same register set for each group because we need
1534 * the derivatives, which are implicitly calculated, to be correct.
1535 */
1536 for (i = 1; i < 4; ++i) {
1537 alloc_temp4(pc, t123[i], 0);
1538
1539 for (c = 0; c <= arg; ++c)
1540 emit_mov(pc, t123[i][c], t[c]);
1541
1542 *(e = exec(pc)) = *(tex);
1543 e->inst[0] &= ~0x01fc;
1544 set_dst(pc, t123[i][0], e);
1545 set_pred(pc, cc[i], r_pred, e);
1546 emit(pc, e);
1547 }
1548 /* finally TEX on the original regs (where we kept the input) */
1549 set_pred(pc, cc[0], r_pred, tex);
1550 emit(pc, tex);
1551
1552 /* put the 3 * n other results into regs for lane 0 */
1553 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1554 for (i = 1; i < 4; ++i) {
1555 for (c = 0; c < n; ++c) {
1556 emit_mov(pc, t[c], t123[i][c]);
1557 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1558 }
1559 free_temp4(pc, t123[i]);
1560 }
1561
1562 emit_nop(pc);
1563 free_temp(pc, r_bits);
1564 }
1565
1566 static void
1567 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1568 struct nv50_reg **src, unsigned unit, unsigned type,
1569 boolean proj, int bias_lod)
1570 {
1571 struct nv50_reg *t[4];
1572 struct nv50_program_exec *e;
1573 unsigned c, dim, arg;
1574
1575 /* t[i] must be within a single 128 bit super-reg */
1576 alloc_temp4(pc, t, 0);
1577
1578 e = exec(pc);
1579 e->inst[0] = 0xf0000000;
1580 set_long(pc, e);
1581 set_dst(pc, t[0], e);
1582
1583 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1584 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1585
1586 /* live flag (don't set if TEX results affect input to another TEX): */
1587 /* e->inst[0] |= 0x00000004; */
1588
1589 get_tex_dim(type, &dim, &arg);
1590
1591 if (type == TGSI_TEXTURE_CUBE) {
1592 e->inst[0] |= 0x08000000;
1593 load_cube_tex_coords(pc, t, src, arg, proj);
1594 } else
1595 if (proj)
1596 load_proj_tex_coords(pc, t, src, dim, arg);
1597 else {
1598 for (c = 0; c < dim; c++)
1599 emit_mov(pc, t[c], src[c]);
1600 if (arg != dim) /* depth reference value (always src.z here) */
1601 emit_mov(pc, t[dim], src[2]);
1602 }
1603
1604 e->inst[0] |= (mask & 0x3) << 25;
1605 e->inst[1] |= (mask & 0xc) << 12;
1606
1607 if (!bias_lod) {
1608 e->inst[0] |= (arg - 1) << 22;
1609 emit(pc, e);
1610 } else
1611 if (bias_lod < 0) {
1612 e->inst[0] |= arg << 22;
1613 e->inst[1] |= 0x20000000; /* texbias */
1614 emit_mov(pc, t[arg], src[3]);
1615 emit_texbias_sequence(pc, t, arg, e);
1616 } else {
1617 e->inst[0] |= arg << 22;
1618 e->inst[1] |= 0x40000000; /* texlod */
1619 emit_mov(pc, t[arg], src[3]);
1620 emit_texlod_sequence(pc, t[arg], src[3], e);
1621 }
1622
1623 #if 1
1624 c = 0;
1625 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1626 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1627 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1628 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1629
1630 free_temp4(pc, t);
1631 #else
1632 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1633 * the texture coordinates, not the fetched values: latency ? */
1634
1635 for (c = 0; c < 4; c++) {
1636 if (mask & (1 << c))
1637 assimilate_temp(pc, dst[c], t[c]);
1638 else
1639 free_temp(pc, t[c]);
1640 }
1641 #endif
1642 }
1643
1644 static void
1645 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1646 {
1647 struct nv50_program_exec *e = exec(pc);
1648
1649 assert(src->type == P_TEMP);
1650
1651 e->inst[0] = 0xc0140000;
1652 e->inst[1] = 0x89800000;
1653 set_long(pc, e);
1654 set_dst(pc, dst, e);
1655 set_src_0(pc, src, e);
1656 set_src_2(pc, src, e);
1657
1658 emit(pc, e);
1659 }
1660
1661 static void
1662 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1663 {
1664 struct nv50_reg *r = src;
1665 struct nv50_program_exec *e = exec(pc);
1666
1667 assert(src->type == P_TEMP);
1668
1669 if (!(src->mod & NV50_MOD_NEG)) { /* ! double negation */
1670 r = alloc_temp(pc, NULL);
1671 emit_neg(pc, r, src);
1672 }
1673
1674 e->inst[0] = 0xc0150000;
1675 e->inst[1] = 0x8a400000;
1676 set_long(pc, e);
1677 set_dst(pc, dst, e);
1678 set_src_0(pc, r, e);
1679 set_src_2(pc, r, e);
1680
1681 if (r != src)
1682 free_temp(pc, r);
1683
1684 emit(pc, e);
1685 }
1686
1687 static void
1688 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1689 {
1690 unsigned q = 0, m = ~0;
1691
1692 assert(!is_long(e));
1693
1694 switch (e->inst[0] >> 28) {
1695 case 0x1:
1696 /* MOV */
1697 q = 0x0403c000;
1698 m = 0xffff7fff;
1699 break;
1700 case 0x8:
1701 /* INTERP (move centroid, perspective and flat bits) */
1702 m = ~0x03000100;
1703 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1704 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1705 break;
1706 case 0x9:
1707 /* RCP */
1708 break;
1709 case 0xB:
1710 /* ADD */
1711 m = ~(127 << 16);
1712 q = ((e->inst[0] & (~m)) >> 2);
1713 break;
1714 case 0xC:
1715 /* MUL */
1716 m = ~0x00008000;
1717 q = ((e->inst[0] & (~m)) << 12);
1718 break;
1719 case 0xE:
1720 /* MAD (if src2 == dst) */
1721 q = ((e->inst[0] & 0x1fc) << 12);
1722 break;
1723 default:
1724 assert(0);
1725 break;
1726 }
1727
1728 set_long(pc, e);
1729 pc->p->exec_size++;
1730
1731 e->inst[0] &= m;
1732 e->inst[1] |= q;
1733 }
1734
1735 /* Some operations support an optional negation flag. */
1736 static boolean
1737 negate_supported(const struct tgsi_full_instruction *insn, int i)
1738 {
1739 switch (insn->Instruction.Opcode) {
1740 case TGSI_OPCODE_DDY:
1741 case TGSI_OPCODE_DP3:
1742 case TGSI_OPCODE_DP4:
1743 case TGSI_OPCODE_MUL:
1744 case TGSI_OPCODE_KIL:
1745 case TGSI_OPCODE_ADD:
1746 case TGSI_OPCODE_SUB:
1747 case TGSI_OPCODE_MAD:
1748 return TRUE;
1749 case TGSI_OPCODE_POW:
1750 if (i == 1)
1751 return TRUE;
1752 return FALSE;
1753 default:
1754 return FALSE;
1755 }
1756 }
1757
1758 /* Return a read mask for source registers deduced from opcode & write mask. */
1759 static unsigned
1760 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1761 {
1762 unsigned x, mask = insn->Dst[0].Register.WriteMask;
1763
1764 switch (insn->Instruction.Opcode) {
1765 case TGSI_OPCODE_COS:
1766 case TGSI_OPCODE_SIN:
1767 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1768 case TGSI_OPCODE_DP3:
1769 return 0x7;
1770 case TGSI_OPCODE_DP4:
1771 case TGSI_OPCODE_DPH:
1772 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1773 return 0xf;
1774 case TGSI_OPCODE_DST:
1775 return mask & (c ? 0xa : 0x6);
1776 case TGSI_OPCODE_EX2:
1777 case TGSI_OPCODE_LG2:
1778 case TGSI_OPCODE_POW:
1779 case TGSI_OPCODE_RCP:
1780 case TGSI_OPCODE_RSQ:
1781 case TGSI_OPCODE_SCS:
1782 return 0x1;
1783 case TGSI_OPCODE_IF:
1784 return 0x1;
1785 case TGSI_OPCODE_LIT:
1786 return 0xb;
1787 case TGSI_OPCODE_TEX:
1788 case TGSI_OPCODE_TXB:
1789 case TGSI_OPCODE_TXL:
1790 case TGSI_OPCODE_TXP:
1791 {
1792 const struct tgsi_instruction_texture *tex;
1793
1794 assert(insn->Instruction.Texture);
1795 tex = &insn->Texture;
1796
1797 mask = 0x7;
1798 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
1799 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
1800 mask |= 0x8; /* bias, lod or proj */
1801
1802 switch (tex->Texture) {
1803 case TGSI_TEXTURE_1D:
1804 mask &= 0x9;
1805 break;
1806 case TGSI_TEXTURE_SHADOW1D:
1807 mask &= 0x5;
1808 break;
1809 case TGSI_TEXTURE_2D:
1810 mask &= 0xb;
1811 break;
1812 default:
1813 break;
1814 }
1815 }
1816 return mask;
1817 case TGSI_OPCODE_XPD:
1818 x = 0;
1819 if (mask & 1) x |= 0x6;
1820 if (mask & 2) x |= 0x5;
1821 if (mask & 4) x |= 0x3;
1822 return x;
1823 default:
1824 break;
1825 }
1826
1827 return mask;
1828 }
1829
1830 static struct nv50_reg *
1831 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1832 {
1833 switch (dst->Register.File) {
1834 case TGSI_FILE_TEMPORARY:
1835 return &pc->temp[dst->Register.Index * 4 + c];
1836 case TGSI_FILE_OUTPUT:
1837 return &pc->result[dst->Register.Index * 4 + c];
1838 case TGSI_FILE_ADDRESS:
1839 {
1840 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
1841 if (!r) {
1842 r = alloc_addr(pc, NULL);
1843 pc->addr[dst->Register.Index * 4 + c] = r;
1844 }
1845 assert(r);
1846 return r;
1847 }
1848 case TGSI_FILE_NULL:
1849 return NULL;
1850 default:
1851 break;
1852 }
1853
1854 return NULL;
1855 }
1856
1857 static struct nv50_reg *
1858 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1859 boolean neg)
1860 {
1861 struct nv50_reg *r = NULL;
1862 struct nv50_reg *temp;
1863 unsigned sgn, c, swz;
1864
1865 if (src->Register.File != TGSI_FILE_CONSTANT)
1866 assert(!src->Register.Indirect);
1867
1868 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1869
1870 c = tgsi_util_get_full_src_register_swizzle(src, chan);
1871 switch (c) {
1872 case TGSI_SWIZZLE_X:
1873 case TGSI_SWIZZLE_Y:
1874 case TGSI_SWIZZLE_Z:
1875 case TGSI_SWIZZLE_W:
1876 switch (src->Register.File) {
1877 case TGSI_FILE_INPUT:
1878 r = &pc->attr[src->Register.Index * 4 + c];
1879 break;
1880 case TGSI_FILE_TEMPORARY:
1881 r = &pc->temp[src->Register.Index * 4 + c];
1882 break;
1883 case TGSI_FILE_CONSTANT:
1884 if (!src->Register.Indirect) {
1885 r = &pc->param[src->Register.Index * 4 + c];
1886 break;
1887 }
1888 /* Indicate indirection by setting r->acc < 0 and
1889 * use the index field to select the address reg.
1890 */
1891 r = MALLOC_STRUCT(nv50_reg);
1892 swz = tgsi_util_get_src_register_swizzle(
1893 &src->Indirect, 0);
1894 ctor_reg(r, P_CONST,
1895 src->Indirect.Index * 4 + swz,
1896 src->Register.Index * 4 + c);
1897 r->acc = -1;
1898 break;
1899 case TGSI_FILE_IMMEDIATE:
1900 r = &pc->immd[src->Register.Index * 4 + c];
1901 break;
1902 case TGSI_FILE_SAMPLER:
1903 break;
1904 case TGSI_FILE_ADDRESS:
1905 r = pc->addr[src->Register.Index * 4 + c];
1906 assert(r);
1907 break;
1908 default:
1909 assert(0);
1910 break;
1911 }
1912 break;
1913 default:
1914 assert(0);
1915 break;
1916 }
1917
1918 switch (sgn) {
1919 case TGSI_UTIL_SIGN_KEEP:
1920 break;
1921 case TGSI_UTIL_SIGN_CLEAR:
1922 temp = temp_temp(pc);
1923 emit_abs(pc, temp, r);
1924 r = temp;
1925 break;
1926 case TGSI_UTIL_SIGN_TOGGLE:
1927 if (neg)
1928 r->mod = NV50_MOD_NEG;
1929 else {
1930 temp = temp_temp(pc);
1931 emit_neg(pc, temp, r);
1932 r = temp;
1933 }
1934 break;
1935 case TGSI_UTIL_SIGN_SET:
1936 temp = temp_temp(pc);
1937 emit_cvt(pc, temp, r, -1, CVTOP_ABS, CVT_F32_F32 | CVT_NEG);
1938 r = temp;
1939 break;
1940 default:
1941 assert(0);
1942 break;
1943 }
1944
1945 return r;
1946 }
1947
1948 /* return TRUE for ops that produce only a single result */
1949 static boolean
1950 is_scalar_op(unsigned op)
1951 {
1952 switch (op) {
1953 case TGSI_OPCODE_COS:
1954 case TGSI_OPCODE_DP2:
1955 case TGSI_OPCODE_DP3:
1956 case TGSI_OPCODE_DP4:
1957 case TGSI_OPCODE_DPH:
1958 case TGSI_OPCODE_EX2:
1959 case TGSI_OPCODE_LG2:
1960 case TGSI_OPCODE_POW:
1961 case TGSI_OPCODE_RCP:
1962 case TGSI_OPCODE_RSQ:
1963 case TGSI_OPCODE_SIN:
1964 /*
1965 case TGSI_OPCODE_KIL:
1966 case TGSI_OPCODE_LIT:
1967 case TGSI_OPCODE_SCS:
1968 */
1969 return TRUE;
1970 default:
1971 return FALSE;
1972 }
1973 }
1974
1975 /* Returns a bitmask indicating which dst components depend
1976 * on source s, component c (reverse of nv50_tgsi_src_mask).
1977 */
1978 static unsigned
1979 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
1980 {
1981 if (is_scalar_op(op))
1982 return 0x1;
1983
1984 switch (op) {
1985 case TGSI_OPCODE_DST:
1986 return (1 << c) & (s ? 0xa : 0x6);
1987 case TGSI_OPCODE_XPD:
1988 switch (c) {
1989 case 0: return 0x6;
1990 case 1: return 0x5;
1991 case 2: return 0x3;
1992 case 3: return 0x0;
1993 default:
1994 assert(0);
1995 return 0x0;
1996 }
1997 case TGSI_OPCODE_LIT:
1998 case TGSI_OPCODE_SCS:
1999 case TGSI_OPCODE_TEX:
2000 case TGSI_OPCODE_TXB:
2001 case TGSI_OPCODE_TXL:
2002 case TGSI_OPCODE_TXP:
2003 /* these take care of dangerous swizzles themselves */
2004 return 0x0;
2005 case TGSI_OPCODE_IF:
2006 case TGSI_OPCODE_KIL:
2007 /* don't call this function for these ops */
2008 assert(0);
2009 return 0;
2010 default:
2011 /* linear vector instruction */
2012 return (1 << c);
2013 }
2014 }
2015
2016 static INLINE boolean
2017 has_pred(struct nv50_program_exec *e, unsigned cc)
2018 {
2019 if (!is_long(e) || is_immd(e))
2020 return FALSE;
2021 return ((e->inst[1] & 0x780) == (cc << 7));
2022 }
2023
2024 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2025 * join_at ENDIF
2026 * @p0.eq bra ENDIF
2027 * single_op
2028 * ENDIF: nop.join
2029 */
2030 static boolean
2031 nv50_kill_branch(struct nv50_pc *pc)
2032 {
2033 int lvl = pc->if_lvl;
2034
2035 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2036 return FALSE;
2037
2038 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2039 * reg may no longer be valid, since we currently always use $p0
2040 */
2041 if (has_pred(pc->if_insn[lvl], 0xf))
2042 return FALSE;
2043 assert(pc->if_insn[lvl] && pc->br_join[lvl]);
2044
2045 /* We'll use the exec allocated for JOIN_AT (as we can't easily
2046 * update prev's next); if exec_tail is BRK, update the pointer.
2047 */
2048 if (pc->loop_lvl && pc->br_loop[pc->loop_lvl - 1] == pc->p->exec_tail)
2049 pc->br_loop[pc->loop_lvl - 1] = pc->br_join[lvl];
2050
2051 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2052
2053 *pc->br_join[lvl] = *pc->p->exec_tail;
2054
2055 FREE(pc->if_insn[lvl]);
2056 FREE(pc->p->exec_tail);
2057
2058 pc->p->exec_tail = pc->br_join[lvl];
2059 pc->p->exec_tail->next = NULL;
2060 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2061
2062 return TRUE;
2063 }
2064
2065 static boolean
2066 nv50_program_tx_insn(struct nv50_pc *pc,
2067 const struct tgsi_full_instruction *inst)
2068 {
2069 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2070 unsigned mask, sat, unit;
2071 int i, c;
2072
2073 mask = inst->Dst[0].Register.WriteMask;
2074 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2075
2076 memset(src, 0, sizeof(src));
2077
2078 for (c = 0; c < 4; c++) {
2079 if ((mask & (1 << c)) && !pc->r_dst[c])
2080 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2081 else
2082 dst[c] = pc->r_dst[c];
2083 rdst[c] = dst[c];
2084 }
2085
2086 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2087 const struct tgsi_full_src_register *fs = &inst->Src[i];
2088 unsigned src_mask;
2089 boolean neg_supp;
2090
2091 src_mask = nv50_tgsi_src_mask(inst, i);
2092 neg_supp = negate_supported(inst, i);
2093
2094 if (fs->Register.File == TGSI_FILE_SAMPLER)
2095 unit = fs->Register.Index;
2096
2097 for (c = 0; c < 4; c++)
2098 if (src_mask & (1 << c))
2099 src[i][c] = reg_instance(pc,
2100 tgsi_src(pc, c, fs, neg_supp));
2101 }
2102
2103 brdc = temp = pc->r_brdc;
2104 if (brdc && brdc->type != P_TEMP) {
2105 temp = temp_temp(pc);
2106 if (sat)
2107 brdc = temp;
2108 } else
2109 if (sat) {
2110 for (c = 0; c < 4; c++) {
2111 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2112 continue;
2113 /* rdst[c] = dst[c]; */ /* done above */
2114 dst[c] = temp_temp(pc);
2115 }
2116 }
2117
2118 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2119
2120 switch (inst->Instruction.Opcode) {
2121 case TGSI_OPCODE_ABS:
2122 for (c = 0; c < 4; c++) {
2123 if (!(mask & (1 << c)))
2124 continue;
2125 emit_abs(pc, dst[c], src[0][c]);
2126 }
2127 break;
2128 case TGSI_OPCODE_ADD:
2129 for (c = 0; c < 4; c++) {
2130 if (!(mask & (1 << c)))
2131 continue;
2132 emit_add(pc, dst[c], src[0][c], src[1][c]);
2133 }
2134 break;
2135 case TGSI_OPCODE_AND:
2136 case TGSI_OPCODE_XOR:
2137 case TGSI_OPCODE_OR:
2138 for (c = 0; c < 4; c++) {
2139 if (!(mask & (1 << c)))
2140 continue;
2141 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2142 inst->Instruction.Opcode);
2143 }
2144 break;
2145 case TGSI_OPCODE_ARL:
2146 assert(src[0][0]);
2147 temp = temp_temp(pc);
2148 emit_cvt(pc, temp, src[0][0], -1, CVTOP_FLOOR, CVT_S32_F32);
2149 emit_arl(pc, dst[0], temp, 4);
2150 break;
2151 case TGSI_OPCODE_BGNLOOP:
2152 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2153 terminate_mbb(pc);
2154 break;
2155 case TGSI_OPCODE_BRK:
2156 emit_branch(pc, -1, 0, NULL);
2157 assert(pc->loop_lvl > 0);
2158 pc->br_loop[pc->loop_lvl - 1] = pc->p->exec_tail;
2159 break;
2160 case TGSI_OPCODE_CEIL:
2161 for (c = 0; c < 4; c++) {
2162 if (!(mask & (1 << c)))
2163 continue;
2164 emit_cvt(pc, dst[c], src[0][c], -1,
2165 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
2166 }
2167 break;
2168 case TGSI_OPCODE_CMP:
2169 pc->allow32 = FALSE;
2170 for (c = 0; c < 4; c++) {
2171 if (!(mask & (1 << c)))
2172 continue;
2173 emit_cvt(pc, NULL, src[0][c], 1, CVTOP_RN, CVT_F32_F32);
2174 emit_mov(pc, dst[c], src[1][c]);
2175 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2176 emit_mov(pc, dst[c], src[2][c]);
2177 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2178 }
2179 break;
2180 case TGSI_OPCODE_COS:
2181 if (mask & 8) {
2182 emit_precossin(pc, temp, src[0][3]);
2183 emit_flop(pc, 5, dst[3], temp);
2184 if (!(mask &= 7))
2185 break;
2186 if (temp == dst[3])
2187 temp = brdc = temp_temp(pc);
2188 }
2189 emit_precossin(pc, temp, src[0][0]);
2190 emit_flop(pc, 5, brdc, temp);
2191 break;
2192 case TGSI_OPCODE_DDX:
2193 for (c = 0; c < 4; c++) {
2194 if (!(mask & (1 << c)))
2195 continue;
2196 emit_ddx(pc, dst[c], src[0][c]);
2197 }
2198 break;
2199 case TGSI_OPCODE_DDY:
2200 for (c = 0; c < 4; c++) {
2201 if (!(mask & (1 << c)))
2202 continue;
2203 emit_ddy(pc, dst[c], src[0][c]);
2204 }
2205 break;
2206 case TGSI_OPCODE_DP3:
2207 emit_mul(pc, temp, src[0][0], src[1][0]);
2208 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2209 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2210 break;
2211 case TGSI_OPCODE_DP4:
2212 emit_mul(pc, temp, src[0][0], src[1][0]);
2213 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2214 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2215 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2216 break;
2217 case TGSI_OPCODE_DPH:
2218 emit_mul(pc, temp, src[0][0], src[1][0]);
2219 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2220 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2221 emit_add(pc, brdc, src[1][3], temp);
2222 break;
2223 case TGSI_OPCODE_DST:
2224 if (mask & (1 << 1))
2225 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2226 if (mask & (1 << 2))
2227 emit_mov(pc, dst[2], src[0][2]);
2228 if (mask & (1 << 3))
2229 emit_mov(pc, dst[3], src[1][3]);
2230 if (mask & (1 << 0))
2231 emit_mov_immdval(pc, dst[0], 1.0f);
2232 break;
2233 case TGSI_OPCODE_ELSE:
2234 emit_branch(pc, -1, 0, NULL);
2235 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2236 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2237 terminate_mbb(pc);
2238 break;
2239 case TGSI_OPCODE_ENDIF:
2240 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2241
2242 /* try to replace branch over 1 insn with a predicated insn */
2243 if (nv50_kill_branch(pc) == TRUE)
2244 break;
2245
2246 if (pc->br_join[pc->if_lvl]) {
2247 pc->br_join[pc->if_lvl]->param.index = pc->p->exec_size;
2248 pc->br_join[pc->if_lvl] = NULL;
2249 }
2250 terminate_mbb(pc);
2251 /* emit a NOP as join point, we could set it on the next
2252 * one, but would have to make sure it is long and !immd
2253 */
2254 emit_nop(pc);
2255 pc->p->exec_tail->inst[1] |= 2;
2256 break;
2257 case TGSI_OPCODE_ENDLOOP:
2258 emit_branch(pc, -1, 0, NULL);
2259 pc->p->exec_tail->param.index = pc->loop_pos[--pc->loop_lvl];
2260 pc->br_loop[pc->loop_lvl]->param.index = pc->p->exec_size;
2261 terminate_mbb(pc);
2262 break;
2263 case TGSI_OPCODE_EX2:
2264 emit_preex2(pc, temp, src[0][0]);
2265 emit_flop(pc, 6, brdc, temp);
2266 break;
2267 case TGSI_OPCODE_FLR:
2268 for (c = 0; c < 4; c++) {
2269 if (!(mask & (1 << c)))
2270 continue;
2271 emit_flr(pc, dst[c], src[0][c]);
2272 }
2273 break;
2274 case TGSI_OPCODE_FRC:
2275 temp = temp_temp(pc);
2276 for (c = 0; c < 4; c++) {
2277 if (!(mask & (1 << c)))
2278 continue;
2279 emit_flr(pc, temp, src[0][c]);
2280 emit_sub(pc, dst[c], src[0][c], temp);
2281 }
2282 break;
2283 case TGSI_OPCODE_IF:
2284 /* emitting a join_at may not be necessary */
2285 assert(pc->if_lvl < MAX_IF_DEPTH);
2286 /* set_pred_wr(pc, 1, 0, pc->if_cond); */
2287 emit_cvt(pc, NULL, src[0][0], 0, CVTOP_ABS | CVTOP_RN,
2288 CVT_F32_F32);
2289 emit_branch(pc, 0, 2, &pc->br_join[pc->if_lvl]);
2290 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2291 terminate_mbb(pc);
2292 break;
2293 case TGSI_OPCODE_KIL:
2294 emit_kil(pc, src[0][0]);
2295 emit_kil(pc, src[0][1]);
2296 emit_kil(pc, src[0][2]);
2297 emit_kil(pc, src[0][3]);
2298 break;
2299 case TGSI_OPCODE_LIT:
2300 emit_lit(pc, &dst[0], mask, &src[0][0]);
2301 break;
2302 case TGSI_OPCODE_LG2:
2303 emit_flop(pc, 3, brdc, src[0][0]);
2304 break;
2305 case TGSI_OPCODE_LRP:
2306 temp = temp_temp(pc);
2307 for (c = 0; c < 4; c++) {
2308 if (!(mask & (1 << c)))
2309 continue;
2310 emit_sub(pc, temp, src[1][c], src[2][c]);
2311 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2312 }
2313 break;
2314 case TGSI_OPCODE_MAD:
2315 for (c = 0; c < 4; c++) {
2316 if (!(mask & (1 << c)))
2317 continue;
2318 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2319 }
2320 break;
2321 case TGSI_OPCODE_MAX:
2322 for (c = 0; c < 4; c++) {
2323 if (!(mask & (1 << c)))
2324 continue;
2325 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
2326 }
2327 break;
2328 case TGSI_OPCODE_MIN:
2329 for (c = 0; c < 4; c++) {
2330 if (!(mask & (1 << c)))
2331 continue;
2332 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
2333 }
2334 break;
2335 case TGSI_OPCODE_MOV:
2336 for (c = 0; c < 4; c++) {
2337 if (!(mask & (1 << c)))
2338 continue;
2339 emit_mov(pc, dst[c], src[0][c]);
2340 }
2341 break;
2342 case TGSI_OPCODE_MUL:
2343 for (c = 0; c < 4; c++) {
2344 if (!(mask & (1 << c)))
2345 continue;
2346 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2347 }
2348 break;
2349 case TGSI_OPCODE_POW:
2350 emit_pow(pc, brdc, src[0][0], src[1][0]);
2351 break;
2352 case TGSI_OPCODE_RCP:
2353 emit_flop(pc, 0, brdc, src[0][0]);
2354 break;
2355 case TGSI_OPCODE_RSQ:
2356 emit_flop(pc, 2, brdc, src[0][0]);
2357 break;
2358 case TGSI_OPCODE_SCS:
2359 temp = temp_temp(pc);
2360 if (mask & 3)
2361 emit_precossin(pc, temp, src[0][0]);
2362 if (mask & (1 << 0))
2363 emit_flop(pc, 5, dst[0], temp);
2364 if (mask & (1 << 1))
2365 emit_flop(pc, 4, dst[1], temp);
2366 if (mask & (1 << 2))
2367 emit_mov_immdval(pc, dst[2], 0.0);
2368 if (mask & (1 << 3))
2369 emit_mov_immdval(pc, dst[3], 1.0);
2370 break;
2371 case TGSI_OPCODE_SIN:
2372 if (mask & 8) {
2373 emit_precossin(pc, temp, src[0][3]);
2374 emit_flop(pc, 4, dst[3], temp);
2375 if (!(mask &= 7))
2376 break;
2377 if (temp == dst[3])
2378 temp = brdc = temp_temp(pc);
2379 }
2380 emit_precossin(pc, temp, src[0][0]);
2381 emit_flop(pc, 4, brdc, temp);
2382 break;
2383 case TGSI_OPCODE_SLT:
2384 case TGSI_OPCODE_SGE:
2385 case TGSI_OPCODE_SEQ:
2386 case TGSI_OPCODE_SGT:
2387 case TGSI_OPCODE_SLE:
2388 case TGSI_OPCODE_SNE:
2389 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
2390 for (c = 0; c < 4; c++) {
2391 if (!(mask & (1 << c)))
2392 continue;
2393 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
2394 }
2395 break;
2396 case TGSI_OPCODE_SUB:
2397 for (c = 0; c < 4; c++) {
2398 if (!(mask & (1 << c)))
2399 continue;
2400 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2401 }
2402 break;
2403 case TGSI_OPCODE_TEX:
2404 emit_tex(pc, dst, mask, src[0], unit,
2405 inst->Texture.Texture, FALSE, 0);
2406 break;
2407 case TGSI_OPCODE_TXB:
2408 emit_tex(pc, dst, mask, src[0], unit,
2409 inst->Texture.Texture, FALSE, -1);
2410 break;
2411 case TGSI_OPCODE_TXL:
2412 emit_tex(pc, dst, mask, src[0], unit,
2413 inst->Texture.Texture, FALSE, 1);
2414 break;
2415 case TGSI_OPCODE_TXP:
2416 emit_tex(pc, dst, mask, src[0], unit,
2417 inst->Texture.Texture, TRUE, 0);
2418 break;
2419 case TGSI_OPCODE_TRUNC:
2420 for (c = 0; c < 4; c++) {
2421 if (!(mask & (1 << c)))
2422 continue;
2423 emit_cvt(pc, dst[c], src[0][c], -1,
2424 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
2425 }
2426 break;
2427 case TGSI_OPCODE_XPD:
2428 temp = temp_temp(pc);
2429 if (mask & (1 << 0)) {
2430 emit_mul(pc, temp, src[0][2], src[1][1]);
2431 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2432 }
2433 if (mask & (1 << 1)) {
2434 emit_mul(pc, temp, src[0][0], src[1][2]);
2435 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2436 }
2437 if (mask & (1 << 2)) {
2438 emit_mul(pc, temp, src[0][1], src[1][0]);
2439 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2440 }
2441 if (mask & (1 << 3))
2442 emit_mov_immdval(pc, dst[3], 1.0);
2443 break;
2444 case TGSI_OPCODE_END:
2445 break;
2446 default:
2447 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2448 return FALSE;
2449 }
2450
2451 if (brdc) {
2452 if (sat)
2453 emit_sat(pc, brdc, brdc);
2454 for (c = 0; c < 4; c++)
2455 if ((mask & (1 << c)) && dst[c] != brdc)
2456 emit_mov(pc, dst[c], brdc);
2457 } else
2458 if (sat) {
2459 for (c = 0; c < 4; c++) {
2460 if (!(mask & (1 << c)))
2461 continue;
2462 /* In this case we saturate later, and dst[c] won't
2463 * be another temp_temp (and thus lost), since rdst
2464 * already is TEMP (see above). */
2465 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2466 continue;
2467 emit_sat(pc, rdst[c], dst[c]);
2468 }
2469 }
2470
2471 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2472 for (c = 0; c < 4; c++) {
2473 if (!src[i][c])
2474 continue;
2475 if (src[i][c]->acc < 0 && src[i][c]->type == P_CONST)
2476 FREE(src[i][c]); /* indirect constant */
2477 }
2478 }
2479
2480 kill_temp_temp(pc);
2481 pc->reg_instance_nr = 0;
2482
2483 return TRUE;
2484 }
2485
2486 static void
2487 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2488 {
2489 struct nv50_reg *reg = NULL;
2490 const struct tgsi_full_src_register *src;
2491 const struct tgsi_dst_register *dst;
2492 unsigned i, c, k, mask;
2493
2494 dst = &insn->Dst[0].Register;
2495 mask = dst->WriteMask;
2496
2497 if (dst->File == TGSI_FILE_TEMPORARY)
2498 reg = pc->temp;
2499 else
2500 if (dst->File == TGSI_FILE_OUTPUT)
2501 reg = pc->result;
2502
2503 if (reg) {
2504 for (c = 0; c < 4; c++) {
2505 if (!(mask & (1 << c)))
2506 continue;
2507 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2508 }
2509 }
2510
2511 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2512 src = &insn->Src[i];
2513
2514 if (src->Register.File == TGSI_FILE_TEMPORARY)
2515 reg = pc->temp;
2516 else
2517 if (src->Register.File == TGSI_FILE_INPUT)
2518 reg = pc->attr;
2519 else
2520 continue;
2521
2522 mask = nv50_tgsi_src_mask(insn, i);
2523
2524 for (c = 0; c < 4; c++) {
2525 if (!(mask & (1 << c)))
2526 continue;
2527 k = tgsi_util_get_full_src_register_swizzle(src, c);
2528
2529 reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
2530 }
2531 }
2532 }
2533
2534 /* Returns a bitmask indicating which dst components need to be
2535 * written to temporaries first to avoid 'corrupting' sources.
2536 *
2537 * m[i] (out) indicate component to write in the i-th position
2538 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2539 */
2540 static unsigned
2541 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2542 {
2543 unsigned i, c, x, unsafe;
2544
2545 for (c = 0; c < 4; c++)
2546 m[c] = c;
2547
2548 /* Swap as long as a dst component written earlier is depended on
2549 * by one written later, but the next one isn't depended on by it.
2550 */
2551 for (c = 0; c < 3; c++) {
2552 if (rdep[m[c + 1]] & (1 << m[c]))
2553 continue; /* if next one is depended on by us */
2554 for (i = c + 1; i < 4; i++)
2555 /* if we are depended on by a later one */
2556 if (rdep[m[c]] & (1 << m[i]))
2557 break;
2558 if (i == 4)
2559 continue;
2560 /* now, swap */
2561 x = m[c];
2562 m[c] = m[c + 1];
2563 m[c + 1] = x;
2564
2565 /* restart */
2566 c = 0;
2567 }
2568
2569 /* mark dependencies that could not be resolved by reordering */
2570 for (i = 0; i < 3; ++i)
2571 for (c = i + 1; c < 4; ++c)
2572 if (rdep[m[i]] & (1 << m[c]))
2573 unsafe |= (1 << i);
2574
2575 /* NOTE: $unsafe is with respect to order, not component */
2576 return unsafe;
2577 }
2578
2579 /* Select a suitable dst register for broadcasting scalar results,
2580 * or return NULL if we have to allocate an extra TEMP.
2581 *
2582 * If e.g. only 1 component is written, we may also emit the final
2583 * result to a write-only register.
2584 */
2585 static struct nv50_reg *
2586 tgsi_broadcast_dst(struct nv50_pc *pc,
2587 const struct tgsi_full_dst_register *fd, unsigned mask)
2588 {
2589 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
2590 int c = ffs(~mask & fd->Register.WriteMask);
2591 if (c)
2592 return tgsi_dst(pc, c - 1, fd);
2593 } else {
2594 int c = ffs(fd->Register.WriteMask) - 1;
2595 if ((1 << c) == fd->Register.WriteMask)
2596 return tgsi_dst(pc, c, fd);
2597 }
2598
2599 return NULL;
2600 }
2601
2602 /* Scan source swizzles and return a bitmask indicating dst regs that
2603 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2604 */
2605 static unsigned
2606 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2607 unsigned rdep[4])
2608 {
2609 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
2610 const struct tgsi_full_src_register *fs;
2611 unsigned i, deqs = 0;
2612
2613 for (i = 0; i < 4; ++i)
2614 rdep[i] = 0;
2615
2616 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2617 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2618 boolean neg_supp = negate_supported(insn, i);
2619
2620 fs = &insn->Src[i];
2621 if (fs->Register.File != fd->Register.File ||
2622 fs->Register.Index != fd->Register.Index)
2623 continue;
2624
2625 for (chn = 0; chn < 4; ++chn) {
2626 unsigned s, c;
2627
2628 if (!(mask & (1 << chn))) /* src is not read */
2629 continue;
2630 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2631 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2632
2633 if (!(fd->Register.WriteMask & (1 << c)))
2634 continue;
2635
2636 /* no danger if src is copied to TEMP first */
2637 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2638 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2639 continue;
2640
2641 rdep[c] |= nv50_tgsi_dst_revdep(
2642 insn->Instruction.Opcode, i, chn);
2643 deqs |= (1 << c);
2644 }
2645 }
2646
2647 return deqs;
2648 }
2649
2650 static boolean
2651 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2652 {
2653 struct tgsi_full_instruction insn = tok->FullInstruction;
2654 const struct tgsi_full_dst_register *fd;
2655 unsigned i, deqs, rdep[4], m[4];
2656
2657 fd = &tok->FullInstruction.Dst[0];
2658 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2659
2660 if (is_scalar_op(insn.Instruction.Opcode)) {
2661 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2662 if (!pc->r_brdc)
2663 pc->r_brdc = temp_temp(pc);
2664 return nv50_program_tx_insn(pc, &insn);
2665 }
2666 pc->r_brdc = NULL;
2667
2668 if (!deqs)
2669 return nv50_program_tx_insn(pc, &insn);
2670
2671 deqs = nv50_revdep_reorder(m, rdep);
2672
2673 for (i = 0; i < 4; ++i) {
2674 assert(pc->r_dst[m[i]] == NULL);
2675
2676 insn.Dst[0].Register.WriteMask =
2677 fd->Register.WriteMask & (1 << m[i]);
2678
2679 if (!insn.Dst[0].Register.WriteMask)
2680 continue;
2681
2682 if (deqs & (1 << i))
2683 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2684
2685 if (!nv50_program_tx_insn(pc, &insn))
2686 return FALSE;
2687 }
2688
2689 for (i = 0; i < 4; i++) {
2690 struct nv50_reg *reg = pc->r_dst[i];
2691 if (!reg)
2692 continue;
2693 pc->r_dst[i] = NULL;
2694
2695 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2696 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2697 else
2698 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2699 free_temp(pc, reg);
2700 }
2701
2702 return TRUE;
2703 }
2704
2705 static void
2706 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2707 {
2708 struct nv50_reg *iv, **ppiv;
2709 unsigned mode = pc->interp_mode[reg->index];
2710
2711 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2712 iv = *ppiv;
2713
2714 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2715 iv = *ppiv = alloc_temp(pc, NULL);
2716 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2717
2718 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2719 emit_flop(pc, 0, iv, iv);
2720
2721 /* XXX: when loading interpolants dynamically, move these
2722 * to the program head, or make sure it can't be skipped.
2723 */
2724 }
2725
2726 emit_interp(pc, reg, iv, mode);
2727 }
2728
2729 /* The face input is always at v[255] (varying space), with a
2730 * value of 0 for back-facing, and 0xffffffff for front-facing.
2731 */
2732 static void
2733 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
2734 {
2735 struct nv50_reg *one = alloc_immd(pc, 1.0f);
2736
2737 assert(a->rhw == -1);
2738 alloc_reg(pc, a); /* do this before rhw is set */
2739 a->rhw = 255;
2740 load_interpolant(pc, a);
2741 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
2742
2743 FREE(one);
2744 }
2745
2746 static boolean
2747 nv50_program_tx_prep(struct nv50_pc *pc)
2748 {
2749 struct tgsi_parse_context tp;
2750 struct nv50_program *p = pc->p;
2751 boolean ret = FALSE;
2752 unsigned i, c, flat_nr = 0;
2753
2754 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2755 while (!tgsi_parse_end_of_tokens(&tp)) {
2756 const union tgsi_full_token *tok = &tp.FullToken;
2757
2758 tgsi_parse_token(&tp);
2759 switch (tok->Token.Type) {
2760 case TGSI_TOKEN_TYPE_IMMEDIATE:
2761 {
2762 const struct tgsi_full_immediate *imm =
2763 &tp.FullToken.FullImmediate;
2764
2765 ctor_immd(pc, imm->u[0].Float,
2766 imm->u[1].Float,
2767 imm->u[2].Float,
2768 imm->u[3].Float);
2769 }
2770 break;
2771 case TGSI_TOKEN_TYPE_DECLARATION:
2772 {
2773 const struct tgsi_full_declaration *d;
2774 unsigned si, last, first, mode;
2775
2776 d = &tp.FullToken.FullDeclaration;
2777 first = d->Range.First;
2778 last = d->Range.Last;
2779
2780 switch (d->Declaration.File) {
2781 case TGSI_FILE_TEMPORARY:
2782 break;
2783 case TGSI_FILE_OUTPUT:
2784 if (!d->Declaration.Semantic ||
2785 p->type == PIPE_SHADER_FRAGMENT)
2786 break;
2787
2788 si = d->Semantic.Index;
2789 switch (d->Semantic.Name) {
2790 case TGSI_SEMANTIC_BCOLOR:
2791 p->cfg.two_side[si].hw = first;
2792 if (p->cfg.io_nr > first)
2793 p->cfg.io_nr = first;
2794 break;
2795 case TGSI_SEMANTIC_PSIZE:
2796 p->cfg.psiz = first;
2797 if (p->cfg.io_nr > first)
2798 p->cfg.io_nr = first;
2799 break;
2800 /*
2801 case TGSI_SEMANTIC_CLIP_DISTANCE:
2802 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2803 break;
2804 */
2805 default:
2806 break;
2807 }
2808 break;
2809 case TGSI_FILE_INPUT:
2810 {
2811 if (p->type != PIPE_SHADER_FRAGMENT)
2812 break;
2813
2814 switch (d->Declaration.Interpolate) {
2815 case TGSI_INTERPOLATE_CONSTANT:
2816 mode = INTERP_FLAT;
2817 flat_nr++;
2818 break;
2819 case TGSI_INTERPOLATE_PERSPECTIVE:
2820 mode = INTERP_PERSPECTIVE;
2821 p->cfg.regs[1] |= 0x08 << 24;
2822 break;
2823 default:
2824 mode = INTERP_LINEAR;
2825 break;
2826 }
2827 if (d->Declaration.Centroid)
2828 mode |= INTERP_CENTROID;
2829
2830 assert(last < 32);
2831 for (i = first; i <= last; i++)
2832 pc->interp_mode[i] = mode;
2833 }
2834 break;
2835 case TGSI_FILE_ADDRESS:
2836 case TGSI_FILE_CONSTANT:
2837 case TGSI_FILE_SAMPLER:
2838 break;
2839 default:
2840 NOUVEAU_ERR("bad decl file %d\n",
2841 d->Declaration.File);
2842 goto out_err;
2843 }
2844 }
2845 break;
2846 case TGSI_TOKEN_TYPE_INSTRUCTION:
2847 pc->insn_nr++;
2848 prep_inspect_insn(pc, &tok->FullInstruction);
2849 break;
2850 default:
2851 break;
2852 }
2853 }
2854
2855 if (p->type == PIPE_SHADER_VERTEX) {
2856 int rid = 0;
2857
2858 for (i = 0; i < pc->attr_nr * 4; ++i) {
2859 if (pc->attr[i].acc) {
2860 pc->attr[i].hw = rid++;
2861 p->cfg.attr[i / 32] |= 1 << (i % 32);
2862 }
2863 }
2864
2865 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
2866 p->cfg.io[i].hw = rid;
2867 p->cfg.io[i].id = i;
2868
2869 for (c = 0; c < 4; ++c) {
2870 int n = i * 4 + c;
2871 if (!pc->result[n].acc)
2872 continue;
2873 pc->result[n].hw = rid++;
2874 p->cfg.io[i].mask |= 1 << c;
2875 }
2876 }
2877
2878 for (c = 0; c < 2; ++c)
2879 if (p->cfg.two_side[c].hw < 0x40)
2880 p->cfg.two_side[c] = p->cfg.io[
2881 p->cfg.two_side[c].hw];
2882
2883 if (p->cfg.psiz < 0x40)
2884 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
2885 } else
2886 if (p->type == PIPE_SHADER_FRAGMENT) {
2887 int rid, aid;
2888 unsigned n = 0, m = pc->attr_nr - flat_nr;
2889
2890 pc->allow32 = TRUE;
2891
2892 int base = (TGSI_SEMANTIC_POSITION ==
2893 p->info.input_semantic_name[0]) ? 0 : 1;
2894
2895 /* non-flat interpolants have to be mapped to
2896 * the lower hardware IDs, so sort them:
2897 */
2898 for (i = 0; i < pc->attr_nr; i++) {
2899 if (pc->interp_mode[i] == INTERP_FLAT)
2900 p->cfg.io[m++].id = i;
2901 else {
2902 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
2903 p->cfg.io[n].linear = TRUE;
2904 p->cfg.io[n++].id = i;
2905 }
2906 }
2907
2908 if (!base) /* set w-coordinate mask from perspective interp */
2909 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
2910
2911 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
2912 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
2913
2914 for (n = 0; n < pc->attr_nr; ++n) {
2915 p->cfg.io[n].hw = rid = aid;
2916 i = p->cfg.io[n].id;
2917
2918 if (p->info.input_semantic_name[n] ==
2919 TGSI_SEMANTIC_FACE) {
2920 load_frontfacing(pc, &pc->attr[i * 4]);
2921 continue;
2922 }
2923
2924 for (c = 0; c < 4; ++c) {
2925 if (!pc->attr[i * 4 + c].acc)
2926 continue;
2927 pc->attr[i * 4 + c].rhw = rid++;
2928 p->cfg.io[n].mask |= 1 << c;
2929
2930 load_interpolant(pc, &pc->attr[i * 4 + c]);
2931 }
2932 aid += popcnt4(p->cfg.io[n].mask);
2933 }
2934
2935 if (!base)
2936 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
2937
2938 m = popcnt4(p->cfg.regs[1] >> 24);
2939
2940 /* set count of non-position inputs and of non-flat
2941 * non-position inputs for FP_INTERPOLANT_CTRL
2942 */
2943 p->cfg.regs[1] |= aid - m;
2944
2945 if (flat_nr) {
2946 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
2947 p->cfg.regs[1] |= (i - m) << 16;
2948 } else
2949 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
2950
2951 /* mark color semantic for light-twoside */
2952 n = 0x40;
2953 for (i = 0; i < pc->attr_nr; i++) {
2954 ubyte si, sn;
2955
2956 sn = p->info.input_semantic_name[p->cfg.io[i].id];
2957 si = p->info.input_semantic_index[p->cfg.io[i].id];
2958
2959 if (sn == TGSI_SEMANTIC_COLOR) {
2960 p->cfg.two_side[si] = p->cfg.io[i];
2961
2962 /* increase colour count */
2963 p->cfg.regs[0] += popcnt4(
2964 p->cfg.two_side[si].mask) << 16;
2965
2966 n = MIN2(n, p->cfg.io[i].hw - m);
2967 }
2968 }
2969 if (n < 0x40)
2970 p->cfg.regs[0] += n;
2971
2972 /* Initialize FP results:
2973 * FragDepth is always first TGSI and last hw output
2974 */
2975 i = p->info.writes_z ? 4 : 0;
2976 for (rid = 0; i < pc->result_nr * 4; i++)
2977 pc->result[i].rhw = rid++;
2978 if (p->info.writes_z)
2979 pc->result[2].rhw = rid;
2980
2981 p->cfg.high_result = rid;
2982
2983 /* separate/different colour results for MRTs ? */
2984 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
2985 p->cfg.regs[2] |= 1;
2986 }
2987
2988 if (pc->immd_nr) {
2989 int rid = 0;
2990
2991 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
2992 if (!pc->immd)
2993 goto out_err;
2994
2995 for (i = 0; i < pc->immd_nr; i++) {
2996 for (c = 0; c < 4; c++, rid++)
2997 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
2998 }
2999 }
3000
3001 ret = TRUE;
3002 out_err:
3003 if (pc->iv_p)
3004 free_temp(pc, pc->iv_p);
3005 if (pc->iv_c)
3006 free_temp(pc, pc->iv_c);
3007
3008 tgsi_parse_free(&tp);
3009 return ret;
3010 }
3011
3012 static void
3013 free_nv50_pc(struct nv50_pc *pc)
3014 {
3015 if (pc->immd)
3016 FREE(pc->immd);
3017 if (pc->param)
3018 FREE(pc->param);
3019 if (pc->result)
3020 FREE(pc->result);
3021 if (pc->attr)
3022 FREE(pc->attr);
3023 if (pc->temp)
3024 FREE(pc->temp);
3025
3026 FREE(pc);
3027 }
3028
3029 static boolean
3030 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3031 {
3032 int i, c;
3033 unsigned rtype[2] = { P_ATTR, P_RESULT };
3034
3035 pc->p = p;
3036 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3037 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3038 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3039 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3040 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3041 assert(pc->addr_nr <= 2);
3042
3043 p->cfg.high_temp = 4;
3044
3045 p->cfg.two_side[0].hw = 0x40;
3046 p->cfg.two_side[1].hw = 0x40;
3047
3048 switch (p->type) {
3049 case PIPE_SHADER_VERTEX:
3050 p->cfg.psiz = 0x40;
3051 p->cfg.clpd = 0x40;
3052 p->cfg.io_nr = pc->result_nr;
3053 break;
3054 case PIPE_SHADER_FRAGMENT:
3055 rtype[0] = rtype[1] = P_TEMP;
3056
3057 p->cfg.regs[0] = 0x01000004;
3058 p->cfg.io_nr = pc->attr_nr;
3059
3060 if (p->info.writes_z) {
3061 p->cfg.regs[2] |= 0x00000100;
3062 p->cfg.regs[3] |= 0x00000011;
3063 }
3064 if (p->info.uses_kill)
3065 p->cfg.regs[2] |= 0x00100000;
3066 break;
3067 }
3068
3069 if (pc->temp_nr) {
3070 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3071 if (!pc->temp)
3072 return FALSE;
3073
3074 for (i = 0; i < pc->temp_nr * 4; ++i)
3075 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3076 }
3077
3078 if (pc->attr_nr) {
3079 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3080 if (!pc->attr)
3081 return FALSE;
3082
3083 for (i = 0; i < pc->attr_nr * 4; ++i)
3084 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3085 }
3086
3087 if (pc->result_nr) {
3088 unsigned nr = pc->result_nr * 4;
3089
3090 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3091 if (!pc->result)
3092 return FALSE;
3093
3094 for (i = 0; i < nr; ++i)
3095 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3096 }
3097
3098 if (pc->param_nr) {
3099 int rid = 0;
3100
3101 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3102 if (!pc->param)
3103 return FALSE;
3104
3105 for (i = 0; i < pc->param_nr; ++i)
3106 for (c = 0; c < 4; ++c, ++rid)
3107 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3108 }
3109
3110 if (pc->addr_nr) {
3111 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3112 if (!pc->addr)
3113 return FALSE;
3114 }
3115 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3116 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
3117
3118 return TRUE;
3119 }
3120
3121 static void
3122 nv50_fp_move_results(struct nv50_pc *pc)
3123 {
3124 struct nv50_reg reg;
3125 unsigned i;
3126
3127 ctor_reg(&reg, P_TEMP, -1, -1);
3128
3129 for (i = 0; i < pc->result_nr * 4; ++i) {
3130 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
3131 continue;
3132 if (pc->result[i].rhw != pc->result[i].hw) {
3133 reg.hw = pc->result[i].rhw;
3134 emit_mov(pc, &reg, &pc->result[i]);
3135 }
3136 }
3137 }
3138
3139 static void
3140 nv50_program_fixup_insns(struct nv50_pc *pc)
3141 {
3142 struct nv50_program_exec *e, **bra_list;
3143 unsigned i, n, pos;
3144
3145 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3146
3147 /* Collect branch instructions, we need to adjust their offsets
3148 * when converting 32 bit instructions to 64 bit ones
3149 */
3150 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3151 if (e->param.index >= 0 && !e->param.mask)
3152 bra_list[n++] = e;
3153
3154 /* last instruction must be long so it can have the exit bit set */
3155 if (!is_long(pc->p->exec_tail))
3156 convert_to_long(pc, pc->p->exec_tail);
3157 /* set exit bit */
3158 pc->p->exec_tail->inst[1] |= 1;
3159
3160 /* !immd on exit insn simultaneously means !join */
3161 assert(!is_immd(pc->p->exec_head));
3162 assert(!is_immd(pc->p->exec_tail));
3163
3164 /* Make sure we don't have any single 32 bit instructions. */
3165 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3166 pos += is_long(e) ? 2 : 1;
3167
3168 if ((pos & 1) && (!e->next || is_long(e->next))) {
3169 for (i = 0; i < n; ++i)
3170 if (bra_list[i]->param.index >= pos)
3171 bra_list[i]->param.index += 1;
3172 convert_to_long(pc, e);
3173 ++pos;
3174 }
3175 }
3176
3177 FREE(bra_list);
3178 }
3179
3180 static boolean
3181 nv50_program_tx(struct nv50_program *p)
3182 {
3183 struct tgsi_parse_context parse;
3184 struct nv50_pc *pc;
3185 boolean ret;
3186
3187 pc = CALLOC_STRUCT(nv50_pc);
3188 if (!pc)
3189 return FALSE;
3190
3191 ret = ctor_nv50_pc(pc, p);
3192 if (ret == FALSE)
3193 goto out_cleanup;
3194
3195 ret = nv50_program_tx_prep(pc);
3196 if (ret == FALSE)
3197 goto out_cleanup;
3198
3199 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3200 while (!tgsi_parse_end_of_tokens(&parse)) {
3201 const union tgsi_full_token *tok = &parse.FullToken;
3202
3203 /* don't allow half insn/immd on first and last instruction */
3204 pc->allow32 = TRUE;
3205 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr)
3206 pc->allow32 = FALSE;
3207
3208 tgsi_parse_token(&parse);
3209
3210 switch (tok->Token.Type) {
3211 case TGSI_TOKEN_TYPE_INSTRUCTION:
3212 ++pc->insn_cur;
3213 ret = nv50_tgsi_insn(pc, tok);
3214 if (ret == FALSE)
3215 goto out_err;
3216 break;
3217 default:
3218 break;
3219 }
3220 }
3221
3222 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3223 nv50_fp_move_results(pc);
3224
3225 nv50_program_fixup_insns(pc);
3226
3227 p->param_nr = pc->param_nr * 4;
3228 p->immd_nr = pc->immd_nr * 4;
3229 p->immd = pc->immd_buf;
3230
3231 out_err:
3232 tgsi_parse_free(&parse);
3233
3234 out_cleanup:
3235 free_nv50_pc(pc);
3236 return ret;
3237 }
3238
3239 static void
3240 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3241 {
3242 if (nv50_program_tx(p) == FALSE)
3243 assert(0);
3244 p->translated = TRUE;
3245 }
3246
3247 static void
3248 nv50_program_upload_data(struct nv50_context *nv50, float *map,
3249 unsigned start, unsigned count, unsigned cbuf)
3250 {
3251 struct nouveau_channel *chan = nv50->screen->base.channel;
3252 struct nouveau_grobj *tesla = nv50->screen->tesla;
3253
3254 while (count) {
3255 unsigned nr = count > 2047 ? 2047 : count;
3256
3257 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3258 OUT_RING (chan, (cbuf << 0) | (start << 8));
3259 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3260 OUT_RINGp (chan, map, nr);
3261
3262 map += nr;
3263 start += nr;
3264 count -= nr;
3265 }
3266 }
3267
3268 static void
3269 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3270 {
3271 struct pipe_screen *pscreen = nv50->pipe.screen;
3272
3273 if (!p->data[0] && p->immd_nr) {
3274 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3275
3276 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3277 while (heap->next && heap->size < p->immd_nr) {
3278 struct nv50_program *evict = heap->next->priv;
3279 nouveau_resource_free(&evict->data[0]);
3280 }
3281
3282 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3283 &p->data[0]))
3284 assert(0);
3285 }
3286
3287 /* immediates only need to be uploaded again when freed */
3288 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3289 p->immd_nr, NV50_CB_PMISC);
3290 }
3291
3292 assert(p->param_nr <= 512);
3293
3294 if (p->param_nr) {
3295 unsigned cb;
3296 float *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3297 PIPE_BUFFER_USAGE_CPU_READ);
3298
3299 if (p->type == PIPE_SHADER_VERTEX)
3300 cb = NV50_CB_PVP;
3301 else
3302 cb = NV50_CB_PFP;
3303
3304 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3305 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3306 }
3307 }
3308
3309 static void
3310 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3311 {
3312 struct nouveau_channel *chan = nv50->screen->base.channel;
3313 struct nv50_program_exec *e;
3314 uint32_t *up, i;
3315 boolean upload = FALSE;
3316
3317 if (!p->bo) {
3318 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3319 p->exec_size * 4, &p->bo);
3320 upload = TRUE;
3321 }
3322
3323 if (p->data[0] && p->data[0]->start != p->data_start[0])
3324 upload = TRUE;
3325
3326 if (!upload)
3327 return;
3328
3329 up = MALLOC(p->exec_size * 4);
3330
3331 for (i = 0, e = p->exec_head; e; e = e->next) {
3332 unsigned ei, ci, bs;
3333
3334 if (e->param.index >= 0 && e->param.mask) {
3335 bs = (e->inst[1] >> 22) & 0x07;
3336 assert(bs < 2);
3337 ei = e->param.shift >> 5;
3338 ci = e->param.index;
3339 if (bs == 0)
3340 ci += p->data[bs]->start;
3341
3342 e->inst[ei] &= ~e->param.mask;
3343 e->inst[ei] |= (ci << e->param.shift);
3344 } else
3345 if (e->param.index >= 0) {
3346 /* zero mask means param is a jump/branch offset */
3347 assert(!(e->param.index & 1));
3348 /* seem to be 8 byte steps */
3349 ei = (e->param.index >> 1) + 0 /* START_ID */;
3350
3351 e->inst[0] &= 0xf0000fff;
3352 e->inst[0] |= ei << 12;
3353 }
3354
3355 up[i++] = e->inst[0];
3356 if (is_long(e))
3357 up[i++] = e->inst[1];
3358 }
3359 assert(i == p->exec_size);
3360
3361 if (p->data[0])
3362 p->data_start[0] = p->data[0]->start;
3363
3364 #ifdef NV50_PROGRAM_DUMP
3365 NOUVEAU_ERR("-------\n");
3366 for (e = p->exec_head; e; e = e->next) {
3367 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3368 if (is_long(e))
3369 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3370 }
3371 #endif
3372 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3373 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3374 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3375 0, 0, p->exec_size * 4, 1, 1);
3376
3377 FREE(up);
3378 }
3379
3380 void
3381 nv50_vertprog_validate(struct nv50_context *nv50)
3382 {
3383 struct nouveau_grobj *tesla = nv50->screen->tesla;
3384 struct nv50_program *p = nv50->vertprog;
3385 struct nouveau_stateobj *so;
3386
3387 if (!p->translated) {
3388 nv50_program_validate(nv50, p);
3389 if (!p->translated)
3390 assert(0);
3391 }
3392
3393 nv50_program_validate_data(nv50, p);
3394 nv50_program_validate_code(nv50, p);
3395
3396 so = so_new(13, 2);
3397 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3398 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3399 NOUVEAU_BO_HIGH, 0, 0);
3400 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3401 NOUVEAU_BO_LOW, 0, 0);
3402 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3403 so_data (so, p->cfg.attr[0]);
3404 so_data (so, p->cfg.attr[1]);
3405 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3406 so_data (so, p->cfg.high_result);
3407 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3408 so_data (so, p->cfg.high_result); //8);
3409 so_data (so, p->cfg.high_temp);
3410 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3411 so_data (so, 0); /* program start offset */
3412 so_ref(so, &nv50->state.vertprog);
3413 so_ref(NULL, &so);
3414 }
3415
3416 void
3417 nv50_fragprog_validate(struct nv50_context *nv50)
3418 {
3419 struct nouveau_grobj *tesla = nv50->screen->tesla;
3420 struct nv50_program *p = nv50->fragprog;
3421 struct nouveau_stateobj *so;
3422
3423 if (!p->translated) {
3424 nv50_program_validate(nv50, p);
3425 if (!p->translated)
3426 assert(0);
3427 }
3428
3429 nv50_program_validate_data(nv50, p);
3430 nv50_program_validate_code(nv50, p);
3431
3432 so = so_new(64, 2);
3433 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3434 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3435 NOUVEAU_BO_HIGH, 0, 0);
3436 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3437 NOUVEAU_BO_LOW, 0, 0);
3438 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3439 so_data (so, p->cfg.high_temp);
3440 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3441 so_data (so, p->cfg.high_result);
3442 so_method(so, tesla, NV50TCL_FP_CTRL_UNK19A8, 1);
3443 so_data (so, p->cfg.regs[2]);
3444 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3445 so_data (so, p->cfg.regs[3]);
3446 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3447 so_data (so, 0); /* program start offset */
3448 so_ref(so, &nv50->state.fragprog);
3449 so_ref(NULL, &so);
3450 }
3451
3452 static void
3453 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3454 {
3455 struct nv50_program *fp = nv50->fragprog;
3456 struct nv50_program *vp = nv50->vertprog;
3457 unsigned i, c, m = base;
3458
3459 /* XXX: this might not work correctly in all cases yet - we'll
3460 * just assume that an FP generic input that is not written in
3461 * the VP is PointCoord.
3462 */
3463 memset(pntc, 0, 8 * sizeof(uint32_t));
3464
3465 for (i = 0; i < fp->cfg.io_nr; i++) {
3466 uint8_t sn, si;
3467 uint8_t j, k = fp->cfg.io[i].id;
3468 unsigned n = popcnt4(fp->cfg.io[i].mask);
3469
3470 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3471 m += n;
3472 continue;
3473 }
3474
3475 for (j = 0; j < vp->info.num_outputs; ++j) {
3476 sn = vp->info.output_semantic_name[j];
3477 si = vp->info.output_semantic_index[j];
3478
3479 if (sn == fp->info.input_semantic_name[k] &&
3480 si == fp->info.input_semantic_index[k])
3481 break;
3482 }
3483
3484 if (j < vp->info.num_outputs) {
3485 ubyte mode =
3486 nv50->rasterizer->pipe.sprite_coord_mode[si];
3487
3488 if (mode == PIPE_SPRITE_COORD_NONE) {
3489 m += n;
3490 continue;
3491 }
3492 }
3493
3494 /* this is either PointCoord or replaced by sprite coords */
3495 for (c = 0; c < 4; c++) {
3496 if (!(fp->cfg.io[i].mask & (1 << c)))
3497 continue;
3498 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3499 ++m;
3500 }
3501 }
3502 }
3503
3504 static int
3505 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3506 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3507 {
3508 int c;
3509 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3510 uint8_t *map = (uint8_t *)p_map;
3511
3512 for (c = 0; c < 4; ++c) {
3513 if (mf & 1) {
3514 if (fpi->linear == TRUE)
3515 lin[mid / 32] |= 1 << (mid % 32);
3516 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3517 }
3518
3519 oid += mv & 1;
3520 mf >>= 1;
3521 mv >>= 1;
3522 }
3523
3524 return mid;
3525 }
3526
3527 void
3528 nv50_linkage_validate(struct nv50_context *nv50)
3529 {
3530 struct nouveau_grobj *tesla = nv50->screen->tesla;
3531 struct nv50_program *vp = nv50->vertprog;
3532 struct nv50_program *fp = nv50->fragprog;
3533 struct nouveau_stateobj *so;
3534 struct nv50_sreg4 dummy, *vpo;
3535 int i, n, c, m = 0;
3536 uint32_t map[16], lin[4], reg[5], pcrd[8];
3537
3538 memset(map, 0, sizeof(map));
3539 memset(lin, 0, sizeof(lin));
3540
3541 reg[1] = 0x00000004; /* low and high clip distance map ids */
3542 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3543 reg[3] = 0x00000000; /* point size map id & enable */
3544 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3545 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3546
3547 dummy.linear = FALSE;
3548 dummy.mask = 0xf; /* map all components of HPOS */
3549 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3550
3551 dummy.mask = 0x0;
3552
3553 if (vp->cfg.clpd < 0x40) {
3554 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3555 map[m++] = vp->cfg.clpd + c;
3556 reg[1] = (m << 8);
3557 }
3558
3559 reg[0] |= m << 8; /* adjust BFC0 id */
3560
3561 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3562 if (nv50->rasterizer->pipe.light_twoside) {
3563 vpo = &vp->cfg.two_side[0];
3564
3565 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3566 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3567 }
3568
3569 reg[0] += m - 4; /* adjust FFC0 id */
3570 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3571
3572 for (i = 0; i < fp->cfg.io_nr; i++) {
3573 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
3574 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
3575
3576 /* position must be mapped first */
3577 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
3578
3579 /* maybe even remove these from cfg.io */
3580 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
3581 continue;
3582
3583 /* VP outputs and vp->cfg.io are in the same order */
3584 for (n = 0; n < vp->info.num_outputs; ++n) {
3585 if (vp->info.output_semantic_name[n] == sn &&
3586 vp->info.output_semantic_index[n] == si)
3587 break;
3588 }
3589 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
3590
3591 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3592 }
3593
3594 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3595 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3596 reg[3] = (m++ << 4) | 1;
3597 }
3598
3599 /* now fill the stateobj */
3600 so = so_new(64, 0);
3601
3602 n = (m + 3) / 4;
3603 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3604 so_data (so, m);
3605 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3606 so_datap (so, map, n);
3607
3608 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3609 so_datap (so, reg, 4);
3610
3611 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3612 so_data (so, reg[4]);
3613
3614 so_method(so, tesla, 0x1540, 4);
3615 so_datap (so, lin, 4);
3616
3617 if (nv50->rasterizer->pipe.point_sprite) {
3618 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3619
3620 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3621 so_datap (so, pcrd, 8);
3622 }
3623
3624 so_ref(so, &nv50->state.programs);
3625 so_ref(NULL, &so);
3626 }
3627
3628 void
3629 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3630 {
3631 while (p->exec_head) {
3632 struct nv50_program_exec *e = p->exec_head;
3633
3634 p->exec_head = e->next;
3635 FREE(e);
3636 }
3637 p->exec_tail = NULL;
3638 p->exec_size = 0;
3639
3640 nouveau_bo_ref(NULL, &p->bo);
3641
3642 nouveau_resource_free(&p->data[0]);
3643
3644 p->translated = 0;
3645 }