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nv50: handle TGSI_OPCODE_IMAX,IMIN,UMAX,UMIN
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
100 #define NV50_MOD_SAT 4
101 #define NV50_MOD_I32 8
102
103 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
104
105 /* STACK: Conditionals and loops have to use the (per warp) stack.
106 * Stack entries consist of an entry type (divergent path, join at),
107 * a mask indicating the active threads of the warp, and an address.
108 * MPs can store 12 stack entries internally, if we need more (and
109 * we probably do), we have to create a stack buffer in VRAM.
110 */
111 /* impose low limits for now */
112 #define NV50_MAX_COND_NESTING 4
113 #define NV50_MAX_LOOP_NESTING 3
114
115 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
116
117 struct nv50_pc {
118 struct nv50_program *p;
119
120 /* hw resources */
121 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
122 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
123
124 /* tgsi resources */
125 struct nv50_reg *temp;
126 int temp_nr;
127 struct nv50_reg *attr;
128 int attr_nr;
129 struct nv50_reg *result;
130 int result_nr;
131 struct nv50_reg *param;
132 int param_nr;
133 struct nv50_reg *immd;
134 uint32_t *immd_buf;
135 int immd_nr;
136 struct nv50_reg **addr;
137 int addr_nr;
138 uint8_t addr_alloc; /* set bit indicates used for TGSI_FILE_ADDRESS */
139
140 struct nv50_reg *temp_temp[16];
141 unsigned temp_temp_nr;
142
143 /* broadcast and destination replacement regs */
144 struct nv50_reg *r_brdc;
145 struct nv50_reg *r_dst[4];
146
147 struct nv50_reg reg_instances[16];
148 unsigned reg_instance_nr;
149
150 unsigned interp_mode[32];
151 /* perspective interpolation registers */
152 struct nv50_reg *iv_p;
153 struct nv50_reg *iv_c;
154
155 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
156 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
157 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
158 int if_lvl, loop_lvl;
159 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
160
161 unsigned *insn_pos; /* actual program offset of each TGSI insn */
162 boolean in_subroutine;
163
164 /* current instruction and total number of insns */
165 unsigned insn_cur;
166 unsigned insn_nr;
167
168 boolean allow32;
169
170 uint8_t edgeflag_out;
171 };
172
173 static INLINE void
174 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
175 {
176 reg->type = type;
177 reg->index = index;
178 reg->hw = hw;
179 reg->mod = 0;
180 reg->rhw = -1;
181 reg->acc = 0;
182 }
183
184 static INLINE unsigned
185 popcnt4(uint32_t val)
186 {
187 static const unsigned cnt[16]
188 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
189 return cnt[val & 0xf];
190 }
191
192 static void
193 terminate_mbb(struct nv50_pc *pc)
194 {
195 int i;
196
197 /* remove records of temporary address register values */
198 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
199 pc->r_addr[i].rhw = -1;
200 }
201
202 static void
203 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
204 {
205 int i = 0;
206
207 if (reg->type == P_RESULT) {
208 if (pc->p->cfg.high_result < (reg->hw + 1))
209 pc->p->cfg.high_result = reg->hw + 1;
210 }
211
212 if (reg->type != P_TEMP)
213 return;
214
215 if (reg->hw >= 0) {
216 /*XXX: do this here too to catch FP temp-as-attr usage..
217 * not clean, but works */
218 if (pc->p->cfg.high_temp < (reg->hw + 1))
219 pc->p->cfg.high_temp = reg->hw + 1;
220 return;
221 }
222
223 if (reg->rhw != -1) {
224 /* try to allocate temporary with index rhw first */
225 if (!(pc->r_temp[reg->rhw])) {
226 pc->r_temp[reg->rhw] = reg;
227 reg->hw = reg->rhw;
228 if (pc->p->cfg.high_temp < (reg->rhw + 1))
229 pc->p->cfg.high_temp = reg->rhw + 1;
230 return;
231 }
232 /* make sure we don't get things like $r0 needs to go
233 * in $r1 and $r1 in $r0
234 */
235 i = pc->result_nr * 4;
236 }
237
238 for (; i < NV50_SU_MAX_TEMP; i++) {
239 if (!(pc->r_temp[i])) {
240 pc->r_temp[i] = reg;
241 reg->hw = i;
242 if (pc->p->cfg.high_temp < (i + 1))
243 pc->p->cfg.high_temp = i + 1;
244 return;
245 }
246 }
247
248 assert(0);
249 }
250
251 static INLINE struct nv50_reg *
252 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
253 {
254 struct nv50_reg *ri;
255
256 assert(pc->reg_instance_nr < 16);
257 ri = &pc->reg_instances[pc->reg_instance_nr++];
258 if (reg) {
259 alloc_reg(pc, reg);
260 *ri = *reg;
261 reg->mod = 0;
262 }
263 return ri;
264 }
265
266 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
267 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
268 * lest we risk temp_temps overwriting regs alloc'd "later".
269 */
270 static struct nv50_reg *
271 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
272 {
273 struct nv50_reg *r;
274 int i;
275
276 if (dst && dst->type == P_TEMP && dst->hw == -1)
277 return dst;
278
279 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
280 if (!pc->r_temp[i]) {
281 r = MALLOC_STRUCT(nv50_reg);
282 ctor_reg(r, P_TEMP, -1, i);
283 pc->r_temp[i] = r;
284 return r;
285 }
286 }
287
288 assert(0);
289 return NULL;
290 }
291
292 /* release the hardware resource held by r */
293 static void
294 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
295 {
296 assert(r->type == P_TEMP);
297 if (r->hw == -1)
298 return;
299
300 assert(pc->r_temp[r->hw] == r);
301 pc->r_temp[r->hw] = NULL;
302
303 r->acc = 0;
304 if (r->index == -1)
305 FREE(r);
306 }
307
308 static void
309 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
310 {
311 if (r->index == -1) {
312 unsigned hw = r->hw;
313
314 FREE(pc->r_temp[hw]);
315 pc->r_temp[hw] = NULL;
316 }
317 }
318
319 static int
320 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
321 {
322 int i;
323
324 if ((idx + 4) >= NV50_SU_MAX_TEMP)
325 return 1;
326
327 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
328 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
329 return alloc_temp4(pc, dst, idx + 4);
330
331 for (i = 0; i < 4; i++) {
332 dst[i] = MALLOC_STRUCT(nv50_reg);
333 ctor_reg(dst[i], P_TEMP, -1, idx + i);
334 pc->r_temp[idx + i] = dst[i];
335 }
336
337 return 0;
338 }
339
340 static void
341 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
342 {
343 int i;
344
345 for (i = 0; i < 4; i++)
346 free_temp(pc, reg[i]);
347 }
348
349 static struct nv50_reg *
350 temp_temp(struct nv50_pc *pc)
351 {
352 if (pc->temp_temp_nr >= 16)
353 assert(0);
354
355 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
356 return pc->temp_temp[pc->temp_temp_nr++];
357 }
358
359 static void
360 kill_temp_temp(struct nv50_pc *pc)
361 {
362 int i;
363
364 for (i = 0; i < pc->temp_temp_nr; i++)
365 free_temp(pc, pc->temp_temp[i]);
366 pc->temp_temp_nr = 0;
367 }
368
369 static int
370 ctor_immd_4u32(struct nv50_pc *pc,
371 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
372 {
373 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
374
375 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
376
377 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
378 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
379 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
380 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
381
382 return pc->immd_nr++;
383 }
384
385 static INLINE int
386 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
387 {
388 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
389 }
390
391 static struct nv50_reg *
392 alloc_immd(struct nv50_pc *pc, float f)
393 {
394 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
395 unsigned hw;
396
397 for (hw = 0; hw < pc->immd_nr * 4; hw++)
398 if (pc->immd_buf[hw] == fui(f))
399 break;
400
401 if (hw == pc->immd_nr * 4)
402 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
403
404 ctor_reg(r, P_IMMD, -1, hw);
405 return r;
406 }
407
408 static struct nv50_program_exec *
409 exec(struct nv50_pc *pc)
410 {
411 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
412
413 e->param.index = -1;
414 return e;
415 }
416
417 static void
418 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
419 {
420 struct nv50_program *p = pc->p;
421
422 if (p->exec_tail)
423 p->exec_tail->next = e;
424 if (!p->exec_head)
425 p->exec_head = e;
426 p->exec_tail = e;
427 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
428 }
429
430 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
431
432 static boolean
433 is_long(struct nv50_program_exec *e)
434 {
435 if (e->inst[0] & 1)
436 return TRUE;
437 return FALSE;
438 }
439
440 static boolean
441 is_immd(struct nv50_program_exec *e)
442 {
443 if (is_long(e) && (e->inst[1] & 3) == 3)
444 return TRUE;
445 return FALSE;
446 }
447
448 static boolean
449 is_join(struct nv50_program_exec *e)
450 {
451 if (is_long(e) && (e->inst[1] & 3) == 2)
452 return TRUE;
453 return FALSE;
454 }
455
456 static INLINE void
457 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
458 struct nv50_program_exec *e)
459 {
460 assert(!is_immd(e));
461 set_long(pc, e);
462 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
463 e->inst[1] |= (pred << 7) | (idx << 12);
464 }
465
466 static INLINE void
467 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
468 struct nv50_program_exec *e)
469 {
470 set_long(pc, e);
471 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
472 e->inst[1] |= (idx << 4) | (on << 6);
473 }
474
475 static INLINE void
476 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
477 {
478 if (is_long(e))
479 return;
480
481 e->inst[0] |= 1;
482 set_pred(pc, 0xf, 0, e);
483 set_pred_wr(pc, 0, 0, e);
484 }
485
486 static INLINE void
487 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
488 {
489 if (dst->type == P_RESULT) {
490 set_long(pc, e);
491 e->inst[1] |= 0x00000008;
492 }
493
494 alloc_reg(pc, dst);
495 if (dst->hw > 63)
496 set_long(pc, e);
497 e->inst[0] |= (dst->hw << 2);
498 }
499
500 static INLINE void
501 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
502 {
503 set_long(pc, e);
504 /* XXX: can't be predicated - bits overlap; cases where both
505 * are required should be avoided by using pc->allow32 */
506 set_pred(pc, 0, 0, e);
507 set_pred_wr(pc, 0, 0, e);
508
509 e->inst[1] |= 0x00000002 | 0x00000001;
510 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
511 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
512 }
513
514 static INLINE void
515 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
516 {
517 assert(!(e->inst[0] & 0x0c000000));
518 assert(!(e->inst[1] & 0x00000004));
519
520 e->inst[0] |= (a->hw & 3) << 26;
521 e->inst[1] |= (a->hw >> 2) << 2;
522 }
523
524 static void
525 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
526 struct nv50_reg *src0, uint16_t src1_val)
527 {
528 struct nv50_program_exec *e = exec(pc);
529
530 e->inst[0] = 0xd0000000 | (src1_val << 9);
531 e->inst[1] = 0x20000000;
532 set_long(pc, e);
533 e->inst[0] |= dst->hw << 2;
534 if (src0) /* otherwise will add to $a0, which is always 0 */
535 set_addr(e, src0);
536
537 emit(pc, e);
538 }
539
540 static struct nv50_reg *
541 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
542 {
543 struct nv50_reg *a_tgsi = NULL, *a = NULL;
544 int i;
545 uint8_t avail = ~pc->addr_alloc;
546
547 if (!ref) {
548 /* allocate for TGSI_FILE_ADDRESS */
549 while (avail) {
550 i = ffs(avail) - 1;
551
552 if (pc->r_addr[i].rhw < 0 ||
553 pc->r_addr[i].acc != pc->insn_cur) {
554 pc->addr_alloc |= (1 << i);
555
556 pc->r_addr[i].rhw = -1;
557 pc->r_addr[i].index = i;
558 return &pc->r_addr[i];
559 }
560 avail &= ~(1 << i);
561 }
562 assert(0);
563 return NULL;
564 }
565
566 /* Allocate and set an address reg so we can access 'ref'.
567 *
568 * If and r_addr->index will be -1 or the hw index the value
569 * value in rhw is relative to. If rhw < 0, the reg has not
570 * been initialized or is in use for TGSI_FILE_ADDRESS.
571 */
572 while (avail) { /* only consider regs that are not TGSI */
573 i = ffs(avail) - 1;
574 avail &= ~(1 << i);
575
576 if ((!a || a->rhw >= 0) && pc->r_addr[i].rhw < 0) {
577 /* prefer an usused reg with low hw index */
578 a = &pc->r_addr[i];
579 continue;
580 }
581 if (!a && pc->r_addr[i].acc != pc->insn_cur)
582 a = &pc->r_addr[i];
583
584 if (ref->hw - pc->r_addr[i].rhw >= 128)
585 continue;
586
587 if ((ref->acc >= 0 && pc->r_addr[i].index < 0) ||
588 (ref->acc < 0 && pc->r_addr[i].index == ref->index)) {
589 pc->r_addr[i].acc = pc->insn_cur;
590 return &pc->r_addr[i];
591 }
592 }
593 assert(a);
594
595 if (ref->acc < 0)
596 a_tgsi = pc->addr[ref->index];
597
598 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
599
600 a->rhw = ref->hw & ~0x7f;
601 a->acc = pc->insn_cur;
602 a->index = a_tgsi ? ref->index : -1;
603 return a;
604 }
605
606 #define INTERP_LINEAR 0
607 #define INTERP_FLAT 1
608 #define INTERP_PERSPECTIVE 2
609 #define INTERP_CENTROID 4
610
611 /* interpolant index has been stored in dst->rhw */
612 static void
613 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
614 unsigned mode)
615 {
616 assert(dst->rhw != -1);
617 struct nv50_program_exec *e = exec(pc);
618
619 e->inst[0] |= 0x80000000;
620 set_dst(pc, dst, e);
621 e->inst[0] |= (dst->rhw << 16);
622
623 if (mode & INTERP_FLAT) {
624 e->inst[0] |= (1 << 8);
625 } else {
626 if (mode & INTERP_PERSPECTIVE) {
627 e->inst[0] |= (1 << 25);
628 alloc_reg(pc, iv);
629 e->inst[0] |= (iv->hw << 9);
630 }
631
632 if (mode & INTERP_CENTROID)
633 e->inst[0] |= (1 << 24);
634 }
635
636 emit(pc, e);
637 }
638
639 static void
640 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
641 struct nv50_program_exec *e)
642 {
643 set_long(pc, e);
644
645 e->param.index = src->hw & 127;
646 e->param.shift = s;
647 e->param.mask = m << (s % 32);
648
649 if (src->hw > 127)
650 set_addr(e, alloc_addr(pc, src));
651 else
652 if (src->acc < 0) {
653 assert(src->type == P_CONST);
654 set_addr(e, pc->addr[src->index]);
655 }
656
657 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
658 }
659
660 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
661 static void
662 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
663 {
664 struct nv50_program_exec *e = exec(pc);
665
666 e->inst[0] = 0x10000000;
667 if (!pc->allow32)
668 set_long(pc, e);
669
670 set_dst(pc, dst, e);
671
672 if (!is_long(e) && src->type == P_IMMD) {
673 set_immd(pc, src, e);
674 /*XXX: 32-bit, but steals part of "half" reg space - need to
675 * catch and handle this case if/when we do half-regs
676 */
677 } else
678 if (src->type == P_IMMD || src->type == P_CONST) {
679 set_long(pc, e);
680 set_data(pc, src, 0x7f, 9, e);
681 e->inst[1] |= 0x20000000; /* mov from c[] */
682 } else {
683 if (src->type == P_ATTR) {
684 set_long(pc, e);
685 e->inst[1] |= 0x00200000;
686 }
687
688 alloc_reg(pc, src);
689 if (src->hw > 63)
690 set_long(pc, e);
691 e->inst[0] |= (src->hw << 9);
692 }
693
694 if (is_long(e) && !is_immd(e)) {
695 e->inst[1] |= 0x04000000; /* 32-bit */
696 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
697 if (!(e->inst[1] & 0x20000000))
698 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
699 } else
700 e->inst[0] |= 0x00008000;
701
702 emit(pc, e);
703 }
704
705 static INLINE void
706 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
707 {
708 struct nv50_reg *imm = alloc_immd(pc, f);
709 emit_mov(pc, dst, imm);
710 FREE(imm);
711 }
712
713 /* Assign the hw of the discarded temporary register src
714 * to the tgsi register dst and free src.
715 */
716 static void
717 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
718 {
719 assert(src->index == -1 && src->hw != -1);
720
721 if (pc->if_lvl || pc->loop_lvl ||
722 (dst->type != P_TEMP) ||
723 (src->hw < pc->result_nr * 4 &&
724 pc->p->type == PIPE_SHADER_FRAGMENT) ||
725 pc->p->info.opcode_count[TGSI_OPCODE_CAL] ||
726 pc->p->info.opcode_count[TGSI_OPCODE_BRA]) {
727
728 emit_mov(pc, dst, src);
729 free_temp(pc, src);
730 return;
731 }
732
733 if (dst->hw != -1)
734 pc->r_temp[dst->hw] = NULL;
735 pc->r_temp[src->hw] = dst;
736 dst->hw = src->hw;
737
738 FREE(src);
739 }
740
741 static void
742 emit_nop(struct nv50_pc *pc)
743 {
744 struct nv50_program_exec *e = exec(pc);
745
746 e->inst[0] = 0xf0000000;
747 set_long(pc, e);
748 e->inst[1] = 0xe0000000;
749 emit(pc, e);
750 }
751
752 static boolean
753 check_swap_src_0_1(struct nv50_pc *pc,
754 struct nv50_reg **s0, struct nv50_reg **s1)
755 {
756 struct nv50_reg *src0 = *s0, *src1 = *s1;
757
758 if (src0->type == P_CONST) {
759 if (src1->type != P_CONST) {
760 *s0 = src1;
761 *s1 = src0;
762 return TRUE;
763 }
764 } else
765 if (src1->type == P_ATTR) {
766 if (src0->type != P_ATTR) {
767 *s0 = src1;
768 *s1 = src0;
769 return TRUE;
770 }
771 }
772
773 return FALSE;
774 }
775
776 static void
777 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
778 struct nv50_program_exec *e)
779 {
780 struct nv50_reg *temp;
781
782 if (src->type != P_TEMP) {
783 temp = temp_temp(pc);
784 emit_mov(pc, temp, src);
785 src = temp;
786 }
787
788 alloc_reg(pc, src);
789 if (src->hw > 63)
790 set_long(pc, e);
791 e->inst[0] |= (src->hw << 9);
792 }
793
794 static void
795 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
796 {
797 if (src->type == P_ATTR) {
798 set_long(pc, e);
799 e->inst[1] |= 0x00200000;
800 } else
801 if (src->type == P_CONST || src->type == P_IMMD) {
802 struct nv50_reg *temp = temp_temp(pc);
803
804 emit_mov(pc, temp, src);
805 src = temp;
806 }
807
808 alloc_reg(pc, src);
809 if (src->hw > 63)
810 set_long(pc, e);
811 e->inst[0] |= (src->hw << 9);
812 }
813
814 static void
815 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
816 {
817 if (src->type == P_ATTR) {
818 struct nv50_reg *temp = temp_temp(pc);
819
820 emit_mov(pc, temp, src);
821 src = temp;
822 } else
823 if (src->type == P_CONST || src->type == P_IMMD) {
824 assert(!(e->inst[0] & 0x00800000));
825 if (e->inst[0] & 0x01000000) {
826 struct nv50_reg *temp = temp_temp(pc);
827
828 emit_mov(pc, temp, src);
829 src = temp;
830 } else {
831 set_data(pc, src, 0x7f, 16, e);
832 e->inst[0] |= 0x00800000;
833 }
834 }
835
836 alloc_reg(pc, src);
837 if (src->hw > 63)
838 set_long(pc, e);
839 e->inst[0] |= ((src->hw & 127) << 16);
840 }
841
842 static void
843 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
844 {
845 set_long(pc, e);
846
847 if (src->type == P_ATTR) {
848 struct nv50_reg *temp = temp_temp(pc);
849
850 emit_mov(pc, temp, src);
851 src = temp;
852 } else
853 if (src->type == P_CONST || src->type == P_IMMD) {
854 assert(!(e->inst[0] & 0x01000000));
855 if (e->inst[0] & 0x00800000) {
856 struct nv50_reg *temp = temp_temp(pc);
857
858 emit_mov(pc, temp, src);
859 src = temp;
860 } else {
861 set_data(pc, src, 0x7f, 32+14, e);
862 e->inst[0] |= 0x01000000;
863 }
864 }
865
866 alloc_reg(pc, src);
867 e->inst[1] |= ((src->hw & 127) << 14);
868 }
869
870 static void
871 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
872 {
873 struct nv50_program_exec *e = exec(pc);
874
875 assert(dst->type == P_TEMP);
876 e->inst[1] = 0x20000000 | (pred << 12);
877 set_long(pc, e);
878 set_dst(pc, dst, e);
879
880 emit(pc, e);
881 }
882
883 static void
884 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
885 {
886 struct nv50_program_exec *e = exec(pc);
887
888 e->inst[0] = 0x000001fc;
889 e->inst[1] = 0xa0000008;
890 set_long(pc, e);
891 set_pred_wr(pc, 1, pred, e);
892 set_src_0_restricted(pc, src, e);
893
894 emit(pc, e);
895 }
896
897 static void
898 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
899 struct nv50_reg *src1)
900 {
901 struct nv50_program_exec *e = exec(pc);
902
903 e->inst[0] |= 0xc0000000;
904
905 if (!pc->allow32)
906 set_long(pc, e);
907
908 check_swap_src_0_1(pc, &src0, &src1);
909 set_dst(pc, dst, e);
910 set_src_0(pc, src0, e);
911 if (src1->type == P_IMMD && !is_long(e)) {
912 if (src0->mod ^ src1->mod)
913 e->inst[0] |= 0x00008000;
914 set_immd(pc, src1, e);
915 } else {
916 set_src_1(pc, src1, e);
917 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
918 if (is_long(e))
919 e->inst[1] |= 0x08000000;
920 else
921 e->inst[0] |= 0x00008000;
922 }
923 }
924
925 emit(pc, e);
926 }
927
928 static void
929 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
930 struct nv50_reg *src0, struct nv50_reg *src1)
931 {
932 struct nv50_program_exec *e = exec(pc);
933
934 e->inst[0] = 0xb0000000;
935
936 alloc_reg(pc, src1);
937 check_swap_src_0_1(pc, &src0, &src1);
938
939 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
940 set_long(pc, e);
941 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
942 ((src1->mod & NV50_MOD_NEG) << 27);
943 }
944
945 set_dst(pc, dst, e);
946 set_src_0(pc, src0, e);
947 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
948 set_src_2(pc, src1, e);
949 else
950 if (src1->type == P_IMMD)
951 set_immd(pc, src1, e);
952 else
953 set_src_1(pc, src1, e);
954
955 emit(pc, e);
956 }
957
958 static void
959 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
960 uint8_t s)
961 {
962 struct nv50_program_exec *e = exec(pc);
963
964 set_long(pc, e);
965 e->inst[1] |= 0xc0000000;
966
967 e->inst[0] |= dst->hw << 2;
968 e->inst[0] |= s << 16; /* shift left */
969 set_src_0_restricted(pc, src, e);
970
971 emit(pc, e);
972 }
973
974 #define NV50_MAX_F32 0x880
975 #define NV50_MAX_S32 0x08c
976 #define NV50_MAX_U32 0x084
977 #define NV50_MIN_F32 0x8a0
978 #define NV50_MIN_S32 0x0ac
979 #define NV50_MIN_U32 0x0a4
980
981 static void
982 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
983 struct nv50_reg *src0, struct nv50_reg *src1)
984 {
985 struct nv50_program_exec *e = exec(pc);
986
987 set_long(pc, e);
988 e->inst[0] |= 0x30000000 | ((sub & 0x800) << 20);
989 e->inst[1] |= (sub << 24);
990
991 check_swap_src_0_1(pc, &src0, &src1);
992 set_dst(pc, dst, e);
993 set_src_0(pc, src0, e);
994 set_src_1(pc, src1, e);
995
996 if (src0->mod & NV50_MOD_ABS)
997 e->inst[1] |= 0x00100000;
998 if (src1->mod & NV50_MOD_ABS)
999 e->inst[1] |= 0x00080000;
1000
1001 emit(pc, e);
1002 }
1003
1004 static INLINE void
1005 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1006 struct nv50_reg *src1)
1007 {
1008 src1->mod ^= NV50_MOD_NEG;
1009 emit_add(pc, dst, src0, src1);
1010 src1->mod ^= NV50_MOD_NEG;
1011 }
1012
1013 static void
1014 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1015 struct nv50_reg *src1, unsigned op)
1016 {
1017 struct nv50_program_exec *e = exec(pc);
1018
1019 e->inst[0] = 0xd0000000;
1020 set_long(pc, e);
1021
1022 check_swap_src_0_1(pc, &src0, &src1);
1023 set_dst(pc, dst, e);
1024 set_src_0(pc, src0, e);
1025
1026 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1027 op != TGSI_OPCODE_XOR)
1028 assert(!"invalid bit op");
1029
1030 assert(!(src0->mod | src1->mod));
1031
1032 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1033 set_immd(pc, src1, e);
1034 if (op == TGSI_OPCODE_OR)
1035 e->inst[0] |= 0x0100;
1036 else
1037 if (op == TGSI_OPCODE_XOR)
1038 e->inst[0] |= 0x8000;
1039 } else {
1040 set_src_1(pc, src1, e);
1041 e->inst[1] |= 0x04000000; /* 32 bit */
1042 if (op == TGSI_OPCODE_OR)
1043 e->inst[1] |= 0x4000;
1044 else
1045 if (op == TGSI_OPCODE_XOR)
1046 e->inst[1] |= 0x8000;
1047 }
1048
1049 emit(pc, e);
1050 }
1051
1052 static void
1053 emit_shift(struct nv50_pc *pc, struct nv50_reg *dst,
1054 struct nv50_reg *src0, struct nv50_reg *src1, unsigned dir)
1055 {
1056 struct nv50_program_exec *e = exec(pc);
1057
1058 e->inst[0] = 0x30000000;
1059 e->inst[1] = 0xc4000000;
1060
1061 set_long(pc, e);
1062 set_dst(pc, dst, e);
1063 set_src_0(pc, src0, e);
1064
1065 if (src1->type == P_IMMD) {
1066 e->inst[1] |= (1 << 20);
1067 e->inst[0] |= (pc->immd_buf[src1->hw] & 0x7f) << 16;
1068 } else
1069 set_src_1(pc, src1, e);
1070
1071 if (dir != TGSI_OPCODE_SHL)
1072 e->inst[1] |= (1 << 29);
1073
1074 if (dir == TGSI_OPCODE_ISHR)
1075 e->inst[1] |= (1 << 27);
1076
1077 emit(pc, e);
1078 }
1079
1080 static void
1081 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1082 struct nv50_reg *src1, struct nv50_reg *src2)
1083 {
1084 struct nv50_program_exec *e = exec(pc);
1085
1086 e->inst[0] |= 0xe0000000;
1087
1088 check_swap_src_0_1(pc, &src0, &src1);
1089 set_dst(pc, dst, e);
1090 set_src_0(pc, src0, e);
1091 set_src_1(pc, src1, e);
1092 set_src_2(pc, src2, e);
1093
1094 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1095 e->inst[1] |= 0x04000000;
1096 if (src2->mod & NV50_MOD_NEG)
1097 e->inst[1] |= 0x08000000;
1098
1099 emit(pc, e);
1100 }
1101
1102 static INLINE void
1103 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1104 struct nv50_reg *src1, struct nv50_reg *src2)
1105 {
1106 src2->mod ^= NV50_MOD_NEG;
1107 emit_mad(pc, dst, src0, src1, src2);
1108 src2->mod ^= NV50_MOD_NEG;
1109 }
1110
1111 #define NV50_FLOP_RCP 0
1112 #define NV50_FLOP_RSQ 2
1113 #define NV50_FLOP_LG2 3
1114 #define NV50_FLOP_SIN 4
1115 #define NV50_FLOP_COS 5
1116 #define NV50_FLOP_EX2 6
1117
1118 /* rcp, rsqrt, lg2 support neg and abs */
1119 static void
1120 emit_flop(struct nv50_pc *pc, unsigned sub,
1121 struct nv50_reg *dst, struct nv50_reg *src)
1122 {
1123 struct nv50_program_exec *e = exec(pc);
1124
1125 e->inst[0] |= 0x90000000;
1126 if (sub || src->mod) {
1127 set_long(pc, e);
1128 e->inst[1] |= (sub << 29);
1129 }
1130
1131 set_dst(pc, dst, e);
1132 set_src_0_restricted(pc, src, e);
1133
1134 assert(!src->mod || sub < 4);
1135
1136 if (src->mod & NV50_MOD_NEG)
1137 e->inst[1] |= 0x04000000;
1138 if (src->mod & NV50_MOD_ABS)
1139 e->inst[1] |= 0x00100000;
1140
1141 emit(pc, e);
1142 }
1143
1144 static void
1145 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1146 {
1147 struct nv50_program_exec *e = exec(pc);
1148
1149 e->inst[0] |= 0xb0000000;
1150
1151 set_dst(pc, dst, e);
1152 set_src_0(pc, src, e);
1153 set_long(pc, e);
1154 e->inst[1] |= (6 << 29) | 0x00004000;
1155
1156 if (src->mod & NV50_MOD_NEG)
1157 e->inst[1] |= 0x04000000;
1158 if (src->mod & NV50_MOD_ABS)
1159 e->inst[1] |= 0x00100000;
1160
1161 emit(pc, e);
1162 }
1163
1164 static void
1165 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1166 {
1167 struct nv50_program_exec *e = exec(pc);
1168
1169 e->inst[0] |= 0xb0000000;
1170
1171 set_dst(pc, dst, e);
1172 set_src_0(pc, src, e);
1173 set_long(pc, e);
1174 e->inst[1] |= (6 << 29);
1175
1176 if (src->mod & NV50_MOD_NEG)
1177 e->inst[1] |= 0x04000000;
1178 if (src->mod & NV50_MOD_ABS)
1179 e->inst[1] |= 0x00100000;
1180
1181 emit(pc, e);
1182 }
1183
1184 #define CVT_RN (0x00 << 16)
1185 #define CVT_FLOOR (0x02 << 16)
1186 #define CVT_CEIL (0x04 << 16)
1187 #define CVT_TRUNC (0x06 << 16)
1188 #define CVT_SAT (0x08 << 16)
1189 #define CVT_ABS (0x10 << 16)
1190
1191 #define CVT_X32_X32 0x04004000
1192 #define CVT_X32_S32 0x04014000
1193 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1194 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1195 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1196 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1197 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1198 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1199 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1200 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1201
1202 #define CVT_NEG 0x20000000
1203 #define CVT_RI 0x08000000
1204
1205 static void
1206 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1207 int wp, uint32_t cvn)
1208 {
1209 struct nv50_program_exec *e;
1210
1211 e = exec(pc);
1212
1213 if (src->mod & NV50_MOD_NEG) cvn |= CVT_NEG;
1214 if (src->mod & NV50_MOD_ABS) cvn |= CVT_ABS;
1215
1216 e->inst[0] = 0xa0000000;
1217 e->inst[1] = cvn;
1218 set_long(pc, e);
1219 set_src_0(pc, src, e);
1220
1221 if (wp >= 0)
1222 set_pred_wr(pc, 1, wp, e);
1223
1224 if (dst)
1225 set_dst(pc, dst, e);
1226 else {
1227 e->inst[0] |= 0x000001fc;
1228 e->inst[1] |= 0x00000008;
1229 }
1230
1231 emit(pc, e);
1232 }
1233
1234 /* nv50 Condition codes:
1235 * 0x1 = LT
1236 * 0x2 = EQ
1237 * 0x3 = LE
1238 * 0x4 = GT
1239 * 0x5 = NE
1240 * 0x6 = GE
1241 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1242 * 0x8 = unordered bit (allows NaN)
1243 *
1244 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1245 */
1246 static void
1247 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1248 struct nv50_reg *src0, struct nv50_reg *src1, uint8_t mode)
1249 {
1250 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1251
1252 struct nv50_program_exec *e = exec(pc);
1253 struct nv50_reg *rdst;
1254
1255 assert(ccode < 16);
1256 if (check_swap_src_0_1(pc, &src0, &src1))
1257 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1258
1259 rdst = dst;
1260 if (dst && dst->type != P_TEMP)
1261 dst = alloc_temp(pc, NULL);
1262
1263 set_long(pc, e);
1264 e->inst[0] |= 0x30000000 | (mode << 24);
1265 e->inst[1] |= 0x60000000 | (ccode << 14);
1266
1267 if (wp >= 0)
1268 set_pred_wr(pc, 1, wp, e);
1269 if (dst)
1270 set_dst(pc, dst, e);
1271 else {
1272 e->inst[0] |= 0x000001fc;
1273 e->inst[1] |= 0x00000008;
1274 }
1275
1276 set_src_0(pc, src0, e);
1277 set_src_1(pc, src1, e);
1278
1279 emit(pc, e);
1280
1281 if (rdst && mode == 0x80) /* convert to float ? */
1282 emit_cvt(pc, rdst, dst, -1, CVT_ABS | CVT_F32_S32);
1283 if (rdst && rdst != dst)
1284 free_temp(pc, dst);
1285 }
1286
1287 static INLINE void
1288 map_tgsi_setop_hw(unsigned op, uint8_t *cc, uint8_t *ty)
1289 {
1290 switch (op) {
1291 case TGSI_OPCODE_SLT: *cc = 0x1; *ty = 0x80; break;
1292 case TGSI_OPCODE_SGE: *cc = 0x6; *ty = 0x80; break;
1293 case TGSI_OPCODE_SEQ: *cc = 0x2; *ty = 0x80; break;
1294 case TGSI_OPCODE_SGT: *cc = 0x4; *ty = 0x80; break;
1295 case TGSI_OPCODE_SLE: *cc = 0x3; *ty = 0x80; break;
1296 case TGSI_OPCODE_SNE: *cc = 0xd; *ty = 0x80; break;
1297
1298 case TGSI_OPCODE_ISLT: *cc = 0x1; *ty = 0x0c; break;
1299 case TGSI_OPCODE_ISGE: *cc = 0x6; *ty = 0x0c; break;
1300 case TGSI_OPCODE_USEQ: *cc = 0x2; *ty = 0x04; break;
1301 case TGSI_OPCODE_USGE: *cc = 0x6; *ty = 0x04; break;
1302 case TGSI_OPCODE_USLT: *cc = 0x1; *ty = 0x04; break;
1303 case TGSI_OPCODE_USNE: *cc = 0x5; *ty = 0x04; break;
1304 default:
1305 assert(0);
1306 return;
1307 }
1308 }
1309
1310 static INLINE void
1311 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1312 {
1313 emit_cvt(pc, dst, src, -1, CVT_FLOOR | CVT_F32_F32 | CVT_RI);
1314 }
1315
1316 static void
1317 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1318 struct nv50_reg *v, struct nv50_reg *e)
1319 {
1320 struct nv50_reg *temp = alloc_temp(pc, NULL);
1321
1322 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1323 emit_mul(pc, temp, temp, e);
1324 emit_preex2(pc, temp, temp);
1325 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1326
1327 free_temp(pc, temp);
1328 }
1329
1330 static INLINE void
1331 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1332 {
1333 emit_cvt(pc, dst, src, -1, CVT_SAT | CVT_F32_F32);
1334 }
1335
1336 static void
1337 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1338 struct nv50_reg **src)
1339 {
1340 struct nv50_reg *one = alloc_immd(pc, 1.0);
1341 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1342 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1343 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1344 struct nv50_reg *tmp[4];
1345 boolean allow32 = pc->allow32;
1346
1347 pc->allow32 = FALSE;
1348
1349 if (mask & (3 << 1)) {
1350 tmp[0] = alloc_temp(pc, NULL);
1351 emit_minmax(pc, NV50_MAX_F32, tmp[0], src[0], zero);
1352 }
1353
1354 if (mask & (1 << 2)) {
1355 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1356
1357 tmp[1] = temp_temp(pc);
1358 emit_minmax(pc, NV50_MAX_F32, tmp[1], src[1], zero);
1359
1360 tmp[3] = temp_temp(pc);
1361 emit_minmax(pc, NV50_MAX_F32, tmp[3], src[3], neg128);
1362 emit_minmax(pc, NV50_MIN_F32, tmp[3], tmp[3], pos128);
1363
1364 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1365 emit_mov(pc, dst[2], zero);
1366 set_pred(pc, 3, 0, pc->p->exec_tail);
1367 }
1368
1369 if (mask & (1 << 1))
1370 assimilate_temp(pc, dst[1], tmp[0]);
1371 else
1372 if (mask & (1 << 2))
1373 free_temp(pc, tmp[0]);
1374
1375 pc->allow32 = allow32;
1376
1377 /* do this last, in case src[i,j] == dst[0,3] */
1378 if (mask & (1 << 0))
1379 emit_mov(pc, dst[0], one);
1380
1381 if (mask & (1 << 3))
1382 emit_mov(pc, dst[3], one);
1383
1384 FREE(pos128);
1385 FREE(neg128);
1386 FREE(zero);
1387 FREE(one);
1388 }
1389
1390 static void
1391 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1392 {
1393 struct nv50_program_exec *e;
1394 const int r_pred = 1;
1395
1396 e = exec(pc);
1397 e->inst[0] = 0x00000002; /* discard */
1398 set_long(pc, e); /* sets cond code to ALWAYS */
1399
1400 if (src) {
1401 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1402 /* write to predicate reg */
1403 emit_cvt(pc, NULL, src, r_pred, CVT_F32_F32);
1404 }
1405
1406 emit(pc, e);
1407 }
1408
1409 static struct nv50_program_exec *
1410 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1411 {
1412 struct nv50_program_exec *e = exec(pc);
1413
1414 e->inst[0] = (op << 28) | 2;
1415 set_long(pc, e);
1416 if (pred >= 0)
1417 set_pred(pc, cc, pred, e);
1418
1419 emit(pc, e);
1420 return e;
1421 }
1422
1423 static INLINE struct nv50_program_exec *
1424 emit_breakaddr(struct nv50_pc *pc)
1425 {
1426 return emit_control_flow(pc, 0x4, -1, 0);
1427 }
1428
1429 static INLINE void
1430 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1431 {
1432 emit_control_flow(pc, 0x5, pred, cc);
1433 }
1434
1435 static INLINE struct nv50_program_exec *
1436 emit_joinat(struct nv50_pc *pc)
1437 {
1438 return emit_control_flow(pc, 0xa, -1, 0);
1439 }
1440
1441 static INLINE struct nv50_program_exec *
1442 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1443 {
1444 return emit_control_flow(pc, 0x1, pred, cc);
1445 }
1446
1447 static INLINE struct nv50_program_exec *
1448 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1449 {
1450 return emit_control_flow(pc, 0x2, pred, cc);
1451 }
1452
1453 static INLINE void
1454 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1455 {
1456 emit_control_flow(pc, 0x3, pred, cc);
1457 }
1458
1459 #define QOP_ADD 0
1460 #define QOP_SUBR 1
1461 #define QOP_SUB 2
1462 #define QOP_MOV_SRC1 3
1463
1464 /* For a quad of threads / top left, top right, bottom left, bottom right
1465 * pixels, do a different operation, and take src0 from a specific thread.
1466 */
1467 static void
1468 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1469 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1470 {
1471 struct nv50_program_exec *e = exec(pc);
1472
1473 e->inst[0] = 0xc0000000;
1474 e->inst[1] = 0x80000000;
1475 set_long(pc, e);
1476 e->inst[0] |= lane_src0 << 16;
1477 set_src_0(pc, src0, e);
1478 set_src_2(pc, src1, e);
1479
1480 if (wp >= 0)
1481 set_pred_wr(pc, 1, wp, e);
1482
1483 if (dst)
1484 set_dst(pc, dst, e);
1485 else {
1486 e->inst[0] |= 0x000001fc;
1487 e->inst[1] |= 0x00000008;
1488 }
1489
1490 e->inst[0] |= (qop & 3) << 20;
1491 e->inst[1] |= (qop >> 2) << 22;
1492
1493 emit(pc, e);
1494 }
1495
1496 static void
1497 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1498 struct nv50_reg **src, unsigned arg, boolean proj)
1499 {
1500 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1501
1502 src[0]->mod |= NV50_MOD_ABS;
1503 src[1]->mod |= NV50_MOD_ABS;
1504 src[2]->mod |= NV50_MOD_ABS;
1505
1506 emit_minmax(pc, NV50_MAX_F32, t[2], src[0], src[1]);
1507 emit_minmax(pc, NV50_MAX_F32, t[2], src[2], t[2]);
1508
1509 src[0]->mod = mod[0];
1510 src[1]->mod = mod[1];
1511 src[2]->mod = mod[2];
1512
1513 if (proj && 0 /* looks more correct without this */)
1514 emit_mul(pc, t[2], t[2], src[3]);
1515 else
1516 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1517 emit_mov(pc, t[3], src[3]);
1518
1519 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1520
1521 emit_mul(pc, t[0], src[0], t[2]);
1522 emit_mul(pc, t[1], src[1], t[2]);
1523 emit_mul(pc, t[2], src[2], t[2]);
1524 }
1525
1526 static void
1527 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1528 struct nv50_reg **src, unsigned dim, unsigned arg)
1529 {
1530 unsigned c, mode;
1531
1532 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1533 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1534
1535 t[3]->rhw = src[3]->rhw;
1536 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1537 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1538
1539 for (c = 0; c < dim; ++c) {
1540 t[c]->rhw = src[c]->rhw;
1541 emit_interp(pc, t[c], t[3], mode);
1542 }
1543 if (arg != dim) { /* depth reference value */
1544 t[dim]->rhw = src[2]->rhw;
1545 emit_interp(pc, t[dim], t[3], mode);
1546 }
1547 } else {
1548 /* XXX: for some reason the blob sometimes uses MAD
1549 * (mad f32 $rX $rY $rZ neg $r63)
1550 */
1551 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1552 for (c = 0; c < dim; ++c)
1553 emit_mul(pc, t[c], src[c], t[3]);
1554 if (arg != dim) /* depth reference value */
1555 emit_mul(pc, t[dim], src[2], t[3]);
1556 }
1557 }
1558
1559 static INLINE void
1560 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1561 {
1562 switch (type) {
1563 case TGSI_TEXTURE_1D:
1564 *arg = *dim = 1;
1565 break;
1566 case TGSI_TEXTURE_SHADOW1D:
1567 *dim = 1;
1568 *arg = 2;
1569 break;
1570 case TGSI_TEXTURE_UNKNOWN:
1571 case TGSI_TEXTURE_2D:
1572 case TGSI_TEXTURE_RECT:
1573 *arg = *dim = 2;
1574 break;
1575 case TGSI_TEXTURE_SHADOW2D:
1576 case TGSI_TEXTURE_SHADOWRECT:
1577 *dim = 2;
1578 *arg = 3;
1579 break;
1580 case TGSI_TEXTURE_3D:
1581 case TGSI_TEXTURE_CUBE:
1582 *dim = *arg = 3;
1583 break;
1584 default:
1585 assert(0);
1586 break;
1587 }
1588 }
1589
1590 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1591 * different LOD values, so branch off groups of equal LOD.
1592 */
1593 static void
1594 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1595 struct nv50_reg *src, struct nv50_program_exec *tex)
1596 {
1597 struct nv50_program_exec *join_at;
1598 unsigned i, target = pc->p->exec_size + 9 * 2;
1599
1600 if (pc->p->type != PIPE_SHADER_FRAGMENT) {
1601 emit(pc, tex);
1602 return;
1603 }
1604 pc->allow32 = FALSE;
1605
1606 /* Subtract lod of each pixel from lod of top left pixel, jump
1607 * texlod insn if result is 0, then repeat for 2 other pixels.
1608 */
1609 join_at = emit_joinat(pc);
1610 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1611 emit_branch(pc, 0, 2)->param.index = target;
1612
1613 for (i = 1; i < 4; ++i) {
1614 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1615 emit_branch(pc, 0, 2)->param.index = target;
1616 }
1617
1618 emit_mov(pc, tlod, src); /* target */
1619 emit(pc, tex); /* texlod */
1620
1621 join_at->param.index = target + 2 * 2;
1622 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1623 }
1624
1625 static void
1626 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1627 struct nv50_program_exec *tex)
1628 {
1629 struct nv50_program_exec *e;
1630 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1631 int r_pred = 0;
1632 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1633
1634 pc->allow32 = FALSE;
1635 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1636
1637 /* Subtract bias value of thread i from bias values of each thread,
1638 * store result in r_pred, and set bit i in r_bits if result was 0.
1639 */
1640 assert(arg < 4);
1641 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1642 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1643 emit_mov(pc, r_bits, &imm_1248);
1644 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1645 }
1646 emit_mov_to_pred(pc, r_pred, r_bits);
1647
1648 /* The lanes of a quad are now grouped by the bit in r_pred they have
1649 * set. Put the input values for TEX into a new register set for each
1650 * group and execute TEX only for a specific group.
1651 * We cannot use the same register set for each group because we need
1652 * the derivatives, which are implicitly calculated, to be correct.
1653 */
1654 for (i = 1; i < 4; ++i) {
1655 alloc_temp4(pc, t123[i], 0);
1656
1657 for (c = 0; c <= arg; ++c)
1658 emit_mov(pc, t123[i][c], t[c]);
1659
1660 *(e = exec(pc)) = *(tex);
1661 e->inst[0] &= ~0x01fc;
1662 set_dst(pc, t123[i][0], e);
1663 set_pred(pc, cc[i], r_pred, e);
1664 emit(pc, e);
1665 }
1666 /* finally TEX on the original regs (where we kept the input) */
1667 set_pred(pc, cc[0], r_pred, tex);
1668 emit(pc, tex);
1669
1670 /* put the 3 * n other results into regs for lane 0 */
1671 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1672 for (i = 1; i < 4; ++i) {
1673 for (c = 0; c < n; ++c) {
1674 emit_mov(pc, t[c], t123[i][c]);
1675 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1676 }
1677 free_temp4(pc, t123[i]);
1678 }
1679
1680 emit_nop(pc);
1681 free_temp(pc, r_bits);
1682 }
1683
1684 static void
1685 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1686 struct nv50_reg **src, unsigned unit, unsigned type,
1687 boolean proj, int bias_lod)
1688 {
1689 struct nv50_reg *t[4];
1690 struct nv50_program_exec *e;
1691 unsigned c, dim, arg;
1692
1693 /* t[i] must be within a single 128 bit super-reg */
1694 alloc_temp4(pc, t, 0);
1695
1696 e = exec(pc);
1697 e->inst[0] = 0xf0000000;
1698 set_long(pc, e);
1699 set_dst(pc, t[0], e);
1700
1701 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1702 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1703
1704 /* live flag (don't set if TEX results affect input to another TEX): */
1705 /* e->inst[0] |= 0x00000004; */
1706
1707 get_tex_dim(type, &dim, &arg);
1708
1709 if (type == TGSI_TEXTURE_CUBE) {
1710 e->inst[0] |= 0x08000000;
1711 load_cube_tex_coords(pc, t, src, arg, proj);
1712 } else
1713 if (proj)
1714 load_proj_tex_coords(pc, t, src, dim, arg);
1715 else {
1716 for (c = 0; c < dim; c++)
1717 emit_mov(pc, t[c], src[c]);
1718 if (arg != dim) /* depth reference value (always src.z here) */
1719 emit_mov(pc, t[dim], src[2]);
1720 }
1721
1722 e->inst[0] |= (mask & 0x3) << 25;
1723 e->inst[1] |= (mask & 0xc) << 12;
1724
1725 if (!bias_lod) {
1726 e->inst[0] |= (arg - 1) << 22;
1727 emit(pc, e);
1728 } else
1729 if (bias_lod < 0) {
1730 assert(pc->p->type == PIPE_SHADER_FRAGMENT);
1731 e->inst[0] |= arg << 22;
1732 e->inst[1] |= 0x20000000; /* texbias */
1733 emit_mov(pc, t[arg], src[3]);
1734 emit_texbias_sequence(pc, t, arg, e);
1735 } else {
1736 e->inst[0] |= arg << 22;
1737 e->inst[1] |= 0x40000000; /* texlod */
1738 emit_mov(pc, t[arg], src[3]);
1739 emit_texlod_sequence(pc, t[arg], src[3], e);
1740 }
1741
1742 #if 1
1743 c = 0;
1744 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1745 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1746 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1747 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1748
1749 free_temp4(pc, t);
1750 #else
1751 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1752 * the texture coordinates, not the fetched values: latency ? */
1753
1754 for (c = 0; c < 4; c++) {
1755 if (mask & (1 << c))
1756 assimilate_temp(pc, dst[c], t[c]);
1757 else
1758 free_temp(pc, t[c]);
1759 }
1760 #endif
1761 }
1762
1763 static void
1764 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1765 {
1766 struct nv50_program_exec *e = exec(pc);
1767
1768 assert(src->type == P_TEMP);
1769
1770 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
1771 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
1772 set_long(pc, e);
1773 set_dst(pc, dst, e);
1774 set_src_0(pc, src, e);
1775 set_src_2(pc, src, e);
1776
1777 emit(pc, e);
1778 }
1779
1780 static void
1781 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1782 {
1783 struct nv50_program_exec *e = exec(pc);
1784
1785 assert(src->type == P_TEMP);
1786
1787 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
1788 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
1789 set_long(pc, e);
1790 set_dst(pc, dst, e);
1791 set_src_0(pc, src, e);
1792 set_src_2(pc, src, e);
1793
1794 emit(pc, e);
1795 }
1796
1797 static void
1798 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1799 {
1800 unsigned q = 0, m = ~0;
1801
1802 assert(!is_long(e));
1803
1804 switch (e->inst[0] >> 28) {
1805 case 0x1:
1806 /* MOV */
1807 q = 0x0403c000;
1808 m = 0xffff7fff;
1809 break;
1810 case 0x8:
1811 /* INTERP (move centroid, perspective and flat bits) */
1812 m = ~0x03000100;
1813 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1814 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1815 break;
1816 case 0x9:
1817 /* RCP */
1818 break;
1819 case 0xB:
1820 /* ADD */
1821 m = ~(127 << 16);
1822 q = ((e->inst[0] & (~m)) >> 2);
1823 break;
1824 case 0xC:
1825 /* MUL */
1826 m = ~0x00008000;
1827 q = ((e->inst[0] & (~m)) << 12);
1828 break;
1829 case 0xE:
1830 /* MAD (if src2 == dst) */
1831 q = ((e->inst[0] & 0x1fc) << 12);
1832 break;
1833 default:
1834 assert(0);
1835 break;
1836 }
1837
1838 set_long(pc, e);
1839 pc->p->exec_size++;
1840
1841 e->inst[0] &= m;
1842 e->inst[1] |= q;
1843 }
1844
1845 /* Some operations support an optional negation flag. */
1846 static int
1847 get_supported_mods(const struct tgsi_full_instruction *insn, int i)
1848 {
1849 switch (insn->Instruction.Opcode) {
1850 case TGSI_OPCODE_ADD:
1851 case TGSI_OPCODE_COS:
1852 case TGSI_OPCODE_DDX:
1853 case TGSI_OPCODE_DDY:
1854 case TGSI_OPCODE_DP3:
1855 case TGSI_OPCODE_DP4:
1856 case TGSI_OPCODE_EX2:
1857 case TGSI_OPCODE_KIL:
1858 case TGSI_OPCODE_LG2:
1859 case TGSI_OPCODE_MAD:
1860 case TGSI_OPCODE_MUL:
1861 case TGSI_OPCODE_POW:
1862 case TGSI_OPCODE_RCP:
1863 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
1864 case TGSI_OPCODE_SCS:
1865 case TGSI_OPCODE_SIN:
1866 case TGSI_OPCODE_SUB:
1867 return NV50_MOD_NEG;
1868 case TGSI_OPCODE_MAX:
1869 case TGSI_OPCODE_MIN:
1870 case TGSI_OPCODE_INEG: /* tgsi src sign toggle/set would be stupid */
1871 return NV50_MOD_ABS;
1872 case TGSI_OPCODE_CEIL:
1873 case TGSI_OPCODE_FLR:
1874 case TGSI_OPCODE_TRUNC:
1875 return NV50_MOD_NEG | NV50_MOD_ABS;
1876 case TGSI_OPCODE_F2I:
1877 case TGSI_OPCODE_F2U:
1878 case TGSI_OPCODE_I2F:
1879 case TGSI_OPCODE_U2F:
1880 return NV50_MOD_NEG | NV50_MOD_ABS | NV50_MOD_I32;
1881 case TGSI_OPCODE_SHL:
1882 case TGSI_OPCODE_IMAX:
1883 case TGSI_OPCODE_IMIN:
1884 case TGSI_OPCODE_ISHR:
1885 case TGSI_OPCODE_UMAX:
1886 case TGSI_OPCODE_UMIN:
1887 case TGSI_OPCODE_USHR:
1888 return NV50_MOD_I32;
1889 default:
1890 return 0;
1891 }
1892 }
1893
1894 /* Return a read mask for source registers deduced from opcode & write mask. */
1895 static unsigned
1896 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1897 {
1898 unsigned x, mask = insn->Dst[0].Register.WriteMask;
1899
1900 switch (insn->Instruction.Opcode) {
1901 case TGSI_OPCODE_COS:
1902 case TGSI_OPCODE_SIN:
1903 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1904 case TGSI_OPCODE_DP3:
1905 return 0x7;
1906 case TGSI_OPCODE_DP4:
1907 case TGSI_OPCODE_DPH:
1908 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1909 return 0xf;
1910 case TGSI_OPCODE_DST:
1911 return mask & (c ? 0xa : 0x6);
1912 case TGSI_OPCODE_EX2:
1913 case TGSI_OPCODE_EXP:
1914 case TGSI_OPCODE_LG2:
1915 case TGSI_OPCODE_LOG:
1916 case TGSI_OPCODE_POW:
1917 case TGSI_OPCODE_RCP:
1918 case TGSI_OPCODE_RSQ:
1919 case TGSI_OPCODE_SCS:
1920 return 0x1;
1921 case TGSI_OPCODE_IF:
1922 return 0x1;
1923 case TGSI_OPCODE_LIT:
1924 return 0xb;
1925 case TGSI_OPCODE_TEX:
1926 case TGSI_OPCODE_TXB:
1927 case TGSI_OPCODE_TXL:
1928 case TGSI_OPCODE_TXP:
1929 {
1930 const struct tgsi_instruction_texture *tex;
1931
1932 assert(insn->Instruction.Texture);
1933 tex = &insn->Texture;
1934
1935 mask = 0x7;
1936 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
1937 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
1938 mask |= 0x8; /* bias, lod or proj */
1939
1940 switch (tex->Texture) {
1941 case TGSI_TEXTURE_1D:
1942 mask &= 0x9;
1943 break;
1944 case TGSI_TEXTURE_SHADOW1D:
1945 mask &= 0x5;
1946 break;
1947 case TGSI_TEXTURE_2D:
1948 mask &= 0xb;
1949 break;
1950 default:
1951 break;
1952 }
1953 }
1954 return mask;
1955 case TGSI_OPCODE_XPD:
1956 x = 0;
1957 if (mask & 1) x |= 0x6;
1958 if (mask & 2) x |= 0x5;
1959 if (mask & 4) x |= 0x3;
1960 return x;
1961 default:
1962 break;
1963 }
1964
1965 return mask;
1966 }
1967
1968 static struct nv50_reg *
1969 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1970 {
1971 switch (dst->Register.File) {
1972 case TGSI_FILE_TEMPORARY:
1973 return &pc->temp[dst->Register.Index * 4 + c];
1974 case TGSI_FILE_OUTPUT:
1975 return &pc->result[dst->Register.Index * 4 + c];
1976 case TGSI_FILE_ADDRESS:
1977 {
1978 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
1979 if (!r) {
1980 r = alloc_addr(pc, NULL);
1981 pc->addr[dst->Register.Index * 4 + c] = r;
1982 }
1983 assert(r);
1984 return r;
1985 }
1986 case TGSI_FILE_NULL:
1987 return NULL;
1988 default:
1989 break;
1990 }
1991
1992 return NULL;
1993 }
1994
1995 static struct nv50_reg *
1996 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1997 int mod)
1998 {
1999 struct nv50_reg *r = NULL;
2000 struct nv50_reg *temp = NULL;
2001 unsigned sgn, c, swz, cvn;
2002
2003 if (src->Register.File != TGSI_FILE_CONSTANT)
2004 assert(!src->Register.Indirect);
2005
2006 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
2007
2008 c = tgsi_util_get_full_src_register_swizzle(src, chan);
2009 switch (c) {
2010 case TGSI_SWIZZLE_X:
2011 case TGSI_SWIZZLE_Y:
2012 case TGSI_SWIZZLE_Z:
2013 case TGSI_SWIZZLE_W:
2014 switch (src->Register.File) {
2015 case TGSI_FILE_INPUT:
2016 r = &pc->attr[src->Register.Index * 4 + c];
2017 break;
2018 case TGSI_FILE_TEMPORARY:
2019 r = &pc->temp[src->Register.Index * 4 + c];
2020 break;
2021 case TGSI_FILE_CONSTANT:
2022 if (!src->Register.Indirect) {
2023 r = &pc->param[src->Register.Index * 4 + c];
2024 break;
2025 }
2026 /* Indicate indirection by setting r->acc < 0 and
2027 * use the index field to select the address reg.
2028 */
2029 r = reg_instance(pc, NULL);
2030 swz = tgsi_util_get_src_register_swizzle(
2031 &src->Indirect, 0);
2032 ctor_reg(r, P_CONST,
2033 src->Indirect.Index * 4 + swz,
2034 src->Register.Index * 4 + c);
2035 r->acc = -1;
2036 break;
2037 case TGSI_FILE_IMMEDIATE:
2038 r = &pc->immd[src->Register.Index * 4 + c];
2039 break;
2040 case TGSI_FILE_SAMPLER:
2041 return NULL;
2042 case TGSI_FILE_ADDRESS:
2043 r = pc->addr[src->Register.Index * 4 + c];
2044 assert(r);
2045 break;
2046 default:
2047 assert(0);
2048 break;
2049 }
2050 break;
2051 default:
2052 assert(0);
2053 break;
2054 }
2055
2056 cvn = (mod & NV50_MOD_I32) ? CVT_S32_S32 : CVT_F32_F32;
2057
2058 switch (sgn) {
2059 case TGSI_UTIL_SIGN_CLEAR:
2060 r->mod = NV50_MOD_ABS;
2061 break;
2062 case TGSI_UTIL_SIGN_SET:
2063 r->mod = NV50_MOD_NEG_ABS;
2064 break;
2065 case TGSI_UTIL_SIGN_TOGGLE:
2066 r->mod = NV50_MOD_NEG;
2067 break;
2068 default:
2069 assert(!r->mod && sgn == TGSI_UTIL_SIGN_KEEP);
2070 break;
2071 }
2072
2073 if ((r->mod & mod) != r->mod) {
2074 temp = temp_temp(pc);
2075 emit_cvt(pc, temp, r, -1, cvn);
2076 r->mod = 0;
2077 r = temp;
2078 } else
2079 r->mod |= mod & NV50_MOD_I32;
2080
2081 assert(r);
2082 if (r->acc >= 0 && r != temp)
2083 return reg_instance(pc, r); /* will clear r->mod */
2084 return r;
2085 }
2086
2087 /* return TRUE for ops that produce only a single result */
2088 static boolean
2089 is_scalar_op(unsigned op)
2090 {
2091 switch (op) {
2092 case TGSI_OPCODE_COS:
2093 case TGSI_OPCODE_DP2:
2094 case TGSI_OPCODE_DP3:
2095 case TGSI_OPCODE_DP4:
2096 case TGSI_OPCODE_DPH:
2097 case TGSI_OPCODE_EX2:
2098 case TGSI_OPCODE_LG2:
2099 case TGSI_OPCODE_POW:
2100 case TGSI_OPCODE_RCP:
2101 case TGSI_OPCODE_RSQ:
2102 case TGSI_OPCODE_SIN:
2103 /*
2104 case TGSI_OPCODE_KIL:
2105 case TGSI_OPCODE_LIT:
2106 case TGSI_OPCODE_SCS:
2107 */
2108 return TRUE;
2109 default:
2110 return FALSE;
2111 }
2112 }
2113
2114 /* Returns a bitmask indicating which dst components depend
2115 * on source s, component c (reverse of nv50_tgsi_src_mask).
2116 */
2117 static unsigned
2118 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2119 {
2120 if (is_scalar_op(op))
2121 return 0x1;
2122
2123 switch (op) {
2124 case TGSI_OPCODE_DST:
2125 return (1 << c) & (s ? 0xa : 0x6);
2126 case TGSI_OPCODE_XPD:
2127 switch (c) {
2128 case 0: return 0x6;
2129 case 1: return 0x5;
2130 case 2: return 0x3;
2131 case 3: return 0x0;
2132 default:
2133 assert(0);
2134 return 0x0;
2135 }
2136 case TGSI_OPCODE_EXP:
2137 case TGSI_OPCODE_LOG:
2138 case TGSI_OPCODE_LIT:
2139 case TGSI_OPCODE_SCS:
2140 case TGSI_OPCODE_TEX:
2141 case TGSI_OPCODE_TXB:
2142 case TGSI_OPCODE_TXL:
2143 case TGSI_OPCODE_TXP:
2144 /* these take care of dangerous swizzles themselves */
2145 return 0x0;
2146 case TGSI_OPCODE_IF:
2147 case TGSI_OPCODE_KIL:
2148 /* don't call this function for these ops */
2149 assert(0);
2150 return 0;
2151 default:
2152 /* linear vector instruction */
2153 return (1 << c);
2154 }
2155 }
2156
2157 static INLINE boolean
2158 has_pred(struct nv50_program_exec *e, unsigned cc)
2159 {
2160 if (!is_long(e) || is_immd(e))
2161 return FALSE;
2162 return ((e->inst[1] & 0x780) == (cc << 7));
2163 }
2164
2165 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2166 * join_at ENDIF
2167 * @p0.eq bra ENDIF
2168 * single_op
2169 * ENDIF: nop.join
2170 */
2171 static boolean
2172 nv50_kill_branch(struct nv50_pc *pc)
2173 {
2174 int lvl = pc->if_lvl;
2175
2176 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2177 return FALSE;
2178 if (is_immd(pc->p->exec_tail))
2179 return FALSE;
2180
2181 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2182 * reg may no longer be valid, since we currently always use $p0
2183 */
2184 if (has_pred(pc->if_insn[lvl], 0xf))
2185 return FALSE;
2186 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2187
2188 /* We'll use the exec allocated for JOIN_AT (we can't easily
2189 * access nv50_program_exec's prev).
2190 */
2191 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2192
2193 *pc->if_join[lvl] = *pc->p->exec_tail;
2194
2195 FREE(pc->if_insn[lvl]);
2196 FREE(pc->p->exec_tail);
2197
2198 pc->p->exec_tail = pc->if_join[lvl];
2199 pc->p->exec_tail->next = NULL;
2200 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2201
2202 return TRUE;
2203 }
2204
2205 static void
2206 nv50_fp_move_results(struct nv50_pc *pc)
2207 {
2208 struct nv50_reg reg;
2209 unsigned i;
2210
2211 ctor_reg(&reg, P_TEMP, -1, -1);
2212
2213 for (i = 0; i < pc->result_nr * 4; ++i) {
2214 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2215 continue;
2216 if (pc->result[i].rhw != pc->result[i].hw) {
2217 reg.hw = pc->result[i].rhw;
2218 emit_mov(pc, &reg, &pc->result[i]);
2219 }
2220 }
2221 }
2222
2223 static boolean
2224 nv50_program_tx_insn(struct nv50_pc *pc,
2225 const struct tgsi_full_instruction *inst)
2226 {
2227 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2228 unsigned mask, sat, unit;
2229 int i, c;
2230
2231 mask = inst->Dst[0].Register.WriteMask;
2232 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2233
2234 memset(src, 0, sizeof(src));
2235
2236 for (c = 0; c < 4; c++) {
2237 if ((mask & (1 << c)) && !pc->r_dst[c])
2238 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2239 else
2240 dst[c] = pc->r_dst[c];
2241 rdst[c] = dst[c];
2242 }
2243
2244 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2245 const struct tgsi_full_src_register *fs = &inst->Src[i];
2246 unsigned src_mask;
2247 int mod_supp;
2248
2249 src_mask = nv50_tgsi_src_mask(inst, i);
2250 mod_supp = get_supported_mods(inst, i);
2251
2252 if (fs->Register.File == TGSI_FILE_SAMPLER)
2253 unit = fs->Register.Index;
2254
2255 for (c = 0; c < 4; c++)
2256 if (src_mask & (1 << c))
2257 src[i][c] = tgsi_src(pc, c, fs, mod_supp);
2258 }
2259
2260 brdc = temp = pc->r_brdc;
2261 if (brdc && brdc->type != P_TEMP) {
2262 temp = temp_temp(pc);
2263 if (sat)
2264 brdc = temp;
2265 } else
2266 if (sat) {
2267 for (c = 0; c < 4; c++) {
2268 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2269 continue;
2270 /* rdst[c] = dst[c]; */ /* done above */
2271 dst[c] = temp_temp(pc);
2272 }
2273 }
2274
2275 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2276
2277 switch (inst->Instruction.Opcode) {
2278 case TGSI_OPCODE_ABS:
2279 for (c = 0; c < 4; c++) {
2280 if (!(mask & (1 << c)))
2281 continue;
2282 emit_cvt(pc, dst[c], src[0][c], -1,
2283 CVT_ABS | CVT_F32_F32);
2284 }
2285 break;
2286 case TGSI_OPCODE_ADD:
2287 for (c = 0; c < 4; c++) {
2288 if (!(mask & (1 << c)))
2289 continue;
2290 emit_add(pc, dst[c], src[0][c], src[1][c]);
2291 }
2292 break;
2293 case TGSI_OPCODE_AND:
2294 case TGSI_OPCODE_XOR:
2295 case TGSI_OPCODE_OR:
2296 for (c = 0; c < 4; c++) {
2297 if (!(mask & (1 << c)))
2298 continue;
2299 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2300 inst->Instruction.Opcode);
2301 }
2302 break;
2303 case TGSI_OPCODE_ARL:
2304 assert(src[0][0]);
2305 temp = temp_temp(pc);
2306 emit_cvt(pc, temp, src[0][0], -1, CVT_FLOOR | CVT_S32_F32);
2307 emit_arl(pc, dst[0], temp, 4);
2308 break;
2309 case TGSI_OPCODE_BGNLOOP:
2310 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2311 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2312 terminate_mbb(pc);
2313 break;
2314 case TGSI_OPCODE_BGNSUB:
2315 assert(!pc->in_subroutine);
2316 pc->in_subroutine = TRUE;
2317 /* probably not necessary, but align to 8 byte boundary */
2318 if (!is_long(pc->p->exec_tail))
2319 convert_to_long(pc, pc->p->exec_tail);
2320 break;
2321 case TGSI_OPCODE_BRK:
2322 assert(pc->loop_lvl > 0);
2323 emit_break(pc, -1, 0);
2324 break;
2325 case TGSI_OPCODE_CAL:
2326 assert(inst->Label.Label < pc->insn_nr);
2327 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2328 /* replaced by actual offset in nv50_program_fixup_insns */
2329 break;
2330 case TGSI_OPCODE_CEIL:
2331 for (c = 0; c < 4; c++) {
2332 if (!(mask & (1 << c)))
2333 continue;
2334 emit_cvt(pc, dst[c], src[0][c], -1,
2335 CVT_CEIL | CVT_F32_F32 | CVT_RI);
2336 }
2337 break;
2338 case TGSI_OPCODE_CMP:
2339 pc->allow32 = FALSE;
2340 for (c = 0; c < 4; c++) {
2341 if (!(mask & (1 << c)))
2342 continue;
2343 emit_cvt(pc, NULL, src[0][c], 1, CVT_F32_F32);
2344 emit_mov(pc, dst[c], src[1][c]);
2345 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2346 emit_mov(pc, dst[c], src[2][c]);
2347 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2348 }
2349 break;
2350 case TGSI_OPCODE_CONT:
2351 assert(pc->loop_lvl > 0);
2352 emit_branch(pc, -1, 0)->param.index =
2353 pc->loop_pos[pc->loop_lvl - 1];
2354 break;
2355 case TGSI_OPCODE_COS:
2356 if (mask & 8) {
2357 emit_precossin(pc, temp, src[0][3]);
2358 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2359 if (!(mask &= 7))
2360 break;
2361 if (temp == dst[3])
2362 temp = brdc = temp_temp(pc);
2363 }
2364 emit_precossin(pc, temp, src[0][0]);
2365 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2366 break;
2367 case TGSI_OPCODE_DDX:
2368 for (c = 0; c < 4; c++) {
2369 if (!(mask & (1 << c)))
2370 continue;
2371 emit_ddx(pc, dst[c], src[0][c]);
2372 }
2373 break;
2374 case TGSI_OPCODE_DDY:
2375 for (c = 0; c < 4; c++) {
2376 if (!(mask & (1 << c)))
2377 continue;
2378 emit_ddy(pc, dst[c], src[0][c]);
2379 }
2380 break;
2381 case TGSI_OPCODE_DP3:
2382 emit_mul(pc, temp, src[0][0], src[1][0]);
2383 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2384 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2385 break;
2386 case TGSI_OPCODE_DP4:
2387 emit_mul(pc, temp, src[0][0], src[1][0]);
2388 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2389 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2390 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2391 break;
2392 case TGSI_OPCODE_DPH:
2393 emit_mul(pc, temp, src[0][0], src[1][0]);
2394 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2395 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2396 emit_add(pc, brdc, src[1][3], temp);
2397 break;
2398 case TGSI_OPCODE_DST:
2399 if (mask & (1 << 1))
2400 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2401 if (mask & (1 << 2))
2402 emit_mov(pc, dst[2], src[0][2]);
2403 if (mask & (1 << 3))
2404 emit_mov(pc, dst[3], src[1][3]);
2405 if (mask & (1 << 0))
2406 emit_mov_immdval(pc, dst[0], 1.0f);
2407 break;
2408 case TGSI_OPCODE_ELSE:
2409 emit_branch(pc, -1, 0);
2410 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2411 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2412 terminate_mbb(pc);
2413 break;
2414 case TGSI_OPCODE_ENDIF:
2415 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2416
2417 /* try to replace branch over 1 insn with a predicated insn */
2418 if (nv50_kill_branch(pc) == TRUE)
2419 break;
2420
2421 if (pc->if_join[pc->if_lvl]) {
2422 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2423 pc->if_join[pc->if_lvl] = NULL;
2424 }
2425 terminate_mbb(pc);
2426 /* emit a NOP as join point, we could set it on the next
2427 * one, but would have to make sure it is long and !immd
2428 */
2429 JOIN_ON(emit_nop(pc));
2430 break;
2431 case TGSI_OPCODE_ENDLOOP:
2432 emit_branch(pc, -1, 0)->param.index =
2433 pc->loop_pos[--pc->loop_lvl];
2434 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2435 terminate_mbb(pc);
2436 break;
2437 case TGSI_OPCODE_ENDSUB:
2438 assert(pc->in_subroutine);
2439 pc->in_subroutine = FALSE;
2440 break;
2441 case TGSI_OPCODE_EX2:
2442 emit_preex2(pc, temp, src[0][0]);
2443 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2444 break;
2445 case TGSI_OPCODE_EXP:
2446 {
2447 struct nv50_reg *t[2];
2448
2449 assert(!temp);
2450 t[0] = temp_temp(pc);
2451 t[1] = temp_temp(pc);
2452
2453 if (mask & 0x6)
2454 emit_mov(pc, t[0], src[0][0]);
2455 if (mask & 0x3)
2456 emit_flr(pc, t[1], src[0][0]);
2457
2458 if (mask & (1 << 1))
2459 emit_sub(pc, dst[1], t[0], t[1]);
2460 if (mask & (1 << 0)) {
2461 emit_preex2(pc, t[1], t[1]);
2462 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2463 }
2464 if (mask & (1 << 2)) {
2465 emit_preex2(pc, t[0], t[0]);
2466 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2467 }
2468 if (mask & (1 << 3))
2469 emit_mov_immdval(pc, dst[3], 1.0f);
2470 }
2471 break;
2472 case TGSI_OPCODE_F2I:
2473 for (c = 0; c < 4; c++) {
2474 if (!(mask & (1 << c)))
2475 continue;
2476 emit_cvt(pc, dst[c], src[0][c], -1,
2477 CVT_TRUNC | CVT_S32_F32);
2478 }
2479 break;
2480 case TGSI_OPCODE_F2U:
2481 for (c = 0; c < 4; c++) {
2482 if (!(mask & (1 << c)))
2483 continue;
2484 emit_cvt(pc, dst[c], src[0][c], -1,
2485 CVT_TRUNC | CVT_U32_F32);
2486 }
2487 break;
2488 case TGSI_OPCODE_FLR:
2489 for (c = 0; c < 4; c++) {
2490 if (!(mask & (1 << c)))
2491 continue;
2492 emit_flr(pc, dst[c], src[0][c]);
2493 }
2494 break;
2495 case TGSI_OPCODE_FRC:
2496 temp = temp_temp(pc);
2497 for (c = 0; c < 4; c++) {
2498 if (!(mask & (1 << c)))
2499 continue;
2500 emit_flr(pc, temp, src[0][c]);
2501 emit_sub(pc, dst[c], src[0][c], temp);
2502 }
2503 break;
2504 case TGSI_OPCODE_I2F:
2505 for (c = 0; c < 4; c++) {
2506 if (!(mask & (1 << c)))
2507 continue;
2508 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_S32);
2509 }
2510 break;
2511 case TGSI_OPCODE_IF:
2512 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2513 emit_cvt(pc, NULL, src[0][0], 0, CVT_ABS | CVT_F32_F32);
2514 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2515 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2516 terminate_mbb(pc);
2517 break;
2518 case TGSI_OPCODE_IMAX:
2519 for (c = 0; c < 4; c++) {
2520 if (!(mask & (1 << c)))
2521 continue;
2522 emit_minmax(pc, 0x08c, dst[c], src[0][c], src[1][c]);
2523 }
2524 break;
2525 case TGSI_OPCODE_IMIN:
2526 for (c = 0; c < 4; c++) {
2527 if (!(mask & (1 << c)))
2528 continue;
2529 emit_minmax(pc, 0x0ac, dst[c], src[0][c], src[1][c]);
2530 }
2531 break;
2532 case TGSI_OPCODE_INEG:
2533 for (c = 0; c < 4; c++) {
2534 if (!(mask & (1 << c)))
2535 continue;
2536 emit_cvt(pc, dst[c], src[0][c], -1,
2537 CVT_S32_S32 | CVT_NEG);
2538 }
2539 break;
2540 case TGSI_OPCODE_KIL:
2541 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2542 emit_kil(pc, src[0][0]);
2543 emit_kil(pc, src[0][1]);
2544 emit_kil(pc, src[0][2]);
2545 emit_kil(pc, src[0][3]);
2546 break;
2547 case TGSI_OPCODE_KILP:
2548 emit_kil(pc, NULL);
2549 break;
2550 case TGSI_OPCODE_LIT:
2551 emit_lit(pc, &dst[0], mask, &src[0][0]);
2552 break;
2553 case TGSI_OPCODE_LG2:
2554 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2555 break;
2556 case TGSI_OPCODE_LOG:
2557 {
2558 struct nv50_reg *t[2];
2559
2560 t[0] = temp_temp(pc);
2561 if (mask & (1 << 1))
2562 t[1] = temp_temp(pc);
2563 else
2564 t[1] = t[0];
2565
2566 emit_cvt(pc, t[0], src[0][0], -1, CVT_ABS | CVT_F32_F32);
2567 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2568 if (mask & (1 << 2))
2569 emit_mov(pc, dst[2], t[1]);
2570 emit_flr(pc, t[1], t[1]);
2571 if (mask & (1 << 0))
2572 emit_mov(pc, dst[0], t[1]);
2573 if (mask & (1 << 1)) {
2574 t[1]->mod = NV50_MOD_NEG;
2575 emit_preex2(pc, t[1], t[1]);
2576 t[1]->mod = 0;
2577 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2578 emit_mul(pc, dst[1], t[0], t[1]);
2579 }
2580 if (mask & (1 << 3))
2581 emit_mov_immdval(pc, dst[3], 1.0f);
2582 }
2583 break;
2584 case TGSI_OPCODE_LRP:
2585 temp = temp_temp(pc);
2586 for (c = 0; c < 4; c++) {
2587 if (!(mask & (1 << c)))
2588 continue;
2589 emit_sub(pc, temp, src[1][c], src[2][c]);
2590 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2591 }
2592 break;
2593 case TGSI_OPCODE_MAD:
2594 for (c = 0; c < 4; c++) {
2595 if (!(mask & (1 << c)))
2596 continue;
2597 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2598 }
2599 break;
2600 case TGSI_OPCODE_MAX:
2601 for (c = 0; c < 4; c++) {
2602 if (!(mask & (1 << c)))
2603 continue;
2604 emit_minmax(pc, 0x880, dst[c], src[0][c], src[1][c]);
2605 }
2606 break;
2607 case TGSI_OPCODE_MIN:
2608 for (c = 0; c < 4; c++) {
2609 if (!(mask & (1 << c)))
2610 continue;
2611 emit_minmax(pc, 0x8a0, dst[c], src[0][c], src[1][c]);
2612 }
2613 break;
2614 case TGSI_OPCODE_MOV:
2615 for (c = 0; c < 4; c++) {
2616 if (!(mask & (1 << c)))
2617 continue;
2618 emit_mov(pc, dst[c], src[0][c]);
2619 }
2620 break;
2621 case TGSI_OPCODE_MUL:
2622 for (c = 0; c < 4; c++) {
2623 if (!(mask & (1 << c)))
2624 continue;
2625 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2626 }
2627 break;
2628 case TGSI_OPCODE_POW:
2629 emit_pow(pc, brdc, src[0][0], src[1][0]);
2630 break;
2631 case TGSI_OPCODE_RCP:
2632 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2633 break;
2634 case TGSI_OPCODE_RET:
2635 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2636 nv50_fp_move_results(pc);
2637 emit_ret(pc, -1, 0);
2638 break;
2639 case TGSI_OPCODE_RSQ:
2640 src[0][0]->mod |= NV50_MOD_ABS;
2641 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2642 break;
2643 case TGSI_OPCODE_SCS:
2644 temp = temp_temp(pc);
2645 if (mask & 3)
2646 emit_precossin(pc, temp, src[0][0]);
2647 if (mask & (1 << 0))
2648 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
2649 if (mask & (1 << 1))
2650 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
2651 if (mask & (1 << 2))
2652 emit_mov_immdval(pc, dst[2], 0.0);
2653 if (mask & (1 << 3))
2654 emit_mov_immdval(pc, dst[3], 1.0);
2655 break;
2656 case TGSI_OPCODE_SHL:
2657 case TGSI_OPCODE_ISHR:
2658 case TGSI_OPCODE_USHR:
2659 for (c = 0; c < 4; c++) {
2660 if (!(mask & (1 << c)))
2661 continue;
2662 emit_shift(pc, dst[c], src[0][c], src[1][c],
2663 inst->Instruction.Opcode);
2664 }
2665 break;
2666 case TGSI_OPCODE_SIN:
2667 if (mask & 8) {
2668 emit_precossin(pc, temp, src[0][3]);
2669 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
2670 if (!(mask &= 7))
2671 break;
2672 if (temp == dst[3])
2673 temp = brdc = temp_temp(pc);
2674 }
2675 emit_precossin(pc, temp, src[0][0]);
2676 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
2677 break;
2678 case TGSI_OPCODE_SLT:
2679 case TGSI_OPCODE_SGE:
2680 case TGSI_OPCODE_SEQ:
2681 case TGSI_OPCODE_SGT:
2682 case TGSI_OPCODE_SLE:
2683 case TGSI_OPCODE_SNE:
2684 case TGSI_OPCODE_ISLT:
2685 case TGSI_OPCODE_ISGE:
2686 case TGSI_OPCODE_USEQ:
2687 case TGSI_OPCODE_USGE:
2688 case TGSI_OPCODE_USLT:
2689 case TGSI_OPCODE_USNE:
2690 {
2691 uint8_t cc, ty;
2692
2693 map_tgsi_setop_hw(inst->Instruction.Opcode, &cc, &ty);
2694
2695 for (c = 0; c < 4; c++) {
2696 if (!(mask & (1 << c)))
2697 continue;
2698 emit_set(pc, cc, dst[c], -1, src[0][c], src[1][c], ty);
2699 }
2700 }
2701 break;
2702 case TGSI_OPCODE_SUB:
2703 for (c = 0; c < 4; c++) {
2704 if (!(mask & (1 << c)))
2705 continue;
2706 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2707 }
2708 break;
2709 case TGSI_OPCODE_TEX:
2710 emit_tex(pc, dst, mask, src[0], unit,
2711 inst->Texture.Texture, FALSE, 0);
2712 break;
2713 case TGSI_OPCODE_TXB:
2714 emit_tex(pc, dst, mask, src[0], unit,
2715 inst->Texture.Texture, FALSE, -1);
2716 break;
2717 case TGSI_OPCODE_TXL:
2718 emit_tex(pc, dst, mask, src[0], unit,
2719 inst->Texture.Texture, FALSE, 1);
2720 break;
2721 case TGSI_OPCODE_TXP:
2722 emit_tex(pc, dst, mask, src[0], unit,
2723 inst->Texture.Texture, TRUE, 0);
2724 break;
2725 case TGSI_OPCODE_TRUNC:
2726 for (c = 0; c < 4; c++) {
2727 if (!(mask & (1 << c)))
2728 continue;
2729 emit_cvt(pc, dst[c], src[0][c], -1,
2730 CVT_TRUNC | CVT_F32_F32 | CVT_RI);
2731 }
2732 break;
2733 case TGSI_OPCODE_U2F:
2734 for (c = 0; c < 4; c++) {
2735 if (!(mask & (1 << c)))
2736 continue;
2737 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_U32);
2738 }
2739 break;
2740 case TGSI_OPCODE_UMAX:
2741 for (c = 0; c < 4; c++) {
2742 if (!(mask & (1 << c)))
2743 continue;
2744 emit_minmax(pc, 0x084, dst[c], src[0][c], src[1][c]);
2745 }
2746 break;
2747 case TGSI_OPCODE_UMIN:
2748 for (c = 0; c < 4; c++) {
2749 if (!(mask & (1 << c)))
2750 continue;
2751 emit_minmax(pc, 0x0a4, dst[c], src[0][c], src[1][c]);
2752 }
2753 break;
2754 case TGSI_OPCODE_XPD:
2755 temp = temp_temp(pc);
2756 if (mask & (1 << 0)) {
2757 emit_mul(pc, temp, src[0][2], src[1][1]);
2758 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2759 }
2760 if (mask & (1 << 1)) {
2761 emit_mul(pc, temp, src[0][0], src[1][2]);
2762 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2763 }
2764 if (mask & (1 << 2)) {
2765 emit_mul(pc, temp, src[0][1], src[1][0]);
2766 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2767 }
2768 if (mask & (1 << 3))
2769 emit_mov_immdval(pc, dst[3], 1.0);
2770 break;
2771 case TGSI_OPCODE_END:
2772 if (pc->p->type == PIPE_SHADER_FRAGMENT)
2773 nv50_fp_move_results(pc);
2774
2775 /* last insn must be long so it can have the exit bit set */
2776 if (!is_long(pc->p->exec_tail))
2777 convert_to_long(pc, pc->p->exec_tail);
2778 else
2779 if (is_immd(pc->p->exec_tail) || is_join(pc->p->exec_tail))
2780 emit_nop(pc);
2781
2782 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
2783 break;
2784 default:
2785 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2786 return FALSE;
2787 }
2788
2789 if (brdc) {
2790 if (sat)
2791 emit_sat(pc, brdc, brdc);
2792 for (c = 0; c < 4; c++)
2793 if ((mask & (1 << c)) && dst[c] != brdc)
2794 emit_mov(pc, dst[c], brdc);
2795 } else
2796 if (sat) {
2797 for (c = 0; c < 4; c++) {
2798 if (!(mask & (1 << c)))
2799 continue;
2800 /* In this case we saturate later, and dst[c] won't
2801 * be another temp_temp (and thus lost), since rdst
2802 * already is TEMP (see above). */
2803 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2804 continue;
2805 emit_sat(pc, rdst[c], dst[c]);
2806 }
2807 }
2808
2809 kill_temp_temp(pc);
2810 pc->reg_instance_nr = 0;
2811
2812 return TRUE;
2813 }
2814
2815 static void
2816 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2817 {
2818 struct nv50_reg *reg = NULL;
2819 const struct tgsi_full_src_register *src;
2820 const struct tgsi_dst_register *dst;
2821 unsigned i, c, k, mask;
2822
2823 dst = &insn->Dst[0].Register;
2824 mask = dst->WriteMask;
2825
2826 if (dst->File == TGSI_FILE_TEMPORARY)
2827 reg = pc->temp;
2828 else
2829 if (dst->File == TGSI_FILE_OUTPUT) {
2830 reg = pc->result;
2831
2832 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
2833 dst->Index == pc->edgeflag_out &&
2834 insn->Src[0].Register.File == TGSI_FILE_INPUT)
2835 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
2836 }
2837
2838 if (reg) {
2839 for (c = 0; c < 4; c++) {
2840 if (!(mask & (1 << c)))
2841 continue;
2842 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2843 }
2844 }
2845
2846 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2847 src = &insn->Src[i];
2848
2849 if (src->Register.File == TGSI_FILE_TEMPORARY)
2850 reg = pc->temp;
2851 else
2852 if (src->Register.File == TGSI_FILE_INPUT)
2853 reg = pc->attr;
2854 else
2855 continue;
2856
2857 mask = nv50_tgsi_src_mask(insn, i);
2858
2859 for (c = 0; c < 4; c++) {
2860 if (!(mask & (1 << c)))
2861 continue;
2862 k = tgsi_util_get_full_src_register_swizzle(src, c);
2863
2864 reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
2865 }
2866 }
2867 }
2868
2869 /* Returns a bitmask indicating which dst components need to be
2870 * written to temporaries first to avoid 'corrupting' sources.
2871 *
2872 * m[i] (out) indicate component to write in the i-th position
2873 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2874 */
2875 static unsigned
2876 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2877 {
2878 unsigned i, c, x, unsafe;
2879
2880 for (c = 0; c < 4; c++)
2881 m[c] = c;
2882
2883 /* Swap as long as a dst component written earlier is depended on
2884 * by one written later, but the next one isn't depended on by it.
2885 */
2886 for (c = 0; c < 3; c++) {
2887 if (rdep[m[c + 1]] & (1 << m[c]))
2888 continue; /* if next one is depended on by us */
2889 for (i = c + 1; i < 4; i++)
2890 /* if we are depended on by a later one */
2891 if (rdep[m[c]] & (1 << m[i]))
2892 break;
2893 if (i == 4)
2894 continue;
2895 /* now, swap */
2896 x = m[c];
2897 m[c] = m[c + 1];
2898 m[c + 1] = x;
2899
2900 /* restart */
2901 c = 0;
2902 }
2903
2904 /* mark dependencies that could not be resolved by reordering */
2905 for (i = 0; i < 3; ++i)
2906 for (c = i + 1; c < 4; ++c)
2907 if (rdep[m[i]] & (1 << m[c]))
2908 unsafe |= (1 << i);
2909
2910 /* NOTE: $unsafe is with respect to order, not component */
2911 return unsafe;
2912 }
2913
2914 /* Select a suitable dst register for broadcasting scalar results,
2915 * or return NULL if we have to allocate an extra TEMP.
2916 *
2917 * If e.g. only 1 component is written, we may also emit the final
2918 * result to a write-only register.
2919 */
2920 static struct nv50_reg *
2921 tgsi_broadcast_dst(struct nv50_pc *pc,
2922 const struct tgsi_full_dst_register *fd, unsigned mask)
2923 {
2924 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
2925 int c = ffs(~mask & fd->Register.WriteMask);
2926 if (c)
2927 return tgsi_dst(pc, c - 1, fd);
2928 } else {
2929 int c = ffs(fd->Register.WriteMask) - 1;
2930 if ((1 << c) == fd->Register.WriteMask)
2931 return tgsi_dst(pc, c, fd);
2932 }
2933
2934 return NULL;
2935 }
2936
2937 /* Scan source swizzles and return a bitmask indicating dst regs that
2938 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2939 */
2940 static unsigned
2941 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2942 unsigned rdep[4])
2943 {
2944 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
2945 const struct tgsi_full_src_register *fs;
2946 unsigned i, deqs = 0;
2947
2948 for (i = 0; i < 4; ++i)
2949 rdep[i] = 0;
2950
2951 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2952 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2953 int ms = get_supported_mods(insn, i);
2954
2955 fs = &insn->Src[i];
2956 if (fs->Register.File != fd->Register.File ||
2957 fs->Register.Index != fd->Register.Index)
2958 continue;
2959
2960 for (chn = 0; chn < 4; ++chn) {
2961 unsigned s, c;
2962
2963 if (!(mask & (1 << chn))) /* src is not read */
2964 continue;
2965 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2966 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2967
2968 if (!(fd->Register.WriteMask & (1 << c)))
2969 continue;
2970
2971 if (s == TGSI_UTIL_SIGN_TOGGLE && !(ms & NV50_MOD_NEG))
2972 continue;
2973 if (s == TGSI_UTIL_SIGN_CLEAR && !(ms & NV50_MOD_ABS))
2974 continue;
2975 if ((s == TGSI_UTIL_SIGN_SET) && ((ms & 3) != 3))
2976 continue;
2977
2978 rdep[c] |= nv50_tgsi_dst_revdep(
2979 insn->Instruction.Opcode, i, chn);
2980 deqs |= (1 << c);
2981 }
2982 }
2983
2984 return deqs;
2985 }
2986
2987 static boolean
2988 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2989 {
2990 struct tgsi_full_instruction insn = tok->FullInstruction;
2991 const struct tgsi_full_dst_register *fd;
2992 unsigned i, deqs, rdep[4], m[4];
2993
2994 fd = &tok->FullInstruction.Dst[0];
2995 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2996
2997 if (is_scalar_op(insn.Instruction.Opcode)) {
2998 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2999 if (!pc->r_brdc)
3000 pc->r_brdc = temp_temp(pc);
3001 return nv50_program_tx_insn(pc, &insn);
3002 }
3003 pc->r_brdc = NULL;
3004
3005 if (!deqs || (!rdep[0] && !rdep[1] && !rdep[2] && !rdep[3]))
3006 return nv50_program_tx_insn(pc, &insn);
3007
3008 deqs = nv50_revdep_reorder(m, rdep);
3009
3010 for (i = 0; i < 4; ++i) {
3011 assert(pc->r_dst[m[i]] == NULL);
3012
3013 insn.Dst[0].Register.WriteMask =
3014 fd->Register.WriteMask & (1 << m[i]);
3015
3016 if (!insn.Dst[0].Register.WriteMask)
3017 continue;
3018
3019 if (deqs & (1 << i))
3020 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
3021
3022 if (!nv50_program_tx_insn(pc, &insn))
3023 return FALSE;
3024 }
3025
3026 for (i = 0; i < 4; i++) {
3027 struct nv50_reg *reg = pc->r_dst[i];
3028 if (!reg)
3029 continue;
3030 pc->r_dst[i] = NULL;
3031
3032 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
3033 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
3034 else
3035 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
3036 free_temp(pc, reg);
3037 }
3038
3039 return TRUE;
3040 }
3041
3042 static void
3043 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
3044 {
3045 struct nv50_reg *iv, **ppiv;
3046 unsigned mode = pc->interp_mode[reg->index];
3047
3048 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
3049 iv = *ppiv;
3050
3051 if ((mode & INTERP_PERSPECTIVE) && !iv) {
3052 iv = *ppiv = alloc_temp(pc, NULL);
3053 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
3054
3055 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
3056 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
3057
3058 /* XXX: when loading interpolants dynamically, move these
3059 * to the program head, or make sure it can't be skipped.
3060 */
3061 }
3062
3063 emit_interp(pc, reg, iv, mode);
3064 }
3065
3066 /* The face input is always at v[255] (varying space), with a
3067 * value of 0 for back-facing, and 0xffffffff for front-facing.
3068 */
3069 static void
3070 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
3071 {
3072 struct nv50_reg *one = alloc_immd(pc, 1.0f);
3073
3074 assert(a->rhw == -1);
3075 alloc_reg(pc, a); /* do this before rhw is set */
3076 a->rhw = 255;
3077 load_interpolant(pc, a);
3078 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
3079
3080 FREE(one);
3081 }
3082
3083 static boolean
3084 nv50_program_tx_prep(struct nv50_pc *pc)
3085 {
3086 struct tgsi_parse_context tp;
3087 struct nv50_program *p = pc->p;
3088 boolean ret = FALSE;
3089 unsigned i, c, flat_nr = 0;
3090
3091 tgsi_parse_init(&tp, pc->p->pipe.tokens);
3092 while (!tgsi_parse_end_of_tokens(&tp)) {
3093 const union tgsi_full_token *tok = &tp.FullToken;
3094
3095 tgsi_parse_token(&tp);
3096 switch (tok->Token.Type) {
3097 case TGSI_TOKEN_TYPE_IMMEDIATE:
3098 {
3099 const struct tgsi_full_immediate *imm =
3100 &tp.FullToken.FullImmediate;
3101
3102 ctor_immd_4f32(pc, imm->u[0].Float,
3103 imm->u[1].Float,
3104 imm->u[2].Float,
3105 imm->u[3].Float);
3106 }
3107 break;
3108 case TGSI_TOKEN_TYPE_DECLARATION:
3109 {
3110 const struct tgsi_full_declaration *d;
3111 unsigned si, last, first, mode;
3112
3113 d = &tp.FullToken.FullDeclaration;
3114 first = d->Range.First;
3115 last = d->Range.Last;
3116
3117 switch (d->Declaration.File) {
3118 case TGSI_FILE_TEMPORARY:
3119 break;
3120 case TGSI_FILE_OUTPUT:
3121 if (!d->Declaration.Semantic ||
3122 p->type == PIPE_SHADER_FRAGMENT)
3123 break;
3124
3125 si = d->Semantic.Index;
3126 switch (d->Semantic.Name) {
3127 case TGSI_SEMANTIC_BCOLOR:
3128 p->cfg.two_side[si].hw = first;
3129 if (p->cfg.io_nr > first)
3130 p->cfg.io_nr = first;
3131 break;
3132 case TGSI_SEMANTIC_PSIZE:
3133 p->cfg.psiz = first;
3134 if (p->cfg.io_nr > first)
3135 p->cfg.io_nr = first;
3136 break;
3137 case TGSI_SEMANTIC_EDGEFLAG:
3138 pc->edgeflag_out = first;
3139 break;
3140 /*
3141 case TGSI_SEMANTIC_CLIP_DISTANCE:
3142 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3143 break;
3144 */
3145 default:
3146 break;
3147 }
3148 break;
3149 case TGSI_FILE_INPUT:
3150 {
3151 if (p->type != PIPE_SHADER_FRAGMENT)
3152 break;
3153
3154 switch (d->Declaration.Interpolate) {
3155 case TGSI_INTERPOLATE_CONSTANT:
3156 mode = INTERP_FLAT;
3157 flat_nr++;
3158 break;
3159 case TGSI_INTERPOLATE_PERSPECTIVE:
3160 mode = INTERP_PERSPECTIVE;
3161 p->cfg.regs[1] |= 0x08 << 24;
3162 break;
3163 default:
3164 mode = INTERP_LINEAR;
3165 break;
3166 }
3167 if (d->Declaration.Centroid)
3168 mode |= INTERP_CENTROID;
3169
3170 assert(last < 32);
3171 for (i = first; i <= last; i++)
3172 pc->interp_mode[i] = mode;
3173 }
3174 break;
3175 case TGSI_FILE_ADDRESS:
3176 case TGSI_FILE_CONSTANT:
3177 case TGSI_FILE_SAMPLER:
3178 break;
3179 default:
3180 NOUVEAU_ERR("bad decl file %d\n",
3181 d->Declaration.File);
3182 goto out_err;
3183 }
3184 }
3185 break;
3186 case TGSI_TOKEN_TYPE_INSTRUCTION:
3187 pc->insn_nr++;
3188 prep_inspect_insn(pc, &tok->FullInstruction);
3189 break;
3190 default:
3191 break;
3192 }
3193 }
3194
3195 if (p->type == PIPE_SHADER_VERTEX) {
3196 int rid = 0;
3197
3198 for (i = 0; i < pc->attr_nr * 4; ++i) {
3199 if (pc->attr[i].acc) {
3200 pc->attr[i].hw = rid++;
3201 p->cfg.attr[i / 32] |= 1 << (i % 32);
3202 }
3203 }
3204
3205 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3206 p->cfg.io[i].hw = rid;
3207 p->cfg.io[i].id = i;
3208
3209 for (c = 0; c < 4; ++c) {
3210 int n = i * 4 + c;
3211 if (!pc->result[n].acc)
3212 continue;
3213 pc->result[n].hw = rid++;
3214 p->cfg.io[i].mask |= 1 << c;
3215 }
3216 }
3217
3218 for (c = 0; c < 2; ++c)
3219 if (p->cfg.two_side[c].hw < 0x40)
3220 p->cfg.two_side[c] = p->cfg.io[
3221 p->cfg.two_side[c].hw];
3222
3223 if (p->cfg.psiz < 0x40)
3224 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
3225 } else
3226 if (p->type == PIPE_SHADER_FRAGMENT) {
3227 int rid, aid;
3228 unsigned n = 0, m = pc->attr_nr - flat_nr;
3229
3230 pc->allow32 = TRUE;
3231
3232 int base = (TGSI_SEMANTIC_POSITION ==
3233 p->info.input_semantic_name[0]) ? 0 : 1;
3234
3235 /* non-flat interpolants have to be mapped to
3236 * the lower hardware IDs, so sort them:
3237 */
3238 for (i = 0; i < pc->attr_nr; i++) {
3239 if (pc->interp_mode[i] == INTERP_FLAT)
3240 p->cfg.io[m++].id = i;
3241 else {
3242 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3243 p->cfg.io[n].linear = TRUE;
3244 p->cfg.io[n++].id = i;
3245 }
3246 }
3247
3248 if (!base) /* set w-coordinate mask from perspective interp */
3249 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
3250
3251 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
3252 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
3253
3254 for (n = 0; n < pc->attr_nr; ++n) {
3255 p->cfg.io[n].hw = rid = aid;
3256 i = p->cfg.io[n].id;
3257
3258 if (p->info.input_semantic_name[n] ==
3259 TGSI_SEMANTIC_FACE) {
3260 load_frontfacing(pc, &pc->attr[i * 4]);
3261 continue;
3262 }
3263
3264 for (c = 0; c < 4; ++c) {
3265 if (!pc->attr[i * 4 + c].acc)
3266 continue;
3267 pc->attr[i * 4 + c].rhw = rid++;
3268 p->cfg.io[n].mask |= 1 << c;
3269
3270 load_interpolant(pc, &pc->attr[i * 4 + c]);
3271 }
3272 aid += popcnt4(p->cfg.io[n].mask);
3273 }
3274
3275 if (!base)
3276 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
3277
3278 m = popcnt4(p->cfg.regs[1] >> 24);
3279
3280 /* set count of non-position inputs and of non-flat
3281 * non-position inputs for FP_INTERPOLANT_CTRL
3282 */
3283 p->cfg.regs[1] |= aid - m;
3284
3285 if (flat_nr) {
3286 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
3287 p->cfg.regs[1] |= (i - m) << 16;
3288 } else
3289 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3290
3291 /* mark color semantic for light-twoside */
3292 n = 0x40;
3293 for (i = 0; i < pc->attr_nr; i++) {
3294 ubyte si, sn;
3295
3296 sn = p->info.input_semantic_name[p->cfg.io[i].id];
3297 si = p->info.input_semantic_index[p->cfg.io[i].id];
3298
3299 if (sn == TGSI_SEMANTIC_COLOR) {
3300 p->cfg.two_side[si] = p->cfg.io[i];
3301
3302 /* increase colour count */
3303 p->cfg.regs[0] += popcnt4(
3304 p->cfg.two_side[si].mask) << 16;
3305
3306 n = MIN2(n, p->cfg.io[i].hw - m);
3307 }
3308 }
3309 if (n < 0x40)
3310 p->cfg.regs[0] += n;
3311
3312 /* Initialize FP results:
3313 * FragDepth is always first TGSI and last hw output
3314 */
3315 i = p->info.writes_z ? 4 : 0;
3316 for (rid = 0; i < pc->result_nr * 4; i++)
3317 pc->result[i].rhw = rid++;
3318 if (p->info.writes_z)
3319 pc->result[2].rhw = rid;
3320
3321 p->cfg.high_result = rid;
3322
3323 /* separate/different colour results for MRTs ? */
3324 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3325 p->cfg.regs[2] |= 1;
3326 }
3327
3328 if (pc->immd_nr) {
3329 int rid = 0;
3330
3331 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3332 if (!pc->immd)
3333 goto out_err;
3334
3335 for (i = 0; i < pc->immd_nr; i++) {
3336 for (c = 0; c < 4; c++, rid++)
3337 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3338 }
3339 }
3340
3341 ret = TRUE;
3342 out_err:
3343 if (pc->iv_p)
3344 free_temp(pc, pc->iv_p);
3345 if (pc->iv_c)
3346 free_temp(pc, pc->iv_c);
3347
3348 tgsi_parse_free(&tp);
3349 return ret;
3350 }
3351
3352 static void
3353 free_nv50_pc(struct nv50_pc *pc)
3354 {
3355 if (pc->immd)
3356 FREE(pc->immd);
3357 if (pc->param)
3358 FREE(pc->param);
3359 if (pc->result)
3360 FREE(pc->result);
3361 if (pc->attr)
3362 FREE(pc->attr);
3363 if (pc->temp)
3364 FREE(pc->temp);
3365
3366 FREE(pc);
3367 }
3368
3369 static boolean
3370 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3371 {
3372 int i, c;
3373 unsigned rtype[2] = { P_ATTR, P_RESULT };
3374
3375 pc->p = p;
3376 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3377 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3378 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3379 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3380 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3381 assert(pc->addr_nr <= 2);
3382
3383 p->cfg.high_temp = 4;
3384
3385 p->cfg.two_side[0].hw = 0x40;
3386 p->cfg.two_side[1].hw = 0x40;
3387
3388 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3389
3390 switch (p->type) {
3391 case PIPE_SHADER_VERTEX:
3392 p->cfg.psiz = 0x40;
3393 p->cfg.clpd = 0x40;
3394 p->cfg.io_nr = pc->result_nr;
3395 break;
3396 case PIPE_SHADER_FRAGMENT:
3397 rtype[0] = rtype[1] = P_TEMP;
3398
3399 p->cfg.regs[0] = 0x01000004;
3400 p->cfg.io_nr = pc->attr_nr;
3401
3402 if (p->info.writes_z) {
3403 p->cfg.regs[2] |= 0x00000100;
3404 p->cfg.regs[3] |= 0x00000011;
3405 }
3406 if (p->info.uses_kill)
3407 p->cfg.regs[2] |= 0x00100000;
3408 break;
3409 }
3410
3411 if (pc->temp_nr) {
3412 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3413 if (!pc->temp)
3414 return FALSE;
3415
3416 for (i = 0; i < pc->temp_nr * 4; ++i)
3417 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3418 }
3419
3420 if (pc->attr_nr) {
3421 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3422 if (!pc->attr)
3423 return FALSE;
3424
3425 for (i = 0; i < pc->attr_nr * 4; ++i)
3426 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3427 }
3428
3429 if (pc->result_nr) {
3430 unsigned nr = pc->result_nr * 4;
3431
3432 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3433 if (!pc->result)
3434 return FALSE;
3435
3436 for (i = 0; i < nr; ++i)
3437 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3438 }
3439
3440 if (pc->param_nr) {
3441 int rid = 0;
3442
3443 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3444 if (!pc->param)
3445 return FALSE;
3446
3447 for (i = 0; i < pc->param_nr; ++i)
3448 for (c = 0; c < 4; ++c, ++rid)
3449 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3450 }
3451
3452 if (pc->addr_nr) {
3453 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3454 if (!pc->addr)
3455 return FALSE;
3456 }
3457 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3458 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
3459
3460 return TRUE;
3461 }
3462
3463 static void
3464 nv50_program_fixup_insns(struct nv50_pc *pc)
3465 {
3466 struct nv50_program_exec *e, **bra_list;
3467 unsigned i, n, pos;
3468
3469 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3470
3471 /* Collect branch instructions, we need to adjust their offsets
3472 * when converting 32 bit instructions to 64 bit ones
3473 */
3474 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3475 if (e->param.index >= 0 && !e->param.mask)
3476 bra_list[n++] = e;
3477
3478 /* Make sure we don't have any single 32 bit instructions. */
3479 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3480 pos += is_long(e) ? 2 : 1;
3481
3482 if ((pos & 1) && (!e->next || is_long(e->next))) {
3483 for (i = 0; i < n; ++i)
3484 if (bra_list[i]->param.index >= pos)
3485 bra_list[i]->param.index += 1;
3486 for (i = 0; i < pc->insn_nr; ++i)
3487 if (pc->insn_pos[i] >= pos)
3488 pc->insn_pos[i] += 1;
3489 convert_to_long(pc, e);
3490 ++pos;
3491 }
3492 }
3493
3494 FREE(bra_list);
3495
3496 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
3497 return;
3498
3499 /* fill in CALL offsets */
3500 for (e = pc->p->exec_head; e; e = e->next) {
3501 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
3502 e->param.index = pc->insn_pos[e->param.index];
3503 }
3504 }
3505
3506 static boolean
3507 nv50_program_tx(struct nv50_program *p)
3508 {
3509 struct tgsi_parse_context parse;
3510 struct nv50_pc *pc;
3511 boolean ret;
3512
3513 pc = CALLOC_STRUCT(nv50_pc);
3514 if (!pc)
3515 return FALSE;
3516
3517 ret = ctor_nv50_pc(pc, p);
3518 if (ret == FALSE)
3519 goto out_cleanup;
3520
3521 ret = nv50_program_tx_prep(pc);
3522 if (ret == FALSE)
3523 goto out_cleanup;
3524
3525 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
3526
3527 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3528 while (!tgsi_parse_end_of_tokens(&parse)) {
3529 const union tgsi_full_token *tok = &parse.FullToken;
3530
3531 /* previously allow32 was FALSE for first & last instruction */
3532 pc->allow32 = TRUE;
3533
3534 tgsi_parse_token(&parse);
3535
3536 switch (tok->Token.Type) {
3537 case TGSI_TOKEN_TYPE_INSTRUCTION:
3538 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
3539 ++pc->insn_cur;
3540 ret = nv50_tgsi_insn(pc, tok);
3541 if (ret == FALSE)
3542 goto out_err;
3543 break;
3544 default:
3545 break;
3546 }
3547 }
3548
3549 nv50_program_fixup_insns(pc);
3550
3551 p->param_nr = pc->param_nr * 4;
3552 p->immd_nr = pc->immd_nr * 4;
3553 p->immd = pc->immd_buf;
3554
3555 out_err:
3556 tgsi_parse_free(&parse);
3557
3558 out_cleanup:
3559 free_nv50_pc(pc);
3560 return ret;
3561 }
3562
3563 static void
3564 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3565 {
3566 if (nv50_program_tx(p) == FALSE)
3567 assert(0);
3568 p->translated = TRUE;
3569 }
3570
3571 static void
3572 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
3573 unsigned start, unsigned count, unsigned cbuf)
3574 {
3575 struct nouveau_channel *chan = nv50->screen->base.channel;
3576 struct nouveau_grobj *tesla = nv50->screen->tesla;
3577
3578 while (count) {
3579 unsigned nr = count > 2047 ? 2047 : count;
3580
3581 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3582 OUT_RING (chan, (cbuf << 0) | (start << 8));
3583 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3584 OUT_RINGp (chan, map, nr);
3585
3586 map += nr;
3587 start += nr;
3588 count -= nr;
3589 }
3590 }
3591
3592 static void
3593 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3594 {
3595 struct pipe_screen *pscreen = nv50->pipe.screen;
3596
3597 if (!p->data[0] && p->immd_nr) {
3598 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3599
3600 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3601 while (heap->next && heap->size < p->immd_nr) {
3602 struct nv50_program *evict = heap->next->priv;
3603 nouveau_resource_free(&evict->data[0]);
3604 }
3605
3606 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3607 &p->data[0]))
3608 assert(0);
3609 }
3610
3611 /* immediates only need to be uploaded again when freed */
3612 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3613 p->immd_nr, NV50_CB_PMISC);
3614 }
3615
3616 assert(p->param_nr <= 512);
3617
3618 if (p->param_nr) {
3619 unsigned cb;
3620 uint32_t *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3621 PIPE_BUFFER_USAGE_CPU_READ);
3622
3623 if (p->type == PIPE_SHADER_VERTEX)
3624 cb = NV50_CB_PVP;
3625 else
3626 cb = NV50_CB_PFP;
3627
3628 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3629 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3630 }
3631 }
3632
3633 static void
3634 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3635 {
3636 struct nouveau_channel *chan = nv50->screen->base.channel;
3637 struct nv50_program_exec *e;
3638 uint32_t *up, i;
3639 boolean upload = FALSE;
3640
3641 if (!p->bo) {
3642 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3643 p->exec_size * 4, &p->bo);
3644 upload = TRUE;
3645 }
3646
3647 if (p->data[0] && p->data[0]->start != p->data_start[0])
3648 upload = TRUE;
3649
3650 if (!upload)
3651 return;
3652
3653 up = MALLOC(p->exec_size * 4);
3654
3655 for (i = 0, e = p->exec_head; e; e = e->next) {
3656 unsigned ei, ci, bs;
3657
3658 if (e->param.index >= 0 && e->param.mask) {
3659 bs = (e->inst[1] >> 22) & 0x07;
3660 assert(bs < 2);
3661 ei = e->param.shift >> 5;
3662 ci = e->param.index;
3663 if (bs == 0)
3664 ci += p->data[bs]->start;
3665
3666 e->inst[ei] &= ~e->param.mask;
3667 e->inst[ei] |= (ci << e->param.shift);
3668 } else
3669 if (e->param.index >= 0) {
3670 /* zero mask means param is a jump/branch offset */
3671 assert(!(e->param.index & 1));
3672 /* seem to be 8 byte steps */
3673 ei = (e->param.index >> 1) + 0 /* START_ID */;
3674
3675 e->inst[0] &= 0xf0000fff;
3676 e->inst[0] |= ei << 12;
3677 }
3678
3679 up[i++] = e->inst[0];
3680 if (is_long(e))
3681 up[i++] = e->inst[1];
3682 }
3683 assert(i == p->exec_size);
3684
3685 if (p->data[0])
3686 p->data_start[0] = p->data[0]->start;
3687
3688 #ifdef NV50_PROGRAM_DUMP
3689 NOUVEAU_ERR("-------\n");
3690 for (e = p->exec_head; e; e = e->next) {
3691 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3692 if (is_long(e))
3693 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3694 }
3695 #endif
3696 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3697 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3698 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3699 0, 0, p->exec_size * 4, 1, 1);
3700
3701 FREE(up);
3702 }
3703
3704 void
3705 nv50_vertprog_validate(struct nv50_context *nv50)
3706 {
3707 struct nouveau_grobj *tesla = nv50->screen->tesla;
3708 struct nv50_program *p = nv50->vertprog;
3709 struct nouveau_stateobj *so;
3710
3711 if (!p->translated) {
3712 nv50_program_validate(nv50, p);
3713 if (!p->translated)
3714 assert(0);
3715 }
3716
3717 nv50_program_validate_data(nv50, p);
3718 nv50_program_validate_code(nv50, p);
3719
3720 so = so_new(5, 8, 2);
3721 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3722 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3723 NOUVEAU_BO_HIGH, 0, 0);
3724 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3725 NOUVEAU_BO_LOW, 0, 0);
3726 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3727 so_data (so, p->cfg.attr[0]);
3728 so_data (so, p->cfg.attr[1]);
3729 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3730 so_data (so, p->cfg.high_result);
3731 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3732 so_data (so, p->cfg.high_result); //8);
3733 so_data (so, p->cfg.high_temp);
3734 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3735 so_data (so, 0); /* program start offset */
3736 so_ref(so, &nv50->state.vertprog);
3737 so_ref(NULL, &so);
3738 }
3739
3740 void
3741 nv50_fragprog_validate(struct nv50_context *nv50)
3742 {
3743 struct nouveau_grobj *tesla = nv50->screen->tesla;
3744 struct nv50_program *p = nv50->fragprog;
3745 struct nouveau_stateobj *so;
3746
3747 if (!p->translated) {
3748 nv50_program_validate(nv50, p);
3749 if (!p->translated)
3750 assert(0);
3751 }
3752
3753 nv50_program_validate_data(nv50, p);
3754 nv50_program_validate_code(nv50, p);
3755
3756 so = so_new(6, 7, 2);
3757 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3758 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3759 NOUVEAU_BO_HIGH, 0, 0);
3760 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3761 NOUVEAU_BO_LOW, 0, 0);
3762 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3763 so_data (so, p->cfg.high_temp);
3764 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3765 so_data (so, p->cfg.high_result);
3766 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
3767 so_data (so, p->cfg.regs[2]);
3768 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3769 so_data (so, p->cfg.regs[3]);
3770 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3771 so_data (so, 0); /* program start offset */
3772 so_ref(so, &nv50->state.fragprog);
3773 so_ref(NULL, &so);
3774 }
3775
3776 static void
3777 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3778 {
3779 struct nv50_program *fp = nv50->fragprog;
3780 struct nv50_program *vp = nv50->vertprog;
3781 unsigned i, c, m = base;
3782
3783 /* XXX: this might not work correctly in all cases yet - we'll
3784 * just assume that an FP generic input that is not written in
3785 * the VP is PointCoord.
3786 */
3787 memset(pntc, 0, 8 * sizeof(uint32_t));
3788
3789 for (i = 0; i < fp->cfg.io_nr; i++) {
3790 uint8_t sn, si;
3791 uint8_t j, k = fp->cfg.io[i].id;
3792 unsigned n = popcnt4(fp->cfg.io[i].mask);
3793
3794 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3795 m += n;
3796 continue;
3797 }
3798
3799 for (j = 0; j < vp->info.num_outputs; ++j) {
3800 sn = vp->info.output_semantic_name[j];
3801 si = vp->info.output_semantic_index[j];
3802
3803 if (sn == fp->info.input_semantic_name[k] &&
3804 si == fp->info.input_semantic_index[k])
3805 break;
3806 }
3807
3808 if (j < vp->info.num_outputs) {
3809 ubyte mode =
3810 nv50->rasterizer->pipe.sprite_coord_mode[si];
3811
3812 if (mode == PIPE_SPRITE_COORD_NONE) {
3813 m += n;
3814 continue;
3815 }
3816 }
3817
3818 /* this is either PointCoord or replaced by sprite coords */
3819 for (c = 0; c < 4; c++) {
3820 if (!(fp->cfg.io[i].mask & (1 << c)))
3821 continue;
3822 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3823 ++m;
3824 }
3825 }
3826 }
3827
3828 static int
3829 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3830 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3831 {
3832 int c;
3833 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3834 uint8_t *map = (uint8_t *)p_map;
3835
3836 for (c = 0; c < 4; ++c) {
3837 if (mf & 1) {
3838 if (fpi->linear == TRUE)
3839 lin[mid / 32] |= 1 << (mid % 32);
3840 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3841 }
3842
3843 oid += mv & 1;
3844 mf >>= 1;
3845 mv >>= 1;
3846 }
3847
3848 return mid;
3849 }
3850
3851 void
3852 nv50_linkage_validate(struct nv50_context *nv50)
3853 {
3854 struct nouveau_grobj *tesla = nv50->screen->tesla;
3855 struct nv50_program *vp = nv50->vertprog;
3856 struct nv50_program *fp = nv50->fragprog;
3857 struct nouveau_stateobj *so;
3858 struct nv50_sreg4 dummy, *vpo;
3859 int i, n, c, m = 0;
3860 uint32_t map[16], lin[4], reg[5], pcrd[8];
3861
3862 memset(map, 0, sizeof(map));
3863 memset(lin, 0, sizeof(lin));
3864
3865 reg[1] = 0x00000004; /* low and high clip distance map ids */
3866 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3867 reg[3] = 0x00000000; /* point size map id & enable */
3868 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3869 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3870
3871 dummy.linear = FALSE;
3872 dummy.mask = 0xf; /* map all components of HPOS */
3873 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3874
3875 dummy.mask = 0x0;
3876
3877 if (vp->cfg.clpd < 0x40) {
3878 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3879 map[m++] = vp->cfg.clpd + c;
3880 reg[1] = (m << 8);
3881 }
3882
3883 reg[0] |= m << 8; /* adjust BFC0 id */
3884
3885 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3886 if (nv50->rasterizer->pipe.light_twoside) {
3887 vpo = &vp->cfg.two_side[0];
3888
3889 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3890 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3891 }
3892
3893 reg[0] += m - 4; /* adjust FFC0 id */
3894 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3895
3896 for (i = 0; i < fp->cfg.io_nr; i++) {
3897 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
3898 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
3899
3900 /* position must be mapped first */
3901 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
3902
3903 /* maybe even remove these from cfg.io */
3904 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
3905 continue;
3906
3907 /* VP outputs and vp->cfg.io are in the same order */
3908 for (n = 0; n < vp->info.num_outputs; ++n) {
3909 if (vp->info.output_semantic_name[n] == sn &&
3910 vp->info.output_semantic_index[n] == si)
3911 break;
3912 }
3913 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
3914
3915 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3916 }
3917
3918 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3919 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3920 reg[3] = (m++ << 4) | 1;
3921 }
3922
3923 /* now fill the stateobj */
3924 so = so_new(6, 58, 0);
3925
3926 n = (m + 3) / 4;
3927 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3928 so_data (so, m);
3929 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3930 so_datap (so, map, n);
3931
3932 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3933 so_datap (so, reg, 4);
3934
3935 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3936 so_data (so, reg[4]);
3937
3938 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
3939 so_datap (so, lin, 4);
3940
3941 if (nv50->rasterizer->pipe.point_sprite) {
3942 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3943
3944 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3945 so_datap (so, pcrd, 8);
3946 }
3947
3948 so_ref(so, &nv50->state.programs);
3949 so_ref(NULL, &so);
3950 }
3951
3952 void
3953 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3954 {
3955 while (p->exec_head) {
3956 struct nv50_program_exec *e = p->exec_head;
3957
3958 p->exec_head = e->next;
3959 FREE(e);
3960 }
3961 p->exec_tail = NULL;
3962 p->exec_size = 0;
3963
3964 nouveau_bo_ref(NULL, &p->bo);
3965
3966 nouveau_resource_free(&p->data[0]);
3967
3968 p->translated = 0;
3969 }