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nv50: handle TGSI_OPCODE_EXP,LOG
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_SAT 4
100
101 /* STACK: Conditionals and loops have to use the (per warp) stack.
102 * Stack entries consist of an entry type (divergent path, join at),
103 * a mask indicating the active threads of the warp, and an address.
104 * MPs can store 12 stack entries internally, if we need more (and
105 * we probably do), we have to create a stack buffer in VRAM.
106 */
107 /* impose low limits for now */
108 #define NV50_MAX_COND_NESTING 4
109 #define NV50_MAX_LOOP_NESTING 3
110
111 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
112
113 struct nv50_pc {
114 struct nv50_program *p;
115
116 /* hw resources */
117 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
118 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
119
120 /* tgsi resources */
121 struct nv50_reg *temp;
122 int temp_nr;
123 struct nv50_reg *attr;
124 int attr_nr;
125 struct nv50_reg *result;
126 int result_nr;
127 struct nv50_reg *param;
128 int param_nr;
129 struct nv50_reg *immd;
130 uint32_t *immd_buf;
131 int immd_nr;
132 struct nv50_reg **addr;
133 int addr_nr;
134 uint8_t addr_alloc; /* set bit indicates used for TGSI_FILE_ADDRESS */
135
136 struct nv50_reg *temp_temp[16];
137 unsigned temp_temp_nr;
138
139 /* broadcast and destination replacement regs */
140 struct nv50_reg *r_brdc;
141 struct nv50_reg *r_dst[4];
142
143 struct nv50_reg reg_instances[16];
144 unsigned reg_instance_nr;
145
146 unsigned interp_mode[32];
147 /* perspective interpolation registers */
148 struct nv50_reg *iv_p;
149 struct nv50_reg *iv_c;
150
151 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
152 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
153 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
154 int if_lvl, loop_lvl;
155 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
156
157 unsigned *insn_pos; /* actual program offset of each TGSI insn */
158 boolean in_subroutine;
159
160 /* current instruction and total number of insns */
161 unsigned insn_cur;
162 unsigned insn_nr;
163
164 boolean allow32;
165
166 uint8_t edgeflag_out;
167 };
168
169 static INLINE void
170 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
171 {
172 reg->type = type;
173 reg->index = index;
174 reg->hw = hw;
175 reg->mod = 0;
176 reg->rhw = -1;
177 reg->acc = 0;
178 }
179
180 static INLINE unsigned
181 popcnt4(uint32_t val)
182 {
183 static const unsigned cnt[16]
184 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
185 return cnt[val & 0xf];
186 }
187
188 static void
189 terminate_mbb(struct nv50_pc *pc)
190 {
191 int i;
192
193 /* remove records of temporary address register values */
194 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
195 pc->r_addr[i].rhw = -1;
196 }
197
198 static void
199 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
200 {
201 int i = 0;
202
203 if (reg->type == P_RESULT) {
204 if (pc->p->cfg.high_result < (reg->hw + 1))
205 pc->p->cfg.high_result = reg->hw + 1;
206 }
207
208 if (reg->type != P_TEMP)
209 return;
210
211 if (reg->hw >= 0) {
212 /*XXX: do this here too to catch FP temp-as-attr usage..
213 * not clean, but works */
214 if (pc->p->cfg.high_temp < (reg->hw + 1))
215 pc->p->cfg.high_temp = reg->hw + 1;
216 return;
217 }
218
219 if (reg->rhw != -1) {
220 /* try to allocate temporary with index rhw first */
221 if (!(pc->r_temp[reg->rhw])) {
222 pc->r_temp[reg->rhw] = reg;
223 reg->hw = reg->rhw;
224 if (pc->p->cfg.high_temp < (reg->rhw + 1))
225 pc->p->cfg.high_temp = reg->rhw + 1;
226 return;
227 }
228 /* make sure we don't get things like $r0 needs to go
229 * in $r1 and $r1 in $r0
230 */
231 i = pc->result_nr * 4;
232 }
233
234 for (; i < NV50_SU_MAX_TEMP; i++) {
235 if (!(pc->r_temp[i])) {
236 pc->r_temp[i] = reg;
237 reg->hw = i;
238 if (pc->p->cfg.high_temp < (i + 1))
239 pc->p->cfg.high_temp = i + 1;
240 return;
241 }
242 }
243
244 assert(0);
245 }
246
247 static INLINE struct nv50_reg *
248 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
249 {
250 struct nv50_reg *ri;
251
252 assert(pc->reg_instance_nr < 16);
253 ri = &pc->reg_instances[pc->reg_instance_nr++];
254 if (reg) {
255 alloc_reg(pc, reg);
256 *ri = *reg;
257 reg->mod = 0;
258 }
259 return ri;
260 }
261
262 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
263 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
264 * lest we risk temp_temps overwriting regs alloc'd "later".
265 */
266 static struct nv50_reg *
267 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
268 {
269 struct nv50_reg *r;
270 int i;
271
272 if (dst && dst->type == P_TEMP && dst->hw == -1)
273 return dst;
274
275 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
276 if (!pc->r_temp[i]) {
277 r = MALLOC_STRUCT(nv50_reg);
278 ctor_reg(r, P_TEMP, -1, i);
279 pc->r_temp[i] = r;
280 return r;
281 }
282 }
283
284 assert(0);
285 return NULL;
286 }
287
288 /* Assign the hw of the discarded temporary register src
289 * to the tgsi register dst and free src.
290 */
291 static void
292 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
293 {
294 assert(src->index == -1 && src->hw != -1);
295
296 if (dst->hw != -1)
297 pc->r_temp[dst->hw] = NULL;
298 pc->r_temp[src->hw] = dst;
299 dst->hw = src->hw;
300
301 FREE(src);
302 }
303
304 /* release the hardware resource held by r */
305 static void
306 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
307 {
308 assert(r->type == P_TEMP);
309 if (r->hw == -1)
310 return;
311
312 assert(pc->r_temp[r->hw] == r);
313 pc->r_temp[r->hw] = NULL;
314
315 r->acc = 0;
316 if (r->index == -1)
317 FREE(r);
318 }
319
320 static void
321 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
322 {
323 if (r->index == -1) {
324 unsigned hw = r->hw;
325
326 FREE(pc->r_temp[hw]);
327 pc->r_temp[hw] = NULL;
328 }
329 }
330
331 static int
332 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
333 {
334 int i;
335
336 if ((idx + 4) >= NV50_SU_MAX_TEMP)
337 return 1;
338
339 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
340 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
341 return alloc_temp4(pc, dst, idx + 4);
342
343 for (i = 0; i < 4; i++) {
344 dst[i] = MALLOC_STRUCT(nv50_reg);
345 ctor_reg(dst[i], P_TEMP, -1, idx + i);
346 pc->r_temp[idx + i] = dst[i];
347 }
348
349 return 0;
350 }
351
352 static void
353 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
354 {
355 int i;
356
357 for (i = 0; i < 4; i++)
358 free_temp(pc, reg[i]);
359 }
360
361 static struct nv50_reg *
362 temp_temp(struct nv50_pc *pc)
363 {
364 if (pc->temp_temp_nr >= 16)
365 assert(0);
366
367 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
368 return pc->temp_temp[pc->temp_temp_nr++];
369 }
370
371 static void
372 kill_temp_temp(struct nv50_pc *pc)
373 {
374 int i;
375
376 for (i = 0; i < pc->temp_temp_nr; i++)
377 free_temp(pc, pc->temp_temp[i]);
378 pc->temp_temp_nr = 0;
379 }
380
381 static int
382 ctor_immd_4u32(struct nv50_pc *pc,
383 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
384 {
385 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
386
387 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
388
389 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
390 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
391 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
392 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
393
394 return pc->immd_nr++;
395 }
396
397 static INLINE int
398 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
399 {
400 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
401 }
402
403 static struct nv50_reg *
404 alloc_immd(struct nv50_pc *pc, float f)
405 {
406 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
407 unsigned hw;
408
409 for (hw = 0; hw < pc->immd_nr * 4; hw++)
410 if (pc->immd_buf[hw] == fui(f))
411 break;
412
413 if (hw == pc->immd_nr * 4)
414 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
415
416 ctor_reg(r, P_IMMD, -1, hw);
417 return r;
418 }
419
420 static struct nv50_program_exec *
421 exec(struct nv50_pc *pc)
422 {
423 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
424
425 e->param.index = -1;
426 return e;
427 }
428
429 static void
430 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
431 {
432 struct nv50_program *p = pc->p;
433
434 if (p->exec_tail)
435 p->exec_tail->next = e;
436 if (!p->exec_head)
437 p->exec_head = e;
438 p->exec_tail = e;
439 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
440 }
441
442 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
443
444 static boolean
445 is_long(struct nv50_program_exec *e)
446 {
447 if (e->inst[0] & 1)
448 return TRUE;
449 return FALSE;
450 }
451
452 static boolean
453 is_immd(struct nv50_program_exec *e)
454 {
455 if (is_long(e) && (e->inst[1] & 3) == 3)
456 return TRUE;
457 return FALSE;
458 }
459
460 static boolean
461 is_join(struct nv50_program_exec *e)
462 {
463 if (is_long(e) && (e->inst[1] & 3) == 2)
464 return TRUE;
465 return FALSE;
466 }
467
468 static INLINE void
469 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
470 struct nv50_program_exec *e)
471 {
472 set_long(pc, e);
473 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
474 e->inst[1] |= (pred << 7) | (idx << 12);
475 }
476
477 static INLINE void
478 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
479 struct nv50_program_exec *e)
480 {
481 set_long(pc, e);
482 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
483 e->inst[1] |= (idx << 4) | (on << 6);
484 }
485
486 static INLINE void
487 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
488 {
489 if (is_long(e))
490 return;
491
492 e->inst[0] |= 1;
493 set_pred(pc, 0xf, 0, e);
494 set_pred_wr(pc, 0, 0, e);
495 }
496
497 static INLINE void
498 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
499 {
500 if (dst->type == P_RESULT) {
501 set_long(pc, e);
502 e->inst[1] |= 0x00000008;
503 }
504
505 alloc_reg(pc, dst);
506 if (dst->hw > 63)
507 set_long(pc, e);
508 e->inst[0] |= (dst->hw << 2);
509 }
510
511 static INLINE void
512 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
513 {
514 set_long(pc, e);
515 /* XXX: can't be predicated - bits overlap; cases where both
516 * are required should be avoided by using pc->allow32 */
517 set_pred(pc, 0, 0, e);
518 set_pred_wr(pc, 0, 0, e);
519
520 e->inst[1] |= 0x00000002 | 0x00000001;
521 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
522 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
523 }
524
525 static INLINE void
526 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
527 {
528 assert(!(e->inst[0] & 0x0c000000));
529 assert(!(e->inst[1] & 0x00000004));
530
531 e->inst[0] |= (a->hw & 3) << 26;
532 e->inst[1] |= (a->hw >> 2) << 2;
533 }
534
535 static void
536 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
537 struct nv50_reg *src0, uint16_t src1_val)
538 {
539 struct nv50_program_exec *e = exec(pc);
540
541 e->inst[0] = 0xd0000000 | (src1_val << 9);
542 e->inst[1] = 0x20000000;
543 set_long(pc, e);
544 e->inst[0] |= dst->hw << 2;
545 if (src0) /* otherwise will add to $a0, which is always 0 */
546 set_addr(e, src0);
547
548 emit(pc, e);
549 }
550
551 static struct nv50_reg *
552 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
553 {
554 struct nv50_reg *a_tgsi = NULL, *a = NULL;
555 int i;
556 uint8_t avail = ~pc->addr_alloc;
557
558 if (!ref) {
559 /* allocate for TGSI_FILE_ADDRESS */
560 while (avail) {
561 i = ffs(avail) - 1;
562
563 if (pc->r_addr[i].rhw < 0 ||
564 pc->r_addr[i].acc != pc->insn_cur) {
565 pc->addr_alloc |= (1 << i);
566
567 pc->r_addr[i].rhw = -1;
568 pc->r_addr[i].index = i;
569 return &pc->r_addr[i];
570 }
571 avail &= ~(1 << i);
572 }
573 assert(0);
574 return NULL;
575 }
576
577 /* Allocate and set an address reg so we can access 'ref'.
578 *
579 * If and r_addr->index will be -1 or the hw index the value
580 * value in rhw is relative to. If rhw < 0, the reg has not
581 * been initialized or is in use for TGSI_FILE_ADDRESS.
582 */
583 while (avail) { /* only consider regs that are not TGSI */
584 i = ffs(avail) - 1;
585 avail &= ~(1 << i);
586
587 if ((!a || a->rhw >= 0) && pc->r_addr[i].rhw < 0) {
588 /* prefer an usused reg with low hw index */
589 a = &pc->r_addr[i];
590 continue;
591 }
592 if (!a && pc->r_addr[i].acc != pc->insn_cur)
593 a = &pc->r_addr[i];
594
595 if (ref->hw - pc->r_addr[i].rhw >= 128)
596 continue;
597
598 if ((ref->acc >= 0 && pc->r_addr[i].index < 0) ||
599 (ref->acc < 0 && pc->r_addr[i].index == ref->index)) {
600 pc->r_addr[i].acc = pc->insn_cur;
601 return &pc->r_addr[i];
602 }
603 }
604 assert(a);
605
606 if (ref->acc < 0)
607 a_tgsi = pc->addr[ref->index];
608
609 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
610
611 a->rhw = ref->hw & ~0x7f;
612 a->acc = pc->insn_cur;
613 a->index = a_tgsi ? ref->index : -1;
614 return a;
615 }
616
617 #define INTERP_LINEAR 0
618 #define INTERP_FLAT 1
619 #define INTERP_PERSPECTIVE 2
620 #define INTERP_CENTROID 4
621
622 /* interpolant index has been stored in dst->rhw */
623 static void
624 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
625 unsigned mode)
626 {
627 assert(dst->rhw != -1);
628 struct nv50_program_exec *e = exec(pc);
629
630 e->inst[0] |= 0x80000000;
631 set_dst(pc, dst, e);
632 e->inst[0] |= (dst->rhw << 16);
633
634 if (mode & INTERP_FLAT) {
635 e->inst[0] |= (1 << 8);
636 } else {
637 if (mode & INTERP_PERSPECTIVE) {
638 e->inst[0] |= (1 << 25);
639 alloc_reg(pc, iv);
640 e->inst[0] |= (iv->hw << 9);
641 }
642
643 if (mode & INTERP_CENTROID)
644 e->inst[0] |= (1 << 24);
645 }
646
647 emit(pc, e);
648 }
649
650 static void
651 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
652 struct nv50_program_exec *e)
653 {
654 set_long(pc, e);
655
656 e->param.index = src->hw & 127;
657 e->param.shift = s;
658 e->param.mask = m << (s % 32);
659
660 if (src->hw > 127)
661 set_addr(e, alloc_addr(pc, src));
662 else
663 if (src->acc < 0) {
664 assert(src->type == P_CONST);
665 set_addr(e, pc->addr[src->index]);
666 }
667
668 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
669 }
670
671 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
672 static void
673 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
674 {
675 struct nv50_program_exec *e = exec(pc);
676
677 e->inst[0] = 0x10000000;
678 if (!pc->allow32)
679 set_long(pc, e);
680
681 set_dst(pc, dst, e);
682
683 if (!is_long(e) && src->type == P_IMMD) {
684 set_immd(pc, src, e);
685 /*XXX: 32-bit, but steals part of "half" reg space - need to
686 * catch and handle this case if/when we do half-regs
687 */
688 } else
689 if (src->type == P_IMMD || src->type == P_CONST) {
690 set_long(pc, e);
691 set_data(pc, src, 0x7f, 9, e);
692 e->inst[1] |= 0x20000000; /* mov from c[] */
693 } else {
694 if (src->type == P_ATTR) {
695 set_long(pc, e);
696 e->inst[1] |= 0x00200000;
697 }
698
699 alloc_reg(pc, src);
700 if (src->hw > 63)
701 set_long(pc, e);
702 e->inst[0] |= (src->hw << 9);
703 }
704
705 if (is_long(e) && !is_immd(e)) {
706 e->inst[1] |= 0x04000000; /* 32-bit */
707 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
708 if (!(e->inst[1] & 0x20000000))
709 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
710 } else
711 e->inst[0] |= 0x00008000;
712
713 emit(pc, e);
714 }
715
716 static INLINE void
717 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
718 {
719 struct nv50_reg *imm = alloc_immd(pc, f);
720 emit_mov(pc, dst, imm);
721 FREE(imm);
722 }
723
724 static void
725 emit_nop(struct nv50_pc *pc)
726 {
727 struct nv50_program_exec *e = exec(pc);
728
729 e->inst[0] = 0xf0000000;
730 set_long(pc, e);
731 e->inst[1] = 0xe0000000;
732 emit(pc, e);
733 }
734
735 static boolean
736 check_swap_src_0_1(struct nv50_pc *pc,
737 struct nv50_reg **s0, struct nv50_reg **s1)
738 {
739 struct nv50_reg *src0 = *s0, *src1 = *s1;
740
741 if (src0->type == P_CONST) {
742 if (src1->type != P_CONST) {
743 *s0 = src1;
744 *s1 = src0;
745 return TRUE;
746 }
747 } else
748 if (src1->type == P_ATTR) {
749 if (src0->type != P_ATTR) {
750 *s0 = src1;
751 *s1 = src0;
752 return TRUE;
753 }
754 }
755
756 return FALSE;
757 }
758
759 static void
760 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
761 struct nv50_program_exec *e)
762 {
763 struct nv50_reg *temp;
764
765 if (src->type != P_TEMP) {
766 temp = temp_temp(pc);
767 emit_mov(pc, temp, src);
768 src = temp;
769 }
770
771 alloc_reg(pc, src);
772 if (src->hw > 63)
773 set_long(pc, e);
774 e->inst[0] |= (src->hw << 9);
775 }
776
777 static void
778 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
779 {
780 if (src->type == P_ATTR) {
781 set_long(pc, e);
782 e->inst[1] |= 0x00200000;
783 } else
784 if (src->type == P_CONST || src->type == P_IMMD) {
785 struct nv50_reg *temp = temp_temp(pc);
786
787 emit_mov(pc, temp, src);
788 src = temp;
789 }
790
791 alloc_reg(pc, src);
792 if (src->hw > 63)
793 set_long(pc, e);
794 e->inst[0] |= (src->hw << 9);
795 }
796
797 static void
798 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
799 {
800 if (src->type == P_ATTR) {
801 struct nv50_reg *temp = temp_temp(pc);
802
803 emit_mov(pc, temp, src);
804 src = temp;
805 } else
806 if (src->type == P_CONST || src->type == P_IMMD) {
807 assert(!(e->inst[0] & 0x00800000));
808 if (e->inst[0] & 0x01000000) {
809 struct nv50_reg *temp = temp_temp(pc);
810
811 emit_mov(pc, temp, src);
812 src = temp;
813 } else {
814 set_data(pc, src, 0x7f, 16, e);
815 e->inst[0] |= 0x00800000;
816 }
817 }
818
819 alloc_reg(pc, src);
820 if (src->hw > 63)
821 set_long(pc, e);
822 e->inst[0] |= ((src->hw & 127) << 16);
823 }
824
825 static void
826 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
827 {
828 set_long(pc, e);
829
830 if (src->type == P_ATTR) {
831 struct nv50_reg *temp = temp_temp(pc);
832
833 emit_mov(pc, temp, src);
834 src = temp;
835 } else
836 if (src->type == P_CONST || src->type == P_IMMD) {
837 assert(!(e->inst[0] & 0x01000000));
838 if (e->inst[0] & 0x00800000) {
839 struct nv50_reg *temp = temp_temp(pc);
840
841 emit_mov(pc, temp, src);
842 src = temp;
843 } else {
844 set_data(pc, src, 0x7f, 32+14, e);
845 e->inst[0] |= 0x01000000;
846 }
847 }
848
849 alloc_reg(pc, src);
850 e->inst[1] |= ((src->hw & 127) << 14);
851 }
852
853 static void
854 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
855 {
856 struct nv50_program_exec *e = exec(pc);
857
858 assert(dst->type == P_TEMP);
859 e->inst[1] = 0x20000000 | (pred << 12);
860 set_long(pc, e);
861 set_dst(pc, dst, e);
862
863 emit(pc, e);
864 }
865
866 static void
867 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
868 {
869 struct nv50_program_exec *e = exec(pc);
870
871 e->inst[0] = 0x000001fc;
872 e->inst[1] = 0xa0000008;
873 set_long(pc, e);
874 set_pred_wr(pc, 1, pred, e);
875 set_src_0_restricted(pc, src, e);
876
877 emit(pc, e);
878 }
879
880 static void
881 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
882 struct nv50_reg *src1)
883 {
884 struct nv50_program_exec *e = exec(pc);
885
886 e->inst[0] |= 0xc0000000;
887
888 if (!pc->allow32)
889 set_long(pc, e);
890
891 check_swap_src_0_1(pc, &src0, &src1);
892 set_dst(pc, dst, e);
893 set_src_0(pc, src0, e);
894 if (src1->type == P_IMMD && !is_long(e)) {
895 if (src0->mod ^ src1->mod)
896 e->inst[0] |= 0x00008000;
897 set_immd(pc, src1, e);
898 } else {
899 set_src_1(pc, src1, e);
900 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
901 if (is_long(e))
902 e->inst[1] |= 0x08000000;
903 else
904 e->inst[0] |= 0x00008000;
905 }
906 }
907
908 emit(pc, e);
909 }
910
911 static void
912 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
913 struct nv50_reg *src0, struct nv50_reg *src1)
914 {
915 struct nv50_program_exec *e = exec(pc);
916
917 e->inst[0] = 0xb0000000;
918
919 alloc_reg(pc, src1);
920 check_swap_src_0_1(pc, &src0, &src1);
921
922 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
923 set_long(pc, e);
924 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
925 ((src1->mod & NV50_MOD_NEG) << 27);
926 }
927
928 set_dst(pc, dst, e);
929 set_src_0(pc, src0, e);
930 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
931 set_src_2(pc, src1, e);
932 else
933 if (src1->type == P_IMMD)
934 set_immd(pc, src1, e);
935 else
936 set_src_1(pc, src1, e);
937
938 emit(pc, e);
939 }
940
941 static void
942 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
943 uint8_t s)
944 {
945 struct nv50_program_exec *e = exec(pc);
946
947 set_long(pc, e);
948 e->inst[1] |= 0xc0000000;
949
950 e->inst[0] |= dst->hw << 2;
951 e->inst[0] |= s << 16; /* shift left */
952 set_src_0_restricted(pc, src, e);
953
954 emit(pc, e);
955 }
956
957 static void
958 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
959 struct nv50_reg *src0, struct nv50_reg *src1)
960 {
961 struct nv50_program_exec *e = exec(pc);
962
963 set_long(pc, e);
964 e->inst[0] |= 0xb0000000;
965 e->inst[1] |= (sub << 29);
966
967 check_swap_src_0_1(pc, &src0, &src1);
968 set_dst(pc, dst, e);
969 set_src_0(pc, src0, e);
970 set_src_1(pc, src1, e);
971
972 if (src0->mod & NV50_MOD_ABS)
973 e->inst[1] |= 0x00100000;
974 if (src1->mod & NV50_MOD_ABS)
975 e->inst[1] |= 0x00080000;
976
977 emit(pc, e);
978 }
979
980 static INLINE void
981 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
982 struct nv50_reg *src1)
983 {
984 src1->mod ^= NV50_MOD_NEG;
985 emit_add(pc, dst, src0, src1);
986 src1->mod ^= NV50_MOD_NEG;
987 }
988
989 static void
990 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
991 struct nv50_reg *src1, unsigned op)
992 {
993 struct nv50_program_exec *e = exec(pc);
994
995 e->inst[0] = 0xd0000000;
996 set_long(pc, e);
997
998 check_swap_src_0_1(pc, &src0, &src1);
999 set_dst(pc, dst, e);
1000 set_src_0(pc, src0, e);
1001
1002 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1003 op != TGSI_OPCODE_XOR)
1004 assert(!"invalid bit op");
1005
1006 assert(!(src0->mod | src1->mod));
1007
1008 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1009 set_immd(pc, src1, e);
1010 if (op == TGSI_OPCODE_OR)
1011 e->inst[0] |= 0x0100;
1012 else
1013 if (op == TGSI_OPCODE_XOR)
1014 e->inst[0] |= 0x8000;
1015 } else {
1016 set_src_1(pc, src1, e);
1017 e->inst[1] |= 0x04000000; /* 32 bit */
1018 if (op == TGSI_OPCODE_OR)
1019 e->inst[1] |= 0x4000;
1020 else
1021 if (op == TGSI_OPCODE_XOR)
1022 e->inst[1] |= 0x8000;
1023 }
1024
1025 emit(pc, e);
1026 }
1027
1028 static void
1029 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1030 struct nv50_reg *src1, struct nv50_reg *src2)
1031 {
1032 struct nv50_program_exec *e = exec(pc);
1033
1034 e->inst[0] |= 0xe0000000;
1035
1036 check_swap_src_0_1(pc, &src0, &src1);
1037 set_dst(pc, dst, e);
1038 set_src_0(pc, src0, e);
1039 set_src_1(pc, src1, e);
1040 set_src_2(pc, src2, e);
1041
1042 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1043 e->inst[1] |= 0x04000000;
1044 if (src2->mod & NV50_MOD_NEG)
1045 e->inst[1] |= 0x08000000;
1046
1047 emit(pc, e);
1048 }
1049
1050 static INLINE void
1051 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1052 struct nv50_reg *src1, struct nv50_reg *src2)
1053 {
1054 src2->mod ^= NV50_MOD_NEG;
1055 emit_mad(pc, dst, src0, src1, src2);
1056 src2->mod ^= NV50_MOD_NEG;
1057 }
1058
1059 #define NV50_FLOP_RCP 0
1060 #define NV50_FLOP_RSQ 2
1061 #define NV50_FLOP_LG2 3
1062 #define NV50_FLOP_SIN 4
1063 #define NV50_FLOP_COS 5
1064 #define NV50_FLOP_EX2 6
1065
1066 /* rcp, rsqrt, lg2 support neg and abs */
1067 static void
1068 emit_flop(struct nv50_pc *pc, unsigned sub,
1069 struct nv50_reg *dst, struct nv50_reg *src)
1070 {
1071 struct nv50_program_exec *e = exec(pc);
1072
1073 e->inst[0] |= 0x90000000;
1074 if (sub || src->mod) {
1075 set_long(pc, e);
1076 e->inst[1] |= (sub << 29);
1077 }
1078
1079 set_dst(pc, dst, e);
1080 set_src_0_restricted(pc, src, e);
1081
1082 assert(!src->mod || sub < 4);
1083
1084 if (src->mod & NV50_MOD_NEG)
1085 e->inst[1] |= 0x04000000;
1086 if (src->mod & NV50_MOD_ABS)
1087 e->inst[1] |= 0x00100000;
1088
1089 emit(pc, e);
1090 }
1091
1092 static void
1093 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1094 {
1095 struct nv50_program_exec *e = exec(pc);
1096
1097 e->inst[0] |= 0xb0000000;
1098
1099 set_dst(pc, dst, e);
1100 set_src_0(pc, src, e);
1101 set_long(pc, e);
1102 e->inst[1] |= (6 << 29) | 0x00004000;
1103
1104 if (src->mod & NV50_MOD_NEG)
1105 e->inst[1] |= 0x04000000;
1106 if (src->mod & NV50_MOD_ABS)
1107 e->inst[1] |= 0x00100000;
1108
1109 emit(pc, e);
1110 }
1111
1112 static void
1113 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1114 {
1115 struct nv50_program_exec *e = exec(pc);
1116
1117 e->inst[0] |= 0xb0000000;
1118
1119 set_dst(pc, dst, e);
1120 set_src_0(pc, src, e);
1121 set_long(pc, e);
1122 e->inst[1] |= (6 << 29);
1123
1124 if (src->mod & NV50_MOD_NEG)
1125 e->inst[1] |= 0x04000000;
1126 if (src->mod & NV50_MOD_ABS)
1127 e->inst[1] |= 0x00100000;
1128
1129 emit(pc, e);
1130 }
1131
1132 #define CVTOP_RN 0x01
1133 #define CVTOP_FLOOR 0x03
1134 #define CVTOP_CEIL 0x05
1135 #define CVTOP_TRUNC 0x07
1136 #define CVTOP_SAT 0x08
1137 #define CVTOP_ABS 0x10
1138
1139 /* 0x04 == 32 bit dst */
1140 /* 0x40 == dst is float */
1141 /* 0x80 == src is float */
1142 #define CVT_F32_F32 0xc4
1143 #define CVT_F32_S32 0x44
1144 #define CVT_S32_F32 0x8c
1145 #define CVT_S32_S32 0x0c
1146 #define CVT_NEG 0x20
1147 #define CVT_RI 0x08
1148
1149 static void
1150 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1151 int wp, unsigned cvn, unsigned fmt)
1152 {
1153 struct nv50_program_exec *e;
1154
1155 e = exec(pc);
1156 set_long(pc, e);
1157
1158 e->inst[0] |= 0xa0000000;
1159 e->inst[1] |= 0x00004000; /* 32 bit src */
1160 e->inst[1] |= (cvn << 16);
1161 e->inst[1] |= (fmt << 24);
1162 set_src_0(pc, src, e);
1163
1164 if (wp >= 0)
1165 set_pred_wr(pc, 1, wp, e);
1166
1167 if (dst)
1168 set_dst(pc, dst, e);
1169 else {
1170 e->inst[0] |= 0x000001fc;
1171 e->inst[1] |= 0x00000008;
1172 }
1173
1174 emit(pc, e);
1175 }
1176
1177 /* nv50 Condition codes:
1178 * 0x1 = LT
1179 * 0x2 = EQ
1180 * 0x3 = LE
1181 * 0x4 = GT
1182 * 0x5 = NE
1183 * 0x6 = GE
1184 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1185 * 0x8 = unordered bit (allows NaN)
1186 */
1187 static void
1188 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1189 struct nv50_reg *src0, struct nv50_reg *src1)
1190 {
1191 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1192
1193 struct nv50_program_exec *e = exec(pc);
1194 struct nv50_reg *rdst;
1195
1196 assert(ccode < 16);
1197 if (check_swap_src_0_1(pc, &src0, &src1))
1198 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1199
1200 rdst = dst;
1201 if (dst && dst->type != P_TEMP)
1202 dst = alloc_temp(pc, NULL);
1203
1204 /* set.u32 */
1205 set_long(pc, e);
1206 e->inst[0] |= 0xb0000000;
1207 e->inst[1] |= 0x60000000 | (ccode << 14);
1208
1209 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1210 * that doesn't seem to match what the hw actually does
1211 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1212 */
1213
1214 if (wp >= 0)
1215 set_pred_wr(pc, 1, wp, e);
1216 if (dst)
1217 set_dst(pc, dst, e);
1218 else {
1219 e->inst[0] |= 0x000001fc;
1220 e->inst[1] |= 0x00000008;
1221 }
1222
1223 set_src_0(pc, src0, e);
1224 set_src_1(pc, src1, e);
1225
1226 emit(pc, e);
1227
1228 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1229 if (rdst)
1230 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
1231 if (rdst && rdst != dst)
1232 free_temp(pc, dst);
1233 }
1234
1235 static INLINE unsigned
1236 map_tgsi_setop_cc(unsigned op)
1237 {
1238 switch (op) {
1239 case TGSI_OPCODE_SLT: return 0x1;
1240 case TGSI_OPCODE_SGE: return 0x6;
1241 case TGSI_OPCODE_SEQ: return 0x2;
1242 case TGSI_OPCODE_SGT: return 0x4;
1243 case TGSI_OPCODE_SLE: return 0x3;
1244 case TGSI_OPCODE_SNE: return 0xd;
1245 default:
1246 assert(0);
1247 return 0;
1248 }
1249 }
1250
1251 static INLINE void
1252 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1253 {
1254 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
1255 }
1256
1257 static void
1258 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1259 struct nv50_reg *v, struct nv50_reg *e)
1260 {
1261 struct nv50_reg *temp = alloc_temp(pc, NULL);
1262
1263 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1264 emit_mul(pc, temp, temp, e);
1265 emit_preex2(pc, temp, temp);
1266 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1267
1268 free_temp(pc, temp);
1269 }
1270
1271 static INLINE void
1272 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1273 {
1274 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
1275 }
1276
1277 static INLINE void
1278 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1279 {
1280 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
1281 }
1282
1283 static void
1284 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1285 struct nv50_reg **src)
1286 {
1287 struct nv50_reg *one = alloc_immd(pc, 1.0);
1288 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1289 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1290 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1291 struct nv50_reg *tmp[4];
1292 boolean allow32 = pc->allow32;
1293
1294 pc->allow32 = FALSE;
1295
1296 if (mask & (3 << 1)) {
1297 tmp[0] = alloc_temp(pc, NULL);
1298 emit_minmax(pc, 4, tmp[0], src[0], zero);
1299 }
1300
1301 if (mask & (1 << 2)) {
1302 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1303
1304 tmp[1] = temp_temp(pc);
1305 emit_minmax(pc, 4, tmp[1], src[1], zero);
1306
1307 tmp[3] = temp_temp(pc);
1308 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1309 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1310
1311 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1312 emit_mov(pc, dst[2], zero);
1313 set_pred(pc, 3, 0, pc->p->exec_tail);
1314 }
1315
1316 if (mask & (1 << 1))
1317 assimilate_temp(pc, dst[1], tmp[0]);
1318 else
1319 if (mask & (1 << 2))
1320 free_temp(pc, tmp[0]);
1321
1322 pc->allow32 = allow32;
1323
1324 /* do this last, in case src[i,j] == dst[0,3] */
1325 if (mask & (1 << 0))
1326 emit_mov(pc, dst[0], one);
1327
1328 if (mask & (1 << 3))
1329 emit_mov(pc, dst[3], one);
1330
1331 FREE(pos128);
1332 FREE(neg128);
1333 FREE(zero);
1334 FREE(one);
1335 }
1336
1337 static INLINE void
1338 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1339 {
1340 emit_cvt(pc, dst, src, -1, CVTOP_RN, CVT_F32_F32 | CVT_NEG);
1341 }
1342
1343 static void
1344 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1345 {
1346 struct nv50_program_exec *e;
1347 const int r_pred = 1;
1348
1349 e = exec(pc);
1350 e->inst[0] = 0x00000002; /* discard */
1351 set_long(pc, e); /* sets cond code to ALWAYS */
1352
1353 if (src) {
1354 unsigned cvn = CVT_F32_F32;
1355
1356 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1357
1358 if (src->mod & NV50_MOD_NEG)
1359 cvn |= CVT_NEG;
1360 /* write predicate reg */
1361 emit_cvt(pc, NULL, src, r_pred, CVTOP_RN, cvn);
1362 }
1363
1364 emit(pc, e);
1365 }
1366
1367 static struct nv50_program_exec *
1368 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1369 {
1370 struct nv50_program_exec *e = exec(pc);
1371
1372 e->inst[0] = (op << 28) | 2;
1373 set_long(pc, e);
1374 if (pred >= 0)
1375 set_pred(pc, cc, pred, e);
1376
1377 emit(pc, e);
1378 return e;
1379 }
1380
1381 static INLINE struct nv50_program_exec *
1382 emit_breakaddr(struct nv50_pc *pc)
1383 {
1384 return emit_control_flow(pc, 0x4, -1, 0);
1385 }
1386
1387 static INLINE void
1388 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1389 {
1390 emit_control_flow(pc, 0x5, pred, cc);
1391 }
1392
1393 static INLINE struct nv50_program_exec *
1394 emit_joinat(struct nv50_pc *pc)
1395 {
1396 return emit_control_flow(pc, 0xa, -1, 0);
1397 }
1398
1399 static INLINE struct nv50_program_exec *
1400 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1401 {
1402 return emit_control_flow(pc, 0x1, pred, cc);
1403 }
1404
1405 static INLINE struct nv50_program_exec *
1406 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1407 {
1408 return emit_control_flow(pc, 0x2, pred, cc);
1409 }
1410
1411 static INLINE void
1412 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1413 {
1414 emit_control_flow(pc, 0x3, pred, cc);
1415 }
1416
1417 #define QOP_ADD 0
1418 #define QOP_SUBR 1
1419 #define QOP_SUB 2
1420 #define QOP_MOV_SRC1 3
1421
1422 /* For a quad of threads / top left, top right, bottom left, bottom right
1423 * pixels, do a different operation, and take src0 from a specific thread.
1424 */
1425 static void
1426 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1427 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1428 {
1429 struct nv50_program_exec *e = exec(pc);
1430
1431 e->inst[0] = 0xc0000000;
1432 e->inst[1] = 0x80000000;
1433 set_long(pc, e);
1434 e->inst[0] |= lane_src0 << 16;
1435 set_src_0(pc, src0, e);
1436 set_src_2(pc, src1, e);
1437
1438 if (wp >= 0)
1439 set_pred_wr(pc, 1, wp, e);
1440
1441 if (dst)
1442 set_dst(pc, dst, e);
1443 else {
1444 e->inst[0] |= 0x000001fc;
1445 e->inst[1] |= 0x00000008;
1446 }
1447
1448 e->inst[0] |= (qop & 3) << 20;
1449 e->inst[1] |= (qop >> 2) << 22;
1450
1451 emit(pc, e);
1452 }
1453
1454 static void
1455 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1456 struct nv50_reg **src, unsigned arg, boolean proj)
1457 {
1458 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1459
1460 src[0]->mod |= NV50_MOD_ABS;
1461 src[1]->mod |= NV50_MOD_ABS;
1462 src[2]->mod |= NV50_MOD_ABS;
1463
1464 emit_minmax(pc, 4, t[2], src[0], src[1]);
1465 emit_minmax(pc, 4, t[2], src[2], t[2]);
1466
1467 src[0]->mod = mod[0];
1468 src[1]->mod = mod[1];
1469 src[2]->mod = mod[2];
1470
1471 if (proj && 0 /* looks more correct without this */)
1472 emit_mul(pc, t[2], t[2], src[3]);
1473 else
1474 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1475 emit_mov(pc, t[3], src[3]);
1476
1477 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1478
1479 emit_mul(pc, t[0], src[0], t[2]);
1480 emit_mul(pc, t[1], src[1], t[2]);
1481 emit_mul(pc, t[2], src[2], t[2]);
1482 }
1483
1484 static void
1485 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1486 struct nv50_reg **src, unsigned dim, unsigned arg)
1487 {
1488 unsigned c, mode;
1489
1490 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1491 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1492
1493 t[3]->rhw = src[3]->rhw;
1494 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1495 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1496
1497 for (c = 0; c < dim; ++c) {
1498 t[c]->rhw = src[c]->rhw;
1499 emit_interp(pc, t[c], t[3], mode);
1500 }
1501 if (arg != dim) { /* depth reference value */
1502 t[dim]->rhw = src[2]->rhw;
1503 emit_interp(pc, t[dim], t[3], mode);
1504 }
1505 } else {
1506 /* XXX: for some reason the blob sometimes uses MAD
1507 * (mad f32 $rX $rY $rZ neg $r63)
1508 */
1509 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1510 for (c = 0; c < dim; ++c)
1511 emit_mul(pc, t[c], src[c], t[3]);
1512 if (arg != dim) /* depth reference value */
1513 emit_mul(pc, t[dim], src[2], t[3]);
1514 }
1515 }
1516
1517 static INLINE void
1518 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1519 {
1520 switch (type) {
1521 case TGSI_TEXTURE_1D:
1522 *arg = *dim = 1;
1523 break;
1524 case TGSI_TEXTURE_SHADOW1D:
1525 *dim = 1;
1526 *arg = 2;
1527 break;
1528 case TGSI_TEXTURE_UNKNOWN:
1529 case TGSI_TEXTURE_2D:
1530 case TGSI_TEXTURE_RECT:
1531 *arg = *dim = 2;
1532 break;
1533 case TGSI_TEXTURE_SHADOW2D:
1534 case TGSI_TEXTURE_SHADOWRECT:
1535 *dim = 2;
1536 *arg = 3;
1537 break;
1538 case TGSI_TEXTURE_3D:
1539 case TGSI_TEXTURE_CUBE:
1540 *dim = *arg = 3;
1541 break;
1542 default:
1543 assert(0);
1544 break;
1545 }
1546 }
1547
1548 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1549 * different LOD values, so branch off groups of equal LOD.
1550 */
1551 static void
1552 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1553 struct nv50_reg *src, struct nv50_program_exec *tex)
1554 {
1555 struct nv50_program_exec *join_at;
1556 unsigned i, target = pc->p->exec_size + 7 * 2;
1557
1558 /* Subtract lod of each pixel from lod of top left pixel, jump
1559 * texlod insn if result is 0, then repeat for 2 other pixels.
1560 */
1561 join_at = emit_joinat(pc);
1562 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1563 emit_branch(pc, 0, 2)->param.index = target;
1564
1565 for (i = 1; i < 4; ++i) {
1566 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1567 emit_branch(pc, 0, 2)->param.index = target;
1568 }
1569
1570 emit_mov(pc, tlod, src); /* target */
1571 emit(pc, tex); /* texlod */
1572
1573 join_at->param.index = target + 2 * 2;
1574 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1575 }
1576
1577 static void
1578 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1579 struct nv50_program_exec *tex)
1580 {
1581 struct nv50_program_exec *e;
1582 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1583 int r_pred = 0;
1584 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1585
1586 pc->allow32 = FALSE;
1587 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1588
1589 /* Subtract bias value of thread i from bias values of each thread,
1590 * store result in r_pred, and set bit i in r_bits if result was 0.
1591 */
1592 assert(arg < 4);
1593 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1594 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1595 emit_mov(pc, r_bits, &imm_1248);
1596 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1597 }
1598 emit_mov_to_pred(pc, r_pred, r_bits);
1599
1600 /* The lanes of a quad are now grouped by the bit in r_pred they have
1601 * set. Put the input values for TEX into a new register set for each
1602 * group and execute TEX only for a specific group.
1603 * We cannot use the same register set for each group because we need
1604 * the derivatives, which are implicitly calculated, to be correct.
1605 */
1606 for (i = 1; i < 4; ++i) {
1607 alloc_temp4(pc, t123[i], 0);
1608
1609 for (c = 0; c <= arg; ++c)
1610 emit_mov(pc, t123[i][c], t[c]);
1611
1612 *(e = exec(pc)) = *(tex);
1613 e->inst[0] &= ~0x01fc;
1614 set_dst(pc, t123[i][0], e);
1615 set_pred(pc, cc[i], r_pred, e);
1616 emit(pc, e);
1617 }
1618 /* finally TEX on the original regs (where we kept the input) */
1619 set_pred(pc, cc[0], r_pred, tex);
1620 emit(pc, tex);
1621
1622 /* put the 3 * n other results into regs for lane 0 */
1623 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1624 for (i = 1; i < 4; ++i) {
1625 for (c = 0; c < n; ++c) {
1626 emit_mov(pc, t[c], t123[i][c]);
1627 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1628 }
1629 free_temp4(pc, t123[i]);
1630 }
1631
1632 emit_nop(pc);
1633 free_temp(pc, r_bits);
1634 }
1635
1636 static void
1637 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1638 struct nv50_reg **src, unsigned unit, unsigned type,
1639 boolean proj, int bias_lod)
1640 {
1641 struct nv50_reg *t[4];
1642 struct nv50_program_exec *e;
1643 unsigned c, dim, arg;
1644
1645 /* t[i] must be within a single 128 bit super-reg */
1646 alloc_temp4(pc, t, 0);
1647
1648 e = exec(pc);
1649 e->inst[0] = 0xf0000000;
1650 set_long(pc, e);
1651 set_dst(pc, t[0], e);
1652
1653 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1654 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1655
1656 /* live flag (don't set if TEX results affect input to another TEX): */
1657 /* e->inst[0] |= 0x00000004; */
1658
1659 get_tex_dim(type, &dim, &arg);
1660
1661 if (type == TGSI_TEXTURE_CUBE) {
1662 e->inst[0] |= 0x08000000;
1663 load_cube_tex_coords(pc, t, src, arg, proj);
1664 } else
1665 if (proj)
1666 load_proj_tex_coords(pc, t, src, dim, arg);
1667 else {
1668 for (c = 0; c < dim; c++)
1669 emit_mov(pc, t[c], src[c]);
1670 if (arg != dim) /* depth reference value (always src.z here) */
1671 emit_mov(pc, t[dim], src[2]);
1672 }
1673
1674 e->inst[0] |= (mask & 0x3) << 25;
1675 e->inst[1] |= (mask & 0xc) << 12;
1676
1677 if (!bias_lod) {
1678 e->inst[0] |= (arg - 1) << 22;
1679 emit(pc, e);
1680 } else
1681 if (bias_lod < 0) {
1682 e->inst[0] |= arg << 22;
1683 e->inst[1] |= 0x20000000; /* texbias */
1684 emit_mov(pc, t[arg], src[3]);
1685 emit_texbias_sequence(pc, t, arg, e);
1686 } else {
1687 e->inst[0] |= arg << 22;
1688 e->inst[1] |= 0x40000000; /* texlod */
1689 emit_mov(pc, t[arg], src[3]);
1690 emit_texlod_sequence(pc, t[arg], src[3], e);
1691 }
1692
1693 #if 1
1694 c = 0;
1695 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1696 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1697 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1698 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1699
1700 free_temp4(pc, t);
1701 #else
1702 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1703 * the texture coordinates, not the fetched values: latency ? */
1704
1705 for (c = 0; c < 4; c++) {
1706 if (mask & (1 << c))
1707 assimilate_temp(pc, dst[c], t[c]);
1708 else
1709 free_temp(pc, t[c]);
1710 }
1711 #endif
1712 }
1713
1714 static void
1715 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1716 {
1717 struct nv50_program_exec *e = exec(pc);
1718
1719 assert(src->type == P_TEMP);
1720
1721 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
1722 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
1723 set_long(pc, e);
1724 set_dst(pc, dst, e);
1725 set_src_0(pc, src, e);
1726 set_src_2(pc, src, e);
1727
1728 emit(pc, e);
1729 }
1730
1731 static void
1732 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1733 {
1734 struct nv50_program_exec *e = exec(pc);
1735
1736 assert(src->type == P_TEMP);
1737
1738 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
1739 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
1740 set_long(pc, e);
1741 set_dst(pc, dst, e);
1742 set_src_0(pc, src, e);
1743 set_src_2(pc, src, e);
1744
1745 emit(pc, e);
1746 }
1747
1748 static void
1749 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1750 {
1751 unsigned q = 0, m = ~0;
1752
1753 assert(!is_long(e));
1754
1755 switch (e->inst[0] >> 28) {
1756 case 0x1:
1757 /* MOV */
1758 q = 0x0403c000;
1759 m = 0xffff7fff;
1760 break;
1761 case 0x8:
1762 /* INTERP (move centroid, perspective and flat bits) */
1763 m = ~0x03000100;
1764 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1765 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1766 break;
1767 case 0x9:
1768 /* RCP */
1769 break;
1770 case 0xB:
1771 /* ADD */
1772 m = ~(127 << 16);
1773 q = ((e->inst[0] & (~m)) >> 2);
1774 break;
1775 case 0xC:
1776 /* MUL */
1777 m = ~0x00008000;
1778 q = ((e->inst[0] & (~m)) << 12);
1779 break;
1780 case 0xE:
1781 /* MAD (if src2 == dst) */
1782 q = ((e->inst[0] & 0x1fc) << 12);
1783 break;
1784 default:
1785 assert(0);
1786 break;
1787 }
1788
1789 set_long(pc, e);
1790 pc->p->exec_size++;
1791
1792 e->inst[0] &= m;
1793 e->inst[1] |= q;
1794 }
1795
1796 /* Some operations support an optional negation flag. */
1797 static boolean
1798 negate_supported(const struct tgsi_full_instruction *insn, int i)
1799 {
1800 switch (insn->Instruction.Opcode) {
1801 case TGSI_OPCODE_ADD:
1802 case TGSI_OPCODE_COS:
1803 case TGSI_OPCODE_DDX:
1804 case TGSI_OPCODE_DDY:
1805 case TGSI_OPCODE_DP3:
1806 case TGSI_OPCODE_DP4:
1807 case TGSI_OPCODE_EX2:
1808 case TGSI_OPCODE_KIL:
1809 case TGSI_OPCODE_LG2:
1810 case TGSI_OPCODE_MAD:
1811 case TGSI_OPCODE_MUL:
1812 case TGSI_OPCODE_POW:
1813 case TGSI_OPCODE_RCP:
1814 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
1815 case TGSI_OPCODE_SCS:
1816 case TGSI_OPCODE_SIN:
1817 case TGSI_OPCODE_SUB:
1818 return TRUE;
1819 default:
1820 return FALSE;
1821 }
1822 }
1823
1824 /* Return a read mask for source registers deduced from opcode & write mask. */
1825 static unsigned
1826 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1827 {
1828 unsigned x, mask = insn->Dst[0].Register.WriteMask;
1829
1830 switch (insn->Instruction.Opcode) {
1831 case TGSI_OPCODE_COS:
1832 case TGSI_OPCODE_SIN:
1833 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1834 case TGSI_OPCODE_DP3:
1835 return 0x7;
1836 case TGSI_OPCODE_DP4:
1837 case TGSI_OPCODE_DPH:
1838 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1839 return 0xf;
1840 case TGSI_OPCODE_DST:
1841 return mask & (c ? 0xa : 0x6);
1842 case TGSI_OPCODE_EX2:
1843 case TGSI_OPCODE_EXP:
1844 case TGSI_OPCODE_LG2:
1845 case TGSI_OPCODE_LOG:
1846 case TGSI_OPCODE_POW:
1847 case TGSI_OPCODE_RCP:
1848 case TGSI_OPCODE_RSQ:
1849 case TGSI_OPCODE_SCS:
1850 return 0x1;
1851 case TGSI_OPCODE_IF:
1852 return 0x1;
1853 case TGSI_OPCODE_LIT:
1854 return 0xb;
1855 case TGSI_OPCODE_TEX:
1856 case TGSI_OPCODE_TXB:
1857 case TGSI_OPCODE_TXL:
1858 case TGSI_OPCODE_TXP:
1859 {
1860 const struct tgsi_instruction_texture *tex;
1861
1862 assert(insn->Instruction.Texture);
1863 tex = &insn->Texture;
1864
1865 mask = 0x7;
1866 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
1867 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
1868 mask |= 0x8; /* bias, lod or proj */
1869
1870 switch (tex->Texture) {
1871 case TGSI_TEXTURE_1D:
1872 mask &= 0x9;
1873 break;
1874 case TGSI_TEXTURE_SHADOW1D:
1875 mask &= 0x5;
1876 break;
1877 case TGSI_TEXTURE_2D:
1878 mask &= 0xb;
1879 break;
1880 default:
1881 break;
1882 }
1883 }
1884 return mask;
1885 case TGSI_OPCODE_XPD:
1886 x = 0;
1887 if (mask & 1) x |= 0x6;
1888 if (mask & 2) x |= 0x5;
1889 if (mask & 4) x |= 0x3;
1890 return x;
1891 default:
1892 break;
1893 }
1894
1895 return mask;
1896 }
1897
1898 static struct nv50_reg *
1899 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1900 {
1901 switch (dst->Register.File) {
1902 case TGSI_FILE_TEMPORARY:
1903 return &pc->temp[dst->Register.Index * 4 + c];
1904 case TGSI_FILE_OUTPUT:
1905 return &pc->result[dst->Register.Index * 4 + c];
1906 case TGSI_FILE_ADDRESS:
1907 {
1908 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
1909 if (!r) {
1910 r = alloc_addr(pc, NULL);
1911 pc->addr[dst->Register.Index * 4 + c] = r;
1912 }
1913 assert(r);
1914 return r;
1915 }
1916 case TGSI_FILE_NULL:
1917 return NULL;
1918 default:
1919 break;
1920 }
1921
1922 return NULL;
1923 }
1924
1925 static struct nv50_reg *
1926 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1927 boolean neg)
1928 {
1929 struct nv50_reg *r = NULL;
1930 struct nv50_reg *temp;
1931 unsigned sgn, c, swz;
1932
1933 if (src->Register.File != TGSI_FILE_CONSTANT)
1934 assert(!src->Register.Indirect);
1935
1936 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1937
1938 c = tgsi_util_get_full_src_register_swizzle(src, chan);
1939 switch (c) {
1940 case TGSI_SWIZZLE_X:
1941 case TGSI_SWIZZLE_Y:
1942 case TGSI_SWIZZLE_Z:
1943 case TGSI_SWIZZLE_W:
1944 switch (src->Register.File) {
1945 case TGSI_FILE_INPUT:
1946 r = &pc->attr[src->Register.Index * 4 + c];
1947 break;
1948 case TGSI_FILE_TEMPORARY:
1949 r = &pc->temp[src->Register.Index * 4 + c];
1950 break;
1951 case TGSI_FILE_CONSTANT:
1952 if (!src->Register.Indirect) {
1953 r = &pc->param[src->Register.Index * 4 + c];
1954 break;
1955 }
1956 /* Indicate indirection by setting r->acc < 0 and
1957 * use the index field to select the address reg.
1958 */
1959 r = reg_instance(pc, NULL);
1960 swz = tgsi_util_get_src_register_swizzle(
1961 &src->Indirect, 0);
1962 ctor_reg(r, P_CONST,
1963 src->Indirect.Index * 4 + swz,
1964 src->Register.Index * 4 + c);
1965 r->acc = -1;
1966 break;
1967 case TGSI_FILE_IMMEDIATE:
1968 r = &pc->immd[src->Register.Index * 4 + c];
1969 break;
1970 case TGSI_FILE_SAMPLER:
1971 break;
1972 case TGSI_FILE_ADDRESS:
1973 r = pc->addr[src->Register.Index * 4 + c];
1974 assert(r);
1975 break;
1976 default:
1977 assert(0);
1978 break;
1979 }
1980 break;
1981 default:
1982 assert(0);
1983 break;
1984 }
1985
1986 switch (sgn) {
1987 case TGSI_UTIL_SIGN_KEEP:
1988 break;
1989 case TGSI_UTIL_SIGN_CLEAR:
1990 temp = temp_temp(pc);
1991 emit_abs(pc, temp, r);
1992 r = temp;
1993 break;
1994 case TGSI_UTIL_SIGN_TOGGLE:
1995 if (neg)
1996 r->mod = NV50_MOD_NEG;
1997 else {
1998 temp = temp_temp(pc);
1999 emit_neg(pc, temp, r);
2000 r = temp;
2001 }
2002 break;
2003 case TGSI_UTIL_SIGN_SET:
2004 temp = temp_temp(pc);
2005 emit_cvt(pc, temp, r, -1, CVTOP_ABS, CVT_F32_F32 | CVT_NEG);
2006 r = temp;
2007 break;
2008 default:
2009 assert(0);
2010 break;
2011 }
2012
2013 if (r && r->acc >= 0 && r != temp)
2014 return reg_instance(pc, r);
2015 return r;
2016 }
2017
2018 /* return TRUE for ops that produce only a single result */
2019 static boolean
2020 is_scalar_op(unsigned op)
2021 {
2022 switch (op) {
2023 case TGSI_OPCODE_COS:
2024 case TGSI_OPCODE_DP2:
2025 case TGSI_OPCODE_DP3:
2026 case TGSI_OPCODE_DP4:
2027 case TGSI_OPCODE_DPH:
2028 case TGSI_OPCODE_EX2:
2029 case TGSI_OPCODE_LG2:
2030 case TGSI_OPCODE_POW:
2031 case TGSI_OPCODE_RCP:
2032 case TGSI_OPCODE_RSQ:
2033 case TGSI_OPCODE_SIN:
2034 /*
2035 case TGSI_OPCODE_KIL:
2036 case TGSI_OPCODE_LIT:
2037 case TGSI_OPCODE_SCS:
2038 */
2039 return TRUE;
2040 default:
2041 return FALSE;
2042 }
2043 }
2044
2045 /* Returns a bitmask indicating which dst components depend
2046 * on source s, component c (reverse of nv50_tgsi_src_mask).
2047 */
2048 static unsigned
2049 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2050 {
2051 if (is_scalar_op(op))
2052 return 0x1;
2053
2054 switch (op) {
2055 case TGSI_OPCODE_DST:
2056 return (1 << c) & (s ? 0xa : 0x6);
2057 case TGSI_OPCODE_XPD:
2058 switch (c) {
2059 case 0: return 0x6;
2060 case 1: return 0x5;
2061 case 2: return 0x3;
2062 case 3: return 0x0;
2063 default:
2064 assert(0);
2065 return 0x0;
2066 }
2067 case TGSI_OPCODE_EXP:
2068 case TGSI_OPCODE_LOG:
2069 case TGSI_OPCODE_LIT:
2070 case TGSI_OPCODE_SCS:
2071 case TGSI_OPCODE_TEX:
2072 case TGSI_OPCODE_TXB:
2073 case TGSI_OPCODE_TXL:
2074 case TGSI_OPCODE_TXP:
2075 /* these take care of dangerous swizzles themselves */
2076 return 0x0;
2077 case TGSI_OPCODE_IF:
2078 case TGSI_OPCODE_KIL:
2079 /* don't call this function for these ops */
2080 assert(0);
2081 return 0;
2082 default:
2083 /* linear vector instruction */
2084 return (1 << c);
2085 }
2086 }
2087
2088 static INLINE boolean
2089 has_pred(struct nv50_program_exec *e, unsigned cc)
2090 {
2091 if (!is_long(e) || is_immd(e))
2092 return FALSE;
2093 return ((e->inst[1] & 0x780) == (cc << 7));
2094 }
2095
2096 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2097 * join_at ENDIF
2098 * @p0.eq bra ENDIF
2099 * single_op
2100 * ENDIF: nop.join
2101 */
2102 static boolean
2103 nv50_kill_branch(struct nv50_pc *pc)
2104 {
2105 int lvl = pc->if_lvl;
2106
2107 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2108 return FALSE;
2109
2110 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2111 * reg may no longer be valid, since we currently always use $p0
2112 */
2113 if (has_pred(pc->if_insn[lvl], 0xf))
2114 return FALSE;
2115 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2116
2117 /* We'll use the exec allocated for JOIN_AT (we can't easily
2118 * access nv50_program_exec's prev).
2119 */
2120 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2121
2122 *pc->if_join[lvl] = *pc->p->exec_tail;
2123
2124 FREE(pc->if_insn[lvl]);
2125 FREE(pc->p->exec_tail);
2126
2127 pc->p->exec_tail = pc->if_join[lvl];
2128 pc->p->exec_tail->next = NULL;
2129 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2130
2131 return TRUE;
2132 }
2133
2134 static void
2135 nv50_fp_move_results(struct nv50_pc *pc)
2136 {
2137 struct nv50_reg reg;
2138 unsigned i;
2139
2140 ctor_reg(&reg, P_TEMP, -1, -1);
2141
2142 for (i = 0; i < pc->result_nr * 4; ++i) {
2143 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2144 continue;
2145 if (pc->result[i].rhw != pc->result[i].hw) {
2146 reg.hw = pc->result[i].rhw;
2147 emit_mov(pc, &reg, &pc->result[i]);
2148 }
2149 }
2150 }
2151
2152 static boolean
2153 nv50_program_tx_insn(struct nv50_pc *pc,
2154 const struct tgsi_full_instruction *inst)
2155 {
2156 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2157 unsigned mask, sat, unit;
2158 int i, c;
2159
2160 mask = inst->Dst[0].Register.WriteMask;
2161 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2162
2163 memset(src, 0, sizeof(src));
2164
2165 for (c = 0; c < 4; c++) {
2166 if ((mask & (1 << c)) && !pc->r_dst[c])
2167 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2168 else
2169 dst[c] = pc->r_dst[c];
2170 rdst[c] = dst[c];
2171 }
2172
2173 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2174 const struct tgsi_full_src_register *fs = &inst->Src[i];
2175 unsigned src_mask;
2176 boolean neg_supp;
2177
2178 src_mask = nv50_tgsi_src_mask(inst, i);
2179 neg_supp = negate_supported(inst, i);
2180
2181 if (fs->Register.File == TGSI_FILE_SAMPLER)
2182 unit = fs->Register.Index;
2183
2184 for (c = 0; c < 4; c++)
2185 if (src_mask & (1 << c))
2186 src[i][c] = tgsi_src(pc, c, fs, neg_supp);
2187 }
2188
2189 brdc = temp = pc->r_brdc;
2190 if (brdc && brdc->type != P_TEMP) {
2191 temp = temp_temp(pc);
2192 if (sat)
2193 brdc = temp;
2194 } else
2195 if (sat) {
2196 for (c = 0; c < 4; c++) {
2197 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2198 continue;
2199 /* rdst[c] = dst[c]; */ /* done above */
2200 dst[c] = temp_temp(pc);
2201 }
2202 }
2203
2204 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2205
2206 switch (inst->Instruction.Opcode) {
2207 case TGSI_OPCODE_ABS:
2208 for (c = 0; c < 4; c++) {
2209 if (!(mask & (1 << c)))
2210 continue;
2211 emit_abs(pc, dst[c], src[0][c]);
2212 }
2213 break;
2214 case TGSI_OPCODE_ADD:
2215 for (c = 0; c < 4; c++) {
2216 if (!(mask & (1 << c)))
2217 continue;
2218 emit_add(pc, dst[c], src[0][c], src[1][c]);
2219 }
2220 break;
2221 case TGSI_OPCODE_AND:
2222 case TGSI_OPCODE_XOR:
2223 case TGSI_OPCODE_OR:
2224 for (c = 0; c < 4; c++) {
2225 if (!(mask & (1 << c)))
2226 continue;
2227 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2228 inst->Instruction.Opcode);
2229 }
2230 break;
2231 case TGSI_OPCODE_ARL:
2232 assert(src[0][0]);
2233 temp = temp_temp(pc);
2234 emit_cvt(pc, temp, src[0][0], -1, CVTOP_FLOOR, CVT_S32_F32);
2235 emit_arl(pc, dst[0], temp, 4);
2236 break;
2237 case TGSI_OPCODE_BGNLOOP:
2238 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2239 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2240 terminate_mbb(pc);
2241 break;
2242 case TGSI_OPCODE_BGNSUB:
2243 assert(!pc->in_subroutine);
2244 pc->in_subroutine = TRUE;
2245 /* probably not necessary, but align to 8 byte boundary */
2246 if (!is_long(pc->p->exec_tail))
2247 convert_to_long(pc, pc->p->exec_tail);
2248 break;
2249 case TGSI_OPCODE_BRK:
2250 assert(pc->loop_lvl > 0);
2251 emit_break(pc, -1, 0);
2252 break;
2253 case TGSI_OPCODE_CAL:
2254 assert(inst->Label.Label < pc->insn_nr);
2255 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2256 /* replaced by actual offset in nv50_program_fixup_insns */
2257 break;
2258 case TGSI_OPCODE_CEIL:
2259 for (c = 0; c < 4; c++) {
2260 if (!(mask & (1 << c)))
2261 continue;
2262 emit_cvt(pc, dst[c], src[0][c], -1,
2263 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
2264 }
2265 break;
2266 case TGSI_OPCODE_CMP:
2267 pc->allow32 = FALSE;
2268 for (c = 0; c < 4; c++) {
2269 if (!(mask & (1 << c)))
2270 continue;
2271 emit_cvt(pc, NULL, src[0][c], 1, CVTOP_RN, CVT_F32_F32);
2272 emit_mov(pc, dst[c], src[1][c]);
2273 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2274 emit_mov(pc, dst[c], src[2][c]);
2275 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2276 }
2277 break;
2278 case TGSI_OPCODE_CONT:
2279 assert(pc->loop_lvl > 0);
2280 emit_branch(pc, -1, 0)->param.index =
2281 pc->loop_pos[pc->loop_lvl - 1];
2282 break;
2283 case TGSI_OPCODE_COS:
2284 if (mask & 8) {
2285 emit_precossin(pc, temp, src[0][3]);
2286 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2287 if (!(mask &= 7))
2288 break;
2289 if (temp == dst[3])
2290 temp = brdc = temp_temp(pc);
2291 }
2292 emit_precossin(pc, temp, src[0][0]);
2293 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2294 break;
2295 case TGSI_OPCODE_DDX:
2296 for (c = 0; c < 4; c++) {
2297 if (!(mask & (1 << c)))
2298 continue;
2299 emit_ddx(pc, dst[c], src[0][c]);
2300 }
2301 break;
2302 case TGSI_OPCODE_DDY:
2303 for (c = 0; c < 4; c++) {
2304 if (!(mask & (1 << c)))
2305 continue;
2306 emit_ddy(pc, dst[c], src[0][c]);
2307 }
2308 break;
2309 case TGSI_OPCODE_DP3:
2310 emit_mul(pc, temp, src[0][0], src[1][0]);
2311 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2312 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2313 break;
2314 case TGSI_OPCODE_DP4:
2315 emit_mul(pc, temp, src[0][0], src[1][0]);
2316 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2317 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2318 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2319 break;
2320 case TGSI_OPCODE_DPH:
2321 emit_mul(pc, temp, src[0][0], src[1][0]);
2322 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2323 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2324 emit_add(pc, brdc, src[1][3], temp);
2325 break;
2326 case TGSI_OPCODE_DST:
2327 if (mask & (1 << 1))
2328 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2329 if (mask & (1 << 2))
2330 emit_mov(pc, dst[2], src[0][2]);
2331 if (mask & (1 << 3))
2332 emit_mov(pc, dst[3], src[1][3]);
2333 if (mask & (1 << 0))
2334 emit_mov_immdval(pc, dst[0], 1.0f);
2335 break;
2336 case TGSI_OPCODE_ELSE:
2337 emit_branch(pc, -1, 0);
2338 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2339 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2340 terminate_mbb(pc);
2341 break;
2342 case TGSI_OPCODE_ENDIF:
2343 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2344
2345 /* try to replace branch over 1 insn with a predicated insn */
2346 if (nv50_kill_branch(pc) == TRUE)
2347 break;
2348
2349 if (pc->if_join[pc->if_lvl]) {
2350 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2351 pc->if_join[pc->if_lvl] = NULL;
2352 }
2353 terminate_mbb(pc);
2354 /* emit a NOP as join point, we could set it on the next
2355 * one, but would have to make sure it is long and !immd
2356 */
2357 JOIN_ON(emit_nop(pc));
2358 break;
2359 case TGSI_OPCODE_ENDLOOP:
2360 emit_branch(pc, -1, 0)->param.index =
2361 pc->loop_pos[--pc->loop_lvl];
2362 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2363 terminate_mbb(pc);
2364 break;
2365 case TGSI_OPCODE_ENDSUB:
2366 assert(pc->in_subroutine);
2367 pc->in_subroutine = FALSE;
2368 break;
2369 case TGSI_OPCODE_EX2:
2370 emit_preex2(pc, temp, src[0][0]);
2371 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2372 break;
2373 case TGSI_OPCODE_EXP:
2374 {
2375 struct nv50_reg *t[2];
2376
2377 assert(!temp);
2378 t[0] = temp_temp(pc);
2379 t[1] = temp_temp(pc);
2380
2381 if (mask & 0x6)
2382 emit_mov(pc, t[0], src[0][0]);
2383 if (mask & 0x3)
2384 emit_flr(pc, t[1], src[0][0]);
2385
2386 if (mask & (1 << 1))
2387 emit_sub(pc, dst[1], t[0], t[1]);
2388 if (mask & (1 << 0)) {
2389 emit_preex2(pc, t[1], t[1]);
2390 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2391 }
2392 if (mask & (1 << 2)) {
2393 emit_preex2(pc, t[0], t[0]);
2394 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2395 }
2396 if (mask & (1 << 3))
2397 emit_mov_immdval(pc, dst[3], 1.0f);
2398 }
2399 break;
2400 case TGSI_OPCODE_FLR:
2401 for (c = 0; c < 4; c++) {
2402 if (!(mask & (1 << c)))
2403 continue;
2404 emit_flr(pc, dst[c], src[0][c]);
2405 }
2406 break;
2407 case TGSI_OPCODE_FRC:
2408 temp = temp_temp(pc);
2409 for (c = 0; c < 4; c++) {
2410 if (!(mask & (1 << c)))
2411 continue;
2412 emit_flr(pc, temp, src[0][c]);
2413 emit_sub(pc, dst[c], src[0][c], temp);
2414 }
2415 break;
2416 case TGSI_OPCODE_IF:
2417 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2418 emit_cvt(pc, NULL, src[0][0], 0, CVTOP_ABS | CVTOP_RN,
2419 CVT_F32_F32);
2420 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2421 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2422 terminate_mbb(pc);
2423 break;
2424 case TGSI_OPCODE_KIL:
2425 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2426 emit_kil(pc, src[0][0]);
2427 emit_kil(pc, src[0][1]);
2428 emit_kil(pc, src[0][2]);
2429 emit_kil(pc, src[0][3]);
2430 break;
2431 case TGSI_OPCODE_KILP:
2432 emit_kil(pc, NULL);
2433 break;
2434 case TGSI_OPCODE_LIT:
2435 emit_lit(pc, &dst[0], mask, &src[0][0]);
2436 break;
2437 case TGSI_OPCODE_LG2:
2438 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2439 break;
2440 case TGSI_OPCODE_LOG:
2441 {
2442 struct nv50_reg *t[2];
2443
2444 t[0] = temp_temp(pc);
2445 if (mask & (1 << 1))
2446 t[1] = temp_temp(pc);
2447 else
2448 t[1] = t[0];
2449
2450 emit_abs(pc, t[0], src[0][0]);
2451 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2452 if (mask & (1 << 2))
2453 emit_mov(pc, dst[2], t[1]);
2454 emit_flr(pc, t[1], t[1]);
2455 if (mask & (1 << 0))
2456 emit_mov(pc, dst[0], t[1]);
2457 if (mask & (1 << 1)) {
2458 t[1]->mod = NV50_MOD_NEG;
2459 emit_preex2(pc, t[1], t[1]);
2460 t[1]->mod = 0;
2461 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2462 emit_mul(pc, dst[1], t[0], t[1]);
2463 }
2464 if (mask & (1 << 3))
2465 emit_mov_immdval(pc, dst[3], 1.0f);
2466 }
2467 break;
2468 case TGSI_OPCODE_LRP:
2469 temp = temp_temp(pc);
2470 for (c = 0; c < 4; c++) {
2471 if (!(mask & (1 << c)))
2472 continue;
2473 emit_sub(pc, temp, src[1][c], src[2][c]);
2474 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2475 }
2476 break;
2477 case TGSI_OPCODE_MAD:
2478 for (c = 0; c < 4; c++) {
2479 if (!(mask & (1 << c)))
2480 continue;
2481 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2482 }
2483 break;
2484 case TGSI_OPCODE_MAX:
2485 for (c = 0; c < 4; c++) {
2486 if (!(mask & (1 << c)))
2487 continue;
2488 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
2489 }
2490 break;
2491 case TGSI_OPCODE_MIN:
2492 for (c = 0; c < 4; c++) {
2493 if (!(mask & (1 << c)))
2494 continue;
2495 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
2496 }
2497 break;
2498 case TGSI_OPCODE_MOV:
2499 for (c = 0; c < 4; c++) {
2500 if (!(mask & (1 << c)))
2501 continue;
2502 emit_mov(pc, dst[c], src[0][c]);
2503 }
2504 break;
2505 case TGSI_OPCODE_MUL:
2506 for (c = 0; c < 4; c++) {
2507 if (!(mask & (1 << c)))
2508 continue;
2509 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2510 }
2511 break;
2512 case TGSI_OPCODE_POW:
2513 emit_pow(pc, brdc, src[0][0], src[1][0]);
2514 break;
2515 case TGSI_OPCODE_RCP:
2516 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2517 break;
2518 case TGSI_OPCODE_RET:
2519 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2520 nv50_fp_move_results(pc);
2521 emit_ret(pc, -1, 0);
2522 break;
2523 case TGSI_OPCODE_RSQ:
2524 src[0][0]->mod |= NV50_MOD_ABS;
2525 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2526 break;
2527 case TGSI_OPCODE_SCS:
2528 temp = temp_temp(pc);
2529 if (mask & 3)
2530 emit_precossin(pc, temp, src[0][0]);
2531 if (mask & (1 << 0))
2532 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
2533 if (mask & (1 << 1))
2534 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
2535 if (mask & (1 << 2))
2536 emit_mov_immdval(pc, dst[2], 0.0);
2537 if (mask & (1 << 3))
2538 emit_mov_immdval(pc, dst[3], 1.0);
2539 break;
2540 case TGSI_OPCODE_SIN:
2541 if (mask & 8) {
2542 emit_precossin(pc, temp, src[0][3]);
2543 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
2544 if (!(mask &= 7))
2545 break;
2546 if (temp == dst[3])
2547 temp = brdc = temp_temp(pc);
2548 }
2549 emit_precossin(pc, temp, src[0][0]);
2550 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
2551 break;
2552 case TGSI_OPCODE_SLT:
2553 case TGSI_OPCODE_SGE:
2554 case TGSI_OPCODE_SEQ:
2555 case TGSI_OPCODE_SGT:
2556 case TGSI_OPCODE_SLE:
2557 case TGSI_OPCODE_SNE:
2558 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
2559 for (c = 0; c < 4; c++) {
2560 if (!(mask & (1 << c)))
2561 continue;
2562 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
2563 }
2564 break;
2565 case TGSI_OPCODE_SUB:
2566 for (c = 0; c < 4; c++) {
2567 if (!(mask & (1 << c)))
2568 continue;
2569 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2570 }
2571 break;
2572 case TGSI_OPCODE_TEX:
2573 emit_tex(pc, dst, mask, src[0], unit,
2574 inst->Texture.Texture, FALSE, 0);
2575 break;
2576 case TGSI_OPCODE_TXB:
2577 emit_tex(pc, dst, mask, src[0], unit,
2578 inst->Texture.Texture, FALSE, -1);
2579 break;
2580 case TGSI_OPCODE_TXL:
2581 emit_tex(pc, dst, mask, src[0], unit,
2582 inst->Texture.Texture, FALSE, 1);
2583 break;
2584 case TGSI_OPCODE_TXP:
2585 emit_tex(pc, dst, mask, src[0], unit,
2586 inst->Texture.Texture, TRUE, 0);
2587 break;
2588 case TGSI_OPCODE_TRUNC:
2589 for (c = 0; c < 4; c++) {
2590 if (!(mask & (1 << c)))
2591 continue;
2592 emit_cvt(pc, dst[c], src[0][c], -1,
2593 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
2594 }
2595 break;
2596 case TGSI_OPCODE_XPD:
2597 temp = temp_temp(pc);
2598 if (mask & (1 << 0)) {
2599 emit_mul(pc, temp, src[0][2], src[1][1]);
2600 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2601 }
2602 if (mask & (1 << 1)) {
2603 emit_mul(pc, temp, src[0][0], src[1][2]);
2604 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2605 }
2606 if (mask & (1 << 2)) {
2607 emit_mul(pc, temp, src[0][1], src[1][0]);
2608 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2609 }
2610 if (mask & (1 << 3))
2611 emit_mov_immdval(pc, dst[3], 1.0);
2612 break;
2613 case TGSI_OPCODE_END:
2614 if (pc->p->type == PIPE_SHADER_FRAGMENT)
2615 nv50_fp_move_results(pc);
2616
2617 /* last insn must be long so it can have the exit bit set */
2618 if (!is_long(pc->p->exec_tail))
2619 convert_to_long(pc, pc->p->exec_tail);
2620 else
2621 if (is_immd(pc->p->exec_tail) || is_join(pc->p->exec_tail))
2622 emit_nop(pc);
2623
2624 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
2625 break;
2626 default:
2627 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2628 return FALSE;
2629 }
2630
2631 if (brdc) {
2632 if (sat)
2633 emit_sat(pc, brdc, brdc);
2634 for (c = 0; c < 4; c++)
2635 if ((mask & (1 << c)) && dst[c] != brdc)
2636 emit_mov(pc, dst[c], brdc);
2637 } else
2638 if (sat) {
2639 for (c = 0; c < 4; c++) {
2640 if (!(mask & (1 << c)))
2641 continue;
2642 /* In this case we saturate later, and dst[c] won't
2643 * be another temp_temp (and thus lost), since rdst
2644 * already is TEMP (see above). */
2645 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2646 continue;
2647 emit_sat(pc, rdst[c], dst[c]);
2648 }
2649 }
2650
2651 kill_temp_temp(pc);
2652 pc->reg_instance_nr = 0;
2653
2654 return TRUE;
2655 }
2656
2657 static void
2658 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2659 {
2660 struct nv50_reg *reg = NULL;
2661 const struct tgsi_full_src_register *src;
2662 const struct tgsi_dst_register *dst;
2663 unsigned i, c, k, mask;
2664
2665 dst = &insn->Dst[0].Register;
2666 mask = dst->WriteMask;
2667
2668 if (dst->File == TGSI_FILE_TEMPORARY)
2669 reg = pc->temp;
2670 else
2671 if (dst->File == TGSI_FILE_OUTPUT) {
2672 reg = pc->result;
2673
2674 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
2675 dst->Index == pc->edgeflag_out &&
2676 insn->Src[0].Register.File == TGSI_FILE_INPUT)
2677 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
2678 }
2679
2680 if (reg) {
2681 for (c = 0; c < 4; c++) {
2682 if (!(mask & (1 << c)))
2683 continue;
2684 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2685 }
2686 }
2687
2688 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2689 src = &insn->Src[i];
2690
2691 if (src->Register.File == TGSI_FILE_TEMPORARY)
2692 reg = pc->temp;
2693 else
2694 if (src->Register.File == TGSI_FILE_INPUT)
2695 reg = pc->attr;
2696 else
2697 continue;
2698
2699 mask = nv50_tgsi_src_mask(insn, i);
2700
2701 for (c = 0; c < 4; c++) {
2702 if (!(mask & (1 << c)))
2703 continue;
2704 k = tgsi_util_get_full_src_register_swizzle(src, c);
2705
2706 reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
2707 }
2708 }
2709 }
2710
2711 /* Returns a bitmask indicating which dst components need to be
2712 * written to temporaries first to avoid 'corrupting' sources.
2713 *
2714 * m[i] (out) indicate component to write in the i-th position
2715 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2716 */
2717 static unsigned
2718 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2719 {
2720 unsigned i, c, x, unsafe;
2721
2722 for (c = 0; c < 4; c++)
2723 m[c] = c;
2724
2725 /* Swap as long as a dst component written earlier is depended on
2726 * by one written later, but the next one isn't depended on by it.
2727 */
2728 for (c = 0; c < 3; c++) {
2729 if (rdep[m[c + 1]] & (1 << m[c]))
2730 continue; /* if next one is depended on by us */
2731 for (i = c + 1; i < 4; i++)
2732 /* if we are depended on by a later one */
2733 if (rdep[m[c]] & (1 << m[i]))
2734 break;
2735 if (i == 4)
2736 continue;
2737 /* now, swap */
2738 x = m[c];
2739 m[c] = m[c + 1];
2740 m[c + 1] = x;
2741
2742 /* restart */
2743 c = 0;
2744 }
2745
2746 /* mark dependencies that could not be resolved by reordering */
2747 for (i = 0; i < 3; ++i)
2748 for (c = i + 1; c < 4; ++c)
2749 if (rdep[m[i]] & (1 << m[c]))
2750 unsafe |= (1 << i);
2751
2752 /* NOTE: $unsafe is with respect to order, not component */
2753 return unsafe;
2754 }
2755
2756 /* Select a suitable dst register for broadcasting scalar results,
2757 * or return NULL if we have to allocate an extra TEMP.
2758 *
2759 * If e.g. only 1 component is written, we may also emit the final
2760 * result to a write-only register.
2761 */
2762 static struct nv50_reg *
2763 tgsi_broadcast_dst(struct nv50_pc *pc,
2764 const struct tgsi_full_dst_register *fd, unsigned mask)
2765 {
2766 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
2767 int c = ffs(~mask & fd->Register.WriteMask);
2768 if (c)
2769 return tgsi_dst(pc, c - 1, fd);
2770 } else {
2771 int c = ffs(fd->Register.WriteMask) - 1;
2772 if ((1 << c) == fd->Register.WriteMask)
2773 return tgsi_dst(pc, c, fd);
2774 }
2775
2776 return NULL;
2777 }
2778
2779 /* Scan source swizzles and return a bitmask indicating dst regs that
2780 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2781 */
2782 static unsigned
2783 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2784 unsigned rdep[4])
2785 {
2786 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
2787 const struct tgsi_full_src_register *fs;
2788 unsigned i, deqs = 0;
2789
2790 for (i = 0; i < 4; ++i)
2791 rdep[i] = 0;
2792
2793 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2794 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2795 boolean neg_supp = negate_supported(insn, i);
2796
2797 fs = &insn->Src[i];
2798 if (fs->Register.File != fd->Register.File ||
2799 fs->Register.Index != fd->Register.Index)
2800 continue;
2801
2802 for (chn = 0; chn < 4; ++chn) {
2803 unsigned s, c;
2804
2805 if (!(mask & (1 << chn))) /* src is not read */
2806 continue;
2807 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2808 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2809
2810 if (!(fd->Register.WriteMask & (1 << c)))
2811 continue;
2812
2813 /* no danger if src is copied to TEMP first */
2814 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2815 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2816 continue;
2817
2818 rdep[c] |= nv50_tgsi_dst_revdep(
2819 insn->Instruction.Opcode, i, chn);
2820 deqs |= (1 << c);
2821 }
2822 }
2823
2824 return deqs;
2825 }
2826
2827 static boolean
2828 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2829 {
2830 struct tgsi_full_instruction insn = tok->FullInstruction;
2831 const struct tgsi_full_dst_register *fd;
2832 unsigned i, deqs, rdep[4], m[4];
2833
2834 fd = &tok->FullInstruction.Dst[0];
2835 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2836
2837 if (is_scalar_op(insn.Instruction.Opcode)) {
2838 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2839 if (!pc->r_brdc)
2840 pc->r_brdc = temp_temp(pc);
2841 return nv50_program_tx_insn(pc, &insn);
2842 }
2843 pc->r_brdc = NULL;
2844
2845 if (!deqs)
2846 return nv50_program_tx_insn(pc, &insn);
2847
2848 deqs = nv50_revdep_reorder(m, rdep);
2849
2850 for (i = 0; i < 4; ++i) {
2851 assert(pc->r_dst[m[i]] == NULL);
2852
2853 insn.Dst[0].Register.WriteMask =
2854 fd->Register.WriteMask & (1 << m[i]);
2855
2856 if (!insn.Dst[0].Register.WriteMask)
2857 continue;
2858
2859 if (deqs & (1 << i))
2860 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2861
2862 if (!nv50_program_tx_insn(pc, &insn))
2863 return FALSE;
2864 }
2865
2866 for (i = 0; i < 4; i++) {
2867 struct nv50_reg *reg = pc->r_dst[i];
2868 if (!reg)
2869 continue;
2870 pc->r_dst[i] = NULL;
2871
2872 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2873 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2874 else
2875 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2876 free_temp(pc, reg);
2877 }
2878
2879 return TRUE;
2880 }
2881
2882 static void
2883 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2884 {
2885 struct nv50_reg *iv, **ppiv;
2886 unsigned mode = pc->interp_mode[reg->index];
2887
2888 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2889 iv = *ppiv;
2890
2891 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2892 iv = *ppiv = alloc_temp(pc, NULL);
2893 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2894
2895 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2896 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
2897
2898 /* XXX: when loading interpolants dynamically, move these
2899 * to the program head, or make sure it can't be skipped.
2900 */
2901 }
2902
2903 emit_interp(pc, reg, iv, mode);
2904 }
2905
2906 /* The face input is always at v[255] (varying space), with a
2907 * value of 0 for back-facing, and 0xffffffff for front-facing.
2908 */
2909 static void
2910 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
2911 {
2912 struct nv50_reg *one = alloc_immd(pc, 1.0f);
2913
2914 assert(a->rhw == -1);
2915 alloc_reg(pc, a); /* do this before rhw is set */
2916 a->rhw = 255;
2917 load_interpolant(pc, a);
2918 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
2919
2920 FREE(one);
2921 }
2922
2923 static boolean
2924 nv50_program_tx_prep(struct nv50_pc *pc)
2925 {
2926 struct tgsi_parse_context tp;
2927 struct nv50_program *p = pc->p;
2928 boolean ret = FALSE;
2929 unsigned i, c, flat_nr = 0;
2930
2931 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2932 while (!tgsi_parse_end_of_tokens(&tp)) {
2933 const union tgsi_full_token *tok = &tp.FullToken;
2934
2935 tgsi_parse_token(&tp);
2936 switch (tok->Token.Type) {
2937 case TGSI_TOKEN_TYPE_IMMEDIATE:
2938 {
2939 const struct tgsi_full_immediate *imm =
2940 &tp.FullToken.FullImmediate;
2941
2942 ctor_immd_4f32(pc, imm->u[0].Float,
2943 imm->u[1].Float,
2944 imm->u[2].Float,
2945 imm->u[3].Float);
2946 }
2947 break;
2948 case TGSI_TOKEN_TYPE_DECLARATION:
2949 {
2950 const struct tgsi_full_declaration *d;
2951 unsigned si, last, first, mode;
2952
2953 d = &tp.FullToken.FullDeclaration;
2954 first = d->Range.First;
2955 last = d->Range.Last;
2956
2957 switch (d->Declaration.File) {
2958 case TGSI_FILE_TEMPORARY:
2959 break;
2960 case TGSI_FILE_OUTPUT:
2961 if (!d->Declaration.Semantic ||
2962 p->type == PIPE_SHADER_FRAGMENT)
2963 break;
2964
2965 si = d->Semantic.Index;
2966 switch (d->Semantic.Name) {
2967 case TGSI_SEMANTIC_BCOLOR:
2968 p->cfg.two_side[si].hw = first;
2969 if (p->cfg.io_nr > first)
2970 p->cfg.io_nr = first;
2971 break;
2972 case TGSI_SEMANTIC_PSIZE:
2973 p->cfg.psiz = first;
2974 if (p->cfg.io_nr > first)
2975 p->cfg.io_nr = first;
2976 break;
2977 case TGSI_SEMANTIC_EDGEFLAG:
2978 pc->edgeflag_out = first;
2979 break;
2980 /*
2981 case TGSI_SEMANTIC_CLIP_DISTANCE:
2982 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2983 break;
2984 */
2985 default:
2986 break;
2987 }
2988 break;
2989 case TGSI_FILE_INPUT:
2990 {
2991 if (p->type != PIPE_SHADER_FRAGMENT)
2992 break;
2993
2994 switch (d->Declaration.Interpolate) {
2995 case TGSI_INTERPOLATE_CONSTANT:
2996 mode = INTERP_FLAT;
2997 flat_nr++;
2998 break;
2999 case TGSI_INTERPOLATE_PERSPECTIVE:
3000 mode = INTERP_PERSPECTIVE;
3001 p->cfg.regs[1] |= 0x08 << 24;
3002 break;
3003 default:
3004 mode = INTERP_LINEAR;
3005 break;
3006 }
3007 if (d->Declaration.Centroid)
3008 mode |= INTERP_CENTROID;
3009
3010 assert(last < 32);
3011 for (i = first; i <= last; i++)
3012 pc->interp_mode[i] = mode;
3013 }
3014 break;
3015 case TGSI_FILE_ADDRESS:
3016 case TGSI_FILE_CONSTANT:
3017 case TGSI_FILE_SAMPLER:
3018 break;
3019 default:
3020 NOUVEAU_ERR("bad decl file %d\n",
3021 d->Declaration.File);
3022 goto out_err;
3023 }
3024 }
3025 break;
3026 case TGSI_TOKEN_TYPE_INSTRUCTION:
3027 pc->insn_nr++;
3028 prep_inspect_insn(pc, &tok->FullInstruction);
3029 break;
3030 default:
3031 break;
3032 }
3033 }
3034
3035 if (p->type == PIPE_SHADER_VERTEX) {
3036 int rid = 0;
3037
3038 for (i = 0; i < pc->attr_nr * 4; ++i) {
3039 if (pc->attr[i].acc) {
3040 pc->attr[i].hw = rid++;
3041 p->cfg.attr[i / 32] |= 1 << (i % 32);
3042 }
3043 }
3044
3045 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3046 p->cfg.io[i].hw = rid;
3047 p->cfg.io[i].id = i;
3048
3049 for (c = 0; c < 4; ++c) {
3050 int n = i * 4 + c;
3051 if (!pc->result[n].acc)
3052 continue;
3053 pc->result[n].hw = rid++;
3054 p->cfg.io[i].mask |= 1 << c;
3055 }
3056 }
3057
3058 for (c = 0; c < 2; ++c)
3059 if (p->cfg.two_side[c].hw < 0x40)
3060 p->cfg.two_side[c] = p->cfg.io[
3061 p->cfg.two_side[c].hw];
3062
3063 if (p->cfg.psiz < 0x40)
3064 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
3065 } else
3066 if (p->type == PIPE_SHADER_FRAGMENT) {
3067 int rid, aid;
3068 unsigned n = 0, m = pc->attr_nr - flat_nr;
3069
3070 pc->allow32 = TRUE;
3071
3072 int base = (TGSI_SEMANTIC_POSITION ==
3073 p->info.input_semantic_name[0]) ? 0 : 1;
3074
3075 /* non-flat interpolants have to be mapped to
3076 * the lower hardware IDs, so sort them:
3077 */
3078 for (i = 0; i < pc->attr_nr; i++) {
3079 if (pc->interp_mode[i] == INTERP_FLAT)
3080 p->cfg.io[m++].id = i;
3081 else {
3082 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3083 p->cfg.io[n].linear = TRUE;
3084 p->cfg.io[n++].id = i;
3085 }
3086 }
3087
3088 if (!base) /* set w-coordinate mask from perspective interp */
3089 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
3090
3091 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
3092 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
3093
3094 for (n = 0; n < pc->attr_nr; ++n) {
3095 p->cfg.io[n].hw = rid = aid;
3096 i = p->cfg.io[n].id;
3097
3098 if (p->info.input_semantic_name[n] ==
3099 TGSI_SEMANTIC_FACE) {
3100 load_frontfacing(pc, &pc->attr[i * 4]);
3101 continue;
3102 }
3103
3104 for (c = 0; c < 4; ++c) {
3105 if (!pc->attr[i * 4 + c].acc)
3106 continue;
3107 pc->attr[i * 4 + c].rhw = rid++;
3108 p->cfg.io[n].mask |= 1 << c;
3109
3110 load_interpolant(pc, &pc->attr[i * 4 + c]);
3111 }
3112 aid += popcnt4(p->cfg.io[n].mask);
3113 }
3114
3115 if (!base)
3116 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
3117
3118 m = popcnt4(p->cfg.regs[1] >> 24);
3119
3120 /* set count of non-position inputs and of non-flat
3121 * non-position inputs for FP_INTERPOLANT_CTRL
3122 */
3123 p->cfg.regs[1] |= aid - m;
3124
3125 if (flat_nr) {
3126 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
3127 p->cfg.regs[1] |= (i - m) << 16;
3128 } else
3129 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3130
3131 /* mark color semantic for light-twoside */
3132 n = 0x40;
3133 for (i = 0; i < pc->attr_nr; i++) {
3134 ubyte si, sn;
3135
3136 sn = p->info.input_semantic_name[p->cfg.io[i].id];
3137 si = p->info.input_semantic_index[p->cfg.io[i].id];
3138
3139 if (sn == TGSI_SEMANTIC_COLOR) {
3140 p->cfg.two_side[si] = p->cfg.io[i];
3141
3142 /* increase colour count */
3143 p->cfg.regs[0] += popcnt4(
3144 p->cfg.two_side[si].mask) << 16;
3145
3146 n = MIN2(n, p->cfg.io[i].hw - m);
3147 }
3148 }
3149 if (n < 0x40)
3150 p->cfg.regs[0] += n;
3151
3152 /* Initialize FP results:
3153 * FragDepth is always first TGSI and last hw output
3154 */
3155 i = p->info.writes_z ? 4 : 0;
3156 for (rid = 0; i < pc->result_nr * 4; i++)
3157 pc->result[i].rhw = rid++;
3158 if (p->info.writes_z)
3159 pc->result[2].rhw = rid;
3160
3161 p->cfg.high_result = rid;
3162
3163 /* separate/different colour results for MRTs ? */
3164 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3165 p->cfg.regs[2] |= 1;
3166 }
3167
3168 if (pc->immd_nr) {
3169 int rid = 0;
3170
3171 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3172 if (!pc->immd)
3173 goto out_err;
3174
3175 for (i = 0; i < pc->immd_nr; i++) {
3176 for (c = 0; c < 4; c++, rid++)
3177 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3178 }
3179 }
3180
3181 ret = TRUE;
3182 out_err:
3183 if (pc->iv_p)
3184 free_temp(pc, pc->iv_p);
3185 if (pc->iv_c)
3186 free_temp(pc, pc->iv_c);
3187
3188 tgsi_parse_free(&tp);
3189 return ret;
3190 }
3191
3192 static void
3193 free_nv50_pc(struct nv50_pc *pc)
3194 {
3195 if (pc->immd)
3196 FREE(pc->immd);
3197 if (pc->param)
3198 FREE(pc->param);
3199 if (pc->result)
3200 FREE(pc->result);
3201 if (pc->attr)
3202 FREE(pc->attr);
3203 if (pc->temp)
3204 FREE(pc->temp);
3205
3206 FREE(pc);
3207 }
3208
3209 static boolean
3210 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3211 {
3212 int i, c;
3213 unsigned rtype[2] = { P_ATTR, P_RESULT };
3214
3215 pc->p = p;
3216 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3217 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3218 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3219 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3220 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3221 assert(pc->addr_nr <= 2);
3222
3223 p->cfg.high_temp = 4;
3224
3225 p->cfg.two_side[0].hw = 0x40;
3226 p->cfg.two_side[1].hw = 0x40;
3227
3228 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3229
3230 switch (p->type) {
3231 case PIPE_SHADER_VERTEX:
3232 p->cfg.psiz = 0x40;
3233 p->cfg.clpd = 0x40;
3234 p->cfg.io_nr = pc->result_nr;
3235 break;
3236 case PIPE_SHADER_FRAGMENT:
3237 rtype[0] = rtype[1] = P_TEMP;
3238
3239 p->cfg.regs[0] = 0x01000004;
3240 p->cfg.io_nr = pc->attr_nr;
3241
3242 if (p->info.writes_z) {
3243 p->cfg.regs[2] |= 0x00000100;
3244 p->cfg.regs[3] |= 0x00000011;
3245 }
3246 if (p->info.uses_kill)
3247 p->cfg.regs[2] |= 0x00100000;
3248 break;
3249 }
3250
3251 if (pc->temp_nr) {
3252 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3253 if (!pc->temp)
3254 return FALSE;
3255
3256 for (i = 0; i < pc->temp_nr * 4; ++i)
3257 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3258 }
3259
3260 if (pc->attr_nr) {
3261 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3262 if (!pc->attr)
3263 return FALSE;
3264
3265 for (i = 0; i < pc->attr_nr * 4; ++i)
3266 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3267 }
3268
3269 if (pc->result_nr) {
3270 unsigned nr = pc->result_nr * 4;
3271
3272 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3273 if (!pc->result)
3274 return FALSE;
3275
3276 for (i = 0; i < nr; ++i)
3277 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3278 }
3279
3280 if (pc->param_nr) {
3281 int rid = 0;
3282
3283 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3284 if (!pc->param)
3285 return FALSE;
3286
3287 for (i = 0; i < pc->param_nr; ++i)
3288 for (c = 0; c < 4; ++c, ++rid)
3289 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3290 }
3291
3292 if (pc->addr_nr) {
3293 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3294 if (!pc->addr)
3295 return FALSE;
3296 }
3297 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3298 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
3299
3300 return TRUE;
3301 }
3302
3303 static void
3304 nv50_program_fixup_insns(struct nv50_pc *pc)
3305 {
3306 struct nv50_program_exec *e, **bra_list;
3307 unsigned i, n, pos;
3308
3309 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3310
3311 /* Collect branch instructions, we need to adjust their offsets
3312 * when converting 32 bit instructions to 64 bit ones
3313 */
3314 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3315 if (e->param.index >= 0 && !e->param.mask)
3316 bra_list[n++] = e;
3317
3318 /* Make sure we don't have any single 32 bit instructions. */
3319 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3320 pos += is_long(e) ? 2 : 1;
3321
3322 if ((pos & 1) && (!e->next || is_long(e->next))) {
3323 for (i = 0; i < n; ++i)
3324 if (bra_list[i]->param.index >= pos)
3325 bra_list[i]->param.index += 1;
3326 for (i = 0; i < pc->insn_nr; ++i)
3327 if (pc->insn_pos[i] >= pos)
3328 pc->insn_pos[i] += 1;
3329 convert_to_long(pc, e);
3330 ++pos;
3331 }
3332 }
3333
3334 FREE(bra_list);
3335
3336 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
3337 return;
3338
3339 /* fill in CALL offsets */
3340 for (e = pc->p->exec_head; e; e = e->next) {
3341 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
3342 e->param.index = pc->insn_pos[e->param.index];
3343 }
3344 }
3345
3346 static boolean
3347 nv50_program_tx(struct nv50_program *p)
3348 {
3349 struct tgsi_parse_context parse;
3350 struct nv50_pc *pc;
3351 boolean ret;
3352
3353 pc = CALLOC_STRUCT(nv50_pc);
3354 if (!pc)
3355 return FALSE;
3356
3357 ret = ctor_nv50_pc(pc, p);
3358 if (ret == FALSE)
3359 goto out_cleanup;
3360
3361 ret = nv50_program_tx_prep(pc);
3362 if (ret == FALSE)
3363 goto out_cleanup;
3364
3365 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
3366
3367 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3368 while (!tgsi_parse_end_of_tokens(&parse)) {
3369 const union tgsi_full_token *tok = &parse.FullToken;
3370
3371 /* previously allow32 was FALSE for first & last instruction */
3372 pc->allow32 = TRUE;
3373
3374 tgsi_parse_token(&parse);
3375
3376 switch (tok->Token.Type) {
3377 case TGSI_TOKEN_TYPE_INSTRUCTION:
3378 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
3379 ++pc->insn_cur;
3380 ret = nv50_tgsi_insn(pc, tok);
3381 if (ret == FALSE)
3382 goto out_err;
3383 break;
3384 default:
3385 break;
3386 }
3387 }
3388
3389 nv50_program_fixup_insns(pc);
3390
3391 p->param_nr = pc->param_nr * 4;
3392 p->immd_nr = pc->immd_nr * 4;
3393 p->immd = pc->immd_buf;
3394
3395 out_err:
3396 tgsi_parse_free(&parse);
3397
3398 out_cleanup:
3399 free_nv50_pc(pc);
3400 return ret;
3401 }
3402
3403 static void
3404 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3405 {
3406 if (nv50_program_tx(p) == FALSE)
3407 assert(0);
3408 p->translated = TRUE;
3409 }
3410
3411 static void
3412 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
3413 unsigned start, unsigned count, unsigned cbuf)
3414 {
3415 struct nouveau_channel *chan = nv50->screen->base.channel;
3416 struct nouveau_grobj *tesla = nv50->screen->tesla;
3417
3418 while (count) {
3419 unsigned nr = count > 2047 ? 2047 : count;
3420
3421 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3422 OUT_RING (chan, (cbuf << 0) | (start << 8));
3423 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3424 OUT_RINGp (chan, map, nr);
3425
3426 map += nr;
3427 start += nr;
3428 count -= nr;
3429 }
3430 }
3431
3432 static void
3433 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3434 {
3435 struct pipe_screen *pscreen = nv50->pipe.screen;
3436
3437 if (!p->data[0] && p->immd_nr) {
3438 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3439
3440 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3441 while (heap->next && heap->size < p->immd_nr) {
3442 struct nv50_program *evict = heap->next->priv;
3443 nouveau_resource_free(&evict->data[0]);
3444 }
3445
3446 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3447 &p->data[0]))
3448 assert(0);
3449 }
3450
3451 /* immediates only need to be uploaded again when freed */
3452 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3453 p->immd_nr, NV50_CB_PMISC);
3454 }
3455
3456 assert(p->param_nr <= 512);
3457
3458 if (p->param_nr) {
3459 unsigned cb;
3460 uint32_t *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3461 PIPE_BUFFER_USAGE_CPU_READ);
3462
3463 if (p->type == PIPE_SHADER_VERTEX)
3464 cb = NV50_CB_PVP;
3465 else
3466 cb = NV50_CB_PFP;
3467
3468 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3469 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3470 }
3471 }
3472
3473 static void
3474 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3475 {
3476 struct nouveau_channel *chan = nv50->screen->base.channel;
3477 struct nv50_program_exec *e;
3478 uint32_t *up, i;
3479 boolean upload = FALSE;
3480
3481 if (!p->bo) {
3482 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3483 p->exec_size * 4, &p->bo);
3484 upload = TRUE;
3485 }
3486
3487 if (p->data[0] && p->data[0]->start != p->data_start[0])
3488 upload = TRUE;
3489
3490 if (!upload)
3491 return;
3492
3493 up = MALLOC(p->exec_size * 4);
3494
3495 for (i = 0, e = p->exec_head; e; e = e->next) {
3496 unsigned ei, ci, bs;
3497
3498 if (e->param.index >= 0 && e->param.mask) {
3499 bs = (e->inst[1] >> 22) & 0x07;
3500 assert(bs < 2);
3501 ei = e->param.shift >> 5;
3502 ci = e->param.index;
3503 if (bs == 0)
3504 ci += p->data[bs]->start;
3505
3506 e->inst[ei] &= ~e->param.mask;
3507 e->inst[ei] |= (ci << e->param.shift);
3508 } else
3509 if (e->param.index >= 0) {
3510 /* zero mask means param is a jump/branch offset */
3511 assert(!(e->param.index & 1));
3512 /* seem to be 8 byte steps */
3513 ei = (e->param.index >> 1) + 0 /* START_ID */;
3514
3515 e->inst[0] &= 0xf0000fff;
3516 e->inst[0] |= ei << 12;
3517 }
3518
3519 up[i++] = e->inst[0];
3520 if (is_long(e))
3521 up[i++] = e->inst[1];
3522 }
3523 assert(i == p->exec_size);
3524
3525 if (p->data[0])
3526 p->data_start[0] = p->data[0]->start;
3527
3528 #ifdef NV50_PROGRAM_DUMP
3529 NOUVEAU_ERR("-------\n");
3530 for (e = p->exec_head; e; e = e->next) {
3531 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3532 if (is_long(e))
3533 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3534 }
3535 #endif
3536 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3537 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3538 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3539 0, 0, p->exec_size * 4, 1, 1);
3540
3541 FREE(up);
3542 }
3543
3544 void
3545 nv50_vertprog_validate(struct nv50_context *nv50)
3546 {
3547 struct nouveau_grobj *tesla = nv50->screen->tesla;
3548 struct nv50_program *p = nv50->vertprog;
3549 struct nouveau_stateobj *so;
3550
3551 if (!p->translated) {
3552 nv50_program_validate(nv50, p);
3553 if (!p->translated)
3554 assert(0);
3555 }
3556
3557 nv50_program_validate_data(nv50, p);
3558 nv50_program_validate_code(nv50, p);
3559
3560 so = so_new(13, 2);
3561 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3562 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3563 NOUVEAU_BO_HIGH, 0, 0);
3564 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3565 NOUVEAU_BO_LOW, 0, 0);
3566 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3567 so_data (so, p->cfg.attr[0]);
3568 so_data (so, p->cfg.attr[1]);
3569 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3570 so_data (so, p->cfg.high_result);
3571 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3572 so_data (so, p->cfg.high_result); //8);
3573 so_data (so, p->cfg.high_temp);
3574 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3575 so_data (so, 0); /* program start offset */
3576 so_ref(so, &nv50->state.vertprog);
3577 so_ref(NULL, &so);
3578 }
3579
3580 void
3581 nv50_fragprog_validate(struct nv50_context *nv50)
3582 {
3583 struct nouveau_grobj *tesla = nv50->screen->tesla;
3584 struct nv50_program *p = nv50->fragprog;
3585 struct nouveau_stateobj *so;
3586
3587 if (!p->translated) {
3588 nv50_program_validate(nv50, p);
3589 if (!p->translated)
3590 assert(0);
3591 }
3592
3593 nv50_program_validate_data(nv50, p);
3594 nv50_program_validate_code(nv50, p);
3595
3596 so = so_new(64, 2);
3597 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3598 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3599 NOUVEAU_BO_HIGH, 0, 0);
3600 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3601 NOUVEAU_BO_LOW, 0, 0);
3602 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3603 so_data (so, p->cfg.high_temp);
3604 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3605 so_data (so, p->cfg.high_result);
3606 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
3607 so_data (so, p->cfg.regs[2]);
3608 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3609 so_data (so, p->cfg.regs[3]);
3610 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3611 so_data (so, 0); /* program start offset */
3612 so_ref(so, &nv50->state.fragprog);
3613 so_ref(NULL, &so);
3614 }
3615
3616 static void
3617 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3618 {
3619 struct nv50_program *fp = nv50->fragprog;
3620 struct nv50_program *vp = nv50->vertprog;
3621 unsigned i, c, m = base;
3622
3623 /* XXX: this might not work correctly in all cases yet - we'll
3624 * just assume that an FP generic input that is not written in
3625 * the VP is PointCoord.
3626 */
3627 memset(pntc, 0, 8 * sizeof(uint32_t));
3628
3629 for (i = 0; i < fp->cfg.io_nr; i++) {
3630 uint8_t sn, si;
3631 uint8_t j, k = fp->cfg.io[i].id;
3632 unsigned n = popcnt4(fp->cfg.io[i].mask);
3633
3634 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3635 m += n;
3636 continue;
3637 }
3638
3639 for (j = 0; j < vp->info.num_outputs; ++j) {
3640 sn = vp->info.output_semantic_name[j];
3641 si = vp->info.output_semantic_index[j];
3642
3643 if (sn == fp->info.input_semantic_name[k] &&
3644 si == fp->info.input_semantic_index[k])
3645 break;
3646 }
3647
3648 if (j < vp->info.num_outputs) {
3649 ubyte mode =
3650 nv50->rasterizer->pipe.sprite_coord_mode[si];
3651
3652 if (mode == PIPE_SPRITE_COORD_NONE) {
3653 m += n;
3654 continue;
3655 }
3656 }
3657
3658 /* this is either PointCoord or replaced by sprite coords */
3659 for (c = 0; c < 4; c++) {
3660 if (!(fp->cfg.io[i].mask & (1 << c)))
3661 continue;
3662 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3663 ++m;
3664 }
3665 }
3666 }
3667
3668 static int
3669 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3670 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3671 {
3672 int c;
3673 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3674 uint8_t *map = (uint8_t *)p_map;
3675
3676 for (c = 0; c < 4; ++c) {
3677 if (mf & 1) {
3678 if (fpi->linear == TRUE)
3679 lin[mid / 32] |= 1 << (mid % 32);
3680 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3681 }
3682
3683 oid += mv & 1;
3684 mf >>= 1;
3685 mv >>= 1;
3686 }
3687
3688 return mid;
3689 }
3690
3691 void
3692 nv50_linkage_validate(struct nv50_context *nv50)
3693 {
3694 struct nouveau_grobj *tesla = nv50->screen->tesla;
3695 struct nv50_program *vp = nv50->vertprog;
3696 struct nv50_program *fp = nv50->fragprog;
3697 struct nouveau_stateobj *so;
3698 struct nv50_sreg4 dummy, *vpo;
3699 int i, n, c, m = 0;
3700 uint32_t map[16], lin[4], reg[5], pcrd[8];
3701
3702 memset(map, 0, sizeof(map));
3703 memset(lin, 0, sizeof(lin));
3704
3705 reg[1] = 0x00000004; /* low and high clip distance map ids */
3706 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3707 reg[3] = 0x00000000; /* point size map id & enable */
3708 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3709 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3710
3711 dummy.linear = FALSE;
3712 dummy.mask = 0xf; /* map all components of HPOS */
3713 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3714
3715 dummy.mask = 0x0;
3716
3717 if (vp->cfg.clpd < 0x40) {
3718 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3719 map[m++] = vp->cfg.clpd + c;
3720 reg[1] = (m << 8);
3721 }
3722
3723 reg[0] |= m << 8; /* adjust BFC0 id */
3724
3725 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3726 if (nv50->rasterizer->pipe.light_twoside) {
3727 vpo = &vp->cfg.two_side[0];
3728
3729 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3730 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3731 }
3732
3733 reg[0] += m - 4; /* adjust FFC0 id */
3734 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3735
3736 for (i = 0; i < fp->cfg.io_nr; i++) {
3737 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
3738 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
3739
3740 /* position must be mapped first */
3741 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
3742
3743 /* maybe even remove these from cfg.io */
3744 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
3745 continue;
3746
3747 /* VP outputs and vp->cfg.io are in the same order */
3748 for (n = 0; n < vp->info.num_outputs; ++n) {
3749 if (vp->info.output_semantic_name[n] == sn &&
3750 vp->info.output_semantic_index[n] == si)
3751 break;
3752 }
3753 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
3754
3755 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3756 }
3757
3758 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3759 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3760 reg[3] = (m++ << 4) | 1;
3761 }
3762
3763 /* now fill the stateobj */
3764 so = so_new(64, 0);
3765
3766 n = (m + 3) / 4;
3767 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3768 so_data (so, m);
3769 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3770 so_datap (so, map, n);
3771
3772 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3773 so_datap (so, reg, 4);
3774
3775 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3776 so_data (so, reg[4]);
3777
3778 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
3779 so_datap (so, lin, 4);
3780
3781 if (nv50->rasterizer->pipe.point_sprite) {
3782 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3783
3784 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3785 so_datap (so, pcrd, 8);
3786 }
3787
3788 so_ref(so, &nv50->state.programs);
3789 so_ref(NULL, &so);
3790 }
3791
3792 void
3793 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3794 {
3795 while (p->exec_head) {
3796 struct nv50_program_exec *e = p->exec_head;
3797
3798 p->exec_head = e->next;
3799 FREE(e);
3800 }
3801 p->exec_tail = NULL;
3802 p->exec_size = 0;
3803
3804 nouveau_bo_ref(NULL, &p->bo);
3805
3806 nouveau_resource_free(&p->data[0]);
3807
3808 p->translated = 0;
3809 }