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Merge branch 'glsl-pp-rework-2'
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95 };
96
97 #define NV50_MOD_NEG 1
98 #define NV50_MOD_ABS 2
99 #define NV50_MOD_SAT 4
100
101 /* arbitrary limits */
102 #define MAX_IF_DEPTH 4
103 #define MAX_LOOP_DEPTH 4
104
105 struct nv50_pc {
106 struct nv50_program *p;
107
108 /* hw resources */
109 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
110 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
111
112 /* tgsi resources */
113 struct nv50_reg *temp;
114 int temp_nr;
115 struct nv50_reg *attr;
116 int attr_nr;
117 struct nv50_reg *result;
118 int result_nr;
119 struct nv50_reg *param;
120 int param_nr;
121 struct nv50_reg *immd;
122 uint32_t *immd_buf;
123 int immd_nr;
124 struct nv50_reg **addr;
125 int addr_nr;
126
127 struct nv50_reg *temp_temp[16];
128 unsigned temp_temp_nr;
129
130 /* broadcast and destination replacement regs */
131 struct nv50_reg *r_brdc;
132 struct nv50_reg *r_dst[4];
133
134 struct nv50_reg reg_instances[16];
135 unsigned reg_instance_nr;
136
137 unsigned interp_mode[32];
138 /* perspective interpolation registers */
139 struct nv50_reg *iv_p;
140 struct nv50_reg *iv_c;
141
142 struct nv50_program_exec *if_cond;
143 struct nv50_program_exec *if_insn[MAX_IF_DEPTH];
144 struct nv50_program_exec *br_join[MAX_IF_DEPTH];
145 struct nv50_program_exec *br_loop[MAX_LOOP_DEPTH]; /* for BRK branch */
146 int if_lvl, loop_lvl;
147 unsigned loop_pos[MAX_LOOP_DEPTH];
148
149 /* current instruction and total number of insns */
150 unsigned insn_cur;
151 unsigned insn_nr;
152
153 boolean allow32;
154 };
155
156 static INLINE struct nv50_reg *
157 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
158 {
159 struct nv50_reg *ri;
160
161 assert(pc->reg_instance_nr < 16);
162 ri = &pc->reg_instances[pc->reg_instance_nr++];
163 if (reg) {
164 *ri = *reg;
165 reg->mod = 0;
166 }
167 return ri;
168 }
169
170 static INLINE void
171 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
172 {
173 reg->type = type;
174 reg->index = index;
175 reg->hw = hw;
176 reg->mod = 0;
177 reg->rhw = -1;
178 reg->acc = 0;
179 }
180
181 static INLINE unsigned
182 popcnt4(uint32_t val)
183 {
184 static const unsigned cnt[16]
185 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
186 return cnt[val & 0xf];
187 }
188
189 static void
190 terminate_mbb(struct nv50_pc *pc)
191 {
192 int i;
193
194 /* remove records of temporary address register values */
195 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
196 if (pc->r_addr[i].index < 0)
197 pc->r_addr[i].rhw = -1;
198 }
199
200 static void
201 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
202 {
203 int i = 0;
204
205 if (reg->type == P_RESULT) {
206 if (pc->p->cfg.high_result < (reg->hw + 1))
207 pc->p->cfg.high_result = reg->hw + 1;
208 }
209
210 if (reg->type != P_TEMP)
211 return;
212
213 if (reg->hw >= 0) {
214 /*XXX: do this here too to catch FP temp-as-attr usage..
215 * not clean, but works */
216 if (pc->p->cfg.high_temp < (reg->hw + 1))
217 pc->p->cfg.high_temp = reg->hw + 1;
218 return;
219 }
220
221 if (reg->rhw != -1) {
222 /* try to allocate temporary with index rhw first */
223 if (!(pc->r_temp[reg->rhw])) {
224 pc->r_temp[reg->rhw] = reg;
225 reg->hw = reg->rhw;
226 if (pc->p->cfg.high_temp < (reg->rhw + 1))
227 pc->p->cfg.high_temp = reg->rhw + 1;
228 return;
229 }
230 /* make sure we don't get things like $r0 needs to go
231 * in $r1 and $r1 in $r0
232 */
233 i = pc->result_nr * 4;
234 }
235
236 for (; i < NV50_SU_MAX_TEMP; i++) {
237 if (!(pc->r_temp[i])) {
238 pc->r_temp[i] = reg;
239 reg->hw = i;
240 if (pc->p->cfg.high_temp < (i + 1))
241 pc->p->cfg.high_temp = i + 1;
242 return;
243 }
244 }
245
246 assert(0);
247 }
248
249 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
250 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
251 * lest we risk temp_temps overwriting regs alloc'd "later".
252 */
253 static struct nv50_reg *
254 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
255 {
256 struct nv50_reg *r;
257 int i;
258
259 if (dst && dst->type == P_TEMP && dst->hw == -1)
260 return dst;
261
262 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
263 if (!pc->r_temp[i]) {
264 r = MALLOC_STRUCT(nv50_reg);
265 ctor_reg(r, P_TEMP, -1, i);
266 pc->r_temp[i] = r;
267 return r;
268 }
269 }
270
271 assert(0);
272 return NULL;
273 }
274
275 /* Assign the hw of the discarded temporary register src
276 * to the tgsi register dst and free src.
277 */
278 static void
279 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
280 {
281 assert(src->index == -1 && src->hw != -1);
282
283 if (dst->hw != -1)
284 pc->r_temp[dst->hw] = NULL;
285 pc->r_temp[src->hw] = dst;
286 dst->hw = src->hw;
287
288 FREE(src);
289 }
290
291 /* release the hardware resource held by r */
292 static void
293 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
294 {
295 assert(r->type == P_TEMP);
296 if (r->hw == -1)
297 return;
298
299 assert(pc->r_temp[r->hw] == r);
300 pc->r_temp[r->hw] = NULL;
301
302 r->acc = 0;
303 if (r->index == -1)
304 FREE(r);
305 }
306
307 static void
308 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
309 {
310 if (r->index == -1) {
311 unsigned hw = r->hw;
312
313 FREE(pc->r_temp[hw]);
314 pc->r_temp[hw] = NULL;
315 }
316 }
317
318 static int
319 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
320 {
321 int i;
322
323 if ((idx + 4) >= NV50_SU_MAX_TEMP)
324 return 1;
325
326 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
327 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
328 return alloc_temp4(pc, dst, idx + 4);
329
330 for (i = 0; i < 4; i++) {
331 dst[i] = MALLOC_STRUCT(nv50_reg);
332 ctor_reg(dst[i], P_TEMP, -1, idx + i);
333 pc->r_temp[idx + i] = dst[i];
334 }
335
336 return 0;
337 }
338
339 static void
340 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
341 {
342 int i;
343
344 for (i = 0; i < 4; i++)
345 free_temp(pc, reg[i]);
346 }
347
348 static struct nv50_reg *
349 temp_temp(struct nv50_pc *pc)
350 {
351 if (pc->temp_temp_nr >= 16)
352 assert(0);
353
354 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
355 return pc->temp_temp[pc->temp_temp_nr++];
356 }
357
358 static void
359 kill_temp_temp(struct nv50_pc *pc)
360 {
361 int i;
362
363 for (i = 0; i < pc->temp_temp_nr; i++)
364 free_temp(pc, pc->temp_temp[i]);
365 pc->temp_temp_nr = 0;
366 }
367
368 static int
369 ctor_immd_4u32(struct nv50_pc *pc,
370 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
371 {
372 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
373
374 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
375
376 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
377 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
378 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
379 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
380
381 return pc->immd_nr++;
382 }
383
384 static INLINE int
385 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
386 {
387 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
388 }
389
390 static struct nv50_reg *
391 alloc_immd(struct nv50_pc *pc, float f)
392 {
393 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
394 unsigned hw;
395
396 for (hw = 0; hw < pc->immd_nr * 4; hw++)
397 if (pc->immd_buf[hw] == fui(f))
398 break;
399
400 if (hw == pc->immd_nr * 4)
401 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
402
403 ctor_reg(r, P_IMMD, -1, hw);
404 return r;
405 }
406
407 static struct nv50_program_exec *
408 exec(struct nv50_pc *pc)
409 {
410 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
411
412 e->param.index = -1;
413 return e;
414 }
415
416 static void
417 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
418 {
419 struct nv50_program *p = pc->p;
420
421 if (p->exec_tail)
422 p->exec_tail->next = e;
423 if (!p->exec_head)
424 p->exec_head = e;
425 p->exec_tail = e;
426 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
427 }
428
429 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
430
431 static boolean
432 is_long(struct nv50_program_exec *e)
433 {
434 if (e->inst[0] & 1)
435 return TRUE;
436 return FALSE;
437 }
438
439 static boolean
440 is_immd(struct nv50_program_exec *e)
441 {
442 if (is_long(e) && (e->inst[1] & 3) == 3)
443 return TRUE;
444 return FALSE;
445 }
446
447 static INLINE void
448 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
449 struct nv50_program_exec *e)
450 {
451 set_long(pc, e);
452 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
453 e->inst[1] |= (pred << 7) | (idx << 12);
454 }
455
456 static INLINE void
457 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
458 struct nv50_program_exec *e)
459 {
460 set_long(pc, e);
461 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
462 e->inst[1] |= (idx << 4) | (on << 6);
463 }
464
465 static INLINE void
466 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
467 {
468 if (is_long(e))
469 return;
470
471 e->inst[0] |= 1;
472 set_pred(pc, 0xf, 0, e);
473 set_pred_wr(pc, 0, 0, e);
474 }
475
476 static INLINE void
477 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
478 {
479 if (dst->type == P_RESULT) {
480 set_long(pc, e);
481 e->inst[1] |= 0x00000008;
482 }
483
484 alloc_reg(pc, dst);
485 if (dst->hw > 63)
486 set_long(pc, e);
487 e->inst[0] |= (dst->hw << 2);
488 }
489
490 static INLINE void
491 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
492 {
493 union {
494 float f;
495 uint32_t ui;
496 } u;
497 u.ui = pc->immd_buf[imm->hw];
498
499 u.f = (imm->mod & NV50_MOD_ABS) ? fabsf(u.f) : u.f;
500 u.f = (imm->mod & NV50_MOD_NEG) ? -u.f : u.f;
501
502 set_long(pc, e);
503 /* XXX: can't be predicated - bits overlap; cases where both
504 * are required should be avoided by using pc->allow32 */
505 set_pred(pc, 0, 0, e);
506 set_pred_wr(pc, 0, 0, e);
507
508 e->inst[1] |= 0x00000002 | 0x00000001;
509 e->inst[0] |= (u.ui & 0x3f) << 16;
510 e->inst[1] |= (u.ui >> 6) << 2;
511 }
512
513 static INLINE void
514 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
515 {
516 assert(!(e->inst[0] & 0x0c000000));
517 assert(!(e->inst[1] & 0x00000004));
518
519 e->inst[0] |= (a->hw & 3) << 26;
520 e->inst[1] |= (a->hw >> 2) << 2;
521 }
522
523 static void
524 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
525 struct nv50_reg *src0, uint16_t src1_val)
526 {
527 struct nv50_program_exec *e = exec(pc);
528
529 e->inst[0] = 0xd0000000 | (src1_val << 9);
530 e->inst[1] = 0x20000000;
531 set_long(pc, e);
532 e->inst[0] |= dst->hw << 2;
533 if (src0) /* otherwise will add to $a0, which is always 0 */
534 set_addr(e, src0);
535
536 emit(pc, e);
537 }
538
539 static struct nv50_reg *
540 alloc_addr(struct nv50_pc *pc, struct nv50_reg *ref)
541 {
542 int i;
543 struct nv50_reg *a_tgsi = NULL, *a = NULL;
544
545 if (!ref) {
546 /* allocate for TGSI address reg */
547 for (i = 0; i < NV50_SU_MAX_ADDR; ++i) {
548 if (pc->r_addr[i].index >= 0)
549 continue;
550 if (pc->r_addr[i].rhw >= 0 &&
551 pc->r_addr[i].acc == pc->insn_cur)
552 continue;
553
554 pc->r_addr[i].rhw = -1;
555 pc->r_addr[i].index = i;
556 return &pc->r_addr[i];
557 }
558 assert(0);
559 return NULL;
560 }
561
562 /* Allocate and set an address reg so we can access 'ref'.
563 *
564 * If and r_addr has index < 0, it is not reserved for TGSI,
565 * and index will be the negative of the TGSI addr index the
566 * value in rhw is relative to, or -256 if rhw is an offset
567 * from 0. If rhw < 0, the reg has not been initialized.
568 */
569 for (i = NV50_SU_MAX_ADDR - 1; i >= 0; --i) {
570 if (pc->r_addr[i].index >= 0) /* occupied for TGSI */
571 continue;
572 if (pc->r_addr[i].rhw < 0) { /* unused */
573 a = &pc->r_addr[i];
574 continue;
575 }
576 if (!a && pc->r_addr[i].acc != pc->insn_cur)
577 a = &pc->r_addr[i];
578
579 if (ref->hw - pc->r_addr[i].rhw >= 128)
580 continue;
581
582 if ((ref->acc >= 0 && pc->r_addr[i].index == -256) ||
583 (ref->acc < 0 && -pc->r_addr[i].index == ref->index)) {
584 pc->r_addr[i].acc = pc->insn_cur;
585 return &pc->r_addr[i];
586 }
587 }
588 assert(a);
589
590 if (ref->acc < 0)
591 a_tgsi = pc->addr[ref->index];
592
593 emit_add_addr_imm(pc, a, a_tgsi, (ref->hw & ~0x7f) * 4);
594
595 a->rhw = ref->hw & ~0x7f;
596 a->acc = pc->insn_cur;
597 a->index = a_tgsi ? -ref->index : -256;
598 return a;
599 }
600
601 #define INTERP_LINEAR 0
602 #define INTERP_FLAT 1
603 #define INTERP_PERSPECTIVE 2
604 #define INTERP_CENTROID 4
605
606 /* interpolant index has been stored in dst->rhw */
607 static void
608 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
609 unsigned mode)
610 {
611 assert(dst->rhw != -1);
612 struct nv50_program_exec *e = exec(pc);
613
614 e->inst[0] |= 0x80000000;
615 set_dst(pc, dst, e);
616 e->inst[0] |= (dst->rhw << 16);
617
618 if (mode & INTERP_FLAT) {
619 e->inst[0] |= (1 << 8);
620 } else {
621 if (mode & INTERP_PERSPECTIVE) {
622 e->inst[0] |= (1 << 25);
623 alloc_reg(pc, iv);
624 e->inst[0] |= (iv->hw << 9);
625 }
626
627 if (mode & INTERP_CENTROID)
628 e->inst[0] |= (1 << 24);
629 }
630
631 emit(pc, e);
632 }
633
634 static void
635 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
636 struct nv50_program_exec *e)
637 {
638 set_long(pc, e);
639
640 e->param.index = src->hw & 127;
641 e->param.shift = s;
642 e->param.mask = m << (s % 32);
643
644 if (src->hw > 127)
645 set_addr(e, alloc_addr(pc, src));
646 else
647 if (src->acc < 0) {
648 assert(src->type == P_CONST);
649 set_addr(e, pc->addr[src->index]);
650 }
651
652 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
653 }
654
655 static void
656 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
657 {
658 struct nv50_program_exec *e = exec(pc);
659
660 e->inst[0] = 0x10000000;
661 if (!pc->allow32)
662 set_long(pc, e);
663
664 set_dst(pc, dst, e);
665
666 if (!is_long(e) && src->type == P_IMMD) {
667 set_immd(pc, src, e);
668 /*XXX: 32-bit, but steals part of "half" reg space - need to
669 * catch and handle this case if/when we do half-regs
670 */
671 } else
672 if (src->type == P_IMMD || src->type == P_CONST) {
673 set_long(pc, e);
674 set_data(pc, src, 0x7f, 9, e);
675 e->inst[1] |= 0x20000000; /* mov from c[] */
676 } else {
677 if (src->type == P_ATTR) {
678 set_long(pc, e);
679 e->inst[1] |= 0x00200000;
680 }
681
682 alloc_reg(pc, src);
683 if (src->hw > 63)
684 set_long(pc, e);
685 e->inst[0] |= (src->hw << 9);
686 }
687
688 if (is_long(e) && !is_immd(e)) {
689 e->inst[1] |= 0x04000000; /* 32-bit */
690 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
691 if (!(e->inst[1] & 0x20000000))
692 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
693 } else
694 e->inst[0] |= 0x00008000;
695
696 emit(pc, e);
697 }
698
699 static INLINE void
700 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
701 {
702 struct nv50_reg *imm = alloc_immd(pc, f);
703 emit_mov(pc, dst, imm);
704 FREE(imm);
705 }
706
707 static void
708 emit_nop(struct nv50_pc *pc)
709 {
710 struct nv50_program_exec *e = exec(pc);
711
712 e->inst[0] = 0xf0000000;
713 set_long(pc, e);
714 e->inst[1] = 0xe0000000;
715 emit(pc, e);
716 }
717
718 static boolean
719 check_swap_src_0_1(struct nv50_pc *pc,
720 struct nv50_reg **s0, struct nv50_reg **s1)
721 {
722 struct nv50_reg *src0 = *s0, *src1 = *s1;
723
724 if (src0->type == P_CONST) {
725 if (src1->type != P_CONST) {
726 *s0 = src1;
727 *s1 = src0;
728 return TRUE;
729 }
730 } else
731 if (src1->type == P_ATTR) {
732 if (src0->type != P_ATTR) {
733 *s0 = src1;
734 *s1 = src0;
735 return TRUE;
736 }
737 }
738
739 return FALSE;
740 }
741
742 static void
743 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
744 struct nv50_program_exec *e)
745 {
746 struct nv50_reg *temp;
747
748 if (src->type != P_TEMP) {
749 temp = temp_temp(pc);
750 emit_mov(pc, temp, src);
751 src = temp;
752 }
753
754 alloc_reg(pc, src);
755 if (src->hw > 63)
756 set_long(pc, e);
757 e->inst[0] |= (src->hw << 9);
758 }
759
760 static void
761 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
762 {
763 if (src->type == P_ATTR) {
764 set_long(pc, e);
765 e->inst[1] |= 0x00200000;
766 } else
767 if (src->type == P_CONST || src->type == P_IMMD) {
768 struct nv50_reg *temp = temp_temp(pc);
769
770 emit_mov(pc, temp, src);
771 src = temp;
772 }
773
774 alloc_reg(pc, src);
775 if (src->hw > 63)
776 set_long(pc, e);
777 e->inst[0] |= (src->hw << 9);
778 }
779
780 static void
781 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
782 {
783 if (src->type == P_ATTR) {
784 struct nv50_reg *temp = temp_temp(pc);
785
786 emit_mov(pc, temp, src);
787 src = temp;
788 } else
789 if (src->type == P_CONST || src->type == P_IMMD) {
790 assert(!(e->inst[0] & 0x00800000));
791 if (e->inst[0] & 0x01000000) {
792 struct nv50_reg *temp = temp_temp(pc);
793
794 emit_mov(pc, temp, src);
795 src = temp;
796 } else {
797 set_data(pc, src, 0x7f, 16, e);
798 e->inst[0] |= 0x00800000;
799 }
800 }
801
802 alloc_reg(pc, src);
803 if (src->hw > 63)
804 set_long(pc, e);
805 e->inst[0] |= ((src->hw & 127) << 16);
806 }
807
808 static void
809 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
810 {
811 set_long(pc, e);
812
813 if (src->type == P_ATTR) {
814 struct nv50_reg *temp = temp_temp(pc);
815
816 emit_mov(pc, temp, src);
817 src = temp;
818 } else
819 if (src->type == P_CONST || src->type == P_IMMD) {
820 assert(!(e->inst[0] & 0x01000000));
821 if (e->inst[0] & 0x00800000) {
822 struct nv50_reg *temp = temp_temp(pc);
823
824 emit_mov(pc, temp, src);
825 src = temp;
826 } else {
827 set_data(pc, src, 0x7f, 32+14, e);
828 e->inst[0] |= 0x01000000;
829 }
830 }
831
832 alloc_reg(pc, src);
833 e->inst[1] |= ((src->hw & 127) << 14);
834 }
835
836 static void
837 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
838 {
839 struct nv50_program_exec *e = exec(pc);
840
841 assert(dst->type == P_TEMP);
842 e->inst[1] = 0x20000000 | (pred << 12);
843 set_long(pc, e);
844 set_dst(pc, dst, e);
845
846 emit(pc, e);
847 }
848
849 static void
850 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
851 {
852 struct nv50_program_exec *e = exec(pc);
853
854 e->inst[0] = 0x000001fc;
855 e->inst[1] = 0xa0000008;
856 set_long(pc, e);
857 set_pred_wr(pc, 1, pred, e);
858 set_src_0_restricted(pc, src, e);
859
860 emit(pc, e);
861 }
862
863 static void
864 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
865 struct nv50_reg *src1)
866 {
867 struct nv50_program_exec *e = exec(pc);
868
869 e->inst[0] |= 0xc0000000;
870
871 if (!pc->allow32)
872 set_long(pc, e);
873
874 check_swap_src_0_1(pc, &src0, &src1);
875 set_dst(pc, dst, e);
876 set_src_0(pc, src0, e);
877 if (src1->type == P_IMMD && !is_long(e)) {
878 if (src0->mod & NV50_MOD_NEG)
879 e->inst[0] |= 0x00008000;
880 set_immd(pc, src1, e);
881 } else {
882 set_src_1(pc, src1, e);
883 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
884 if (is_long(e))
885 e->inst[1] |= 0x08000000;
886 else
887 e->inst[0] |= 0x00008000;
888 }
889 }
890
891 emit(pc, e);
892 }
893
894 static void
895 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
896 struct nv50_reg *src0, struct nv50_reg *src1)
897 {
898 struct nv50_program_exec *e = exec(pc);
899
900 e->inst[0] = 0xb0000000;
901
902 alloc_reg(pc, src1);
903 check_swap_src_0_1(pc, &src0, &src1);
904
905 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
906 set_long(pc, e);
907 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
908 ((src1->mod & NV50_MOD_NEG) << 27);
909 }
910
911 set_dst(pc, dst, e);
912 set_src_0(pc, src0, e);
913 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
914 set_src_2(pc, src1, e);
915 else
916 if (src1->type == P_IMMD)
917 set_immd(pc, src1, e);
918 else
919 set_src_1(pc, src1, e);
920
921 emit(pc, e);
922 }
923
924 static void
925 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
926 uint8_t s)
927 {
928 struct nv50_program_exec *e = exec(pc);
929
930 set_long(pc, e);
931 e->inst[1] |= 0xc0000000;
932
933 e->inst[0] |= dst->hw << 2;
934 e->inst[0] |= s << 16; /* shift left */
935 set_src_0_restricted(pc, src, e);
936
937 emit(pc, e);
938 }
939
940 static void
941 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
942 struct nv50_reg *src0, struct nv50_reg *src1)
943 {
944 struct nv50_program_exec *e = exec(pc);
945
946 set_long(pc, e);
947 e->inst[0] |= 0xb0000000;
948 e->inst[1] |= (sub << 29);
949
950 check_swap_src_0_1(pc, &src0, &src1);
951 set_dst(pc, dst, e);
952 set_src_0(pc, src0, e);
953 set_src_1(pc, src1, e);
954
955 if (src0->mod & NV50_MOD_ABS)
956 e->inst[1] |= 0x00100000;
957 if (src1->mod & NV50_MOD_ABS)
958 e->inst[1] |= 0x00080000;
959
960 emit(pc, e);
961 }
962
963 static INLINE void
964 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
965 struct nv50_reg *src1)
966 {
967 src1->mod ^= NV50_MOD_NEG;
968 emit_add(pc, dst, src0, src1);
969 src1->mod ^= NV50_MOD_NEG;
970 }
971
972 static void
973 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
974 struct nv50_reg *src1, unsigned op)
975 {
976 struct nv50_program_exec *e = exec(pc);
977
978 e->inst[0] = 0xd0000000;
979 set_long(pc, e);
980
981 check_swap_src_0_1(pc, &src0, &src1);
982 set_dst(pc, dst, e);
983 set_src_0(pc, src0, e);
984
985 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
986 op != TGSI_OPCODE_XOR)
987 assert(!"invalid bit op");
988
989 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
990 set_immd(pc, src1, e);
991 if (op == TGSI_OPCODE_OR)
992 e->inst[0] |= 0x0100;
993 else
994 if (op == TGSI_OPCODE_XOR)
995 e->inst[0] |= 0x8000;
996 } else {
997 set_src_1(pc, src1, e);
998 e->inst[1] |= 0x04000000; /* 32 bit */
999 if (op == TGSI_OPCODE_OR)
1000 e->inst[1] |= 0x4000;
1001 else
1002 if (op == TGSI_OPCODE_XOR)
1003 e->inst[1] |= 0x8000;
1004 }
1005
1006 emit(pc, e);
1007 }
1008
1009 static void
1010 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1011 struct nv50_reg *src1, struct nv50_reg *src2)
1012 {
1013 struct nv50_program_exec *e = exec(pc);
1014
1015 e->inst[0] |= 0xe0000000;
1016
1017 check_swap_src_0_1(pc, &src0, &src1);
1018 set_dst(pc, dst, e);
1019 set_src_0(pc, src0, e);
1020 set_src_1(pc, src1, e);
1021 set_src_2(pc, src2, e);
1022
1023 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1024 e->inst[1] |= 0x04000000;
1025 if (src2->mod & NV50_MOD_NEG)
1026 e->inst[1] |= 0x08000000;
1027
1028 emit(pc, e);
1029 }
1030
1031 static INLINE void
1032 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1033 struct nv50_reg *src1, struct nv50_reg *src2)
1034 {
1035 src2->mod ^= NV50_MOD_NEG;
1036 emit_mad(pc, dst, src0, src1, src2);
1037 src2->mod ^= NV50_MOD_NEG;
1038 }
1039
1040 static void
1041 emit_flop(struct nv50_pc *pc, unsigned sub,
1042 struct nv50_reg *dst, struct nv50_reg *src)
1043 {
1044 struct nv50_program_exec *e = exec(pc);
1045
1046 e->inst[0] |= 0x90000000;
1047 if (sub) {
1048 set_long(pc, e);
1049 e->inst[1] |= (sub << 29);
1050 }
1051
1052 set_dst(pc, dst, e);
1053
1054 if (sub == 0 || sub == 2)
1055 set_src_0_restricted(pc, src, e);
1056 else
1057 set_src_0(pc, src, e);
1058
1059 emit(pc, e);
1060 }
1061
1062 static void
1063 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1064 {
1065 struct nv50_program_exec *e = exec(pc);
1066
1067 e->inst[0] |= 0xb0000000;
1068
1069 set_dst(pc, dst, e);
1070 set_src_0(pc, src, e);
1071 set_long(pc, e);
1072 e->inst[1] |= (6 << 29) | 0x00004000;
1073
1074 emit(pc, e);
1075 }
1076
1077 static void
1078 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1079 {
1080 struct nv50_program_exec *e = exec(pc);
1081
1082 e->inst[0] |= 0xb0000000;
1083
1084 set_dst(pc, dst, e);
1085 set_src_0(pc, src, e);
1086 set_long(pc, e);
1087 e->inst[1] |= (6 << 29);
1088
1089 emit(pc, e);
1090 }
1091
1092 #define CVTOP_RN 0x01
1093 #define CVTOP_FLOOR 0x03
1094 #define CVTOP_CEIL 0x05
1095 #define CVTOP_TRUNC 0x07
1096 #define CVTOP_SAT 0x08
1097 #define CVTOP_ABS 0x10
1098
1099 /* 0x04 == 32 bit dst */
1100 /* 0x40 == dst is float */
1101 /* 0x80 == src is float */
1102 #define CVT_F32_F32 0xc4
1103 #define CVT_F32_S32 0x44
1104 #define CVT_S32_F32 0x8c
1105 #define CVT_S32_S32 0x0c
1106 #define CVT_NEG 0x20
1107 #define CVT_RI 0x08
1108
1109 static void
1110 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1111 int wp, unsigned cvn, unsigned fmt)
1112 {
1113 struct nv50_program_exec *e;
1114
1115 e = exec(pc);
1116 set_long(pc, e);
1117
1118 e->inst[0] |= 0xa0000000;
1119 e->inst[1] |= 0x00004000; /* 32 bit src */
1120 e->inst[1] |= (cvn << 16);
1121 e->inst[1] |= (fmt << 24);
1122 set_src_0(pc, src, e);
1123
1124 if (wp >= 0)
1125 set_pred_wr(pc, 1, wp, e);
1126
1127 if (dst)
1128 set_dst(pc, dst, e);
1129 else {
1130 e->inst[0] |= 0x000001fc;
1131 e->inst[1] |= 0x00000008;
1132 }
1133
1134 emit(pc, e);
1135 }
1136
1137 /* nv50 Condition codes:
1138 * 0x1 = LT
1139 * 0x2 = EQ
1140 * 0x3 = LE
1141 * 0x4 = GT
1142 * 0x5 = NE
1143 * 0x6 = GE
1144 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1145 * 0x8 = unordered bit (allows NaN)
1146 */
1147 static void
1148 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1149 struct nv50_reg *src0, struct nv50_reg *src1)
1150 {
1151 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1152
1153 struct nv50_program_exec *e = exec(pc);
1154 struct nv50_reg *rdst;
1155
1156 assert(ccode < 16);
1157 if (check_swap_src_0_1(pc, &src0, &src1))
1158 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1159
1160 rdst = dst;
1161 if (dst && dst->type != P_TEMP)
1162 dst = alloc_temp(pc, NULL);
1163
1164 /* set.u32 */
1165 set_long(pc, e);
1166 e->inst[0] |= 0xb0000000;
1167 e->inst[1] |= 0x60000000 | (ccode << 14);
1168
1169 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
1170 * that doesn't seem to match what the hw actually does
1171 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
1172 */
1173
1174 if (wp >= 0)
1175 set_pred_wr(pc, 1, wp, e);
1176 if (dst)
1177 set_dst(pc, dst, e);
1178 else {
1179 e->inst[0] |= 0x000001fc;
1180 e->inst[1] |= 0x00000008;
1181 }
1182
1183 set_src_0(pc, src0, e);
1184 set_src_1(pc, src1, e);
1185
1186 emit(pc, e);
1187 pc->if_cond = pc->p->exec_tail; /* record for OPCODE_IF */
1188
1189 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
1190 if (rdst)
1191 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
1192 if (rdst && rdst != dst)
1193 free_temp(pc, dst);
1194 }
1195
1196 static INLINE unsigned
1197 map_tgsi_setop_cc(unsigned op)
1198 {
1199 switch (op) {
1200 case TGSI_OPCODE_SLT: return 0x1;
1201 case TGSI_OPCODE_SGE: return 0x6;
1202 case TGSI_OPCODE_SEQ: return 0x2;
1203 case TGSI_OPCODE_SGT: return 0x4;
1204 case TGSI_OPCODE_SLE: return 0x3;
1205 case TGSI_OPCODE_SNE: return 0xd;
1206 default:
1207 assert(0);
1208 return 0;
1209 }
1210 }
1211
1212 static INLINE void
1213 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1214 {
1215 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
1216 }
1217
1218 static void
1219 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1220 struct nv50_reg *v, struct nv50_reg *e)
1221 {
1222 struct nv50_reg *temp = alloc_temp(pc, NULL);
1223
1224 emit_flop(pc, 3, temp, v);
1225 emit_mul(pc, temp, temp, e);
1226 emit_preex2(pc, temp, temp);
1227 emit_flop(pc, 6, dst, temp);
1228
1229 free_temp(pc, temp);
1230 }
1231
1232 static INLINE void
1233 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1234 {
1235 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
1236 }
1237
1238 static INLINE void
1239 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1240 {
1241 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
1242 }
1243
1244 static void
1245 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1246 struct nv50_reg **src)
1247 {
1248 struct nv50_reg *one = alloc_immd(pc, 1.0);
1249 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1250 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1251 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1252 struct nv50_reg *tmp[4];
1253 boolean allow32 = pc->allow32;
1254
1255 pc->allow32 = FALSE;
1256
1257 if (mask & (3 << 1)) {
1258 tmp[0] = alloc_temp(pc, NULL);
1259 emit_minmax(pc, 4, tmp[0], src[0], zero);
1260 }
1261
1262 if (mask & (1 << 2)) {
1263 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1264
1265 tmp[1] = temp_temp(pc);
1266 emit_minmax(pc, 4, tmp[1], src[1], zero);
1267
1268 tmp[3] = temp_temp(pc);
1269 emit_minmax(pc, 4, tmp[3], src[3], neg128);
1270 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
1271
1272 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1273 emit_mov(pc, dst[2], zero);
1274 set_pred(pc, 3, 0, pc->p->exec_tail);
1275 }
1276
1277 if (mask & (1 << 1))
1278 assimilate_temp(pc, dst[1], tmp[0]);
1279 else
1280 if (mask & (1 << 2))
1281 free_temp(pc, tmp[0]);
1282
1283 pc->allow32 = allow32;
1284
1285 /* do this last, in case src[i,j] == dst[0,3] */
1286 if (mask & (1 << 0))
1287 emit_mov(pc, dst[0], one);
1288
1289 if (mask & (1 << 3))
1290 emit_mov(pc, dst[3], one);
1291
1292 FREE(pos128);
1293 FREE(neg128);
1294 FREE(zero);
1295 FREE(one);
1296 }
1297
1298 static INLINE void
1299 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1300 {
1301 emit_cvt(pc, dst, src, -1, CVTOP_RN, CVT_F32_F32 | CVT_NEG);
1302 }
1303
1304 static void
1305 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1306 {
1307 struct nv50_program_exec *e;
1308 const int r_pred = 1;
1309 unsigned cvn = CVT_F32_F32;
1310
1311 if (src->mod & NV50_MOD_NEG)
1312 cvn |= CVT_NEG;
1313 /* write predicate reg */
1314 emit_cvt(pc, NULL, src, r_pred, CVTOP_RN, cvn);
1315
1316 /* conditional discard */
1317 e = exec(pc);
1318 e->inst[0] = 0x00000002;
1319 set_long(pc, e);
1320 set_pred(pc, 0x1 /* LT */, r_pred, e);
1321 emit(pc, e);
1322 }
1323
1324 static struct nv50_program_exec *
1325 emit_branch(struct nv50_pc *pc, int pred, unsigned cc,
1326 struct nv50_program_exec **join)
1327 {
1328 struct nv50_program_exec *e = exec(pc);
1329
1330 if (join) {
1331 set_long(pc, e);
1332 e->inst[0] |= 0xa0000002;
1333 emit(pc, e);
1334 *join = e;
1335 e = exec(pc);
1336 }
1337
1338 set_long(pc, e);
1339 e->inst[0] |= 0x10000002;
1340 if (pred >= 0)
1341 set_pred(pc, cc, pred, e);
1342 emit(pc, e);
1343 return pc->p->exec_tail;
1344 }
1345
1346 #define QOP_ADD 0
1347 #define QOP_SUBR 1
1348 #define QOP_SUB 2
1349 #define QOP_MOV_SRC1 3
1350
1351 /* For a quad of threads / top left, top right, bottom left, bottom right
1352 * pixels, do a different operation, and take src0 from a specific thread.
1353 */
1354 static void
1355 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1356 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1357 {
1358 struct nv50_program_exec *e = exec(pc);
1359
1360 e->inst[0] = 0xc0000000;
1361 e->inst[1] = 0x80000000;
1362 set_long(pc, e);
1363 e->inst[0] |= lane_src0 << 16;
1364 set_src_0(pc, src0, e);
1365 set_src_2(pc, src1, e);
1366
1367 if (wp >= 0)
1368 set_pred_wr(pc, 1, wp, e);
1369
1370 if (dst)
1371 set_dst(pc, dst, e);
1372 else {
1373 e->inst[0] |= 0x000001fc;
1374 e->inst[1] |= 0x00000008;
1375 }
1376
1377 e->inst[0] |= (qop & 3) << 20;
1378 e->inst[1] |= (qop >> 2) << 22;
1379
1380 emit(pc, e);
1381 }
1382
1383 static void
1384 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1385 struct nv50_reg **src, unsigned arg, boolean proj)
1386 {
1387 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1388
1389 src[0]->mod |= NV50_MOD_ABS;
1390 src[1]->mod |= NV50_MOD_ABS;
1391 src[2]->mod |= NV50_MOD_ABS;
1392
1393 emit_minmax(pc, 4, t[2], src[0], src[1]);
1394 emit_minmax(pc, 4, t[2], src[2], t[2]);
1395
1396 src[0]->mod = mod[0];
1397 src[1]->mod = mod[1];
1398 src[2]->mod = mod[2];
1399
1400 if (proj && 0 /* looks more correct without this */)
1401 emit_mul(pc, t[2], t[2], src[3]);
1402 else
1403 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1404 emit_mov(pc, t[3], src[3]);
1405
1406 emit_flop(pc, 0, t[2], t[2]);
1407
1408 emit_mul(pc, t[0], src[0], t[2]);
1409 emit_mul(pc, t[1], src[1], t[2]);
1410 emit_mul(pc, t[2], src[2], t[2]);
1411 }
1412
1413 static void
1414 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1415 struct nv50_reg **src, unsigned dim, unsigned arg)
1416 {
1417 unsigned c, mode;
1418
1419 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1420 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1421
1422 t[3]->rhw = src[3]->rhw;
1423 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1424 emit_flop(pc, 0, t[3], t[3]);
1425
1426 for (c = 0; c < dim; ++c) {
1427 t[c]->rhw = src[c]->rhw;
1428 emit_interp(pc, t[c], t[3], mode);
1429 }
1430 if (arg != dim) { /* depth reference value */
1431 t[dim]->rhw = src[2]->rhw;
1432 emit_interp(pc, t[dim], t[3], mode);
1433 }
1434 } else {
1435 /* XXX: for some reason the blob sometimes uses MAD
1436 * (mad f32 $rX $rY $rZ neg $r63)
1437 */
1438 emit_flop(pc, 0, t[3], src[3]);
1439 for (c = 0; c < dim; ++c)
1440 emit_mul(pc, t[c], src[c], t[3]);
1441 if (arg != dim) /* depth reference value */
1442 emit_mul(pc, t[dim], src[2], t[3]);
1443 }
1444 }
1445
1446 static INLINE void
1447 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1448 {
1449 switch (type) {
1450 case TGSI_TEXTURE_1D:
1451 *arg = *dim = 1;
1452 break;
1453 case TGSI_TEXTURE_SHADOW1D:
1454 *dim = 1;
1455 *arg = 2;
1456 break;
1457 case TGSI_TEXTURE_UNKNOWN:
1458 case TGSI_TEXTURE_2D:
1459 case TGSI_TEXTURE_RECT:
1460 *arg = *dim = 2;
1461 break;
1462 case TGSI_TEXTURE_SHADOW2D:
1463 case TGSI_TEXTURE_SHADOWRECT:
1464 *dim = 2;
1465 *arg = 3;
1466 break;
1467 case TGSI_TEXTURE_3D:
1468 case TGSI_TEXTURE_CUBE:
1469 *dim = *arg = 3;
1470 break;
1471 default:
1472 assert(0);
1473 break;
1474 }
1475 }
1476
1477 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1478 * different LOD values, so branch off groups of equal LOD.
1479 */
1480 static void
1481 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1482 struct nv50_reg *src, struct nv50_program_exec *tex)
1483 {
1484 struct nv50_program_exec *join_at;
1485 unsigned i, target = pc->p->exec_size + 7 * 2;
1486
1487 /* Subtract lod of each pixel from lod of top left pixel, jump
1488 * texlod insn if result is 0, then repeat for 2 other pixels.
1489 */
1490 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1491 emit_branch(pc, 0, 2, &join_at)->param.index = target;
1492
1493 for (i = 1; i < 4; ++i) {
1494 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1495 emit_branch(pc, 0, 2, NULL)->param.index = target;
1496 }
1497
1498 emit_mov(pc, tlod, src); /* target */
1499 emit(pc, tex); /* texlod */
1500
1501 join_at->param.index = target + 2 * 2;
1502 emit_nop(pc);
1503 pc->p->exec_tail->inst[1] |= 2; /* join _after_ tex */
1504 }
1505
1506 static void
1507 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1508 struct nv50_program_exec *tex)
1509 {
1510 struct nv50_program_exec *e;
1511 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1512 int r_pred = 0;
1513 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1514
1515 pc->allow32 = FALSE;
1516 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1517
1518 /* Subtract bias value of thread i from bias values of each thread,
1519 * store result in r_pred, and set bit i in r_bits if result was 0.
1520 */
1521 assert(arg < 4);
1522 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1523 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1524 emit_mov(pc, r_bits, &imm_1248);
1525 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1526 }
1527 emit_mov_to_pred(pc, r_pred, r_bits);
1528
1529 /* The lanes of a quad are now grouped by the bit in r_pred they have
1530 * set. Put the input values for TEX into a new register set for each
1531 * group and execute TEX only for a specific group.
1532 * We cannot use the same register set for each group because we need
1533 * the derivatives, which are implicitly calculated, to be correct.
1534 */
1535 for (i = 1; i < 4; ++i) {
1536 alloc_temp4(pc, t123[i], 0);
1537
1538 for (c = 0; c <= arg; ++c)
1539 emit_mov(pc, t123[i][c], t[c]);
1540
1541 *(e = exec(pc)) = *(tex);
1542 e->inst[0] &= ~0x01fc;
1543 set_dst(pc, t123[i][0], e);
1544 set_pred(pc, cc[i], r_pred, e);
1545 emit(pc, e);
1546 }
1547 /* finally TEX on the original regs (where we kept the input) */
1548 set_pred(pc, cc[0], r_pred, tex);
1549 emit(pc, tex);
1550
1551 /* put the 3 * n other results into regs for lane 0 */
1552 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1553 for (i = 1; i < 4; ++i) {
1554 for (c = 0; c < n; ++c) {
1555 emit_mov(pc, t[c], t123[i][c]);
1556 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1557 }
1558 free_temp4(pc, t123[i]);
1559 }
1560
1561 emit_nop(pc);
1562 free_temp(pc, r_bits);
1563 }
1564
1565 static void
1566 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1567 struct nv50_reg **src, unsigned unit, unsigned type,
1568 boolean proj, int bias_lod)
1569 {
1570 struct nv50_reg *t[4];
1571 struct nv50_program_exec *e;
1572 unsigned c, dim, arg;
1573
1574 /* t[i] must be within a single 128 bit super-reg */
1575 alloc_temp4(pc, t, 0);
1576
1577 e = exec(pc);
1578 e->inst[0] = 0xf0000000;
1579 set_long(pc, e);
1580 set_dst(pc, t[0], e);
1581
1582 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1583 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1584
1585 /* live flag (don't set if TEX results affect input to another TEX): */
1586 /* e->inst[0] |= 0x00000004; */
1587
1588 get_tex_dim(type, &dim, &arg);
1589
1590 if (type == TGSI_TEXTURE_CUBE) {
1591 e->inst[0] |= 0x08000000;
1592 load_cube_tex_coords(pc, t, src, arg, proj);
1593 } else
1594 if (proj)
1595 load_proj_tex_coords(pc, t, src, dim, arg);
1596 else {
1597 for (c = 0; c < dim; c++)
1598 emit_mov(pc, t[c], src[c]);
1599 if (arg != dim) /* depth reference value (always src.z here) */
1600 emit_mov(pc, t[dim], src[2]);
1601 }
1602
1603 e->inst[0] |= (mask & 0x3) << 25;
1604 e->inst[1] |= (mask & 0xc) << 12;
1605
1606 if (!bias_lod) {
1607 e->inst[0] |= (arg - 1) << 22;
1608 emit(pc, e);
1609 } else
1610 if (bias_lod < 0) {
1611 e->inst[0] |= arg << 22;
1612 e->inst[1] |= 0x20000000; /* texbias */
1613 emit_mov(pc, t[arg], src[3]);
1614 emit_texbias_sequence(pc, t, arg, e);
1615 } else {
1616 e->inst[0] |= arg << 22;
1617 e->inst[1] |= 0x40000000; /* texlod */
1618 emit_mov(pc, t[arg], src[3]);
1619 emit_texlod_sequence(pc, t[arg], src[3], e);
1620 }
1621
1622 #if 1
1623 c = 0;
1624 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
1625 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
1626 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
1627 if (mask & 8) emit_mov(pc, dst[3], t[c]);
1628
1629 free_temp4(pc, t);
1630 #else
1631 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1632 * the texture coordinates, not the fetched values: latency ? */
1633
1634 for (c = 0; c < 4; c++) {
1635 if (mask & (1 << c))
1636 assimilate_temp(pc, dst[c], t[c]);
1637 else
1638 free_temp(pc, t[c]);
1639 }
1640 #endif
1641 }
1642
1643 static void
1644 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1645 {
1646 struct nv50_program_exec *e = exec(pc);
1647
1648 assert(src->type == P_TEMP);
1649
1650 e->inst[0] = 0xc0140000;
1651 e->inst[1] = 0x89800000;
1652 set_long(pc, e);
1653 set_dst(pc, dst, e);
1654 set_src_0(pc, src, e);
1655 set_src_2(pc, src, e);
1656
1657 emit(pc, e);
1658 }
1659
1660 static void
1661 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1662 {
1663 struct nv50_reg *r = src;
1664 struct nv50_program_exec *e = exec(pc);
1665
1666 assert(src->type == P_TEMP);
1667
1668 if (!(src->mod & NV50_MOD_NEG)) { /* ! double negation */
1669 r = alloc_temp(pc, NULL);
1670 emit_neg(pc, r, src);
1671 }
1672
1673 e->inst[0] = 0xc0150000;
1674 e->inst[1] = 0x8a400000;
1675 set_long(pc, e);
1676 set_dst(pc, dst, e);
1677 set_src_0(pc, r, e);
1678 set_src_2(pc, r, e);
1679
1680 if (r != src)
1681 free_temp(pc, r);
1682
1683 emit(pc, e);
1684 }
1685
1686 static void
1687 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1688 {
1689 unsigned q = 0, m = ~0;
1690
1691 assert(!is_long(e));
1692
1693 switch (e->inst[0] >> 28) {
1694 case 0x1:
1695 /* MOV */
1696 q = 0x0403c000;
1697 m = 0xffff7fff;
1698 break;
1699 case 0x8:
1700 /* INTERP (move centroid, perspective and flat bits) */
1701 m = ~0x03000100;
1702 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1703 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1704 break;
1705 case 0x9:
1706 /* RCP */
1707 break;
1708 case 0xB:
1709 /* ADD */
1710 m = ~(127 << 16);
1711 q = ((e->inst[0] & (~m)) >> 2);
1712 break;
1713 case 0xC:
1714 /* MUL */
1715 m = ~0x00008000;
1716 q = ((e->inst[0] & (~m)) << 12);
1717 break;
1718 case 0xE:
1719 /* MAD (if src2 == dst) */
1720 q = ((e->inst[0] & 0x1fc) << 12);
1721 break;
1722 default:
1723 assert(0);
1724 break;
1725 }
1726
1727 set_long(pc, e);
1728 pc->p->exec_size++;
1729
1730 e->inst[0] &= m;
1731 e->inst[1] |= q;
1732 }
1733
1734 /* Some operations support an optional negation flag. */
1735 static boolean
1736 negate_supported(const struct tgsi_full_instruction *insn, int i)
1737 {
1738 switch (insn->Instruction.Opcode) {
1739 case TGSI_OPCODE_DDY:
1740 case TGSI_OPCODE_DP3:
1741 case TGSI_OPCODE_DP4:
1742 case TGSI_OPCODE_MUL:
1743 case TGSI_OPCODE_KIL:
1744 case TGSI_OPCODE_ADD:
1745 case TGSI_OPCODE_SUB:
1746 case TGSI_OPCODE_MAD:
1747 return TRUE;
1748 case TGSI_OPCODE_POW:
1749 if (i == 1)
1750 return TRUE;
1751 return FALSE;
1752 default:
1753 return FALSE;
1754 }
1755 }
1756
1757 /* Return a read mask for source registers deduced from opcode & write mask. */
1758 static unsigned
1759 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1760 {
1761 unsigned x, mask = insn->Dst[0].Register.WriteMask;
1762
1763 switch (insn->Instruction.Opcode) {
1764 case TGSI_OPCODE_COS:
1765 case TGSI_OPCODE_SIN:
1766 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1767 case TGSI_OPCODE_DP3:
1768 return 0x7;
1769 case TGSI_OPCODE_DP4:
1770 case TGSI_OPCODE_DPH:
1771 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1772 return 0xf;
1773 case TGSI_OPCODE_DST:
1774 return mask & (c ? 0xa : 0x6);
1775 case TGSI_OPCODE_EX2:
1776 case TGSI_OPCODE_LG2:
1777 case TGSI_OPCODE_POW:
1778 case TGSI_OPCODE_RCP:
1779 case TGSI_OPCODE_RSQ:
1780 case TGSI_OPCODE_SCS:
1781 return 0x1;
1782 case TGSI_OPCODE_IF:
1783 return 0x1;
1784 case TGSI_OPCODE_LIT:
1785 return 0xb;
1786 case TGSI_OPCODE_TEX:
1787 case TGSI_OPCODE_TXB:
1788 case TGSI_OPCODE_TXL:
1789 case TGSI_OPCODE_TXP:
1790 {
1791 const struct tgsi_instruction_texture *tex;
1792
1793 assert(insn->Instruction.Texture);
1794 tex = &insn->Texture;
1795
1796 mask = 0x7;
1797 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
1798 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
1799 mask |= 0x8; /* bias, lod or proj */
1800
1801 switch (tex->Texture) {
1802 case TGSI_TEXTURE_1D:
1803 mask &= 0x9;
1804 break;
1805 case TGSI_TEXTURE_SHADOW1D:
1806 mask &= 0x5;
1807 break;
1808 case TGSI_TEXTURE_2D:
1809 mask &= 0xb;
1810 break;
1811 default:
1812 break;
1813 }
1814 }
1815 return mask;
1816 case TGSI_OPCODE_XPD:
1817 x = 0;
1818 if (mask & 1) x |= 0x6;
1819 if (mask & 2) x |= 0x5;
1820 if (mask & 4) x |= 0x3;
1821 return x;
1822 default:
1823 break;
1824 }
1825
1826 return mask;
1827 }
1828
1829 static struct nv50_reg *
1830 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1831 {
1832 switch (dst->Register.File) {
1833 case TGSI_FILE_TEMPORARY:
1834 return &pc->temp[dst->Register.Index * 4 + c];
1835 case TGSI_FILE_OUTPUT:
1836 return &pc->result[dst->Register.Index * 4 + c];
1837 case TGSI_FILE_ADDRESS:
1838 {
1839 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
1840 if (!r) {
1841 r = alloc_addr(pc, NULL);
1842 pc->addr[dst->Register.Index * 4 + c] = r;
1843 }
1844 assert(r);
1845 return r;
1846 }
1847 case TGSI_FILE_NULL:
1848 return NULL;
1849 default:
1850 break;
1851 }
1852
1853 return NULL;
1854 }
1855
1856 static struct nv50_reg *
1857 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1858 boolean neg)
1859 {
1860 struct nv50_reg *r = NULL;
1861 struct nv50_reg *temp;
1862 unsigned sgn, c, swz;
1863
1864 if (src->Register.File != TGSI_FILE_CONSTANT)
1865 assert(!src->Register.Indirect);
1866
1867 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1868
1869 c = tgsi_util_get_full_src_register_swizzle(src, chan);
1870 switch (c) {
1871 case TGSI_SWIZZLE_X:
1872 case TGSI_SWIZZLE_Y:
1873 case TGSI_SWIZZLE_Z:
1874 case TGSI_SWIZZLE_W:
1875 switch (src->Register.File) {
1876 case TGSI_FILE_INPUT:
1877 r = &pc->attr[src->Register.Index * 4 + c];
1878 break;
1879 case TGSI_FILE_TEMPORARY:
1880 r = &pc->temp[src->Register.Index * 4 + c];
1881 break;
1882 case TGSI_FILE_CONSTANT:
1883 if (!src->Register.Indirect) {
1884 r = &pc->param[src->Register.Index * 4 + c];
1885 break;
1886 }
1887 /* Indicate indirection by setting r->acc < 0 and
1888 * use the index field to select the address reg.
1889 */
1890 r = reg_instance(pc, NULL);
1891 swz = tgsi_util_get_src_register_swizzle(
1892 &src->Indirect, 0);
1893 ctor_reg(r, P_CONST,
1894 src->Indirect.Index * 4 + swz,
1895 src->Register.Index * 4 + c);
1896 r->acc = -1;
1897 break;
1898 case TGSI_FILE_IMMEDIATE:
1899 r = &pc->immd[src->Register.Index * 4 + c];
1900 break;
1901 case TGSI_FILE_SAMPLER:
1902 break;
1903 case TGSI_FILE_ADDRESS:
1904 r = pc->addr[src->Register.Index * 4 + c];
1905 assert(r);
1906 break;
1907 default:
1908 assert(0);
1909 break;
1910 }
1911 break;
1912 default:
1913 assert(0);
1914 break;
1915 }
1916
1917 switch (sgn) {
1918 case TGSI_UTIL_SIGN_KEEP:
1919 break;
1920 case TGSI_UTIL_SIGN_CLEAR:
1921 temp = temp_temp(pc);
1922 emit_abs(pc, temp, r);
1923 r = temp;
1924 break;
1925 case TGSI_UTIL_SIGN_TOGGLE:
1926 if (neg)
1927 r->mod = NV50_MOD_NEG;
1928 else {
1929 temp = temp_temp(pc);
1930 emit_neg(pc, temp, r);
1931 r = temp;
1932 }
1933 break;
1934 case TGSI_UTIL_SIGN_SET:
1935 temp = temp_temp(pc);
1936 emit_cvt(pc, temp, r, -1, CVTOP_ABS, CVT_F32_F32 | CVT_NEG);
1937 r = temp;
1938 break;
1939 default:
1940 assert(0);
1941 break;
1942 }
1943
1944 if (r && r->acc >= 0 && r != temp)
1945 return reg_instance(pc, r);
1946 return r;
1947 }
1948
1949 /* return TRUE for ops that produce only a single result */
1950 static boolean
1951 is_scalar_op(unsigned op)
1952 {
1953 switch (op) {
1954 case TGSI_OPCODE_COS:
1955 case TGSI_OPCODE_DP2:
1956 case TGSI_OPCODE_DP3:
1957 case TGSI_OPCODE_DP4:
1958 case TGSI_OPCODE_DPH:
1959 case TGSI_OPCODE_EX2:
1960 case TGSI_OPCODE_LG2:
1961 case TGSI_OPCODE_POW:
1962 case TGSI_OPCODE_RCP:
1963 case TGSI_OPCODE_RSQ:
1964 case TGSI_OPCODE_SIN:
1965 /*
1966 case TGSI_OPCODE_KIL:
1967 case TGSI_OPCODE_LIT:
1968 case TGSI_OPCODE_SCS:
1969 */
1970 return TRUE;
1971 default:
1972 return FALSE;
1973 }
1974 }
1975
1976 /* Returns a bitmask indicating which dst components depend
1977 * on source s, component c (reverse of nv50_tgsi_src_mask).
1978 */
1979 static unsigned
1980 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
1981 {
1982 if (is_scalar_op(op))
1983 return 0x1;
1984
1985 switch (op) {
1986 case TGSI_OPCODE_DST:
1987 return (1 << c) & (s ? 0xa : 0x6);
1988 case TGSI_OPCODE_XPD:
1989 switch (c) {
1990 case 0: return 0x6;
1991 case 1: return 0x5;
1992 case 2: return 0x3;
1993 case 3: return 0x0;
1994 default:
1995 assert(0);
1996 return 0x0;
1997 }
1998 case TGSI_OPCODE_LIT:
1999 case TGSI_OPCODE_SCS:
2000 case TGSI_OPCODE_TEX:
2001 case TGSI_OPCODE_TXB:
2002 case TGSI_OPCODE_TXL:
2003 case TGSI_OPCODE_TXP:
2004 /* these take care of dangerous swizzles themselves */
2005 return 0x0;
2006 case TGSI_OPCODE_IF:
2007 case TGSI_OPCODE_KIL:
2008 /* don't call this function for these ops */
2009 assert(0);
2010 return 0;
2011 default:
2012 /* linear vector instruction */
2013 return (1 << c);
2014 }
2015 }
2016
2017 static INLINE boolean
2018 has_pred(struct nv50_program_exec *e, unsigned cc)
2019 {
2020 if (!is_long(e) || is_immd(e))
2021 return FALSE;
2022 return ((e->inst[1] & 0x780) == (cc << 7));
2023 }
2024
2025 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2026 * join_at ENDIF
2027 * @p0.eq bra ENDIF
2028 * single_op
2029 * ENDIF: nop.join
2030 */
2031 static boolean
2032 nv50_kill_branch(struct nv50_pc *pc)
2033 {
2034 int lvl = pc->if_lvl;
2035
2036 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2037 return FALSE;
2038
2039 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2040 * reg may no longer be valid, since we currently always use $p0
2041 */
2042 if (has_pred(pc->if_insn[lvl], 0xf))
2043 return FALSE;
2044 assert(pc->if_insn[lvl] && pc->br_join[lvl]);
2045
2046 /* We'll use the exec allocated for JOIN_AT (as we can't easily
2047 * update prev's next); if exec_tail is BRK, update the pointer.
2048 */
2049 if (pc->loop_lvl && pc->br_loop[pc->loop_lvl - 1] == pc->p->exec_tail)
2050 pc->br_loop[pc->loop_lvl - 1] = pc->br_join[lvl];
2051
2052 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2053
2054 *pc->br_join[lvl] = *pc->p->exec_tail;
2055
2056 FREE(pc->if_insn[lvl]);
2057 FREE(pc->p->exec_tail);
2058
2059 pc->p->exec_tail = pc->br_join[lvl];
2060 pc->p->exec_tail->next = NULL;
2061 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2062
2063 return TRUE;
2064 }
2065
2066 static boolean
2067 nv50_program_tx_insn(struct nv50_pc *pc,
2068 const struct tgsi_full_instruction *inst)
2069 {
2070 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2071 unsigned mask, sat, unit;
2072 int i, c;
2073
2074 mask = inst->Dst[0].Register.WriteMask;
2075 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2076
2077 memset(src, 0, sizeof(src));
2078
2079 for (c = 0; c < 4; c++) {
2080 if ((mask & (1 << c)) && !pc->r_dst[c])
2081 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2082 else
2083 dst[c] = pc->r_dst[c];
2084 rdst[c] = dst[c];
2085 }
2086
2087 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2088 const struct tgsi_full_src_register *fs = &inst->Src[i];
2089 unsigned src_mask;
2090 boolean neg_supp;
2091
2092 src_mask = nv50_tgsi_src_mask(inst, i);
2093 neg_supp = negate_supported(inst, i);
2094
2095 if (fs->Register.File == TGSI_FILE_SAMPLER)
2096 unit = fs->Register.Index;
2097
2098 for (c = 0; c < 4; c++)
2099 if (src_mask & (1 << c))
2100 src[i][c] = tgsi_src(pc, c, fs, neg_supp);
2101 }
2102
2103 brdc = temp = pc->r_brdc;
2104 if (brdc && brdc->type != P_TEMP) {
2105 temp = temp_temp(pc);
2106 if (sat)
2107 brdc = temp;
2108 } else
2109 if (sat) {
2110 for (c = 0; c < 4; c++) {
2111 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2112 continue;
2113 /* rdst[c] = dst[c]; */ /* done above */
2114 dst[c] = temp_temp(pc);
2115 }
2116 }
2117
2118 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2119
2120 switch (inst->Instruction.Opcode) {
2121 case TGSI_OPCODE_ABS:
2122 for (c = 0; c < 4; c++) {
2123 if (!(mask & (1 << c)))
2124 continue;
2125 emit_abs(pc, dst[c], src[0][c]);
2126 }
2127 break;
2128 case TGSI_OPCODE_ADD:
2129 for (c = 0; c < 4; c++) {
2130 if (!(mask & (1 << c)))
2131 continue;
2132 emit_add(pc, dst[c], src[0][c], src[1][c]);
2133 }
2134 break;
2135 case TGSI_OPCODE_AND:
2136 case TGSI_OPCODE_XOR:
2137 case TGSI_OPCODE_OR:
2138 for (c = 0; c < 4; c++) {
2139 if (!(mask & (1 << c)))
2140 continue;
2141 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2142 inst->Instruction.Opcode);
2143 }
2144 break;
2145 case TGSI_OPCODE_ARL:
2146 assert(src[0][0]);
2147 temp = temp_temp(pc);
2148 emit_cvt(pc, temp, src[0][0], -1, CVTOP_FLOOR, CVT_S32_F32);
2149 emit_arl(pc, dst[0], temp, 4);
2150 break;
2151 case TGSI_OPCODE_BGNLOOP:
2152 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2153 terminate_mbb(pc);
2154 break;
2155 case TGSI_OPCODE_BRK:
2156 emit_branch(pc, -1, 0, NULL);
2157 assert(pc->loop_lvl > 0);
2158 pc->br_loop[pc->loop_lvl - 1] = pc->p->exec_tail;
2159 break;
2160 case TGSI_OPCODE_CEIL:
2161 for (c = 0; c < 4; c++) {
2162 if (!(mask & (1 << c)))
2163 continue;
2164 emit_cvt(pc, dst[c], src[0][c], -1,
2165 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
2166 }
2167 break;
2168 case TGSI_OPCODE_CMP:
2169 pc->allow32 = FALSE;
2170 for (c = 0; c < 4; c++) {
2171 if (!(mask & (1 << c)))
2172 continue;
2173 emit_cvt(pc, NULL, src[0][c], 1, CVTOP_RN, CVT_F32_F32);
2174 emit_mov(pc, dst[c], src[1][c]);
2175 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2176 emit_mov(pc, dst[c], src[2][c]);
2177 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2178 }
2179 break;
2180 case TGSI_OPCODE_COS:
2181 if (mask & 8) {
2182 emit_precossin(pc, temp, src[0][3]);
2183 emit_flop(pc, 5, dst[3], temp);
2184 if (!(mask &= 7))
2185 break;
2186 if (temp == dst[3])
2187 temp = brdc = temp_temp(pc);
2188 }
2189 emit_precossin(pc, temp, src[0][0]);
2190 emit_flop(pc, 5, brdc, temp);
2191 break;
2192 case TGSI_OPCODE_DDX:
2193 for (c = 0; c < 4; c++) {
2194 if (!(mask & (1 << c)))
2195 continue;
2196 emit_ddx(pc, dst[c], src[0][c]);
2197 }
2198 break;
2199 case TGSI_OPCODE_DDY:
2200 for (c = 0; c < 4; c++) {
2201 if (!(mask & (1 << c)))
2202 continue;
2203 emit_ddy(pc, dst[c], src[0][c]);
2204 }
2205 break;
2206 case TGSI_OPCODE_DP3:
2207 emit_mul(pc, temp, src[0][0], src[1][0]);
2208 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2209 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2210 break;
2211 case TGSI_OPCODE_DP4:
2212 emit_mul(pc, temp, src[0][0], src[1][0]);
2213 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2214 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2215 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2216 break;
2217 case TGSI_OPCODE_DPH:
2218 emit_mul(pc, temp, src[0][0], src[1][0]);
2219 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2220 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2221 emit_add(pc, brdc, src[1][3], temp);
2222 break;
2223 case TGSI_OPCODE_DST:
2224 if (mask & (1 << 1))
2225 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2226 if (mask & (1 << 2))
2227 emit_mov(pc, dst[2], src[0][2]);
2228 if (mask & (1 << 3))
2229 emit_mov(pc, dst[3], src[1][3]);
2230 if (mask & (1 << 0))
2231 emit_mov_immdval(pc, dst[0], 1.0f);
2232 break;
2233 case TGSI_OPCODE_ELSE:
2234 emit_branch(pc, -1, 0, NULL);
2235 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2236 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2237 terminate_mbb(pc);
2238 break;
2239 case TGSI_OPCODE_ENDIF:
2240 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2241
2242 /* try to replace branch over 1 insn with a predicated insn */
2243 if (nv50_kill_branch(pc) == TRUE)
2244 break;
2245
2246 if (pc->br_join[pc->if_lvl]) {
2247 pc->br_join[pc->if_lvl]->param.index = pc->p->exec_size;
2248 pc->br_join[pc->if_lvl] = NULL;
2249 }
2250 terminate_mbb(pc);
2251 /* emit a NOP as join point, we could set it on the next
2252 * one, but would have to make sure it is long and !immd
2253 */
2254 emit_nop(pc);
2255 pc->p->exec_tail->inst[1] |= 2;
2256 break;
2257 case TGSI_OPCODE_ENDLOOP:
2258 emit_branch(pc, -1, 0, NULL);
2259 pc->p->exec_tail->param.index = pc->loop_pos[--pc->loop_lvl];
2260 pc->br_loop[pc->loop_lvl]->param.index = pc->p->exec_size;
2261 terminate_mbb(pc);
2262 break;
2263 case TGSI_OPCODE_EX2:
2264 emit_preex2(pc, temp, src[0][0]);
2265 emit_flop(pc, 6, brdc, temp);
2266 break;
2267 case TGSI_OPCODE_FLR:
2268 for (c = 0; c < 4; c++) {
2269 if (!(mask & (1 << c)))
2270 continue;
2271 emit_flr(pc, dst[c], src[0][c]);
2272 }
2273 break;
2274 case TGSI_OPCODE_FRC:
2275 temp = temp_temp(pc);
2276 for (c = 0; c < 4; c++) {
2277 if (!(mask & (1 << c)))
2278 continue;
2279 emit_flr(pc, temp, src[0][c]);
2280 emit_sub(pc, dst[c], src[0][c], temp);
2281 }
2282 break;
2283 case TGSI_OPCODE_IF:
2284 /* emitting a join_at may not be necessary */
2285 assert(pc->if_lvl < MAX_IF_DEPTH);
2286 /* set_pred_wr(pc, 1, 0, pc->if_cond); */
2287 emit_cvt(pc, NULL, src[0][0], 0, CVTOP_ABS | CVTOP_RN,
2288 CVT_F32_F32);
2289 emit_branch(pc, 0, 2, &pc->br_join[pc->if_lvl]);
2290 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2291 terminate_mbb(pc);
2292 break;
2293 case TGSI_OPCODE_KIL:
2294 emit_kil(pc, src[0][0]);
2295 emit_kil(pc, src[0][1]);
2296 emit_kil(pc, src[0][2]);
2297 emit_kil(pc, src[0][3]);
2298 break;
2299 case TGSI_OPCODE_LIT:
2300 emit_lit(pc, &dst[0], mask, &src[0][0]);
2301 break;
2302 case TGSI_OPCODE_LG2:
2303 emit_flop(pc, 3, brdc, src[0][0]);
2304 break;
2305 case TGSI_OPCODE_LRP:
2306 temp = temp_temp(pc);
2307 for (c = 0; c < 4; c++) {
2308 if (!(mask & (1 << c)))
2309 continue;
2310 emit_sub(pc, temp, src[1][c], src[2][c]);
2311 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2312 }
2313 break;
2314 case TGSI_OPCODE_MAD:
2315 for (c = 0; c < 4; c++) {
2316 if (!(mask & (1 << c)))
2317 continue;
2318 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2319 }
2320 break;
2321 case TGSI_OPCODE_MAX:
2322 for (c = 0; c < 4; c++) {
2323 if (!(mask & (1 << c)))
2324 continue;
2325 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
2326 }
2327 break;
2328 case TGSI_OPCODE_MIN:
2329 for (c = 0; c < 4; c++) {
2330 if (!(mask & (1 << c)))
2331 continue;
2332 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
2333 }
2334 break;
2335 case TGSI_OPCODE_MOV:
2336 for (c = 0; c < 4; c++) {
2337 if (!(mask & (1 << c)))
2338 continue;
2339 emit_mov(pc, dst[c], src[0][c]);
2340 }
2341 break;
2342 case TGSI_OPCODE_MUL:
2343 for (c = 0; c < 4; c++) {
2344 if (!(mask & (1 << c)))
2345 continue;
2346 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2347 }
2348 break;
2349 case TGSI_OPCODE_POW:
2350 emit_pow(pc, brdc, src[0][0], src[1][0]);
2351 break;
2352 case TGSI_OPCODE_RCP:
2353 emit_flop(pc, 0, brdc, src[0][0]);
2354 break;
2355 case TGSI_OPCODE_RSQ:
2356 emit_flop(pc, 2, brdc, src[0][0]);
2357 break;
2358 case TGSI_OPCODE_SCS:
2359 temp = temp_temp(pc);
2360 if (mask & 3)
2361 emit_precossin(pc, temp, src[0][0]);
2362 if (mask & (1 << 0))
2363 emit_flop(pc, 5, dst[0], temp);
2364 if (mask & (1 << 1))
2365 emit_flop(pc, 4, dst[1], temp);
2366 if (mask & (1 << 2))
2367 emit_mov_immdval(pc, dst[2], 0.0);
2368 if (mask & (1 << 3))
2369 emit_mov_immdval(pc, dst[3], 1.0);
2370 break;
2371 case TGSI_OPCODE_SIN:
2372 if (mask & 8) {
2373 emit_precossin(pc, temp, src[0][3]);
2374 emit_flop(pc, 4, dst[3], temp);
2375 if (!(mask &= 7))
2376 break;
2377 if (temp == dst[3])
2378 temp = brdc = temp_temp(pc);
2379 }
2380 emit_precossin(pc, temp, src[0][0]);
2381 emit_flop(pc, 4, brdc, temp);
2382 break;
2383 case TGSI_OPCODE_SLT:
2384 case TGSI_OPCODE_SGE:
2385 case TGSI_OPCODE_SEQ:
2386 case TGSI_OPCODE_SGT:
2387 case TGSI_OPCODE_SLE:
2388 case TGSI_OPCODE_SNE:
2389 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
2390 for (c = 0; c < 4; c++) {
2391 if (!(mask & (1 << c)))
2392 continue;
2393 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
2394 }
2395 break;
2396 case TGSI_OPCODE_SUB:
2397 for (c = 0; c < 4; c++) {
2398 if (!(mask & (1 << c)))
2399 continue;
2400 emit_sub(pc, dst[c], src[0][c], src[1][c]);
2401 }
2402 break;
2403 case TGSI_OPCODE_TEX:
2404 emit_tex(pc, dst, mask, src[0], unit,
2405 inst->Texture.Texture, FALSE, 0);
2406 break;
2407 case TGSI_OPCODE_TXB:
2408 emit_tex(pc, dst, mask, src[0], unit,
2409 inst->Texture.Texture, FALSE, -1);
2410 break;
2411 case TGSI_OPCODE_TXL:
2412 emit_tex(pc, dst, mask, src[0], unit,
2413 inst->Texture.Texture, FALSE, 1);
2414 break;
2415 case TGSI_OPCODE_TXP:
2416 emit_tex(pc, dst, mask, src[0], unit,
2417 inst->Texture.Texture, TRUE, 0);
2418 break;
2419 case TGSI_OPCODE_TRUNC:
2420 for (c = 0; c < 4; c++) {
2421 if (!(mask & (1 << c)))
2422 continue;
2423 emit_cvt(pc, dst[c], src[0][c], -1,
2424 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
2425 }
2426 break;
2427 case TGSI_OPCODE_XPD:
2428 temp = temp_temp(pc);
2429 if (mask & (1 << 0)) {
2430 emit_mul(pc, temp, src[0][2], src[1][1]);
2431 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
2432 }
2433 if (mask & (1 << 1)) {
2434 emit_mul(pc, temp, src[0][0], src[1][2]);
2435 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
2436 }
2437 if (mask & (1 << 2)) {
2438 emit_mul(pc, temp, src[0][1], src[1][0]);
2439 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
2440 }
2441 if (mask & (1 << 3))
2442 emit_mov_immdval(pc, dst[3], 1.0);
2443 break;
2444 case TGSI_OPCODE_END:
2445 break;
2446 default:
2447 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
2448 return FALSE;
2449 }
2450
2451 if (brdc) {
2452 if (sat)
2453 emit_sat(pc, brdc, brdc);
2454 for (c = 0; c < 4; c++)
2455 if ((mask & (1 << c)) && dst[c] != brdc)
2456 emit_mov(pc, dst[c], brdc);
2457 } else
2458 if (sat) {
2459 for (c = 0; c < 4; c++) {
2460 if (!(mask & (1 << c)))
2461 continue;
2462 /* In this case we saturate later, and dst[c] won't
2463 * be another temp_temp (and thus lost), since rdst
2464 * already is TEMP (see above). */
2465 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
2466 continue;
2467 emit_sat(pc, rdst[c], dst[c]);
2468 }
2469 }
2470
2471 kill_temp_temp(pc);
2472 pc->reg_instance_nr = 0;
2473
2474 return TRUE;
2475 }
2476
2477 static void
2478 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
2479 {
2480 struct nv50_reg *reg = NULL;
2481 const struct tgsi_full_src_register *src;
2482 const struct tgsi_dst_register *dst;
2483 unsigned i, c, k, mask;
2484
2485 dst = &insn->Dst[0].Register;
2486 mask = dst->WriteMask;
2487
2488 if (dst->File == TGSI_FILE_TEMPORARY)
2489 reg = pc->temp;
2490 else
2491 if (dst->File == TGSI_FILE_OUTPUT)
2492 reg = pc->result;
2493
2494 if (reg) {
2495 for (c = 0; c < 4; c++) {
2496 if (!(mask & (1 << c)))
2497 continue;
2498 reg[dst->Index * 4 + c].acc = pc->insn_nr;
2499 }
2500 }
2501
2502 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2503 src = &insn->Src[i];
2504
2505 if (src->Register.File == TGSI_FILE_TEMPORARY)
2506 reg = pc->temp;
2507 else
2508 if (src->Register.File == TGSI_FILE_INPUT)
2509 reg = pc->attr;
2510 else
2511 continue;
2512
2513 mask = nv50_tgsi_src_mask(insn, i);
2514
2515 for (c = 0; c < 4; c++) {
2516 if (!(mask & (1 << c)))
2517 continue;
2518 k = tgsi_util_get_full_src_register_swizzle(src, c);
2519
2520 reg[src->Register.Index * 4 + k].acc = pc->insn_nr;
2521 }
2522 }
2523 }
2524
2525 /* Returns a bitmask indicating which dst components need to be
2526 * written to temporaries first to avoid 'corrupting' sources.
2527 *
2528 * m[i] (out) indicate component to write in the i-th position
2529 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
2530 */
2531 static unsigned
2532 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
2533 {
2534 unsigned i, c, x, unsafe;
2535
2536 for (c = 0; c < 4; c++)
2537 m[c] = c;
2538
2539 /* Swap as long as a dst component written earlier is depended on
2540 * by one written later, but the next one isn't depended on by it.
2541 */
2542 for (c = 0; c < 3; c++) {
2543 if (rdep[m[c + 1]] & (1 << m[c]))
2544 continue; /* if next one is depended on by us */
2545 for (i = c + 1; i < 4; i++)
2546 /* if we are depended on by a later one */
2547 if (rdep[m[c]] & (1 << m[i]))
2548 break;
2549 if (i == 4)
2550 continue;
2551 /* now, swap */
2552 x = m[c];
2553 m[c] = m[c + 1];
2554 m[c + 1] = x;
2555
2556 /* restart */
2557 c = 0;
2558 }
2559
2560 /* mark dependencies that could not be resolved by reordering */
2561 for (i = 0; i < 3; ++i)
2562 for (c = i + 1; c < 4; ++c)
2563 if (rdep[m[i]] & (1 << m[c]))
2564 unsafe |= (1 << i);
2565
2566 /* NOTE: $unsafe is with respect to order, not component */
2567 return unsafe;
2568 }
2569
2570 /* Select a suitable dst register for broadcasting scalar results,
2571 * or return NULL if we have to allocate an extra TEMP.
2572 *
2573 * If e.g. only 1 component is written, we may also emit the final
2574 * result to a write-only register.
2575 */
2576 static struct nv50_reg *
2577 tgsi_broadcast_dst(struct nv50_pc *pc,
2578 const struct tgsi_full_dst_register *fd, unsigned mask)
2579 {
2580 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
2581 int c = ffs(~mask & fd->Register.WriteMask);
2582 if (c)
2583 return tgsi_dst(pc, c - 1, fd);
2584 } else {
2585 int c = ffs(fd->Register.WriteMask) - 1;
2586 if ((1 << c) == fd->Register.WriteMask)
2587 return tgsi_dst(pc, c, fd);
2588 }
2589
2590 return NULL;
2591 }
2592
2593 /* Scan source swizzles and return a bitmask indicating dst regs that
2594 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2595 */
2596 static unsigned
2597 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2598 unsigned rdep[4])
2599 {
2600 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
2601 const struct tgsi_full_src_register *fs;
2602 unsigned i, deqs = 0;
2603
2604 for (i = 0; i < 4; ++i)
2605 rdep[i] = 0;
2606
2607 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2608 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2609 boolean neg_supp = negate_supported(insn, i);
2610
2611 fs = &insn->Src[i];
2612 if (fs->Register.File != fd->Register.File ||
2613 fs->Register.Index != fd->Register.Index)
2614 continue;
2615
2616 for (chn = 0; chn < 4; ++chn) {
2617 unsigned s, c;
2618
2619 if (!(mask & (1 << chn))) /* src is not read */
2620 continue;
2621 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
2622 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2623
2624 if (!(fd->Register.WriteMask & (1 << c)))
2625 continue;
2626
2627 /* no danger if src is copied to TEMP first */
2628 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2629 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2630 continue;
2631
2632 rdep[c] |= nv50_tgsi_dst_revdep(
2633 insn->Instruction.Opcode, i, chn);
2634 deqs |= (1 << c);
2635 }
2636 }
2637
2638 return deqs;
2639 }
2640
2641 static boolean
2642 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2643 {
2644 struct tgsi_full_instruction insn = tok->FullInstruction;
2645 const struct tgsi_full_dst_register *fd;
2646 unsigned i, deqs, rdep[4], m[4];
2647
2648 fd = &tok->FullInstruction.Dst[0];
2649 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2650
2651 if (is_scalar_op(insn.Instruction.Opcode)) {
2652 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2653 if (!pc->r_brdc)
2654 pc->r_brdc = temp_temp(pc);
2655 return nv50_program_tx_insn(pc, &insn);
2656 }
2657 pc->r_brdc = NULL;
2658
2659 if (!deqs)
2660 return nv50_program_tx_insn(pc, &insn);
2661
2662 deqs = nv50_revdep_reorder(m, rdep);
2663
2664 for (i = 0; i < 4; ++i) {
2665 assert(pc->r_dst[m[i]] == NULL);
2666
2667 insn.Dst[0].Register.WriteMask =
2668 fd->Register.WriteMask & (1 << m[i]);
2669
2670 if (!insn.Dst[0].Register.WriteMask)
2671 continue;
2672
2673 if (deqs & (1 << i))
2674 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2675
2676 if (!nv50_program_tx_insn(pc, &insn))
2677 return FALSE;
2678 }
2679
2680 for (i = 0; i < 4; i++) {
2681 struct nv50_reg *reg = pc->r_dst[i];
2682 if (!reg)
2683 continue;
2684 pc->r_dst[i] = NULL;
2685
2686 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2687 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2688 else
2689 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2690 free_temp(pc, reg);
2691 }
2692
2693 return TRUE;
2694 }
2695
2696 static void
2697 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2698 {
2699 struct nv50_reg *iv, **ppiv;
2700 unsigned mode = pc->interp_mode[reg->index];
2701
2702 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2703 iv = *ppiv;
2704
2705 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2706 iv = *ppiv = alloc_temp(pc, NULL);
2707 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2708
2709 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2710 emit_flop(pc, 0, iv, iv);
2711
2712 /* XXX: when loading interpolants dynamically, move these
2713 * to the program head, or make sure it can't be skipped.
2714 */
2715 }
2716
2717 emit_interp(pc, reg, iv, mode);
2718 }
2719
2720 /* The face input is always at v[255] (varying space), with a
2721 * value of 0 for back-facing, and 0xffffffff for front-facing.
2722 */
2723 static void
2724 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
2725 {
2726 struct nv50_reg *one = alloc_immd(pc, 1.0f);
2727
2728 assert(a->rhw == -1);
2729 alloc_reg(pc, a); /* do this before rhw is set */
2730 a->rhw = 255;
2731 load_interpolant(pc, a);
2732 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
2733
2734 FREE(one);
2735 }
2736
2737 static boolean
2738 nv50_program_tx_prep(struct nv50_pc *pc)
2739 {
2740 struct tgsi_parse_context tp;
2741 struct nv50_program *p = pc->p;
2742 boolean ret = FALSE;
2743 unsigned i, c, flat_nr = 0;
2744
2745 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2746 while (!tgsi_parse_end_of_tokens(&tp)) {
2747 const union tgsi_full_token *tok = &tp.FullToken;
2748
2749 tgsi_parse_token(&tp);
2750 switch (tok->Token.Type) {
2751 case TGSI_TOKEN_TYPE_IMMEDIATE:
2752 {
2753 const struct tgsi_full_immediate *imm =
2754 &tp.FullToken.FullImmediate;
2755
2756 ctor_immd_4f32(pc, imm->u[0].Float,
2757 imm->u[1].Float,
2758 imm->u[2].Float,
2759 imm->u[3].Float);
2760 }
2761 break;
2762 case TGSI_TOKEN_TYPE_DECLARATION:
2763 {
2764 const struct tgsi_full_declaration *d;
2765 unsigned si, last, first, mode;
2766
2767 d = &tp.FullToken.FullDeclaration;
2768 first = d->Range.First;
2769 last = d->Range.Last;
2770
2771 switch (d->Declaration.File) {
2772 case TGSI_FILE_TEMPORARY:
2773 break;
2774 case TGSI_FILE_OUTPUT:
2775 if (!d->Declaration.Semantic ||
2776 p->type == PIPE_SHADER_FRAGMENT)
2777 break;
2778
2779 si = d->Semantic.Index;
2780 switch (d->Semantic.Name) {
2781 case TGSI_SEMANTIC_BCOLOR:
2782 p->cfg.two_side[si].hw = first;
2783 if (p->cfg.io_nr > first)
2784 p->cfg.io_nr = first;
2785 break;
2786 case TGSI_SEMANTIC_PSIZE:
2787 p->cfg.psiz = first;
2788 if (p->cfg.io_nr > first)
2789 p->cfg.io_nr = first;
2790 break;
2791 /*
2792 case TGSI_SEMANTIC_CLIP_DISTANCE:
2793 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2794 break;
2795 */
2796 default:
2797 break;
2798 }
2799 break;
2800 case TGSI_FILE_INPUT:
2801 {
2802 if (p->type != PIPE_SHADER_FRAGMENT)
2803 break;
2804
2805 switch (d->Declaration.Interpolate) {
2806 case TGSI_INTERPOLATE_CONSTANT:
2807 mode = INTERP_FLAT;
2808 flat_nr++;
2809 break;
2810 case TGSI_INTERPOLATE_PERSPECTIVE:
2811 mode = INTERP_PERSPECTIVE;
2812 p->cfg.regs[1] |= 0x08 << 24;
2813 break;
2814 default:
2815 mode = INTERP_LINEAR;
2816 break;
2817 }
2818 if (d->Declaration.Centroid)
2819 mode |= INTERP_CENTROID;
2820
2821 assert(last < 32);
2822 for (i = first; i <= last; i++)
2823 pc->interp_mode[i] = mode;
2824 }
2825 break;
2826 case TGSI_FILE_ADDRESS:
2827 case TGSI_FILE_CONSTANT:
2828 case TGSI_FILE_SAMPLER:
2829 break;
2830 default:
2831 NOUVEAU_ERR("bad decl file %d\n",
2832 d->Declaration.File);
2833 goto out_err;
2834 }
2835 }
2836 break;
2837 case TGSI_TOKEN_TYPE_INSTRUCTION:
2838 pc->insn_nr++;
2839 prep_inspect_insn(pc, &tok->FullInstruction);
2840 break;
2841 default:
2842 break;
2843 }
2844 }
2845
2846 if (p->type == PIPE_SHADER_VERTEX) {
2847 int rid = 0;
2848
2849 for (i = 0; i < pc->attr_nr * 4; ++i) {
2850 if (pc->attr[i].acc) {
2851 pc->attr[i].hw = rid++;
2852 p->cfg.attr[i / 32] |= 1 << (i % 32);
2853 }
2854 }
2855
2856 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
2857 p->cfg.io[i].hw = rid;
2858 p->cfg.io[i].id = i;
2859
2860 for (c = 0; c < 4; ++c) {
2861 int n = i * 4 + c;
2862 if (!pc->result[n].acc)
2863 continue;
2864 pc->result[n].hw = rid++;
2865 p->cfg.io[i].mask |= 1 << c;
2866 }
2867 }
2868
2869 for (c = 0; c < 2; ++c)
2870 if (p->cfg.two_side[c].hw < 0x40)
2871 p->cfg.two_side[c] = p->cfg.io[
2872 p->cfg.two_side[c].hw];
2873
2874 if (p->cfg.psiz < 0x40)
2875 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
2876 } else
2877 if (p->type == PIPE_SHADER_FRAGMENT) {
2878 int rid, aid;
2879 unsigned n = 0, m = pc->attr_nr - flat_nr;
2880
2881 pc->allow32 = TRUE;
2882
2883 int base = (TGSI_SEMANTIC_POSITION ==
2884 p->info.input_semantic_name[0]) ? 0 : 1;
2885
2886 /* non-flat interpolants have to be mapped to
2887 * the lower hardware IDs, so sort them:
2888 */
2889 for (i = 0; i < pc->attr_nr; i++) {
2890 if (pc->interp_mode[i] == INTERP_FLAT)
2891 p->cfg.io[m++].id = i;
2892 else {
2893 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
2894 p->cfg.io[n].linear = TRUE;
2895 p->cfg.io[n++].id = i;
2896 }
2897 }
2898
2899 if (!base) /* set w-coordinate mask from perspective interp */
2900 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
2901
2902 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
2903 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
2904
2905 for (n = 0; n < pc->attr_nr; ++n) {
2906 p->cfg.io[n].hw = rid = aid;
2907 i = p->cfg.io[n].id;
2908
2909 if (p->info.input_semantic_name[n] ==
2910 TGSI_SEMANTIC_FACE) {
2911 load_frontfacing(pc, &pc->attr[i * 4]);
2912 continue;
2913 }
2914
2915 for (c = 0; c < 4; ++c) {
2916 if (!pc->attr[i * 4 + c].acc)
2917 continue;
2918 pc->attr[i * 4 + c].rhw = rid++;
2919 p->cfg.io[n].mask |= 1 << c;
2920
2921 load_interpolant(pc, &pc->attr[i * 4 + c]);
2922 }
2923 aid += popcnt4(p->cfg.io[n].mask);
2924 }
2925
2926 if (!base)
2927 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
2928
2929 m = popcnt4(p->cfg.regs[1] >> 24);
2930
2931 /* set count of non-position inputs and of non-flat
2932 * non-position inputs for FP_INTERPOLANT_CTRL
2933 */
2934 p->cfg.regs[1] |= aid - m;
2935
2936 if (flat_nr) {
2937 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
2938 p->cfg.regs[1] |= (i - m) << 16;
2939 } else
2940 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
2941
2942 /* mark color semantic for light-twoside */
2943 n = 0x40;
2944 for (i = 0; i < pc->attr_nr; i++) {
2945 ubyte si, sn;
2946
2947 sn = p->info.input_semantic_name[p->cfg.io[i].id];
2948 si = p->info.input_semantic_index[p->cfg.io[i].id];
2949
2950 if (sn == TGSI_SEMANTIC_COLOR) {
2951 p->cfg.two_side[si] = p->cfg.io[i];
2952
2953 /* increase colour count */
2954 p->cfg.regs[0] += popcnt4(
2955 p->cfg.two_side[si].mask) << 16;
2956
2957 n = MIN2(n, p->cfg.io[i].hw - m);
2958 }
2959 }
2960 if (n < 0x40)
2961 p->cfg.regs[0] += n;
2962
2963 /* Initialize FP results:
2964 * FragDepth is always first TGSI and last hw output
2965 */
2966 i = p->info.writes_z ? 4 : 0;
2967 for (rid = 0; i < pc->result_nr * 4; i++)
2968 pc->result[i].rhw = rid++;
2969 if (p->info.writes_z)
2970 pc->result[2].rhw = rid;
2971
2972 p->cfg.high_result = rid;
2973
2974 /* separate/different colour results for MRTs ? */
2975 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
2976 p->cfg.regs[2] |= 1;
2977 }
2978
2979 if (pc->immd_nr) {
2980 int rid = 0;
2981
2982 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
2983 if (!pc->immd)
2984 goto out_err;
2985
2986 for (i = 0; i < pc->immd_nr; i++) {
2987 for (c = 0; c < 4; c++, rid++)
2988 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
2989 }
2990 }
2991
2992 ret = TRUE;
2993 out_err:
2994 if (pc->iv_p)
2995 free_temp(pc, pc->iv_p);
2996 if (pc->iv_c)
2997 free_temp(pc, pc->iv_c);
2998
2999 tgsi_parse_free(&tp);
3000 return ret;
3001 }
3002
3003 static void
3004 free_nv50_pc(struct nv50_pc *pc)
3005 {
3006 if (pc->immd)
3007 FREE(pc->immd);
3008 if (pc->param)
3009 FREE(pc->param);
3010 if (pc->result)
3011 FREE(pc->result);
3012 if (pc->attr)
3013 FREE(pc->attr);
3014 if (pc->temp)
3015 FREE(pc->temp);
3016
3017 FREE(pc);
3018 }
3019
3020 static boolean
3021 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3022 {
3023 int i, c;
3024 unsigned rtype[2] = { P_ATTR, P_RESULT };
3025
3026 pc->p = p;
3027 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3028 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3029 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3030 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3031 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3032 assert(pc->addr_nr <= 2);
3033
3034 p->cfg.high_temp = 4;
3035
3036 p->cfg.two_side[0].hw = 0x40;
3037 p->cfg.two_side[1].hw = 0x40;
3038
3039 switch (p->type) {
3040 case PIPE_SHADER_VERTEX:
3041 p->cfg.psiz = 0x40;
3042 p->cfg.clpd = 0x40;
3043 p->cfg.io_nr = pc->result_nr;
3044 break;
3045 case PIPE_SHADER_FRAGMENT:
3046 rtype[0] = rtype[1] = P_TEMP;
3047
3048 p->cfg.regs[0] = 0x01000004;
3049 p->cfg.io_nr = pc->attr_nr;
3050
3051 if (p->info.writes_z) {
3052 p->cfg.regs[2] |= 0x00000100;
3053 p->cfg.regs[3] |= 0x00000011;
3054 }
3055 if (p->info.uses_kill)
3056 p->cfg.regs[2] |= 0x00100000;
3057 break;
3058 }
3059
3060 if (pc->temp_nr) {
3061 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3062 if (!pc->temp)
3063 return FALSE;
3064
3065 for (i = 0; i < pc->temp_nr * 4; ++i)
3066 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3067 }
3068
3069 if (pc->attr_nr) {
3070 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3071 if (!pc->attr)
3072 return FALSE;
3073
3074 for (i = 0; i < pc->attr_nr * 4; ++i)
3075 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3076 }
3077
3078 if (pc->result_nr) {
3079 unsigned nr = pc->result_nr * 4;
3080
3081 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3082 if (!pc->result)
3083 return FALSE;
3084
3085 for (i = 0; i < nr; ++i)
3086 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3087 }
3088
3089 if (pc->param_nr) {
3090 int rid = 0;
3091
3092 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3093 if (!pc->param)
3094 return FALSE;
3095
3096 for (i = 0; i < pc->param_nr; ++i)
3097 for (c = 0; c < 4; ++c, ++rid)
3098 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3099 }
3100
3101 if (pc->addr_nr) {
3102 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3103 if (!pc->addr)
3104 return FALSE;
3105 }
3106 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3107 ctor_reg(&pc->r_addr[i], P_ADDR, -256, i + 1);
3108
3109 return TRUE;
3110 }
3111
3112 static void
3113 nv50_fp_move_results(struct nv50_pc *pc)
3114 {
3115 struct nv50_reg reg;
3116 unsigned i;
3117
3118 ctor_reg(&reg, P_TEMP, -1, -1);
3119
3120 for (i = 0; i < pc->result_nr * 4; ++i) {
3121 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
3122 continue;
3123 if (pc->result[i].rhw != pc->result[i].hw) {
3124 reg.hw = pc->result[i].rhw;
3125 emit_mov(pc, &reg, &pc->result[i]);
3126 }
3127 }
3128 }
3129
3130 static void
3131 nv50_program_fixup_insns(struct nv50_pc *pc)
3132 {
3133 struct nv50_program_exec *e, **bra_list;
3134 unsigned i, n, pos;
3135
3136 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3137
3138 /* Collect branch instructions, we need to adjust their offsets
3139 * when converting 32 bit instructions to 64 bit ones
3140 */
3141 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3142 if (e->param.index >= 0 && !e->param.mask)
3143 bra_list[n++] = e;
3144
3145 /* last instruction must be long so it can have the exit bit set */
3146 if (!is_long(pc->p->exec_tail))
3147 convert_to_long(pc, pc->p->exec_tail);
3148 /* set exit bit */
3149 pc->p->exec_tail->inst[1] |= 1;
3150
3151 /* !immd on exit insn simultaneously means !join */
3152 assert(!is_immd(pc->p->exec_head));
3153 assert(!is_immd(pc->p->exec_tail));
3154
3155 /* Make sure we don't have any single 32 bit instructions. */
3156 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3157 pos += is_long(e) ? 2 : 1;
3158
3159 if ((pos & 1) && (!e->next || is_long(e->next))) {
3160 for (i = 0; i < n; ++i)
3161 if (bra_list[i]->param.index >= pos)
3162 bra_list[i]->param.index += 1;
3163 convert_to_long(pc, e);
3164 ++pos;
3165 }
3166 }
3167
3168 FREE(bra_list);
3169 }
3170
3171 static boolean
3172 nv50_program_tx(struct nv50_program *p)
3173 {
3174 struct tgsi_parse_context parse;
3175 struct nv50_pc *pc;
3176 boolean ret;
3177
3178 pc = CALLOC_STRUCT(nv50_pc);
3179 if (!pc)
3180 return FALSE;
3181
3182 ret = ctor_nv50_pc(pc, p);
3183 if (ret == FALSE)
3184 goto out_cleanup;
3185
3186 ret = nv50_program_tx_prep(pc);
3187 if (ret == FALSE)
3188 goto out_cleanup;
3189
3190 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3191 while (!tgsi_parse_end_of_tokens(&parse)) {
3192 const union tgsi_full_token *tok = &parse.FullToken;
3193
3194 /* don't allow half insn/immd on first and last instruction */
3195 pc->allow32 = TRUE;
3196 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr)
3197 pc->allow32 = FALSE;
3198
3199 tgsi_parse_token(&parse);
3200
3201 switch (tok->Token.Type) {
3202 case TGSI_TOKEN_TYPE_INSTRUCTION:
3203 ++pc->insn_cur;
3204 ret = nv50_tgsi_insn(pc, tok);
3205 if (ret == FALSE)
3206 goto out_err;
3207 break;
3208 default:
3209 break;
3210 }
3211 }
3212
3213 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3214 nv50_fp_move_results(pc);
3215
3216 nv50_program_fixup_insns(pc);
3217
3218 p->param_nr = pc->param_nr * 4;
3219 p->immd_nr = pc->immd_nr * 4;
3220 p->immd = pc->immd_buf;
3221
3222 out_err:
3223 tgsi_parse_free(&parse);
3224
3225 out_cleanup:
3226 free_nv50_pc(pc);
3227 return ret;
3228 }
3229
3230 static void
3231 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3232 {
3233 if (nv50_program_tx(p) == FALSE)
3234 assert(0);
3235 p->translated = TRUE;
3236 }
3237
3238 static void
3239 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
3240 unsigned start, unsigned count, unsigned cbuf)
3241 {
3242 struct nouveau_channel *chan = nv50->screen->base.channel;
3243 struct nouveau_grobj *tesla = nv50->screen->tesla;
3244
3245 while (count) {
3246 unsigned nr = count > 2047 ? 2047 : count;
3247
3248 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3249 OUT_RING (chan, (cbuf << 0) | (start << 8));
3250 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3251 OUT_RINGp (chan, map, nr);
3252
3253 map += nr;
3254 start += nr;
3255 count -= nr;
3256 }
3257 }
3258
3259 static void
3260 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3261 {
3262 struct pipe_screen *pscreen = nv50->pipe.screen;
3263
3264 if (!p->data[0] && p->immd_nr) {
3265 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3266
3267 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3268 while (heap->next && heap->size < p->immd_nr) {
3269 struct nv50_program *evict = heap->next->priv;
3270 nouveau_resource_free(&evict->data[0]);
3271 }
3272
3273 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3274 &p->data[0]))
3275 assert(0);
3276 }
3277
3278 /* immediates only need to be uploaded again when freed */
3279 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3280 p->immd_nr, NV50_CB_PMISC);
3281 }
3282
3283 assert(p->param_nr <= 512);
3284
3285 if (p->param_nr) {
3286 unsigned cb;
3287 uint32_t *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3288 PIPE_BUFFER_USAGE_CPU_READ);
3289
3290 if (p->type == PIPE_SHADER_VERTEX)
3291 cb = NV50_CB_PVP;
3292 else
3293 cb = NV50_CB_PFP;
3294
3295 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
3296 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
3297 }
3298 }
3299
3300 static void
3301 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
3302 {
3303 struct nouveau_channel *chan = nv50->screen->base.channel;
3304 struct nv50_program_exec *e;
3305 uint32_t *up, i;
3306 boolean upload = FALSE;
3307
3308 if (!p->bo) {
3309 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
3310 p->exec_size * 4, &p->bo);
3311 upload = TRUE;
3312 }
3313
3314 if (p->data[0] && p->data[0]->start != p->data_start[0])
3315 upload = TRUE;
3316
3317 if (!upload)
3318 return;
3319
3320 up = MALLOC(p->exec_size * 4);
3321
3322 for (i = 0, e = p->exec_head; e; e = e->next) {
3323 unsigned ei, ci, bs;
3324
3325 if (e->param.index >= 0 && e->param.mask) {
3326 bs = (e->inst[1] >> 22) & 0x07;
3327 assert(bs < 2);
3328 ei = e->param.shift >> 5;
3329 ci = e->param.index;
3330 if (bs == 0)
3331 ci += p->data[bs]->start;
3332
3333 e->inst[ei] &= ~e->param.mask;
3334 e->inst[ei] |= (ci << e->param.shift);
3335 } else
3336 if (e->param.index >= 0) {
3337 /* zero mask means param is a jump/branch offset */
3338 assert(!(e->param.index & 1));
3339 /* seem to be 8 byte steps */
3340 ei = (e->param.index >> 1) + 0 /* START_ID */;
3341
3342 e->inst[0] &= 0xf0000fff;
3343 e->inst[0] |= ei << 12;
3344 }
3345
3346 up[i++] = e->inst[0];
3347 if (is_long(e))
3348 up[i++] = e->inst[1];
3349 }
3350 assert(i == p->exec_size);
3351
3352 if (p->data[0])
3353 p->data_start[0] = p->data[0]->start;
3354
3355 #ifdef NV50_PROGRAM_DUMP
3356 NOUVEAU_ERR("-------\n");
3357 for (e = p->exec_head; e; e = e->next) {
3358 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
3359 if (is_long(e))
3360 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
3361 }
3362 #endif
3363 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
3364 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
3365 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
3366 0, 0, p->exec_size * 4, 1, 1);
3367
3368 FREE(up);
3369 }
3370
3371 void
3372 nv50_vertprog_validate(struct nv50_context *nv50)
3373 {
3374 struct nouveau_grobj *tesla = nv50->screen->tesla;
3375 struct nv50_program *p = nv50->vertprog;
3376 struct nouveau_stateobj *so;
3377
3378 if (!p->translated) {
3379 nv50_program_validate(nv50, p);
3380 if (!p->translated)
3381 assert(0);
3382 }
3383
3384 nv50_program_validate_data(nv50, p);
3385 nv50_program_validate_code(nv50, p);
3386
3387 so = so_new(13, 2);
3388 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
3389 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3390 NOUVEAU_BO_HIGH, 0, 0);
3391 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3392 NOUVEAU_BO_LOW, 0, 0);
3393 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
3394 so_data (so, p->cfg.attr[0]);
3395 so_data (so, p->cfg.attr[1]);
3396 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
3397 so_data (so, p->cfg.high_result);
3398 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
3399 so_data (so, p->cfg.high_result); //8);
3400 so_data (so, p->cfg.high_temp);
3401 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
3402 so_data (so, 0); /* program start offset */
3403 so_ref(so, &nv50->state.vertprog);
3404 so_ref(NULL, &so);
3405 }
3406
3407 void
3408 nv50_fragprog_validate(struct nv50_context *nv50)
3409 {
3410 struct nouveau_grobj *tesla = nv50->screen->tesla;
3411 struct nv50_program *p = nv50->fragprog;
3412 struct nouveau_stateobj *so;
3413
3414 if (!p->translated) {
3415 nv50_program_validate(nv50, p);
3416 if (!p->translated)
3417 assert(0);
3418 }
3419
3420 nv50_program_validate_data(nv50, p);
3421 nv50_program_validate_code(nv50, p);
3422
3423 so = so_new(64, 2);
3424 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
3425 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3426 NOUVEAU_BO_HIGH, 0, 0);
3427 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
3428 NOUVEAU_BO_LOW, 0, 0);
3429 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
3430 so_data (so, p->cfg.high_temp);
3431 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
3432 so_data (so, p->cfg.high_result);
3433 so_method(so, tesla, NV50TCL_FP_CTRL_UNK19A8, 1);
3434 so_data (so, p->cfg.regs[2]);
3435 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
3436 so_data (so, p->cfg.regs[3]);
3437 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
3438 so_data (so, 0); /* program start offset */
3439 so_ref(so, &nv50->state.fragprog);
3440 so_ref(NULL, &so);
3441 }
3442
3443 static void
3444 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
3445 {
3446 struct nv50_program *fp = nv50->fragprog;
3447 struct nv50_program *vp = nv50->vertprog;
3448 unsigned i, c, m = base;
3449
3450 /* XXX: this might not work correctly in all cases yet - we'll
3451 * just assume that an FP generic input that is not written in
3452 * the VP is PointCoord.
3453 */
3454 memset(pntc, 0, 8 * sizeof(uint32_t));
3455
3456 for (i = 0; i < fp->cfg.io_nr; i++) {
3457 uint8_t sn, si;
3458 uint8_t j, k = fp->cfg.io[i].id;
3459 unsigned n = popcnt4(fp->cfg.io[i].mask);
3460
3461 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
3462 m += n;
3463 continue;
3464 }
3465
3466 for (j = 0; j < vp->info.num_outputs; ++j) {
3467 sn = vp->info.output_semantic_name[j];
3468 si = vp->info.output_semantic_index[j];
3469
3470 if (sn == fp->info.input_semantic_name[k] &&
3471 si == fp->info.input_semantic_index[k])
3472 break;
3473 }
3474
3475 if (j < vp->info.num_outputs) {
3476 ubyte mode =
3477 nv50->rasterizer->pipe.sprite_coord_mode[si];
3478
3479 if (mode == PIPE_SPRITE_COORD_NONE) {
3480 m += n;
3481 continue;
3482 }
3483 }
3484
3485 /* this is either PointCoord or replaced by sprite coords */
3486 for (c = 0; c < 4; c++) {
3487 if (!(fp->cfg.io[i].mask & (1 << c)))
3488 continue;
3489 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
3490 ++m;
3491 }
3492 }
3493 }
3494
3495 static int
3496 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
3497 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
3498 {
3499 int c;
3500 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
3501 uint8_t *map = (uint8_t *)p_map;
3502
3503 for (c = 0; c < 4; ++c) {
3504 if (mf & 1) {
3505 if (fpi->linear == TRUE)
3506 lin[mid / 32] |= 1 << (mid % 32);
3507 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
3508 }
3509
3510 oid += mv & 1;
3511 mf >>= 1;
3512 mv >>= 1;
3513 }
3514
3515 return mid;
3516 }
3517
3518 void
3519 nv50_linkage_validate(struct nv50_context *nv50)
3520 {
3521 struct nouveau_grobj *tesla = nv50->screen->tesla;
3522 struct nv50_program *vp = nv50->vertprog;
3523 struct nv50_program *fp = nv50->fragprog;
3524 struct nouveau_stateobj *so;
3525 struct nv50_sreg4 dummy, *vpo;
3526 int i, n, c, m = 0;
3527 uint32_t map[16], lin[4], reg[5], pcrd[8];
3528
3529 memset(map, 0, sizeof(map));
3530 memset(lin, 0, sizeof(lin));
3531
3532 reg[1] = 0x00000004; /* low and high clip distance map ids */
3533 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
3534 reg[3] = 0x00000000; /* point size map id & enable */
3535 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
3536 reg[4] = fp->cfg.regs[1]; /* interpolant info */
3537
3538 dummy.linear = FALSE;
3539 dummy.mask = 0xf; /* map all components of HPOS */
3540 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
3541
3542 dummy.mask = 0x0;
3543
3544 if (vp->cfg.clpd < 0x40) {
3545 for (c = 0; c < vp->cfg.clpd_nr; ++c)
3546 map[m++] = vp->cfg.clpd + c;
3547 reg[1] = (m << 8);
3548 }
3549
3550 reg[0] |= m << 8; /* adjust BFC0 id */
3551
3552 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
3553 if (nv50->rasterizer->pipe.light_twoside) {
3554 vpo = &vp->cfg.two_side[0];
3555
3556 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
3557 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
3558 }
3559
3560 reg[0] += m - 4; /* adjust FFC0 id */
3561 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
3562
3563 for (i = 0; i < fp->cfg.io_nr; i++) {
3564 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
3565 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
3566
3567 /* position must be mapped first */
3568 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
3569
3570 /* maybe even remove these from cfg.io */
3571 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
3572 continue;
3573
3574 /* VP outputs and vp->cfg.io are in the same order */
3575 for (n = 0; n < vp->info.num_outputs; ++n) {
3576 if (vp->info.output_semantic_name[n] == sn &&
3577 vp->info.output_semantic_index[n] == si)
3578 break;
3579 }
3580 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
3581
3582 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3583 }
3584
3585 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3586 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3587 reg[3] = (m++ << 4) | 1;
3588 }
3589
3590 /* now fill the stateobj */
3591 so = so_new(64, 0);
3592
3593 n = (m + 3) / 4;
3594 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3595 so_data (so, m);
3596 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3597 so_datap (so, map, n);
3598
3599 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3600 so_datap (so, reg, 4);
3601
3602 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3603 so_data (so, reg[4]);
3604
3605 so_method(so, tesla, 0x1540, 4);
3606 so_datap (so, lin, 4);
3607
3608 if (nv50->rasterizer->pipe.point_sprite) {
3609 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3610
3611 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3612 so_datap (so, pcrd, 8);
3613 }
3614
3615 so_ref(so, &nv50->state.programs);
3616 so_ref(NULL, &so);
3617 }
3618
3619 void
3620 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3621 {
3622 while (p->exec_head) {
3623 struct nv50_program_exec *e = p->exec_head;
3624
3625 p->exec_head = e->next;
3626 FREE(e);
3627 }
3628 p->exec_tail = NULL;
3629 p->exec_size = 0;
3630
3631 nouveau_bo_ref(NULL, &p->bo);
3632
3633 nouveau_resource_free(&p->data[0]);
3634
3635 p->translated = 0;
3636 }