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nv50: get access to primitive input space
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 127
35 #define NV50_SU_MAX_ADDR 4
36 //#define NV50_PROGRAM_DUMP
37
38 /* $a5 and $a6 always seem to be 0, and using $a7 gives you noise */
39
40 /* ARL - gallium craps itself on progs/vp/arl.txt
41 *
42 * MSB - Like MAD, but MUL+SUB
43 * - Fuck it off, introduce a way to negate args for ops that
44 * support it.
45 *
46 * Look into inlining IMMD for ops other than MOV (make it general?)
47 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
48 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
49 *
50 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
51 * case, if the emit_src() causes the inst to suddenly become long.
52 *
53 * Verify half-insns work where expected - and force disable them where they
54 * don't work - MUL has it forcibly disabled atm as it fixes POW..
55 *
56 * FUCK! watch dst==src vectors, can overwrite components that are needed.
57 * ie. SUB R0, R0.yzxw, R0
58 *
59 * Things to check with renouveau:
60 * FP attr/result assignment - how?
61 * attrib
62 * - 0x16bc maps vp output onto fp hpos
63 * - 0x16c0 maps vp output onto fp col0
64 * result
65 * - colr always 0-3
66 * - depr always 4
67 * 0x16bc->0x16e8 --> some binding between vp/fp regs
68 * 0x16b8 --> VP output count
69 *
70 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
71 * "MOV rcol.x, fcol.y" = 0x00000004
72 * 0x19a8 --> as above but 0x00000100 and 0x00000000
73 * - 0x00100000 used when KIL used
74 * 0x196c --> as above but 0x00000011 and 0x00000000
75 *
76 * 0x1988 --> 0xXXNNNNNN
77 * - XX == FP high something
78 */
79 struct nv50_reg {
80 enum {
81 P_TEMP,
82 P_ATTR,
83 P_RESULT,
84 P_CONST,
85 P_IMMD,
86 P_ADDR
87 } type;
88 int index;
89
90 int hw;
91 int mod;
92
93 int rhw; /* result hw for FP outputs, or interpolant index */
94 int acc; /* instruction where this reg is last read (first insn == 1) */
95
96 int vtx; /* vertex index, for GP inputs (TGSI Dimension.Index) */
97 int indirect[2]; /* index into pc->addr, or -1 */
98 };
99
100 #define NV50_MOD_NEG 1
101 #define NV50_MOD_ABS 2
102 #define NV50_MOD_NEG_ABS (NV50_MOD_NEG | NV50_MOD_ABS)
103 #define NV50_MOD_SAT 4
104 #define NV50_MOD_I32 8
105
106 /* NV50_MOD_I32 is used to indicate integer mode for neg/abs */
107
108 /* STACK: Conditionals and loops have to use the (per warp) stack.
109 * Stack entries consist of an entry type (divergent path, join at),
110 * a mask indicating the active threads of the warp, and an address.
111 * MPs can store 12 stack entries internally, if we need more (and
112 * we probably do), we have to create a stack buffer in VRAM.
113 */
114 /* impose low limits for now */
115 #define NV50_MAX_COND_NESTING 4
116 #define NV50_MAX_LOOP_NESTING 3
117
118 #define JOIN_ON(e) e; pc->p->exec_tail->inst[1] |= 2
119
120 struct nv50_pc {
121 struct nv50_program *p;
122
123 /* hw resources */
124 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
125 struct nv50_reg r_addr[NV50_SU_MAX_ADDR];
126
127 /* tgsi resources */
128 struct nv50_reg *temp;
129 int temp_nr;
130 struct nv50_reg *attr;
131 int attr_nr;
132 struct nv50_reg *result;
133 int result_nr;
134 struct nv50_reg *param;
135 int param_nr;
136 struct nv50_reg *immd;
137 uint32_t *immd_buf;
138 int immd_nr;
139 struct nv50_reg **addr;
140 int addr_nr;
141
142 struct nv50_reg *temp_temp[16];
143 struct nv50_program_exec *temp_temp_exec[16];
144 unsigned temp_temp_nr;
145
146 /* broadcast and destination replacement regs */
147 struct nv50_reg *r_brdc;
148 struct nv50_reg *r_dst[4];
149
150 struct nv50_reg reg_instances[16];
151 unsigned reg_instance_nr;
152
153 unsigned interp_mode[32];
154 /* perspective interpolation registers */
155 struct nv50_reg *iv_p;
156 struct nv50_reg *iv_c;
157
158 struct nv50_program_exec *if_insn[NV50_MAX_COND_NESTING];
159 struct nv50_program_exec *if_join[NV50_MAX_COND_NESTING];
160 struct nv50_program_exec *loop_brka[NV50_MAX_LOOP_NESTING];
161 int if_lvl, loop_lvl;
162 unsigned loop_pos[NV50_MAX_LOOP_NESTING];
163
164 unsigned *insn_pos; /* actual program offset of each TGSI insn */
165 boolean in_subroutine;
166
167 /* current instruction and total number of insns */
168 unsigned insn_cur;
169 unsigned insn_nr;
170
171 boolean allow32;
172
173 uint8_t edgeflag_out;
174 };
175
176 static struct nv50_reg *get_address_reg(struct nv50_pc *, struct nv50_reg *);
177
178 static INLINE void
179 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
180 {
181 reg->type = type;
182 reg->index = index;
183 reg->hw = hw;
184 reg->mod = 0;
185 reg->rhw = -1;
186 reg->vtx = -1;
187 reg->acc = 0;
188 reg->indirect[0] = reg->indirect[1] = -1;
189 }
190
191 static INLINE unsigned
192 popcnt4(uint32_t val)
193 {
194 static const unsigned cnt[16]
195 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
196 return cnt[val & 0xf];
197 }
198
199 static void
200 terminate_mbb(struct nv50_pc *pc)
201 {
202 int i;
203
204 /* remove records of temporary address register values */
205 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
206 if (pc->r_addr[i].index < 0)
207 pc->r_addr[i].acc = 0;
208 }
209
210 static void
211 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
212 {
213 int i = 0;
214
215 if (reg->type == P_RESULT) {
216 if (pc->p->cfg.high_result < (reg->hw + 1))
217 pc->p->cfg.high_result = reg->hw + 1;
218 }
219
220 if (reg->type != P_TEMP)
221 return;
222
223 if (reg->hw >= 0) {
224 /*XXX: do this here too to catch FP temp-as-attr usage..
225 * not clean, but works */
226 if (pc->p->cfg.high_temp < (reg->hw + 1))
227 pc->p->cfg.high_temp = reg->hw + 1;
228 return;
229 }
230
231 if (reg->rhw != -1) {
232 /* try to allocate temporary with index rhw first */
233 if (!(pc->r_temp[reg->rhw])) {
234 pc->r_temp[reg->rhw] = reg;
235 reg->hw = reg->rhw;
236 if (pc->p->cfg.high_temp < (reg->rhw + 1))
237 pc->p->cfg.high_temp = reg->rhw + 1;
238 return;
239 }
240 /* make sure we don't get things like $r0 needs to go
241 * in $r1 and $r1 in $r0
242 */
243 i = pc->result_nr * 4;
244 }
245
246 for (; i < NV50_SU_MAX_TEMP; i++) {
247 if (!(pc->r_temp[i])) {
248 pc->r_temp[i] = reg;
249 reg->hw = i;
250 if (pc->p->cfg.high_temp < (i + 1))
251 pc->p->cfg.high_temp = i + 1;
252 return;
253 }
254 }
255
256 NOUVEAU_ERR("out of registers\n");
257 abort();
258 }
259
260 static INLINE struct nv50_reg *
261 reg_instance(struct nv50_pc *pc, struct nv50_reg *reg)
262 {
263 struct nv50_reg *ri;
264
265 assert(pc->reg_instance_nr < 16);
266 ri = &pc->reg_instances[pc->reg_instance_nr++];
267 if (reg) {
268 alloc_reg(pc, reg);
269 *ri = *reg;
270 reg->indirect[0] = reg->indirect[1] = -1;
271 reg->mod = 0;
272 }
273 return ri;
274 }
275
276 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
277 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
278 * lest we risk temp_temps overwriting regs alloc'd "later".
279 */
280 static struct nv50_reg *
281 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
282 {
283 struct nv50_reg *r;
284 int i;
285
286 if (dst && dst->type == P_TEMP && dst->hw == -1)
287 return dst;
288
289 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
290 if (!pc->r_temp[i]) {
291 r = MALLOC_STRUCT(nv50_reg);
292 ctor_reg(r, P_TEMP, -1, i);
293 pc->r_temp[i] = r;
294 return r;
295 }
296 }
297
298 NOUVEAU_ERR("out of registers\n");
299 abort();
300 return NULL;
301 }
302
303 /* release the hardware resource held by r */
304 static void
305 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
306 {
307 assert(r->type == P_TEMP);
308 if (r->hw == -1)
309 return;
310
311 assert(pc->r_temp[r->hw] == r);
312 pc->r_temp[r->hw] = NULL;
313
314 r->acc = 0;
315 if (r->index == -1)
316 FREE(r);
317 }
318
319 static void
320 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
321 {
322 if (r->index == -1) {
323 unsigned hw = r->hw;
324
325 FREE(pc->r_temp[hw]);
326 pc->r_temp[hw] = NULL;
327 }
328 }
329
330 static int
331 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
332 {
333 int i;
334
335 if ((idx + 4) >= NV50_SU_MAX_TEMP)
336 return 1;
337
338 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
339 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
340 return alloc_temp4(pc, dst, idx + 4);
341
342 for (i = 0; i < 4; i++) {
343 dst[i] = MALLOC_STRUCT(nv50_reg);
344 ctor_reg(dst[i], P_TEMP, -1, idx + i);
345 pc->r_temp[idx + i] = dst[i];
346 }
347
348 return 0;
349 }
350
351 static void
352 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
353 {
354 int i;
355
356 for (i = 0; i < 4; i++)
357 free_temp(pc, reg[i]);
358 }
359
360 static struct nv50_reg *
361 temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
362 {
363 if (pc->temp_temp_nr >= 16)
364 assert(0);
365
366 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
367 pc->temp_temp_exec[pc->temp_temp_nr] = e;
368 return pc->temp_temp[pc->temp_temp_nr++];
369 }
370
371 /* This *must* be called for all nv50_program_exec that have been
372 * given as argument to temp_temp, or the temps will be leaked !
373 */
374 static void
375 kill_temp_temp(struct nv50_pc *pc, struct nv50_program_exec *e)
376 {
377 int i;
378
379 for (i = 0; i < pc->temp_temp_nr; i++)
380 if (pc->temp_temp_exec[i] == e)
381 free_temp(pc, pc->temp_temp[i]);
382 if (!e)
383 pc->temp_temp_nr = 0;
384 }
385
386 static int
387 ctor_immd_4u32(struct nv50_pc *pc,
388 uint32_t x, uint32_t y, uint32_t z, uint32_t w)
389 {
390 unsigned size = pc->immd_nr * 4 * sizeof(uint32_t);
391
392 pc->immd_buf = REALLOC(pc->immd_buf, size, size + 4 * sizeof(uint32_t));
393
394 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
395 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
396 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
397 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
398
399 return pc->immd_nr++;
400 }
401
402 static INLINE int
403 ctor_immd_4f32(struct nv50_pc *pc, float x, float y, float z, float w)
404 {
405 return ctor_immd_4u32(pc, fui(x), fui(y), fui(z), fui(w));
406 }
407
408 static struct nv50_reg *
409 alloc_immd(struct nv50_pc *pc, float f)
410 {
411 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
412 unsigned hw;
413
414 for (hw = 0; hw < pc->immd_nr * 4; hw++)
415 if (pc->immd_buf[hw] == fui(f))
416 break;
417
418 if (hw == pc->immd_nr * 4)
419 hw = ctor_immd_4f32(pc, f, -f, 0.5 * f, 0) * 4;
420
421 ctor_reg(r, P_IMMD, -1, hw);
422 return r;
423 }
424
425 static struct nv50_program_exec *
426 exec(struct nv50_pc *pc)
427 {
428 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
429
430 e->param.index = -1;
431 return e;
432 }
433
434 static void
435 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
436 {
437 struct nv50_program *p = pc->p;
438
439 if (p->exec_tail)
440 p->exec_tail->next = e;
441 if (!p->exec_head)
442 p->exec_head = e;
443 p->exec_tail = e;
444 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
445
446 kill_temp_temp(pc, e);
447 }
448
449 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
450
451 static boolean
452 is_long(struct nv50_program_exec *e)
453 {
454 if (e->inst[0] & 1)
455 return TRUE;
456 return FALSE;
457 }
458
459 static boolean
460 is_immd(struct nv50_program_exec *e)
461 {
462 if (is_long(e) && (e->inst[1] & 3) == 3)
463 return TRUE;
464 return FALSE;
465 }
466
467 static boolean
468 is_join(struct nv50_program_exec *e)
469 {
470 if (is_long(e) && (e->inst[1] & 3) == 2)
471 return TRUE;
472 return FALSE;
473 }
474
475 static INLINE void
476 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
477 struct nv50_program_exec *e)
478 {
479 assert(!is_immd(e));
480 set_long(pc, e);
481 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
482 e->inst[1] |= (pred << 7) | (idx << 12);
483 }
484
485 static INLINE void
486 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
487 struct nv50_program_exec *e)
488 {
489 set_long(pc, e);
490 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
491 e->inst[1] |= (idx << 4) | (on << 6);
492 }
493
494 static INLINE void
495 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
496 {
497 if (is_long(e))
498 return;
499
500 e->inst[0] |= 1;
501 set_pred(pc, 0xf, 0, e);
502 set_pred_wr(pc, 0, 0, e);
503 }
504
505 static INLINE void
506 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
507 {
508 if (dst->type == P_RESULT) {
509 set_long(pc, e);
510 e->inst[1] |= 0x00000008;
511 }
512
513 alloc_reg(pc, dst);
514 if (dst->hw > 63)
515 set_long(pc, e);
516 e->inst[0] |= (dst->hw << 2);
517 }
518
519 static INLINE void
520 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
521 {
522 set_long(pc, e);
523 /* XXX: can't be predicated - bits overlap; cases where both
524 * are required should be avoided by using pc->allow32 */
525 set_pred(pc, 0, 0, e);
526 set_pred_wr(pc, 0, 0, e);
527
528 e->inst[1] |= 0x00000002 | 0x00000001;
529 e->inst[0] |= (pc->immd_buf[imm->hw] & 0x3f) << 16;
530 e->inst[1] |= (pc->immd_buf[imm->hw] >> 6) << 2;
531 }
532
533 static INLINE void
534 set_addr(struct nv50_program_exec *e, struct nv50_reg *a)
535 {
536 assert(a->type == P_ADDR);
537
538 assert(!(e->inst[0] & 0x0c000000));
539 assert(!(e->inst[1] & 0x00000004));
540
541 e->inst[0] |= (a->hw & 3) << 26;
542 e->inst[1] |= a->hw & 4;
543 }
544
545 static void
546 emit_arl(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, uint8_t);
547
548 static void
549 emit_shl_imm(struct nv50_pc *, struct nv50_reg *, struct nv50_reg *, int);
550
551 static void
552 emit_mov_from_addr(struct nv50_pc *pc, struct nv50_reg *dst,
553 struct nv50_reg *src)
554 {
555 struct nv50_program_exec *e = exec(pc);
556
557 e->inst[1] = 0x40000000;
558 set_long(pc, e);
559 set_dst(pc, dst, e);
560 set_addr(e, src);
561
562 emit(pc, e);
563 }
564
565 static void
566 emit_add_addr_imm(struct nv50_pc *pc, struct nv50_reg *dst,
567 struct nv50_reg *src0, uint16_t src1_val)
568 {
569 struct nv50_program_exec *e = exec(pc);
570
571 e->inst[0] = 0xd0000000 | (src1_val << 9);
572 e->inst[1] = 0x20000000;
573 set_long(pc, e);
574 e->inst[0] |= dst->hw << 2;
575 if (src0) /* otherwise will add to $a0, which is always 0 */
576 set_addr(e, src0);
577
578 emit(pc, e);
579 }
580
581 #define INTERP_LINEAR 0
582 #define INTERP_FLAT 1
583 #define INTERP_PERSPECTIVE 2
584 #define INTERP_CENTROID 4
585
586 /* interpolant index has been stored in dst->rhw */
587 static void
588 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
589 unsigned mode)
590 {
591 assert(dst->rhw != -1);
592 struct nv50_program_exec *e = exec(pc);
593
594 e->inst[0] |= 0x80000000;
595 set_dst(pc, dst, e);
596 e->inst[0] |= (dst->rhw << 16);
597
598 if (mode & INTERP_FLAT) {
599 e->inst[0] |= (1 << 8);
600 } else {
601 if (mode & INTERP_PERSPECTIVE) {
602 e->inst[0] |= (1 << 25);
603 alloc_reg(pc, iv);
604 e->inst[0] |= (iv->hw << 9);
605 }
606
607 if (mode & INTERP_CENTROID)
608 e->inst[0] |= (1 << 24);
609 }
610
611 emit(pc, e);
612 }
613
614 static void
615 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
616 struct nv50_program_exec *e)
617 {
618 set_long(pc, e);
619
620 e->param.index = src->hw & 127;
621 e->param.shift = s;
622 e->param.mask = m << (s % 32);
623
624 if (src->hw < 0 || src->hw > 127) /* need (additional) address reg */
625 set_addr(e, get_address_reg(pc, src));
626 else
627 if (src->acc < 0) {
628 assert(src->type == P_CONST);
629 set_addr(e, pc->addr[src->indirect[0]]);
630 }
631
632 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
633 }
634
635 /* Never apply nv50_reg::mod in emit_mov, or carefully check the code !!! */
636 static void
637 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
638 {
639 struct nv50_program_exec *e = exec(pc);
640
641 e->inst[0] = 0x10000000;
642 if (!pc->allow32)
643 set_long(pc, e);
644
645 set_dst(pc, dst, e);
646
647 if (!is_long(e) && src->type == P_IMMD) {
648 set_immd(pc, src, e);
649 /*XXX: 32-bit, but steals part of "half" reg space - need to
650 * catch and handle this case if/when we do half-regs
651 */
652 } else
653 if (src->type == P_IMMD || src->type == P_CONST) {
654 set_long(pc, e);
655 set_data(pc, src, 0x7f, 9, e);
656 e->inst[1] |= 0x20000000; /* mov from c[] */
657 } else {
658 if (src->type == P_ATTR) {
659 set_long(pc, e);
660 e->inst[1] |= 0x00200000;
661
662 if (src->vtx >= 0) {
663 /* indirect (vertex base + c) load from p[] */
664 e->inst[0] |= 0x01800000;
665 set_addr(e, get_address_reg(pc, src));
666 }
667 }
668
669 alloc_reg(pc, src);
670 if (src->hw > 63)
671 set_long(pc, e);
672 e->inst[0] |= (src->hw << 9);
673 }
674
675 if (is_long(e) && !is_immd(e)) {
676 e->inst[1] |= 0x04000000; /* 32-bit */
677 e->inst[1] |= 0x0000c000; /* 32-bit c[] load / lane mask 0:1 */
678 if (!(e->inst[1] & 0x20000000))
679 e->inst[1] |= 0x00030000; /* lane mask 2:3 */
680 } else
681 e->inst[0] |= 0x00008000;
682
683 emit(pc, e);
684 }
685
686 static INLINE void
687 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
688 {
689 struct nv50_reg *imm = alloc_immd(pc, f);
690 emit_mov(pc, dst, imm);
691 FREE(imm);
692 }
693
694 /* Assign the hw of the discarded temporary register src
695 * to the tgsi register dst and free src.
696 */
697 static void
698 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
699 {
700 assert(src->index == -1 && src->hw != -1);
701
702 if (pc->if_lvl || pc->loop_lvl ||
703 (dst->type != P_TEMP) ||
704 (src->hw < pc->result_nr * 4 &&
705 pc->p->type == PIPE_SHADER_FRAGMENT) ||
706 pc->p->info.opcode_count[TGSI_OPCODE_CAL] ||
707 pc->p->info.opcode_count[TGSI_OPCODE_BRA]) {
708
709 emit_mov(pc, dst, src);
710 free_temp(pc, src);
711 return;
712 }
713
714 if (dst->hw != -1)
715 pc->r_temp[dst->hw] = NULL;
716 pc->r_temp[src->hw] = dst;
717 dst->hw = src->hw;
718
719 FREE(src);
720 }
721
722 static void
723 emit_nop(struct nv50_pc *pc)
724 {
725 struct nv50_program_exec *e = exec(pc);
726
727 e->inst[0] = 0xf0000000;
728 set_long(pc, e);
729 e->inst[1] = 0xe0000000;
730 emit(pc, e);
731 }
732
733 static boolean
734 check_swap_src_0_1(struct nv50_pc *pc,
735 struct nv50_reg **s0, struct nv50_reg **s1)
736 {
737 struct nv50_reg *src0 = *s0, *src1 = *s1;
738
739 if (src0->type == P_CONST) {
740 if (src1->type != P_CONST) {
741 *s0 = src1;
742 *s1 = src0;
743 return TRUE;
744 }
745 } else
746 if (src1->type == P_ATTR) {
747 if (src0->type != P_ATTR) {
748 *s0 = src1;
749 *s1 = src0;
750 return TRUE;
751 }
752 }
753
754 return FALSE;
755 }
756
757 static void
758 set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src,
759 struct nv50_program_exec *e)
760 {
761 struct nv50_reg *temp;
762
763 if (src->type != P_TEMP) {
764 temp = temp_temp(pc, e);
765 emit_mov(pc, temp, src);
766 src = temp;
767 }
768
769 alloc_reg(pc, src);
770 if (src->hw > 63)
771 set_long(pc, e);
772 e->inst[0] |= (src->hw << 9);
773 }
774
775 static void
776 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
777 {
778 if (src->type == P_ATTR) {
779 set_long(pc, e);
780 e->inst[1] |= 0x00200000;
781
782 if (src->vtx >= 0) {
783 e->inst[0] |= 0x01800000; /* src from p[] */
784 set_addr(e, get_address_reg(pc, src));
785 }
786 } else
787 if (src->type == P_CONST || src->type == P_IMMD) {
788 struct nv50_reg *temp = temp_temp(pc, e);
789
790 emit_mov(pc, temp, src);
791 src = temp;
792 }
793
794 alloc_reg(pc, src);
795 if (src->hw > 63)
796 set_long(pc, e);
797 e->inst[0] |= (src->hw << 9);
798 }
799
800 static void
801 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
802 {
803 if (src->type == P_ATTR) {
804 struct nv50_reg *temp = temp_temp(pc, e);
805
806 emit_mov(pc, temp, src);
807 src = temp;
808 } else
809 if (src->type == P_CONST || src->type == P_IMMD) {
810 if (e->inst[0] & 0x01800000) {
811 struct nv50_reg *temp = temp_temp(pc, e);
812
813 emit_mov(pc, temp, src);
814 src = temp;
815 } else {
816 assert(!(e->inst[0] & 0x00800000));
817 set_data(pc, src, 0x7f, 16, e);
818 e->inst[0] |= 0x00800000;
819 }
820 }
821
822 alloc_reg(pc, src);
823 if (src->hw > 63)
824 set_long(pc, e);
825 e->inst[0] |= ((src->hw & 127) << 16);
826 }
827
828 static void
829 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
830 {
831 set_long(pc, e);
832
833 if (src->type == P_ATTR) {
834 struct nv50_reg *temp = temp_temp(pc, e);
835
836 emit_mov(pc, temp, src);
837 src = temp;
838 } else
839 if (src->type == P_CONST || src->type == P_IMMD) {
840 if (e->inst[0] & 0x01800000) {
841 struct nv50_reg *temp = temp_temp(pc, e);
842
843 emit_mov(pc, temp, src);
844 src = temp;
845 } else {
846 assert(!(e->inst[0] & 0x01000000));
847 set_data(pc, src, 0x7f, 32+14, e);
848 e->inst[0] |= 0x01000000;
849 }
850 }
851
852 alloc_reg(pc, src);
853 e->inst[1] |= ((src->hw & 127) << 14);
854 }
855
856 static void
857 set_half_src(struct nv50_pc *pc, struct nv50_reg *src, int lh,
858 struct nv50_program_exec *e, int pos)
859 {
860 struct nv50_reg *r = src;
861
862 alloc_reg(pc, r);
863 if (r->type != P_TEMP) {
864 r = temp_temp(pc, e);
865 emit_mov(pc, r, src);
866 }
867
868 if (r->hw > (NV50_SU_MAX_TEMP / 2)) {
869 NOUVEAU_ERR("out of low GPRs\n");
870 abort();
871 }
872
873 e->inst[pos / 32] |= ((src->hw * 2) + lh) << (pos % 32);
874 }
875
876 static void
877 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
878 {
879 struct nv50_program_exec *e = exec(pc);
880
881 assert(dst->type == P_TEMP);
882 e->inst[1] = 0x20000000 | (pred << 12);
883 set_long(pc, e);
884 set_dst(pc, dst, e);
885
886 emit(pc, e);
887 }
888
889 static void
890 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
891 {
892 struct nv50_program_exec *e = exec(pc);
893
894 e->inst[0] = 0x000001fc;
895 e->inst[1] = 0xa0000008;
896 set_long(pc, e);
897 set_pred_wr(pc, 1, pred, e);
898 set_src_0_restricted(pc, src, e);
899
900 emit(pc, e);
901 }
902
903 static void
904 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
905 struct nv50_reg *src1)
906 {
907 struct nv50_program_exec *e = exec(pc);
908
909 e->inst[0] |= 0xc0000000;
910
911 if (!pc->allow32)
912 set_long(pc, e);
913
914 check_swap_src_0_1(pc, &src0, &src1);
915 set_dst(pc, dst, e);
916 set_src_0(pc, src0, e);
917 if (src1->type == P_IMMD && !is_long(e)) {
918 if (src0->mod ^ src1->mod)
919 e->inst[0] |= 0x00008000;
920 set_immd(pc, src1, e);
921 } else {
922 set_src_1(pc, src1, e);
923 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG) {
924 if (is_long(e))
925 e->inst[1] |= 0x08000000;
926 else
927 e->inst[0] |= 0x00008000;
928 }
929 }
930
931 emit(pc, e);
932 }
933
934 static void
935 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
936 struct nv50_reg *src0, struct nv50_reg *src1)
937 {
938 struct nv50_program_exec *e = exec(pc);
939
940 e->inst[0] = 0xb0000000;
941
942 alloc_reg(pc, src1);
943 check_swap_src_0_1(pc, &src0, &src1);
944
945 if (!pc->allow32 || (src0->mod | src1->mod) || src1->hw > 63) {
946 set_long(pc, e);
947 e->inst[1] |= ((src0->mod & NV50_MOD_NEG) << 26) |
948 ((src1->mod & NV50_MOD_NEG) << 27);
949 }
950
951 set_dst(pc, dst, e);
952 set_src_0(pc, src0, e);
953 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
954 set_src_2(pc, src1, e);
955 else
956 if (src1->type == P_IMMD)
957 set_immd(pc, src1, e);
958 else
959 set_src_1(pc, src1, e);
960
961 emit(pc, e);
962 }
963
964 static void
965 emit_arl(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
966 uint8_t s)
967 {
968 struct nv50_program_exec *e = exec(pc);
969
970 set_long(pc, e);
971 e->inst[1] |= 0xc0000000;
972
973 e->inst[0] |= dst->hw << 2;
974 e->inst[0] |= s << 16; /* shift left */
975 set_src_0(pc, src, e);
976
977 emit(pc, e);
978 }
979
980 static boolean
981 address_reg_suitable(struct nv50_reg *a, struct nv50_reg *r)
982 {
983 if (!r)
984 return FALSE;
985
986 if (r->vtx != a->vtx)
987 return FALSE;
988 if (r->vtx >= 0)
989 return (r->indirect[1] == a->indirect[1]);
990
991 if (r->hw < a->rhw || (r->hw - a->rhw) >= 128)
992 return FALSE;
993
994 if (a->index >= 0)
995 return (a->index == r->indirect[0]);
996 return (a->indirect[0] == r->indirect[0]);
997 }
998
999 static void
1000 load_vertex_base(struct nv50_pc *pc, struct nv50_reg *dst,
1001 struct nv50_reg *a, int shift)
1002 {
1003 struct nv50_reg mem, *temp;
1004
1005 ctor_reg(&mem, P_ATTR, -1, dst->vtx);
1006
1007 assert(dst->type == P_ADDR);
1008 if (!a) {
1009 emit_arl(pc, dst, &mem, 0);
1010 return;
1011 }
1012 temp = alloc_temp(pc, NULL);
1013
1014 if (shift) {
1015 emit_mov_from_addr(pc, temp, a);
1016 if (shift < 0)
1017 emit_shl_imm(pc, temp, temp, shift);
1018 emit_arl(pc, dst, temp, MAX2(shift, 0));
1019 }
1020 emit_mov(pc, temp, &mem);
1021 set_addr(pc->p->exec_tail, dst);
1022
1023 emit_arl(pc, dst, temp, 0);
1024 free_temp(pc, temp);
1025 }
1026
1027 /* case (ref == NULL): allocate address register for TGSI_FILE_ADDRESS
1028 * case (vtx >= 0, acc >= 0): load vertex base from a[vtx * 4] to $aX
1029 * case (vtx >= 0, acc < 0): load vertex base from s[$aY + vtx * 4] to $aX
1030 * case (vtx < 0, acc >= 0): memory address too high to encode
1031 * case (vtx < 0, acc < 0): get source register for TGSI_FILE_ADDRESS
1032 */
1033 static struct nv50_reg *
1034 get_address_reg(struct nv50_pc *pc, struct nv50_reg *ref)
1035 {
1036 int i;
1037 struct nv50_reg *a_ref, *a = NULL;
1038
1039 for (i = 0; i < NV50_SU_MAX_ADDR; ++i) {
1040 if (pc->r_addr[i].acc == 0)
1041 a = &pc->r_addr[i]; /* an unused address reg */
1042 else
1043 if (address_reg_suitable(&pc->r_addr[i], ref)) {
1044 pc->r_addr[i].acc = pc->insn_cur;
1045 return &pc->r_addr[i];
1046 } else
1047 if (!a && pc->r_addr[i].index < 0 &&
1048 pc->r_addr[i].acc < pc->insn_cur)
1049 a = &pc->r_addr[i];
1050 }
1051 if (!a) {
1052 /* We'll be able to spill address regs when this
1053 * mess is replaced with a proper compiler ...
1054 */
1055 NOUVEAU_ERR("out of address regs\n");
1056 abort();
1057 return NULL;
1058 }
1059
1060 /* initialize and reserve for this TGSI instruction */
1061 a->rhw = 0;
1062 a->index = a->indirect[0] = a->indirect[1] = -1;
1063 a->acc = pc->insn_cur;
1064
1065 if (!ref) {
1066 a->vtx = -1;
1067 return a;
1068 }
1069 a->vtx = ref->vtx;
1070
1071 /* now put in the correct value ... */
1072
1073 if (ref->vtx >= 0) {
1074 a->indirect[1] = ref->indirect[1];
1075
1076 /* For an indirect vertex index, we need to shift address right
1077 * by 2, the address register will contain vtx * 16, we need to
1078 * load from a[vtx * 4].
1079 */
1080 load_vertex_base(pc, a, (ref->acc < 0) ?
1081 pc->addr[ref->indirect[1]] : NULL, -2);
1082 } else {
1083 assert(ref->acc < 0 || ref->indirect[0] < 0);
1084
1085 a->rhw = ref->hw & ~0x7f;
1086 a->indirect[0] = ref->indirect[0];
1087 a_ref = (ref->acc < 0) ? pc->addr[ref->indirect[0]] : NULL;
1088
1089 emit_add_addr_imm(pc, a, a_ref, a->rhw * 4);
1090 }
1091 return a;
1092 }
1093
1094 #define NV50_MAX_F32 0x880
1095 #define NV50_MAX_S32 0x08c
1096 #define NV50_MAX_U32 0x084
1097 #define NV50_MIN_F32 0x8a0
1098 #define NV50_MIN_S32 0x0ac
1099 #define NV50_MIN_U32 0x0a4
1100
1101 static void
1102 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
1103 struct nv50_reg *src0, struct nv50_reg *src1)
1104 {
1105 struct nv50_program_exec *e = exec(pc);
1106
1107 set_long(pc, e);
1108 e->inst[0] |= 0x30000000 | ((sub & 0x800) << 20);
1109 e->inst[1] |= (sub << 24);
1110
1111 check_swap_src_0_1(pc, &src0, &src1);
1112 set_dst(pc, dst, e);
1113 set_src_0(pc, src0, e);
1114 set_src_1(pc, src1, e);
1115
1116 if (src0->mod & NV50_MOD_ABS)
1117 e->inst[1] |= 0x00100000;
1118 if (src1->mod & NV50_MOD_ABS)
1119 e->inst[1] |= 0x00080000;
1120
1121 emit(pc, e);
1122 }
1123
1124 static INLINE void
1125 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1126 struct nv50_reg *src1)
1127 {
1128 src1->mod ^= NV50_MOD_NEG;
1129 emit_add(pc, dst, src0, src1);
1130 src1->mod ^= NV50_MOD_NEG;
1131 }
1132
1133 static void
1134 emit_bitop2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1135 struct nv50_reg *src1, unsigned op)
1136 {
1137 struct nv50_program_exec *e = exec(pc);
1138
1139 e->inst[0] = 0xd0000000;
1140 set_long(pc, e);
1141
1142 check_swap_src_0_1(pc, &src0, &src1);
1143 set_dst(pc, dst, e);
1144 set_src_0(pc, src0, e);
1145
1146 if (op != TGSI_OPCODE_AND && op != TGSI_OPCODE_OR &&
1147 op != TGSI_OPCODE_XOR)
1148 assert(!"invalid bit op");
1149
1150 assert(!(src0->mod | src1->mod));
1151
1152 if (src1->type == P_IMMD && src0->type == P_TEMP && pc->allow32) {
1153 set_immd(pc, src1, e);
1154 if (op == TGSI_OPCODE_OR)
1155 e->inst[0] |= 0x0100;
1156 else
1157 if (op == TGSI_OPCODE_XOR)
1158 e->inst[0] |= 0x8000;
1159 } else {
1160 set_src_1(pc, src1, e);
1161 e->inst[1] |= 0x04000000; /* 32 bit */
1162 if (op == TGSI_OPCODE_OR)
1163 e->inst[1] |= 0x4000;
1164 else
1165 if (op == TGSI_OPCODE_XOR)
1166 e->inst[1] |= 0x8000;
1167 }
1168
1169 emit(pc, e);
1170 }
1171
1172 static void
1173 emit_not(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1174 {
1175 struct nv50_program_exec *e = exec(pc);
1176
1177 e->inst[0] = 0xd0000000;
1178 e->inst[1] = 0x0402c000;
1179 set_long(pc, e);
1180 set_dst(pc, dst, e);
1181 set_src_1(pc, src, e);
1182
1183 emit(pc, e);
1184 }
1185
1186 static void
1187 emit_shift(struct nv50_pc *pc, struct nv50_reg *dst,
1188 struct nv50_reg *src0, struct nv50_reg *src1, unsigned dir)
1189 {
1190 struct nv50_program_exec *e = exec(pc);
1191
1192 e->inst[0] = 0x30000000;
1193 e->inst[1] = 0xc4000000;
1194
1195 set_long(pc, e);
1196 set_dst(pc, dst, e);
1197 set_src_0(pc, src0, e);
1198
1199 if (src1->type == P_IMMD) {
1200 e->inst[1] |= (1 << 20);
1201 e->inst[0] |= (pc->immd_buf[src1->hw] & 0x7f) << 16;
1202 } else
1203 set_src_1(pc, src1, e);
1204
1205 if (dir != TGSI_OPCODE_SHL)
1206 e->inst[1] |= (1 << 29);
1207
1208 if (dir == TGSI_OPCODE_ISHR)
1209 e->inst[1] |= (1 << 27);
1210
1211 emit(pc, e);
1212 }
1213
1214 static void
1215 emit_shl_imm(struct nv50_pc *pc, struct nv50_reg *dst,
1216 struct nv50_reg *src, int s)
1217 {
1218 struct nv50_program_exec *e = exec(pc);
1219
1220 e->inst[0] = 0x30000000;
1221 e->inst[1] = 0xc4100000;
1222 if (s < 0) {
1223 e->inst[1] |= 1 << 29;
1224 s = -s;
1225 }
1226 e->inst[1] |= ((s & 0x7f) << 16);
1227
1228 set_long(pc, e);
1229 set_dst(pc, dst, e);
1230 set_src_0(pc, src, e);
1231
1232 emit(pc, e);
1233 }
1234
1235 static void
1236 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1237 struct nv50_reg *src1, struct nv50_reg *src2)
1238 {
1239 struct nv50_program_exec *e = exec(pc);
1240
1241 e->inst[0] |= 0xe0000000;
1242
1243 check_swap_src_0_1(pc, &src0, &src1);
1244 set_dst(pc, dst, e);
1245 set_src_0(pc, src0, e);
1246 set_src_1(pc, src1, e);
1247 set_src_2(pc, src2, e);
1248
1249 if ((src0->mod ^ src1->mod) & NV50_MOD_NEG)
1250 e->inst[1] |= 0x04000000;
1251 if (src2->mod & NV50_MOD_NEG)
1252 e->inst[1] |= 0x08000000;
1253
1254 emit(pc, e);
1255 }
1256
1257 static INLINE void
1258 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
1259 struct nv50_reg *src1, struct nv50_reg *src2)
1260 {
1261 src2->mod ^= NV50_MOD_NEG;
1262 emit_mad(pc, dst, src0, src1, src2);
1263 src2->mod ^= NV50_MOD_NEG;
1264 }
1265
1266 #define NV50_FLOP_RCP 0
1267 #define NV50_FLOP_RSQ 2
1268 #define NV50_FLOP_LG2 3
1269 #define NV50_FLOP_SIN 4
1270 #define NV50_FLOP_COS 5
1271 #define NV50_FLOP_EX2 6
1272
1273 /* rcp, rsqrt, lg2 support neg and abs */
1274 static void
1275 emit_flop(struct nv50_pc *pc, unsigned sub,
1276 struct nv50_reg *dst, struct nv50_reg *src)
1277 {
1278 struct nv50_program_exec *e = exec(pc);
1279
1280 e->inst[0] |= 0x90000000;
1281 if (sub || src->mod) {
1282 set_long(pc, e);
1283 e->inst[1] |= (sub << 29);
1284 }
1285
1286 set_dst(pc, dst, e);
1287 set_src_0_restricted(pc, src, e);
1288
1289 assert(!src->mod || sub < 4);
1290
1291 if (src->mod & NV50_MOD_NEG)
1292 e->inst[1] |= 0x04000000;
1293 if (src->mod & NV50_MOD_ABS)
1294 e->inst[1] |= 0x00100000;
1295
1296 emit(pc, e);
1297 }
1298
1299 static void
1300 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1301 {
1302 struct nv50_program_exec *e = exec(pc);
1303
1304 e->inst[0] |= 0xb0000000;
1305
1306 set_dst(pc, dst, e);
1307 set_src_0(pc, src, e);
1308 set_long(pc, e);
1309 e->inst[1] |= (6 << 29) | 0x00004000;
1310
1311 if (src->mod & NV50_MOD_NEG)
1312 e->inst[1] |= 0x04000000;
1313 if (src->mod & NV50_MOD_ABS)
1314 e->inst[1] |= 0x00100000;
1315
1316 emit(pc, e);
1317 }
1318
1319 static void
1320 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1321 {
1322 struct nv50_program_exec *e = exec(pc);
1323
1324 e->inst[0] |= 0xb0000000;
1325
1326 set_dst(pc, dst, e);
1327 set_src_0(pc, src, e);
1328 set_long(pc, e);
1329 e->inst[1] |= (6 << 29);
1330
1331 if (src->mod & NV50_MOD_NEG)
1332 e->inst[1] |= 0x04000000;
1333 if (src->mod & NV50_MOD_ABS)
1334 e->inst[1] |= 0x00100000;
1335
1336 emit(pc, e);
1337 }
1338
1339 #define CVT_RN (0x00 << 16)
1340 #define CVT_FLOOR (0x02 << 16)
1341 #define CVT_CEIL (0x04 << 16)
1342 #define CVT_TRUNC (0x06 << 16)
1343 #define CVT_SAT (0x08 << 16)
1344 #define CVT_ABS (0x10 << 16)
1345
1346 #define CVT_X32_X32 0x04004000
1347 #define CVT_X32_S32 0x04014000
1348 #define CVT_F32_F32 ((0xc0 << 24) | CVT_X32_X32)
1349 #define CVT_S32_F32 ((0x88 << 24) | CVT_X32_X32)
1350 #define CVT_U32_F32 ((0x80 << 24) | CVT_X32_X32)
1351 #define CVT_F32_S32 ((0x40 << 24) | CVT_X32_S32)
1352 #define CVT_F32_U32 ((0x40 << 24) | CVT_X32_X32)
1353 #define CVT_S32_S32 ((0x08 << 24) | CVT_X32_S32)
1354 #define CVT_S32_U32 ((0x08 << 24) | CVT_X32_X32)
1355 #define CVT_U32_S32 ((0x00 << 24) | CVT_X32_S32)
1356
1357 #define CVT_NEG 0x20000000
1358 #define CVT_RI 0x08000000
1359
1360 static void
1361 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
1362 int wp, uint32_t cvn)
1363 {
1364 struct nv50_program_exec *e;
1365
1366 e = exec(pc);
1367
1368 if (src->mod & NV50_MOD_NEG) cvn |= CVT_NEG;
1369 if (src->mod & NV50_MOD_ABS) cvn |= CVT_ABS;
1370
1371 e->inst[0] = 0xa0000000;
1372 e->inst[1] = cvn;
1373 set_long(pc, e);
1374 set_src_0(pc, src, e);
1375
1376 if (wp >= 0)
1377 set_pred_wr(pc, 1, wp, e);
1378
1379 if (dst)
1380 set_dst(pc, dst, e);
1381 else {
1382 e->inst[0] |= 0x000001fc;
1383 e->inst[1] |= 0x00000008;
1384 }
1385
1386 emit(pc, e);
1387 }
1388
1389 /* nv50 Condition codes:
1390 * 0x1 = LT
1391 * 0x2 = EQ
1392 * 0x3 = LE
1393 * 0x4 = GT
1394 * 0x5 = NE
1395 * 0x6 = GE
1396 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
1397 * 0x8 = unordered bit (allows NaN)
1398 *
1399 * mode = 0x04 (u32), 0x0c (s32), 0x80 (f32)
1400 */
1401 static void
1402 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
1403 struct nv50_reg *src0, struct nv50_reg *src1, uint8_t mode)
1404 {
1405 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
1406
1407 struct nv50_program_exec *e = exec(pc);
1408 struct nv50_reg *rdst;
1409
1410 assert(ccode < 16);
1411 if (check_swap_src_0_1(pc, &src0, &src1))
1412 ccode = cc_swapped[ccode & 7] | (ccode & 8);
1413
1414 rdst = dst;
1415 if (dst && dst->type != P_TEMP)
1416 dst = alloc_temp(pc, NULL);
1417
1418 set_long(pc, e);
1419 e->inst[0] |= 0x30000000 | (mode << 24);
1420 e->inst[1] |= 0x60000000 | (ccode << 14);
1421
1422 if (wp >= 0)
1423 set_pred_wr(pc, 1, wp, e);
1424 if (dst)
1425 set_dst(pc, dst, e);
1426 else {
1427 e->inst[0] |= 0x000001fc;
1428 e->inst[1] |= 0x00000008;
1429 }
1430
1431 set_src_0(pc, src0, e);
1432 set_src_1(pc, src1, e);
1433
1434 emit(pc, e);
1435
1436 if (rdst && mode == 0x80) /* convert to float ? */
1437 emit_cvt(pc, rdst, dst, -1, CVT_ABS | CVT_F32_S32);
1438 if (rdst && rdst != dst)
1439 free_temp(pc, dst);
1440 }
1441
1442 static INLINE void
1443 map_tgsi_setop_hw(unsigned op, uint8_t *cc, uint8_t *ty)
1444 {
1445 switch (op) {
1446 case TGSI_OPCODE_SLT: *cc = 0x1; *ty = 0x80; break;
1447 case TGSI_OPCODE_SGE: *cc = 0x6; *ty = 0x80; break;
1448 case TGSI_OPCODE_SEQ: *cc = 0x2; *ty = 0x80; break;
1449 case TGSI_OPCODE_SGT: *cc = 0x4; *ty = 0x80; break;
1450 case TGSI_OPCODE_SLE: *cc = 0x3; *ty = 0x80; break;
1451 case TGSI_OPCODE_SNE: *cc = 0xd; *ty = 0x80; break;
1452
1453 case TGSI_OPCODE_ISLT: *cc = 0x1; *ty = 0x0c; break;
1454 case TGSI_OPCODE_ISGE: *cc = 0x6; *ty = 0x0c; break;
1455 case TGSI_OPCODE_USEQ: *cc = 0x2; *ty = 0x04; break;
1456 case TGSI_OPCODE_USGE: *cc = 0x6; *ty = 0x04; break;
1457 case TGSI_OPCODE_USLT: *cc = 0x1; *ty = 0x04; break;
1458 case TGSI_OPCODE_USNE: *cc = 0x5; *ty = 0x04; break;
1459 default:
1460 assert(0);
1461 return;
1462 }
1463 }
1464
1465 static void
1466 emit_add_b32(struct nv50_pc *pc, struct nv50_reg *dst,
1467 struct nv50_reg *src0, struct nv50_reg *rsrc1)
1468 {
1469 struct nv50_program_exec *e = exec(pc);
1470 struct nv50_reg *src1;
1471
1472 e->inst[0] = 0x20000000;
1473
1474 alloc_reg(pc, rsrc1);
1475 check_swap_src_0_1(pc, &src0, &rsrc1);
1476
1477 src1 = rsrc1;
1478 if (src0->mod & rsrc1->mod & NV50_MOD_NEG) {
1479 src1 = temp_temp(pc, e);
1480 emit_cvt(pc, src1, rsrc1, -1, CVT_S32_S32);
1481 }
1482
1483 if (!pc->allow32 || src1->hw > 63 ||
1484 (src1->type != P_TEMP && src1->type != P_IMMD))
1485 set_long(pc, e);
1486
1487 set_dst(pc, dst, e);
1488 set_src_0(pc, src0, e);
1489
1490 if (is_long(e)) {
1491 e->inst[1] |= 1 << 26;
1492 set_src_2(pc, src1, e);
1493 } else {
1494 e->inst[0] |= 0x8000;
1495 if (src1->type == P_IMMD)
1496 set_immd(pc, src1, e);
1497 else
1498 set_src_1(pc, src1, e);
1499 }
1500
1501 if (src0->mod & NV50_MOD_NEG)
1502 e->inst[0] |= 1 << 28;
1503 else
1504 if (src1->mod & NV50_MOD_NEG)
1505 e->inst[0] |= 1 << 22;
1506
1507 emit(pc, e);
1508 }
1509
1510 static void
1511 emit_mad_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1512 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1,
1513 struct nv50_reg *src2)
1514 {
1515 struct nv50_program_exec *e = exec(pc);
1516
1517 e->inst[0] = 0x60000000;
1518 if (!pc->allow32)
1519 set_long(pc, e);
1520 set_dst(pc, dst, e);
1521
1522 set_half_src(pc, src0, lh_0, e, 9);
1523 set_half_src(pc, src1, lh_1, e, 16);
1524 alloc_reg(pc, src2);
1525 if (is_long(e) || (src2->type != P_TEMP) || (src2->hw != dst->hw))
1526 set_src_2(pc, src2, e);
1527
1528 emit(pc, e);
1529 }
1530
1531 static void
1532 emit_mul_u16(struct nv50_pc *pc, struct nv50_reg *dst,
1533 struct nv50_reg *src0, int lh_0, struct nv50_reg *src1, int lh_1)
1534 {
1535 struct nv50_program_exec *e = exec(pc);
1536
1537 e->inst[0] = 0x40000000;
1538 set_long(pc, e);
1539 set_dst(pc, dst, e);
1540
1541 set_half_src(pc, src0, lh_0, e, 9);
1542 set_half_src(pc, src1, lh_1, e, 16);
1543
1544 emit(pc, e);
1545 }
1546
1547 static void
1548 emit_sad(struct nv50_pc *pc, struct nv50_reg *dst,
1549 struct nv50_reg *src0, struct nv50_reg *src1, struct nv50_reg *src2)
1550 {
1551 struct nv50_program_exec *e = exec(pc);
1552
1553 e->inst[0] = 0x50000000;
1554 if (!pc->allow32)
1555 set_long(pc, e);
1556 check_swap_src_0_1(pc, &src0, &src1);
1557 set_dst(pc, dst, e);
1558 set_src_0(pc, src0, e);
1559 set_src_1(pc, src1, e);
1560 alloc_reg(pc, src2);
1561 if (is_long(e) || (src2->type != dst->type) || (src2->hw != dst->hw))
1562 set_src_2(pc, src2, e);
1563
1564 if (is_long(e))
1565 e->inst[1] |= 0x0c << 24;
1566 else
1567 e->inst[0] |= 0x81 << 8;
1568
1569 emit(pc, e);
1570 }
1571
1572 static INLINE void
1573 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1574 {
1575 emit_cvt(pc, dst, src, -1, CVT_FLOOR | CVT_F32_F32 | CVT_RI);
1576 }
1577
1578 static void
1579 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
1580 struct nv50_reg *v, struct nv50_reg *e)
1581 {
1582 struct nv50_reg *temp = alloc_temp(pc, NULL);
1583
1584 emit_flop(pc, NV50_FLOP_LG2, temp, v);
1585 emit_mul(pc, temp, temp, e);
1586 emit_preex2(pc, temp, temp);
1587 emit_flop(pc, NV50_FLOP_EX2, dst, temp);
1588
1589 free_temp(pc, temp);
1590 }
1591
1592 static INLINE void
1593 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1594 {
1595 emit_cvt(pc, dst, src, -1, CVT_SAT | CVT_F32_F32);
1596 }
1597
1598 static void
1599 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1600 struct nv50_reg **src)
1601 {
1602 struct nv50_reg *one = alloc_immd(pc, 1.0);
1603 struct nv50_reg *zero = alloc_immd(pc, 0.0);
1604 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
1605 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
1606 struct nv50_reg *tmp[4];
1607 boolean allow32 = pc->allow32;
1608
1609 pc->allow32 = FALSE;
1610
1611 if (mask & (3 << 1)) {
1612 tmp[0] = alloc_temp(pc, NULL);
1613 emit_minmax(pc, NV50_MAX_F32, tmp[0], src[0], zero);
1614 }
1615
1616 if (mask & (1 << 2)) {
1617 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
1618
1619 tmp[1] = temp_temp(pc, NULL);
1620 emit_minmax(pc, NV50_MAX_F32, tmp[1], src[1], zero);
1621
1622 tmp[3] = temp_temp(pc, NULL);
1623 emit_minmax(pc, NV50_MAX_F32, tmp[3], src[3], neg128);
1624 emit_minmax(pc, NV50_MIN_F32, tmp[3], tmp[3], pos128);
1625
1626 emit_pow(pc, dst[2], tmp[1], tmp[3]);
1627 emit_mov(pc, dst[2], zero);
1628 set_pred(pc, 3, 0, pc->p->exec_tail);
1629 }
1630
1631 if (mask & (1 << 1))
1632 assimilate_temp(pc, dst[1], tmp[0]);
1633 else
1634 if (mask & (1 << 2))
1635 free_temp(pc, tmp[0]);
1636
1637 pc->allow32 = allow32;
1638
1639 /* do this last, in case src[i,j] == dst[0,3] */
1640 if (mask & (1 << 0))
1641 emit_mov(pc, dst[0], one);
1642
1643 if (mask & (1 << 3))
1644 emit_mov(pc, dst[3], one);
1645
1646 FREE(pos128);
1647 FREE(neg128);
1648 FREE(zero);
1649 FREE(one);
1650 }
1651
1652 static void
1653 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1654 {
1655 struct nv50_program_exec *e;
1656 const int r_pred = 1;
1657
1658 e = exec(pc);
1659 e->inst[0] = 0x00000002; /* discard */
1660 set_long(pc, e); /* sets cond code to ALWAYS */
1661
1662 if (src) {
1663 set_pred(pc, 0x1 /* cc = LT */, r_pred, e);
1664 /* write to predicate reg */
1665 emit_cvt(pc, NULL, src, r_pred, CVT_F32_F32);
1666 }
1667
1668 emit(pc, e);
1669 }
1670
1671 static struct nv50_program_exec *
1672 emit_control_flow(struct nv50_pc *pc, unsigned op, int pred, unsigned cc)
1673 {
1674 struct nv50_program_exec *e = exec(pc);
1675
1676 e->inst[0] = (op << 28) | 2;
1677 set_long(pc, e);
1678 if (pred >= 0)
1679 set_pred(pc, cc, pred, e);
1680
1681 emit(pc, e);
1682 return e;
1683 }
1684
1685 static INLINE struct nv50_program_exec *
1686 emit_breakaddr(struct nv50_pc *pc)
1687 {
1688 return emit_control_flow(pc, 0x4, -1, 0);
1689 }
1690
1691 static INLINE void
1692 emit_break(struct nv50_pc *pc, int pred, unsigned cc)
1693 {
1694 emit_control_flow(pc, 0x5, pred, cc);
1695 }
1696
1697 static INLINE struct nv50_program_exec *
1698 emit_joinat(struct nv50_pc *pc)
1699 {
1700 return emit_control_flow(pc, 0xa, -1, 0);
1701 }
1702
1703 static INLINE struct nv50_program_exec *
1704 emit_branch(struct nv50_pc *pc, int pred, unsigned cc)
1705 {
1706 return emit_control_flow(pc, 0x1, pred, cc);
1707 }
1708
1709 static INLINE struct nv50_program_exec *
1710 emit_call(struct nv50_pc *pc, int pred, unsigned cc)
1711 {
1712 return emit_control_flow(pc, 0x2, pred, cc);
1713 }
1714
1715 static INLINE void
1716 emit_ret(struct nv50_pc *pc, int pred, unsigned cc)
1717 {
1718 emit_control_flow(pc, 0x3, pred, cc);
1719 }
1720
1721 #define QOP_ADD 0
1722 #define QOP_SUBR 1
1723 #define QOP_SUB 2
1724 #define QOP_MOV_SRC1 3
1725
1726 /* For a quad of threads / top left, top right, bottom left, bottom right
1727 * pixels, do a different operation, and take src0 from a specific thread.
1728 */
1729 static void
1730 emit_quadop(struct nv50_pc *pc, struct nv50_reg *dst, int wp, int lane_src0,
1731 struct nv50_reg *src0, struct nv50_reg *src1, ubyte qop)
1732 {
1733 struct nv50_program_exec *e = exec(pc);
1734
1735 e->inst[0] = 0xc0000000;
1736 e->inst[1] = 0x80000000;
1737 set_long(pc, e);
1738 e->inst[0] |= lane_src0 << 16;
1739 set_src_0(pc, src0, e);
1740 set_src_2(pc, src1, e);
1741
1742 if (wp >= 0)
1743 set_pred_wr(pc, 1, wp, e);
1744
1745 if (dst)
1746 set_dst(pc, dst, e);
1747 else {
1748 e->inst[0] |= 0x000001fc;
1749 e->inst[1] |= 0x00000008;
1750 }
1751
1752 e->inst[0] |= (qop & 3) << 20;
1753 e->inst[1] |= (qop >> 2) << 22;
1754
1755 emit(pc, e);
1756 }
1757
1758 static void
1759 load_cube_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1760 struct nv50_reg **src, unsigned arg, boolean proj)
1761 {
1762 int mod[3] = { src[0]->mod, src[1]->mod, src[2]->mod };
1763
1764 src[0]->mod |= NV50_MOD_ABS;
1765 src[1]->mod |= NV50_MOD_ABS;
1766 src[2]->mod |= NV50_MOD_ABS;
1767
1768 emit_minmax(pc, NV50_MAX_F32, t[2], src[0], src[1]);
1769 emit_minmax(pc, NV50_MAX_F32, t[2], src[2], t[2]);
1770
1771 src[0]->mod = mod[0];
1772 src[1]->mod = mod[1];
1773 src[2]->mod = mod[2];
1774
1775 if (proj && 0 /* looks more correct without this */)
1776 emit_mul(pc, t[2], t[2], src[3]);
1777 else
1778 if (arg == 4) /* there is no textureProj(samplerCubeShadow) */
1779 emit_mov(pc, t[3], src[3]);
1780
1781 emit_flop(pc, NV50_FLOP_RCP, t[2], t[2]);
1782
1783 emit_mul(pc, t[0], src[0], t[2]);
1784 emit_mul(pc, t[1], src[1], t[2]);
1785 emit_mul(pc, t[2], src[2], t[2]);
1786 }
1787
1788 static void
1789 load_proj_tex_coords(struct nv50_pc *pc, struct nv50_reg *t[4],
1790 struct nv50_reg **src, unsigned dim, unsigned arg)
1791 {
1792 unsigned c, mode;
1793
1794 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1795 mode = pc->interp_mode[src[0]->index] | INTERP_PERSPECTIVE;
1796
1797 t[3]->rhw = src[3]->rhw;
1798 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1799 emit_flop(pc, NV50_FLOP_RCP, t[3], t[3]);
1800
1801 for (c = 0; c < dim; ++c) {
1802 t[c]->rhw = src[c]->rhw;
1803 emit_interp(pc, t[c], t[3], mode);
1804 }
1805 if (arg != dim) { /* depth reference value */
1806 t[dim]->rhw = src[2]->rhw;
1807 emit_interp(pc, t[dim], t[3], mode);
1808 }
1809 } else {
1810 /* XXX: for some reason the blob sometimes uses MAD
1811 * (mad f32 $rX $rY $rZ neg $r63)
1812 */
1813 emit_flop(pc, NV50_FLOP_RCP, t[3], src[3]);
1814 for (c = 0; c < dim; ++c)
1815 emit_mul(pc, t[c], src[c], t[3]);
1816 if (arg != dim) /* depth reference value */
1817 emit_mul(pc, t[dim], src[2], t[3]);
1818 }
1819 }
1820
1821 static INLINE void
1822 get_tex_dim(unsigned type, unsigned *dim, unsigned *arg)
1823 {
1824 switch (type) {
1825 case TGSI_TEXTURE_1D:
1826 *arg = *dim = 1;
1827 break;
1828 case TGSI_TEXTURE_SHADOW1D:
1829 *dim = 1;
1830 *arg = 2;
1831 break;
1832 case TGSI_TEXTURE_UNKNOWN:
1833 case TGSI_TEXTURE_2D:
1834 case TGSI_TEXTURE_RECT:
1835 *arg = *dim = 2;
1836 break;
1837 case TGSI_TEXTURE_SHADOW2D:
1838 case TGSI_TEXTURE_SHADOWRECT:
1839 *dim = 2;
1840 *arg = 3;
1841 break;
1842 case TGSI_TEXTURE_3D:
1843 case TGSI_TEXTURE_CUBE:
1844 *dim = *arg = 3;
1845 break;
1846 default:
1847 assert(0);
1848 break;
1849 }
1850 }
1851
1852 /* We shouldn't execute TEXLOD if any of the pixels in a quad have
1853 * different LOD values, so branch off groups of equal LOD.
1854 */
1855 static void
1856 emit_texlod_sequence(struct nv50_pc *pc, struct nv50_reg *tlod,
1857 struct nv50_reg *src, struct nv50_program_exec *tex)
1858 {
1859 struct nv50_program_exec *join_at;
1860 unsigned i, target = pc->p->exec_size + 9 * 2;
1861
1862 if (pc->p->type != PIPE_SHADER_FRAGMENT) {
1863 emit(pc, tex);
1864 return;
1865 }
1866 pc->allow32 = FALSE;
1867
1868 /* Subtract lod of each pixel from lod of top left pixel, jump
1869 * texlod insn if result is 0, then repeat for 2 other pixels.
1870 */
1871 join_at = emit_joinat(pc);
1872 emit_quadop(pc, NULL, 0, 0, tlod, tlod, 0x55);
1873 emit_branch(pc, 0, 2)->param.index = target;
1874
1875 for (i = 1; i < 4; ++i) {
1876 emit_quadop(pc, NULL, 0, i, tlod, tlod, 0x55);
1877 emit_branch(pc, 0, 2)->param.index = target;
1878 }
1879
1880 emit_mov(pc, tlod, src); /* target */
1881 emit(pc, tex); /* texlod */
1882
1883 join_at->param.index = target + 2 * 2;
1884 JOIN_ON(emit_nop(pc)); /* join _after_ tex */
1885 }
1886
1887 static void
1888 emit_texbias_sequence(struct nv50_pc *pc, struct nv50_reg *t[4], unsigned arg,
1889 struct nv50_program_exec *tex)
1890 {
1891 struct nv50_program_exec *e;
1892 struct nv50_reg imm_1248, *t123[4][4], *r_bits = alloc_temp(pc, NULL);
1893 int r_pred = 0;
1894 unsigned n, c, i, cc[4] = { 0x0a, 0x13, 0x11, 0x10 };
1895
1896 pc->allow32 = FALSE;
1897 ctor_reg(&imm_1248, P_IMMD, -1, ctor_immd_4u32(pc, 1, 2, 4, 8) * 4);
1898
1899 /* Subtract bias value of thread i from bias values of each thread,
1900 * store result in r_pred, and set bit i in r_bits if result was 0.
1901 */
1902 assert(arg < 4);
1903 for (i = 0; i < 4; ++i, ++imm_1248.hw) {
1904 emit_quadop(pc, NULL, r_pred, i, t[arg], t[arg], 0x55);
1905 emit_mov(pc, r_bits, &imm_1248);
1906 set_pred(pc, 2, r_pred, pc->p->exec_tail);
1907 }
1908 emit_mov_to_pred(pc, r_pred, r_bits);
1909
1910 /* The lanes of a quad are now grouped by the bit in r_pred they have
1911 * set. Put the input values for TEX into a new register set for each
1912 * group and execute TEX only for a specific group.
1913 * We cannot use the same register set for each group because we need
1914 * the derivatives, which are implicitly calculated, to be correct.
1915 */
1916 for (i = 1; i < 4; ++i) {
1917 alloc_temp4(pc, t123[i], 0);
1918
1919 for (c = 0; c <= arg; ++c)
1920 emit_mov(pc, t123[i][c], t[c]);
1921
1922 *(e = exec(pc)) = *(tex);
1923 e->inst[0] &= ~0x01fc;
1924 set_dst(pc, t123[i][0], e);
1925 set_pred(pc, cc[i], r_pred, e);
1926 emit(pc, e);
1927 }
1928 /* finally TEX on the original regs (where we kept the input) */
1929 set_pred(pc, cc[0], r_pred, tex);
1930 emit(pc, tex);
1931
1932 /* put the 3 * n other results into regs for lane 0 */
1933 n = popcnt4(((e->inst[0] >> 25) & 0x3) | ((e->inst[1] >> 12) & 0xc));
1934 for (i = 1; i < 4; ++i) {
1935 for (c = 0; c < n; ++c) {
1936 emit_mov(pc, t[c], t123[i][c]);
1937 set_pred(pc, cc[i], r_pred, pc->p->exec_tail);
1938 }
1939 free_temp4(pc, t123[i]);
1940 }
1941
1942 emit_nop(pc);
1943 free_temp(pc, r_bits);
1944 }
1945
1946 static void
1947 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1948 struct nv50_reg **src, unsigned unit, unsigned type,
1949 boolean proj, int bias_lod)
1950 {
1951 struct nv50_reg *t[4];
1952 struct nv50_program_exec *e;
1953 unsigned c, dim, arg;
1954
1955 /* t[i] must be within a single 128 bit super-reg */
1956 alloc_temp4(pc, t, 0);
1957
1958 e = exec(pc);
1959 e->inst[0] = 0xf0000000;
1960 set_long(pc, e);
1961 set_dst(pc, t[0], e);
1962
1963 /* TIC and TSC binding indices (TSC is ignored as TSC_LINKED = TRUE): */
1964 e->inst[0] |= (unit << 9) /* | (unit << 17) */;
1965
1966 /* live flag (don't set if TEX results affect input to another TEX): */
1967 /* e->inst[0] |= 0x00000004; */
1968
1969 get_tex_dim(type, &dim, &arg);
1970
1971 if (type == TGSI_TEXTURE_CUBE) {
1972 e->inst[0] |= 0x08000000;
1973 load_cube_tex_coords(pc, t, src, arg, proj);
1974 } else
1975 if (proj)
1976 load_proj_tex_coords(pc, t, src, dim, arg);
1977 else {
1978 for (c = 0; c < dim; c++)
1979 emit_mov(pc, t[c], src[c]);
1980 if (arg != dim) /* depth reference value (always src.z here) */
1981 emit_mov(pc, t[dim], src[2]);
1982 }
1983
1984 e->inst[0] |= (mask & 0x3) << 25;
1985 e->inst[1] |= (mask & 0xc) << 12;
1986
1987 if (!bias_lod) {
1988 e->inst[0] |= (arg - 1) << 22;
1989 emit(pc, e);
1990 } else
1991 if (bias_lod < 0) {
1992 assert(pc->p->type == PIPE_SHADER_FRAGMENT);
1993 e->inst[0] |= arg << 22;
1994 e->inst[1] |= 0x20000000; /* texbias */
1995 emit_mov(pc, t[arg], src[3]);
1996 emit_texbias_sequence(pc, t, arg, e);
1997 } else {
1998 e->inst[0] |= arg << 22;
1999 e->inst[1] |= 0x40000000; /* texlod */
2000 emit_mov(pc, t[arg], src[3]);
2001 emit_texlod_sequence(pc, t[arg], src[3], e);
2002 }
2003
2004 #if 1
2005 c = 0;
2006 if (mask & 1) emit_mov(pc, dst[0], t[c++]);
2007 if (mask & 2) emit_mov(pc, dst[1], t[c++]);
2008 if (mask & 4) emit_mov(pc, dst[2], t[c++]);
2009 if (mask & 8) emit_mov(pc, dst[3], t[c]);
2010
2011 free_temp4(pc, t);
2012 #else
2013 /* XXX: if p.e. MUL is used directly after TEX, it would still use
2014 * the texture coordinates, not the fetched values: latency ? */
2015
2016 for (c = 0; c < 4; c++) {
2017 if (mask & (1 << c))
2018 assimilate_temp(pc, dst[c], t[c]);
2019 else
2020 free_temp(pc, t[c]);
2021 }
2022 #endif
2023 }
2024
2025 static void
2026 emit_ddx(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2027 {
2028 struct nv50_program_exec *e = exec(pc);
2029
2030 assert(src->type == P_TEMP);
2031
2032 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0240000 : 0xc0140000;
2033 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x86400000 : 0x89800000;
2034 set_long(pc, e);
2035 set_dst(pc, dst, e);
2036 set_src_0(pc, src, e);
2037 set_src_2(pc, src, e);
2038
2039 emit(pc, e);
2040 }
2041
2042 static void
2043 emit_ddy(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
2044 {
2045 struct nv50_program_exec *e = exec(pc);
2046
2047 assert(src->type == P_TEMP);
2048
2049 e->inst[0] = (src->mod & NV50_MOD_NEG) ? 0xc0250000 : 0xc0150000;
2050 e->inst[1] = (src->mod & NV50_MOD_NEG) ? 0x85800000 : 0x8a400000;
2051 set_long(pc, e);
2052 set_dst(pc, dst, e);
2053 set_src_0(pc, src, e);
2054 set_src_2(pc, src, e);
2055
2056 emit(pc, e);
2057 }
2058
2059 static void
2060 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
2061 {
2062 unsigned q = 0, m = ~0;
2063
2064 assert(!is_long(e));
2065
2066 switch (e->inst[0] >> 28) {
2067 case 0x1:
2068 /* MOV */
2069 q = 0x0403c000;
2070 m = 0xffff7fff;
2071 break;
2072 case 0x2:
2073 case 0x3:
2074 /* ADD, SUB, SUBR b32 */
2075 m = ~(0x8000 | (127 << 16));
2076 q = ((e->inst[0] & (~m)) >> 2) | (1 << 26);
2077 break;
2078 case 0x5:
2079 /* SAD */
2080 m = ~(0x81 << 8);
2081 q = (0x0c << 24) | ((e->inst[0] & (0x7f << 2)) << 12);
2082 break;
2083 case 0x6:
2084 /* MAD u16 */
2085 q = (e->inst[0] & (0x7f << 2)) << 12;
2086 break;
2087 case 0x8:
2088 /* INTERP (move centroid, perspective and flat bits) */
2089 m = ~0x03000100;
2090 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
2091 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
2092 break;
2093 case 0x9:
2094 /* RCP */
2095 break;
2096 case 0xB:
2097 /* ADD */
2098 m = ~(127 << 16);
2099 q = ((e->inst[0] & (~m)) >> 2);
2100 break;
2101 case 0xC:
2102 /* MUL */
2103 m = ~0x00008000;
2104 q = ((e->inst[0] & (~m)) << 12);
2105 break;
2106 case 0xE:
2107 /* MAD (if src2 == dst) */
2108 q = ((e->inst[0] & 0x1fc) << 12);
2109 break;
2110 default:
2111 assert(0);
2112 break;
2113 }
2114
2115 set_long(pc, e);
2116 pc->p->exec_size++;
2117
2118 e->inst[0] &= m;
2119 e->inst[1] |= q;
2120 }
2121
2122 /* Some operations support an optional negation flag. */
2123 static int
2124 get_supported_mods(const struct tgsi_full_instruction *insn, int i)
2125 {
2126 switch (insn->Instruction.Opcode) {
2127 case TGSI_OPCODE_ADD:
2128 case TGSI_OPCODE_COS:
2129 case TGSI_OPCODE_DDX:
2130 case TGSI_OPCODE_DDY:
2131 case TGSI_OPCODE_DP3:
2132 case TGSI_OPCODE_DP4:
2133 case TGSI_OPCODE_EX2:
2134 case TGSI_OPCODE_KIL:
2135 case TGSI_OPCODE_LG2:
2136 case TGSI_OPCODE_MAD:
2137 case TGSI_OPCODE_MUL:
2138 case TGSI_OPCODE_POW:
2139 case TGSI_OPCODE_RCP:
2140 case TGSI_OPCODE_RSQ: /* ignored, RSQ = rsqrt(abs(src.x)) */
2141 case TGSI_OPCODE_SCS:
2142 case TGSI_OPCODE_SIN:
2143 case TGSI_OPCODE_SUB:
2144 return NV50_MOD_NEG;
2145 case TGSI_OPCODE_MAX:
2146 case TGSI_OPCODE_MIN:
2147 case TGSI_OPCODE_INEG: /* tgsi src sign toggle/set would be stupid */
2148 return NV50_MOD_ABS;
2149 case TGSI_OPCODE_CEIL:
2150 case TGSI_OPCODE_FLR:
2151 case TGSI_OPCODE_TRUNC:
2152 return NV50_MOD_NEG | NV50_MOD_ABS;
2153 case TGSI_OPCODE_F2I:
2154 case TGSI_OPCODE_F2U:
2155 case TGSI_OPCODE_I2F:
2156 case TGSI_OPCODE_U2F:
2157 return NV50_MOD_NEG | NV50_MOD_ABS | NV50_MOD_I32;
2158 case TGSI_OPCODE_UADD:
2159 return NV50_MOD_NEG | NV50_MOD_I32;
2160 case TGSI_OPCODE_SAD:
2161 case TGSI_OPCODE_SHL:
2162 case TGSI_OPCODE_IMAX:
2163 case TGSI_OPCODE_IMIN:
2164 case TGSI_OPCODE_ISHR:
2165 case TGSI_OPCODE_NOT:
2166 case TGSI_OPCODE_UMAD:
2167 case TGSI_OPCODE_UMAX:
2168 case TGSI_OPCODE_UMIN:
2169 case TGSI_OPCODE_UMUL:
2170 case TGSI_OPCODE_USHR:
2171 return NV50_MOD_I32;
2172 default:
2173 return 0;
2174 }
2175 }
2176
2177 /* Return a read mask for source registers deduced from opcode & write mask. */
2178 static unsigned
2179 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
2180 {
2181 unsigned x, mask = insn->Dst[0].Register.WriteMask;
2182
2183 switch (insn->Instruction.Opcode) {
2184 case TGSI_OPCODE_COS:
2185 case TGSI_OPCODE_SIN:
2186 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
2187 case TGSI_OPCODE_DP3:
2188 return 0x7;
2189 case TGSI_OPCODE_DP4:
2190 case TGSI_OPCODE_DPH:
2191 case TGSI_OPCODE_KIL: /* WriteMask ignored */
2192 return 0xf;
2193 case TGSI_OPCODE_DST:
2194 return mask & (c ? 0xa : 0x6);
2195 case TGSI_OPCODE_EX2:
2196 case TGSI_OPCODE_EXP:
2197 case TGSI_OPCODE_LG2:
2198 case TGSI_OPCODE_LOG:
2199 case TGSI_OPCODE_POW:
2200 case TGSI_OPCODE_RCP:
2201 case TGSI_OPCODE_RSQ:
2202 case TGSI_OPCODE_SCS:
2203 return 0x1;
2204 case TGSI_OPCODE_IF:
2205 return 0x1;
2206 case TGSI_OPCODE_LIT:
2207 return 0xb;
2208 case TGSI_OPCODE_TEX:
2209 case TGSI_OPCODE_TXB:
2210 case TGSI_OPCODE_TXL:
2211 case TGSI_OPCODE_TXP:
2212 {
2213 const struct tgsi_instruction_texture *tex;
2214
2215 assert(insn->Instruction.Texture);
2216 tex = &insn->Texture;
2217
2218 mask = 0x7;
2219 if (insn->Instruction.Opcode != TGSI_OPCODE_TEX &&
2220 insn->Instruction.Opcode != TGSI_OPCODE_TXD)
2221 mask |= 0x8; /* bias, lod or proj */
2222
2223 switch (tex->Texture) {
2224 case TGSI_TEXTURE_1D:
2225 mask &= 0x9;
2226 break;
2227 case TGSI_TEXTURE_SHADOW1D:
2228 mask &= 0x5;
2229 break;
2230 case TGSI_TEXTURE_2D:
2231 mask &= 0xb;
2232 break;
2233 default:
2234 break;
2235 }
2236 }
2237 return mask;
2238 case TGSI_OPCODE_XPD:
2239 x = 0;
2240 if (mask & 1) x |= 0x6;
2241 if (mask & 2) x |= 0x5;
2242 if (mask & 4) x |= 0x3;
2243 return x;
2244 default:
2245 break;
2246 }
2247
2248 return mask;
2249 }
2250
2251 static struct nv50_reg *
2252 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
2253 {
2254 switch (dst->Register.File) {
2255 case TGSI_FILE_TEMPORARY:
2256 return &pc->temp[dst->Register.Index * 4 + c];
2257 case TGSI_FILE_OUTPUT:
2258 return &pc->result[dst->Register.Index * 4 + c];
2259 case TGSI_FILE_ADDRESS:
2260 {
2261 struct nv50_reg *r = pc->addr[dst->Register.Index * 4 + c];
2262 if (!r) {
2263 r = get_address_reg(pc, NULL);
2264 r->index = dst->Register.Index * 4 + c;
2265 pc->addr[r->index] = r;
2266 }
2267 assert(r);
2268 return r;
2269 }
2270 case TGSI_FILE_NULL:
2271 return NULL;
2272 default:
2273 break;
2274 }
2275
2276 return NULL;
2277 }
2278
2279 static struct nv50_reg *
2280 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
2281 int mod)
2282 {
2283 struct nv50_reg *r = NULL;
2284 struct nv50_reg *temp = NULL;
2285 unsigned sgn, c, swz, cvn;
2286
2287 if (src->Register.File != TGSI_FILE_CONSTANT)
2288 assert(!src->Register.Indirect);
2289
2290 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
2291
2292 c = tgsi_util_get_full_src_register_swizzle(src, chan);
2293 switch (c) {
2294 case TGSI_SWIZZLE_X:
2295 case TGSI_SWIZZLE_Y:
2296 case TGSI_SWIZZLE_Z:
2297 case TGSI_SWIZZLE_W:
2298 switch (src->Register.File) {
2299 case TGSI_FILE_INPUT:
2300 r = &pc->attr[src->Register.Index * 4 + c];
2301
2302 if (!src->Dimension.Dimension)
2303 break;
2304 r = reg_instance(pc, r);
2305 r->vtx = src->Dimension.Index;
2306
2307 if (!src->Dimension.Indirect)
2308 break;
2309 swz = tgsi_util_get_src_register_swizzle(
2310 &src->DimIndirect, 0);
2311 r->acc = -1;
2312 r->indirect[1] = src->DimIndirect.Index * 4 + swz;
2313 break;
2314 case TGSI_FILE_TEMPORARY:
2315 r = &pc->temp[src->Register.Index * 4 + c];
2316 break;
2317 case TGSI_FILE_CONSTANT:
2318 if (!src->Register.Indirect) {
2319 r = &pc->param[src->Register.Index * 4 + c];
2320 break;
2321 }
2322 /* Indicate indirection by setting r->acc < 0 and
2323 * use the index field to select the address reg.
2324 */
2325 r = reg_instance(pc, NULL);
2326 ctor_reg(r, P_CONST, -1, src->Register.Index * 4 + c);
2327
2328 swz = tgsi_util_get_src_register_swizzle(
2329 &src->Indirect, 0);
2330 r->acc = -1;
2331 r->indirect[0] = src->Indirect.Index * 4 + swz;
2332 break;
2333 case TGSI_FILE_IMMEDIATE:
2334 r = &pc->immd[src->Register.Index * 4 + c];
2335 break;
2336 case TGSI_FILE_SAMPLER:
2337 return NULL;
2338 case TGSI_FILE_ADDRESS:
2339 r = pc->addr[src->Register.Index * 4 + c];
2340 assert(r);
2341 break;
2342 default:
2343 assert(0);
2344 break;
2345 }
2346 break;
2347 default:
2348 assert(0);
2349 break;
2350 }
2351
2352 cvn = (mod & NV50_MOD_I32) ? CVT_S32_S32 : CVT_F32_F32;
2353
2354 switch (sgn) {
2355 case TGSI_UTIL_SIGN_CLEAR:
2356 r->mod = NV50_MOD_ABS;
2357 break;
2358 case TGSI_UTIL_SIGN_SET:
2359 r->mod = NV50_MOD_NEG_ABS;
2360 break;
2361 case TGSI_UTIL_SIGN_TOGGLE:
2362 r->mod = NV50_MOD_NEG;
2363 break;
2364 default:
2365 assert(!r->mod && sgn == TGSI_UTIL_SIGN_KEEP);
2366 break;
2367 }
2368
2369 if ((r->mod & mod) != r->mod) {
2370 temp = temp_temp(pc, NULL);
2371 emit_cvt(pc, temp, r, -1, cvn);
2372 r->mod = 0;
2373 r = temp;
2374 } else
2375 r->mod |= mod & NV50_MOD_I32;
2376
2377 assert(r);
2378 if (r->acc >= 0 && r->vtx < 0 && r != temp)
2379 return reg_instance(pc, r); /* will clear r->mod */
2380 return r;
2381 }
2382
2383 /* return TRUE for ops that produce only a single result */
2384 static boolean
2385 is_scalar_op(unsigned op)
2386 {
2387 switch (op) {
2388 case TGSI_OPCODE_COS:
2389 case TGSI_OPCODE_DP2:
2390 case TGSI_OPCODE_DP3:
2391 case TGSI_OPCODE_DP4:
2392 case TGSI_OPCODE_DPH:
2393 case TGSI_OPCODE_EX2:
2394 case TGSI_OPCODE_LG2:
2395 case TGSI_OPCODE_POW:
2396 case TGSI_OPCODE_RCP:
2397 case TGSI_OPCODE_RSQ:
2398 case TGSI_OPCODE_SIN:
2399 /*
2400 case TGSI_OPCODE_KIL:
2401 case TGSI_OPCODE_LIT:
2402 case TGSI_OPCODE_SCS:
2403 */
2404 return TRUE;
2405 default:
2406 return FALSE;
2407 }
2408 }
2409
2410 /* Returns a bitmask indicating which dst components depend
2411 * on source s, component c (reverse of nv50_tgsi_src_mask).
2412 */
2413 static unsigned
2414 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
2415 {
2416 if (is_scalar_op(op))
2417 return 0x1;
2418
2419 switch (op) {
2420 case TGSI_OPCODE_DST:
2421 return (1 << c) & (s ? 0xa : 0x6);
2422 case TGSI_OPCODE_XPD:
2423 switch (c) {
2424 case 0: return 0x6;
2425 case 1: return 0x5;
2426 case 2: return 0x3;
2427 case 3: return 0x0;
2428 default:
2429 assert(0);
2430 return 0x0;
2431 }
2432 case TGSI_OPCODE_EXP:
2433 case TGSI_OPCODE_LOG:
2434 case TGSI_OPCODE_LIT:
2435 case TGSI_OPCODE_SCS:
2436 case TGSI_OPCODE_TEX:
2437 case TGSI_OPCODE_TXB:
2438 case TGSI_OPCODE_TXL:
2439 case TGSI_OPCODE_TXP:
2440 /* these take care of dangerous swizzles themselves */
2441 return 0x0;
2442 case TGSI_OPCODE_IF:
2443 case TGSI_OPCODE_KIL:
2444 /* don't call this function for these ops */
2445 assert(0);
2446 return 0;
2447 default:
2448 /* linear vector instruction */
2449 return (1 << c);
2450 }
2451 }
2452
2453 static INLINE boolean
2454 has_pred(struct nv50_program_exec *e, unsigned cc)
2455 {
2456 if (!is_long(e) || is_immd(e))
2457 return FALSE;
2458 return ((e->inst[1] & 0x780) == (cc << 7));
2459 }
2460
2461 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
2462 * join_at ENDIF
2463 * @p0.eq bra ENDIF
2464 * single_op
2465 * ENDIF: nop.join
2466 */
2467 static boolean
2468 nv50_kill_branch(struct nv50_pc *pc)
2469 {
2470 int lvl = pc->if_lvl;
2471
2472 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
2473 return FALSE;
2474 if (is_immd(pc->p->exec_tail))
2475 return FALSE;
2476
2477 /* if ccode == 'true', the BRA is from an ELSE and the predicate
2478 * reg may no longer be valid, since we currently always use $p0
2479 */
2480 if (has_pred(pc->if_insn[lvl], 0xf))
2481 return FALSE;
2482 assert(pc->if_insn[lvl] && pc->if_join[lvl]);
2483
2484 /* We'll use the exec allocated for JOIN_AT (we can't easily
2485 * access nv50_program_exec's prev).
2486 */
2487 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
2488
2489 *pc->if_join[lvl] = *pc->p->exec_tail;
2490
2491 FREE(pc->if_insn[lvl]);
2492 FREE(pc->p->exec_tail);
2493
2494 pc->p->exec_tail = pc->if_join[lvl];
2495 pc->p->exec_tail->next = NULL;
2496 set_pred(pc, 0xd, 0, pc->p->exec_tail);
2497
2498 return TRUE;
2499 }
2500
2501 static void
2502 nv50_fp_move_results(struct nv50_pc *pc)
2503 {
2504 struct nv50_reg reg;
2505 unsigned i;
2506
2507 ctor_reg(&reg, P_TEMP, -1, -1);
2508
2509 for (i = 0; i < pc->result_nr * 4; ++i) {
2510 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2511 continue;
2512 if (pc->result[i].rhw != pc->result[i].hw) {
2513 reg.hw = pc->result[i].rhw;
2514 emit_mov(pc, &reg, &pc->result[i]);
2515 }
2516 }
2517 }
2518
2519 static boolean
2520 nv50_program_tx_insn(struct nv50_pc *pc,
2521 const struct tgsi_full_instruction *inst)
2522 {
2523 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
2524 unsigned mask, sat, unit;
2525 int i, c;
2526
2527 mask = inst->Dst[0].Register.WriteMask;
2528 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
2529
2530 memset(src, 0, sizeof(src));
2531
2532 for (c = 0; c < 4; c++) {
2533 if ((mask & (1 << c)) && !pc->r_dst[c])
2534 dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
2535 else
2536 dst[c] = pc->r_dst[c];
2537 rdst[c] = dst[c];
2538 }
2539
2540 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2541 const struct tgsi_full_src_register *fs = &inst->Src[i];
2542 unsigned src_mask;
2543 int mod_supp;
2544
2545 src_mask = nv50_tgsi_src_mask(inst, i);
2546 mod_supp = get_supported_mods(inst, i);
2547
2548 if (fs->Register.File == TGSI_FILE_SAMPLER)
2549 unit = fs->Register.Index;
2550
2551 for (c = 0; c < 4; c++)
2552 if (src_mask & (1 << c))
2553 src[i][c] = tgsi_src(pc, c, fs, mod_supp);
2554 }
2555
2556 brdc = temp = pc->r_brdc;
2557 if (brdc && brdc->type != P_TEMP) {
2558 temp = temp_temp(pc, NULL);
2559 if (sat)
2560 brdc = temp;
2561 } else
2562 if (sat) {
2563 for (c = 0; c < 4; c++) {
2564 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
2565 continue;
2566 /* rdst[c] = dst[c]; */ /* done above */
2567 dst[c] = temp_temp(pc, NULL);
2568 }
2569 }
2570
2571 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
2572
2573 switch (inst->Instruction.Opcode) {
2574 case TGSI_OPCODE_ABS:
2575 for (c = 0; c < 4; c++) {
2576 if (!(mask & (1 << c)))
2577 continue;
2578 emit_cvt(pc, dst[c], src[0][c], -1,
2579 CVT_ABS | CVT_F32_F32);
2580 }
2581 break;
2582 case TGSI_OPCODE_ADD:
2583 for (c = 0; c < 4; c++) {
2584 if (!(mask & (1 << c)))
2585 continue;
2586 emit_add(pc, dst[c], src[0][c], src[1][c]);
2587 }
2588 break;
2589 case TGSI_OPCODE_AND:
2590 case TGSI_OPCODE_XOR:
2591 case TGSI_OPCODE_OR:
2592 for (c = 0; c < 4; c++) {
2593 if (!(mask & (1 << c)))
2594 continue;
2595 emit_bitop2(pc, dst[c], src[0][c], src[1][c],
2596 inst->Instruction.Opcode);
2597 }
2598 break;
2599 case TGSI_OPCODE_ARL:
2600 temp = temp_temp(pc, NULL);
2601 for (c = 0; c < 4; c++) {
2602 if (!(mask & (1 << c)))
2603 continue;
2604 emit_cvt(pc, temp, src[0][c], -1,
2605 CVT_FLOOR | CVT_S32_F32);
2606 emit_arl(pc, dst[c], temp, 4);
2607 }
2608 break;
2609 case TGSI_OPCODE_BGNLOOP:
2610 pc->loop_brka[pc->loop_lvl] = emit_breakaddr(pc);
2611 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
2612 terminate_mbb(pc);
2613 break;
2614 case TGSI_OPCODE_BGNSUB:
2615 assert(!pc->in_subroutine);
2616 pc->in_subroutine = TRUE;
2617 /* probably not necessary, but align to 8 byte boundary */
2618 if (!is_long(pc->p->exec_tail))
2619 convert_to_long(pc, pc->p->exec_tail);
2620 break;
2621 case TGSI_OPCODE_BRK:
2622 assert(pc->loop_lvl > 0);
2623 emit_break(pc, -1, 0);
2624 break;
2625 case TGSI_OPCODE_CAL:
2626 assert(inst->Label.Label < pc->insn_nr);
2627 emit_call(pc, -1, 0)->param.index = inst->Label.Label;
2628 /* replaced by actual offset in nv50_program_fixup_insns */
2629 break;
2630 case TGSI_OPCODE_CEIL:
2631 for (c = 0; c < 4; c++) {
2632 if (!(mask & (1 << c)))
2633 continue;
2634 emit_cvt(pc, dst[c], src[0][c], -1,
2635 CVT_CEIL | CVT_F32_F32 | CVT_RI);
2636 }
2637 break;
2638 case TGSI_OPCODE_CMP:
2639 pc->allow32 = FALSE;
2640 for (c = 0; c < 4; c++) {
2641 if (!(mask & (1 << c)))
2642 continue;
2643 emit_cvt(pc, NULL, src[0][c], 1, CVT_F32_F32);
2644 emit_mov(pc, dst[c], src[1][c]);
2645 set_pred(pc, 0x1, 1, pc->p->exec_tail); /* @SF */
2646 emit_mov(pc, dst[c], src[2][c]);
2647 set_pred(pc, 0x6, 1, pc->p->exec_tail); /* @NSF */
2648 }
2649 break;
2650 case TGSI_OPCODE_CONT:
2651 assert(pc->loop_lvl > 0);
2652 emit_branch(pc, -1, 0)->param.index =
2653 pc->loop_pos[pc->loop_lvl - 1];
2654 break;
2655 case TGSI_OPCODE_COS:
2656 if (mask & 8) {
2657 emit_precossin(pc, temp, src[0][3]);
2658 emit_flop(pc, NV50_FLOP_COS, dst[3], temp);
2659 if (!(mask &= 7))
2660 break;
2661 if (temp == dst[3])
2662 temp = brdc = temp_temp(pc, NULL);
2663 }
2664 emit_precossin(pc, temp, src[0][0]);
2665 emit_flop(pc, NV50_FLOP_COS, brdc, temp);
2666 break;
2667 case TGSI_OPCODE_DDX:
2668 for (c = 0; c < 4; c++) {
2669 if (!(mask & (1 << c)))
2670 continue;
2671 emit_ddx(pc, dst[c], src[0][c]);
2672 }
2673 break;
2674 case TGSI_OPCODE_DDY:
2675 for (c = 0; c < 4; c++) {
2676 if (!(mask & (1 << c)))
2677 continue;
2678 emit_ddy(pc, dst[c], src[0][c]);
2679 }
2680 break;
2681 case TGSI_OPCODE_DP3:
2682 emit_mul(pc, temp, src[0][0], src[1][0]);
2683 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2684 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
2685 break;
2686 case TGSI_OPCODE_DP4:
2687 emit_mul(pc, temp, src[0][0], src[1][0]);
2688 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2689 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2690 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
2691 break;
2692 case TGSI_OPCODE_DPH:
2693 emit_mul(pc, temp, src[0][0], src[1][0]);
2694 emit_mad(pc, temp, src[0][1], src[1][1], temp);
2695 emit_mad(pc, temp, src[0][2], src[1][2], temp);
2696 emit_add(pc, brdc, src[1][3], temp);
2697 break;
2698 case TGSI_OPCODE_DST:
2699 if (mask & (1 << 1))
2700 emit_mul(pc, dst[1], src[0][1], src[1][1]);
2701 if (mask & (1 << 2))
2702 emit_mov(pc, dst[2], src[0][2]);
2703 if (mask & (1 << 3))
2704 emit_mov(pc, dst[3], src[1][3]);
2705 if (mask & (1 << 0))
2706 emit_mov_immdval(pc, dst[0], 1.0f);
2707 break;
2708 case TGSI_OPCODE_ELSE:
2709 emit_branch(pc, -1, 0);
2710 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2711 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
2712 terminate_mbb(pc);
2713 break;
2714 case TGSI_OPCODE_ENDIF:
2715 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
2716
2717 /* try to replace branch over 1 insn with a predicated insn */
2718 if (nv50_kill_branch(pc) == TRUE)
2719 break;
2720
2721 if (pc->if_join[pc->if_lvl]) {
2722 pc->if_join[pc->if_lvl]->param.index = pc->p->exec_size;
2723 pc->if_join[pc->if_lvl] = NULL;
2724 }
2725 terminate_mbb(pc);
2726 /* emit a NOP as join point, we could set it on the next
2727 * one, but would have to make sure it is long and !immd
2728 */
2729 JOIN_ON(emit_nop(pc));
2730 break;
2731 case TGSI_OPCODE_ENDLOOP:
2732 emit_branch(pc, -1, 0)->param.index =
2733 pc->loop_pos[--pc->loop_lvl];
2734 pc->loop_brka[pc->loop_lvl]->param.index = pc->p->exec_size;
2735 terminate_mbb(pc);
2736 break;
2737 case TGSI_OPCODE_ENDSUB:
2738 assert(pc->in_subroutine);
2739 terminate_mbb(pc);
2740 pc->in_subroutine = FALSE;
2741 break;
2742 case TGSI_OPCODE_EX2:
2743 emit_preex2(pc, temp, src[0][0]);
2744 emit_flop(pc, NV50_FLOP_EX2, brdc, temp);
2745 break;
2746 case TGSI_OPCODE_EXP:
2747 {
2748 struct nv50_reg *t[2];
2749
2750 assert(!temp);
2751 t[0] = temp_temp(pc, NULL);
2752 t[1] = temp_temp(pc, NULL);
2753
2754 if (mask & 0x6)
2755 emit_mov(pc, t[0], src[0][0]);
2756 if (mask & 0x3)
2757 emit_flr(pc, t[1], src[0][0]);
2758
2759 if (mask & (1 << 1))
2760 emit_sub(pc, dst[1], t[0], t[1]);
2761 if (mask & (1 << 0)) {
2762 emit_preex2(pc, t[1], t[1]);
2763 emit_flop(pc, NV50_FLOP_EX2, dst[0], t[1]);
2764 }
2765 if (mask & (1 << 2)) {
2766 emit_preex2(pc, t[0], t[0]);
2767 emit_flop(pc, NV50_FLOP_EX2, dst[2], t[0]);
2768 }
2769 if (mask & (1 << 3))
2770 emit_mov_immdval(pc, dst[3], 1.0f);
2771 }
2772 break;
2773 case TGSI_OPCODE_F2I:
2774 for (c = 0; c < 4; c++) {
2775 if (!(mask & (1 << c)))
2776 continue;
2777 emit_cvt(pc, dst[c], src[0][c], -1,
2778 CVT_TRUNC | CVT_S32_F32);
2779 }
2780 break;
2781 case TGSI_OPCODE_F2U:
2782 for (c = 0; c < 4; c++) {
2783 if (!(mask & (1 << c)))
2784 continue;
2785 emit_cvt(pc, dst[c], src[0][c], -1,
2786 CVT_TRUNC | CVT_U32_F32);
2787 }
2788 break;
2789 case TGSI_OPCODE_FLR:
2790 for (c = 0; c < 4; c++) {
2791 if (!(mask & (1 << c)))
2792 continue;
2793 emit_flr(pc, dst[c], src[0][c]);
2794 }
2795 break;
2796 case TGSI_OPCODE_FRC:
2797 temp = temp_temp(pc, NULL);
2798 for (c = 0; c < 4; c++) {
2799 if (!(mask & (1 << c)))
2800 continue;
2801 emit_flr(pc, temp, src[0][c]);
2802 emit_sub(pc, dst[c], src[0][c], temp);
2803 }
2804 break;
2805 case TGSI_OPCODE_I2F:
2806 for (c = 0; c < 4; c++) {
2807 if (!(mask & (1 << c)))
2808 continue;
2809 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_S32);
2810 }
2811 break;
2812 case TGSI_OPCODE_IF:
2813 assert(pc->if_lvl < NV50_MAX_COND_NESTING);
2814 emit_cvt(pc, NULL, src[0][0], 0, CVT_ABS | CVT_F32_F32);
2815 pc->if_join[pc->if_lvl] = emit_joinat(pc);
2816 pc->if_insn[pc->if_lvl++] = emit_branch(pc, 0, 2);;
2817 terminate_mbb(pc);
2818 break;
2819 case TGSI_OPCODE_IMAX:
2820 for (c = 0; c < 4; c++) {
2821 if (!(mask & (1 << c)))
2822 continue;
2823 emit_minmax(pc, 0x08c, dst[c], src[0][c], src[1][c]);
2824 }
2825 break;
2826 case TGSI_OPCODE_IMIN:
2827 for (c = 0; c < 4; c++) {
2828 if (!(mask & (1 << c)))
2829 continue;
2830 emit_minmax(pc, 0x0ac, dst[c], src[0][c], src[1][c]);
2831 }
2832 break;
2833 case TGSI_OPCODE_INEG:
2834 for (c = 0; c < 4; c++) {
2835 if (!(mask & (1 << c)))
2836 continue;
2837 emit_cvt(pc, dst[c], src[0][c], -1,
2838 CVT_S32_S32 | CVT_NEG);
2839 }
2840 break;
2841 case TGSI_OPCODE_KIL:
2842 assert(src[0][0] && src[0][1] && src[0][2] && src[0][3]);
2843 emit_kil(pc, src[0][0]);
2844 emit_kil(pc, src[0][1]);
2845 emit_kil(pc, src[0][2]);
2846 emit_kil(pc, src[0][3]);
2847 break;
2848 case TGSI_OPCODE_KILP:
2849 emit_kil(pc, NULL);
2850 break;
2851 case TGSI_OPCODE_LIT:
2852 emit_lit(pc, &dst[0], mask, &src[0][0]);
2853 break;
2854 case TGSI_OPCODE_LG2:
2855 emit_flop(pc, NV50_FLOP_LG2, brdc, src[0][0]);
2856 break;
2857 case TGSI_OPCODE_LOG:
2858 {
2859 struct nv50_reg *t[2];
2860
2861 t[0] = temp_temp(pc, NULL);
2862 if (mask & (1 << 1))
2863 t[1] = temp_temp(pc, NULL);
2864 else
2865 t[1] = t[0];
2866
2867 emit_cvt(pc, t[0], src[0][0], -1, CVT_ABS | CVT_F32_F32);
2868 emit_flop(pc, NV50_FLOP_LG2, t[1], t[0]);
2869 if (mask & (1 << 2))
2870 emit_mov(pc, dst[2], t[1]);
2871 emit_flr(pc, t[1], t[1]);
2872 if (mask & (1 << 0))
2873 emit_mov(pc, dst[0], t[1]);
2874 if (mask & (1 << 1)) {
2875 t[1]->mod = NV50_MOD_NEG;
2876 emit_preex2(pc, t[1], t[1]);
2877 t[1]->mod = 0;
2878 emit_flop(pc, NV50_FLOP_EX2, t[1], t[1]);
2879 emit_mul(pc, dst[1], t[0], t[1]);
2880 }
2881 if (mask & (1 << 3))
2882 emit_mov_immdval(pc, dst[3], 1.0f);
2883 }
2884 break;
2885 case TGSI_OPCODE_LRP:
2886 temp = temp_temp(pc, NULL);
2887 for (c = 0; c < 4; c++) {
2888 if (!(mask & (1 << c)))
2889 continue;
2890 emit_sub(pc, temp, src[1][c], src[2][c]);
2891 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
2892 }
2893 break;
2894 case TGSI_OPCODE_MAD:
2895 for (c = 0; c < 4; c++) {
2896 if (!(mask & (1 << c)))
2897 continue;
2898 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2899 }
2900 break;
2901 case TGSI_OPCODE_MAX:
2902 for (c = 0; c < 4; c++) {
2903 if (!(mask & (1 << c)))
2904 continue;
2905 emit_minmax(pc, 0x880, dst[c], src[0][c], src[1][c]);
2906 }
2907 break;
2908 case TGSI_OPCODE_MIN:
2909 for (c = 0; c < 4; c++) {
2910 if (!(mask & (1 << c)))
2911 continue;
2912 emit_minmax(pc, 0x8a0, dst[c], src[0][c], src[1][c]);
2913 }
2914 break;
2915 case TGSI_OPCODE_MOV:
2916 for (c = 0; c < 4; c++) {
2917 if (!(mask & (1 << c)))
2918 continue;
2919 emit_mov(pc, dst[c], src[0][c]);
2920 }
2921 break;
2922 case TGSI_OPCODE_MUL:
2923 for (c = 0; c < 4; c++) {
2924 if (!(mask & (1 << c)))
2925 continue;
2926 emit_mul(pc, dst[c], src[0][c], src[1][c]);
2927 }
2928 break;
2929 case TGSI_OPCODE_NOT:
2930 for (c = 0; c < 4; c++) {
2931 if (!(mask & (1 << c)))
2932 continue;
2933 emit_not(pc, dst[c], src[0][c]);
2934 }
2935 break;
2936 case TGSI_OPCODE_POW:
2937 emit_pow(pc, brdc, src[0][0], src[1][0]);
2938 break;
2939 case TGSI_OPCODE_RCP:
2940 if (!sat && popcnt4(mask) == 1)
2941 brdc = dst[ffs(mask) - 1];
2942 emit_flop(pc, NV50_FLOP_RCP, brdc, src[0][0]);
2943 break;
2944 case TGSI_OPCODE_RET:
2945 if (pc->p->type == PIPE_SHADER_FRAGMENT && !pc->in_subroutine)
2946 nv50_fp_move_results(pc);
2947 emit_ret(pc, -1, 0);
2948 break;
2949 case TGSI_OPCODE_RSQ:
2950 if (!sat && popcnt4(mask) == 1)
2951 brdc = dst[ffs(mask) - 1];
2952 src[0][0]->mod |= NV50_MOD_ABS;
2953 emit_flop(pc, NV50_FLOP_RSQ, brdc, src[0][0]);
2954 break;
2955 case TGSI_OPCODE_SAD:
2956 for (c = 0; c < 4; c++) {
2957 if (!(mask & (1 << c)))
2958 continue;
2959 emit_sad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
2960 }
2961 break;
2962 case TGSI_OPCODE_SCS:
2963 temp = temp_temp(pc, NULL);
2964 if (mask & 3)
2965 emit_precossin(pc, temp, src[0][0]);
2966 if (mask & (1 << 0))
2967 emit_flop(pc, NV50_FLOP_COS, dst[0], temp);
2968 if (mask & (1 << 1))
2969 emit_flop(pc, NV50_FLOP_SIN, dst[1], temp);
2970 if (mask & (1 << 2))
2971 emit_mov_immdval(pc, dst[2], 0.0);
2972 if (mask & (1 << 3))
2973 emit_mov_immdval(pc, dst[3], 1.0);
2974 break;
2975 case TGSI_OPCODE_SHL:
2976 case TGSI_OPCODE_ISHR:
2977 case TGSI_OPCODE_USHR:
2978 for (c = 0; c < 4; c++) {
2979 if (!(mask & (1 << c)))
2980 continue;
2981 emit_shift(pc, dst[c], src[0][c], src[1][c],
2982 inst->Instruction.Opcode);
2983 }
2984 break;
2985 case TGSI_OPCODE_SIN:
2986 if (mask & 8) {
2987 emit_precossin(pc, temp, src[0][3]);
2988 emit_flop(pc, NV50_FLOP_SIN, dst[3], temp);
2989 if (!(mask &= 7))
2990 break;
2991 if (temp == dst[3])
2992 temp = brdc = temp_temp(pc, NULL);
2993 }
2994 emit_precossin(pc, temp, src[0][0]);
2995 emit_flop(pc, NV50_FLOP_SIN, brdc, temp);
2996 break;
2997 case TGSI_OPCODE_SLT:
2998 case TGSI_OPCODE_SGE:
2999 case TGSI_OPCODE_SEQ:
3000 case TGSI_OPCODE_SGT:
3001 case TGSI_OPCODE_SLE:
3002 case TGSI_OPCODE_SNE:
3003 case TGSI_OPCODE_ISLT:
3004 case TGSI_OPCODE_ISGE:
3005 case TGSI_OPCODE_USEQ:
3006 case TGSI_OPCODE_USGE:
3007 case TGSI_OPCODE_USLT:
3008 case TGSI_OPCODE_USNE:
3009 {
3010 uint8_t cc, ty;
3011
3012 map_tgsi_setop_hw(inst->Instruction.Opcode, &cc, &ty);
3013
3014 for (c = 0; c < 4; c++) {
3015 if (!(mask & (1 << c)))
3016 continue;
3017 emit_set(pc, cc, dst[c], -1, src[0][c], src[1][c], ty);
3018 }
3019 }
3020 break;
3021 case TGSI_OPCODE_SUB:
3022 for (c = 0; c < 4; c++) {
3023 if (!(mask & (1 << c)))
3024 continue;
3025 emit_sub(pc, dst[c], src[0][c], src[1][c]);
3026 }
3027 break;
3028 case TGSI_OPCODE_TEX:
3029 emit_tex(pc, dst, mask, src[0], unit,
3030 inst->Texture.Texture, FALSE, 0);
3031 break;
3032 case TGSI_OPCODE_TXB:
3033 emit_tex(pc, dst, mask, src[0], unit,
3034 inst->Texture.Texture, FALSE, -1);
3035 break;
3036 case TGSI_OPCODE_TXL:
3037 emit_tex(pc, dst, mask, src[0], unit,
3038 inst->Texture.Texture, FALSE, 1);
3039 break;
3040 case TGSI_OPCODE_TXP:
3041 emit_tex(pc, dst, mask, src[0], unit,
3042 inst->Texture.Texture, TRUE, 0);
3043 break;
3044 case TGSI_OPCODE_TRUNC:
3045 for (c = 0; c < 4; c++) {
3046 if (!(mask & (1 << c)))
3047 continue;
3048 emit_cvt(pc, dst[c], src[0][c], -1,
3049 CVT_TRUNC | CVT_F32_F32 | CVT_RI);
3050 }
3051 break;
3052 case TGSI_OPCODE_U2F:
3053 for (c = 0; c < 4; c++) {
3054 if (!(mask & (1 << c)))
3055 continue;
3056 emit_cvt(pc, dst[c], src[0][c], -1, CVT_F32_U32);
3057 }
3058 break;
3059 case TGSI_OPCODE_UADD:
3060 for (c = 0; c < 4; c++) {
3061 if (!(mask & (1 << c)))
3062 continue;
3063 emit_add_b32(pc, dst[c], src[0][c], src[1][c]);
3064 }
3065 break;
3066 case TGSI_OPCODE_UMAX:
3067 for (c = 0; c < 4; c++) {
3068 if (!(mask & (1 << c)))
3069 continue;
3070 emit_minmax(pc, 0x084, dst[c], src[0][c], src[1][c]);
3071 }
3072 break;
3073 case TGSI_OPCODE_UMIN:
3074 for (c = 0; c < 4; c++) {
3075 if (!(mask & (1 << c)))
3076 continue;
3077 emit_minmax(pc, 0x0a4, dst[c], src[0][c], src[1][c]);
3078 }
3079 break;
3080 case TGSI_OPCODE_UMAD:
3081 {
3082 assert(!temp);
3083 temp = temp_temp(pc, NULL);
3084 for (c = 0; c < 4; c++) {
3085 if (!(mask & (1 << c)))
3086 continue;
3087 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3088 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3089 temp);
3090 emit_shl_imm(pc, temp, temp, 16);
3091 emit_mad_u16(pc, temp, src[0][c], 0, src[1][c], 0,
3092 temp);
3093 emit_add_b32(pc, dst[c], temp, src[2][c]);
3094 }
3095 }
3096 break;
3097 case TGSI_OPCODE_UMUL:
3098 {
3099 assert(!temp);
3100 temp = temp_temp(pc, NULL);
3101 for (c = 0; c < 4; c++) {
3102 if (!(mask & (1 << c)))
3103 continue;
3104 emit_mul_u16(pc, temp, src[0][c], 0, src[1][c], 1);
3105 emit_mad_u16(pc, temp, src[0][c], 1, src[1][c], 0,
3106 temp);
3107 emit_shl_imm(pc, temp, temp, 16);
3108 emit_mad_u16(pc, dst[c], src[0][c], 0, src[1][c], 0,
3109 temp);
3110 }
3111 }
3112 break;
3113 case TGSI_OPCODE_XPD:
3114 temp = temp_temp(pc, NULL);
3115 if (mask & (1 << 0)) {
3116 emit_mul(pc, temp, src[0][2], src[1][1]);
3117 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
3118 }
3119 if (mask & (1 << 1)) {
3120 emit_mul(pc, temp, src[0][0], src[1][2]);
3121 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
3122 }
3123 if (mask & (1 << 2)) {
3124 emit_mul(pc, temp, src[0][1], src[1][0]);
3125 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
3126 }
3127 if (mask & (1 << 3))
3128 emit_mov_immdval(pc, dst[3], 1.0);
3129 break;
3130 case TGSI_OPCODE_END:
3131 if (pc->p->type == PIPE_SHADER_FRAGMENT)
3132 nv50_fp_move_results(pc);
3133
3134 /* last insn must be long so it can have the exit bit set */
3135 if (!is_long(pc->p->exec_tail))
3136 convert_to_long(pc, pc->p->exec_tail);
3137 else
3138 if (is_immd(pc->p->exec_tail) || is_join(pc->p->exec_tail))
3139 emit_nop(pc);
3140
3141 pc->p->exec_tail->inst[1] |= 1; /* set exit bit */
3142
3143 terminate_mbb(pc);
3144 break;
3145 default:
3146 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
3147 return FALSE;
3148 }
3149
3150 if (brdc) {
3151 if (sat)
3152 emit_sat(pc, brdc, brdc);
3153 for (c = 0; c < 4; c++)
3154 if ((mask & (1 << c)) && dst[c] != brdc)
3155 emit_mov(pc, dst[c], brdc);
3156 } else
3157 if (sat) {
3158 for (c = 0; c < 4; c++) {
3159 if (!(mask & (1 << c)))
3160 continue;
3161 /* In this case we saturate later, and dst[c] won't
3162 * be another temp_temp (and thus lost), since rdst
3163 * already is TEMP (see above). */
3164 if (rdst[c]->type == P_TEMP && rdst[c]->index < 0)
3165 continue;
3166 emit_sat(pc, rdst[c], dst[c]);
3167 }
3168 }
3169
3170 kill_temp_temp(pc, NULL);
3171 pc->reg_instance_nr = 0;
3172
3173 return TRUE;
3174 }
3175
3176 static void
3177 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
3178 {
3179 struct nv50_reg *r, *reg = NULL;
3180 const struct tgsi_full_src_register *src;
3181 const struct tgsi_dst_register *dst;
3182 unsigned i, c, k, mask;
3183
3184 dst = &insn->Dst[0].Register;
3185 mask = dst->WriteMask;
3186
3187 if (dst->File == TGSI_FILE_TEMPORARY)
3188 reg = pc->temp;
3189 else
3190 if (dst->File == TGSI_FILE_OUTPUT) {
3191 reg = pc->result;
3192
3193 if (insn->Instruction.Opcode == TGSI_OPCODE_MOV &&
3194 dst->Index == pc->edgeflag_out &&
3195 insn->Src[0].Register.File == TGSI_FILE_INPUT)
3196 pc->p->cfg.edgeflag_in = insn->Src[0].Register.Index;
3197 }
3198
3199 if (reg) {
3200 for (c = 0; c < 4; c++) {
3201 if (!(mask & (1 << c)))
3202 continue;
3203 reg[dst->Index * 4 + c].acc = pc->insn_nr;
3204 }
3205 }
3206
3207 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3208 src = &insn->Src[i];
3209
3210 if (src->Register.File == TGSI_FILE_TEMPORARY)
3211 reg = pc->temp;
3212 else
3213 if (src->Register.File == TGSI_FILE_INPUT)
3214 reg = pc->attr;
3215 else
3216 continue;
3217
3218 mask = nv50_tgsi_src_mask(insn, i);
3219
3220 for (c = 0; c < 4; c++) {
3221 if (!(mask & (1 << c)))
3222 continue;
3223 k = tgsi_util_get_full_src_register_swizzle(src, c);
3224
3225 r = &reg[src->Register.Index * 4 + k];
3226
3227 /* If used before written, pre-allocate the reg,
3228 * lest we overwrite results from a subroutine.
3229 */
3230 if (!r->acc && r->type == P_TEMP)
3231 alloc_reg(pc, r);
3232
3233 r->acc = pc->insn_nr;
3234 }
3235 }
3236 }
3237
3238 /* Returns a bitmask indicating which dst components need to be
3239 * written to temporaries first to avoid 'corrupting' sources.
3240 *
3241 * m[i] (out) indicate component to write in the i-th position
3242 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
3243 */
3244 static unsigned
3245 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
3246 {
3247 unsigned i, c, x, unsafe;
3248
3249 for (c = 0; c < 4; c++)
3250 m[c] = c;
3251
3252 /* Swap as long as a dst component written earlier is depended on
3253 * by one written later, but the next one isn't depended on by it.
3254 */
3255 for (c = 0; c < 3; c++) {
3256 if (rdep[m[c + 1]] & (1 << m[c]))
3257 continue; /* if next one is depended on by us */
3258 for (i = c + 1; i < 4; i++)
3259 /* if we are depended on by a later one */
3260 if (rdep[m[c]] & (1 << m[i]))
3261 break;
3262 if (i == 4)
3263 continue;
3264 /* now, swap */
3265 x = m[c];
3266 m[c] = m[c + 1];
3267 m[c + 1] = x;
3268
3269 /* restart */
3270 c = 0;
3271 }
3272
3273 /* mark dependencies that could not be resolved by reordering */
3274 for (i = 0; i < 3; ++i)
3275 for (c = i + 1; c < 4; ++c)
3276 if (rdep[m[i]] & (1 << m[c]))
3277 unsafe |= (1 << i);
3278
3279 /* NOTE: $unsafe is with respect to order, not component */
3280 return unsafe;
3281 }
3282
3283 /* Select a suitable dst register for broadcasting scalar results,
3284 * or return NULL if we have to allocate an extra TEMP.
3285 *
3286 * If e.g. only 1 component is written, we may also emit the final
3287 * result to a write-only register.
3288 */
3289 static struct nv50_reg *
3290 tgsi_broadcast_dst(struct nv50_pc *pc,
3291 const struct tgsi_full_dst_register *fd, unsigned mask)
3292 {
3293 if (fd->Register.File == TGSI_FILE_TEMPORARY) {
3294 int c = ffs(~mask & fd->Register.WriteMask);
3295 if (c)
3296 return tgsi_dst(pc, c - 1, fd);
3297 } else {
3298 int c = ffs(fd->Register.WriteMask) - 1;
3299 if ((1 << c) == fd->Register.WriteMask)
3300 return tgsi_dst(pc, c, fd);
3301 }
3302
3303 return NULL;
3304 }
3305
3306 /* Scan source swizzles and return a bitmask indicating dst regs that
3307 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
3308 */
3309 static unsigned
3310 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
3311 unsigned rdep[4])
3312 {
3313 const struct tgsi_full_dst_register *fd = &insn->Dst[0];
3314 const struct tgsi_full_src_register *fs;
3315 unsigned i, deqs = 0;
3316
3317 for (i = 0; i < 4; ++i)
3318 rdep[i] = 0;
3319
3320 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
3321 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
3322 int ms = get_supported_mods(insn, i);
3323
3324 fs = &insn->Src[i];
3325 if (fs->Register.File != fd->Register.File ||
3326 fs->Register.Index != fd->Register.Index)
3327 continue;
3328
3329 for (chn = 0; chn < 4; ++chn) {
3330 unsigned s, c;
3331
3332 if (!(mask & (1 << chn))) /* src is not read */
3333 continue;
3334 c = tgsi_util_get_full_src_register_swizzle(fs, chn);
3335 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
3336
3337 if (!(fd->Register.WriteMask & (1 << c)))
3338 continue;
3339
3340 if (s == TGSI_UTIL_SIGN_TOGGLE && !(ms & NV50_MOD_NEG))
3341 continue;
3342 if (s == TGSI_UTIL_SIGN_CLEAR && !(ms & NV50_MOD_ABS))
3343 continue;
3344 if ((s == TGSI_UTIL_SIGN_SET) && ((ms & 3) != 3))
3345 continue;
3346
3347 rdep[c] |= nv50_tgsi_dst_revdep(
3348 insn->Instruction.Opcode, i, chn);
3349 deqs |= (1 << c);
3350 }
3351 }
3352
3353 return deqs;
3354 }
3355
3356 static boolean
3357 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
3358 {
3359 struct tgsi_full_instruction insn = tok->FullInstruction;
3360 const struct tgsi_full_dst_register *fd;
3361 unsigned i, deqs, rdep[4], m[4];
3362
3363 fd = &tok->FullInstruction.Dst[0];
3364 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
3365
3366 if (is_scalar_op(insn.Instruction.Opcode)) {
3367 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
3368 if (!pc->r_brdc)
3369 pc->r_brdc = temp_temp(pc, NULL);
3370 return nv50_program_tx_insn(pc, &insn);
3371 }
3372 pc->r_brdc = NULL;
3373
3374 if (!deqs || (!rdep[0] && !rdep[1] && !rdep[2] && !rdep[3]))
3375 return nv50_program_tx_insn(pc, &insn);
3376
3377 deqs = nv50_revdep_reorder(m, rdep);
3378
3379 for (i = 0; i < 4; ++i) {
3380 assert(pc->r_dst[m[i]] == NULL);
3381
3382 insn.Dst[0].Register.WriteMask =
3383 fd->Register.WriteMask & (1 << m[i]);
3384
3385 if (!insn.Dst[0].Register.WriteMask)
3386 continue;
3387
3388 if (deqs & (1 << i))
3389 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
3390
3391 if (!nv50_program_tx_insn(pc, &insn))
3392 return FALSE;
3393 }
3394
3395 for (i = 0; i < 4; i++) {
3396 struct nv50_reg *reg = pc->r_dst[i];
3397 if (!reg)
3398 continue;
3399 pc->r_dst[i] = NULL;
3400
3401 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
3402 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
3403 else
3404 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
3405 free_temp(pc, reg);
3406 }
3407
3408 return TRUE;
3409 }
3410
3411 static void
3412 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
3413 {
3414 struct nv50_reg *iv, **ppiv;
3415 unsigned mode = pc->interp_mode[reg->index];
3416
3417 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
3418 iv = *ppiv;
3419
3420 if ((mode & INTERP_PERSPECTIVE) && !iv) {
3421 iv = *ppiv = alloc_temp(pc, NULL);
3422 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
3423
3424 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
3425 emit_flop(pc, NV50_FLOP_RCP, iv, iv);
3426
3427 /* XXX: when loading interpolants dynamically, move these
3428 * to the program head, or make sure it can't be skipped.
3429 */
3430 }
3431
3432 emit_interp(pc, reg, iv, mode);
3433 }
3434
3435 /* The face input is always at v[255] (varying space), with a
3436 * value of 0 for back-facing, and 0xffffffff for front-facing.
3437 */
3438 static void
3439 load_frontfacing(struct nv50_pc *pc, struct nv50_reg *a)
3440 {
3441 struct nv50_reg *one = alloc_immd(pc, 1.0f);
3442
3443 assert(a->rhw == -1);
3444 alloc_reg(pc, a); /* do this before rhw is set */
3445 a->rhw = 255;
3446 load_interpolant(pc, a);
3447 emit_bitop2(pc, a, a, one, TGSI_OPCODE_AND);
3448
3449 FREE(one);
3450 }
3451
3452 static boolean
3453 nv50_program_tx_prep(struct nv50_pc *pc)
3454 {
3455 struct tgsi_parse_context tp;
3456 struct nv50_program *p = pc->p;
3457 boolean ret = FALSE;
3458 unsigned i, c, flat_nr = 0;
3459
3460 tgsi_parse_init(&tp, pc->p->pipe.tokens);
3461 while (!tgsi_parse_end_of_tokens(&tp)) {
3462 const union tgsi_full_token *tok = &tp.FullToken;
3463
3464 tgsi_parse_token(&tp);
3465 switch (tok->Token.Type) {
3466 case TGSI_TOKEN_TYPE_IMMEDIATE:
3467 {
3468 const struct tgsi_full_immediate *imm =
3469 &tp.FullToken.FullImmediate;
3470
3471 ctor_immd_4f32(pc, imm->u[0].Float,
3472 imm->u[1].Float,
3473 imm->u[2].Float,
3474 imm->u[3].Float);
3475 }
3476 break;
3477 case TGSI_TOKEN_TYPE_DECLARATION:
3478 {
3479 const struct tgsi_full_declaration *d;
3480 unsigned si, last, first, mode;
3481
3482 d = &tp.FullToken.FullDeclaration;
3483 first = d->Range.First;
3484 last = d->Range.Last;
3485
3486 switch (d->Declaration.File) {
3487 case TGSI_FILE_TEMPORARY:
3488 break;
3489 case TGSI_FILE_OUTPUT:
3490 if (!d->Declaration.Semantic ||
3491 p->type == PIPE_SHADER_FRAGMENT)
3492 break;
3493
3494 si = d->Semantic.Index;
3495 switch (d->Semantic.Name) {
3496 case TGSI_SEMANTIC_BCOLOR:
3497 p->cfg.two_side[si].hw = first;
3498 if (p->cfg.io_nr > first)
3499 p->cfg.io_nr = first;
3500 break;
3501 case TGSI_SEMANTIC_PSIZE:
3502 p->cfg.psiz = first;
3503 if (p->cfg.io_nr > first)
3504 p->cfg.io_nr = first;
3505 break;
3506 case TGSI_SEMANTIC_EDGEFLAG:
3507 pc->edgeflag_out = first;
3508 break;
3509 /*
3510 case TGSI_SEMANTIC_CLIP_DISTANCE:
3511 p->cfg.clpd = MIN2(p->cfg.clpd, first);
3512 break;
3513 */
3514 default:
3515 break;
3516 }
3517 break;
3518 case TGSI_FILE_INPUT:
3519 {
3520 if (p->type != PIPE_SHADER_FRAGMENT)
3521 break;
3522
3523 switch (d->Declaration.Interpolate) {
3524 case TGSI_INTERPOLATE_CONSTANT:
3525 mode = INTERP_FLAT;
3526 flat_nr++;
3527 break;
3528 case TGSI_INTERPOLATE_PERSPECTIVE:
3529 mode = INTERP_PERSPECTIVE;
3530 p->cfg.regs[1] |= 0x08 << 24;
3531 break;
3532 default:
3533 mode = INTERP_LINEAR;
3534 break;
3535 }
3536 if (d->Declaration.Centroid)
3537 mode |= INTERP_CENTROID;
3538
3539 assert(last < 32);
3540 for (i = first; i <= last; i++)
3541 pc->interp_mode[i] = mode;
3542 }
3543 break;
3544 case TGSI_FILE_ADDRESS:
3545 case TGSI_FILE_CONSTANT:
3546 case TGSI_FILE_SAMPLER:
3547 break;
3548 default:
3549 NOUVEAU_ERR("bad decl file %d\n",
3550 d->Declaration.File);
3551 goto out_err;
3552 }
3553 }
3554 break;
3555 case TGSI_TOKEN_TYPE_INSTRUCTION:
3556 pc->insn_nr++;
3557 prep_inspect_insn(pc, &tok->FullInstruction);
3558 break;
3559 default:
3560 break;
3561 }
3562 }
3563
3564 if (p->type == PIPE_SHADER_VERTEX) {
3565 int rid = 0;
3566
3567 for (i = 0; i < pc->attr_nr * 4; ++i) {
3568 if (pc->attr[i].acc) {
3569 pc->attr[i].hw = rid++;
3570 p->cfg.attr[i / 32] |= 1 << (i % 32);
3571 }
3572 }
3573
3574 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
3575 p->cfg.io[i].hw = rid;
3576 p->cfg.io[i].id = i;
3577
3578 for (c = 0; c < 4; ++c) {
3579 int n = i * 4 + c;
3580 if (!pc->result[n].acc)
3581 continue;
3582 pc->result[n].hw = rid++;
3583 p->cfg.io[i].mask |= 1 << c;
3584 }
3585 }
3586
3587 for (c = 0; c < 2; ++c)
3588 if (p->cfg.two_side[c].hw < 0x40)
3589 p->cfg.two_side[c] = p->cfg.io[
3590 p->cfg.two_side[c].hw];
3591
3592 if (p->cfg.psiz < 0x40)
3593 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
3594 } else
3595 if (p->type == PIPE_SHADER_FRAGMENT) {
3596 int rid, aid;
3597 unsigned n = 0, m = pc->attr_nr - flat_nr;
3598
3599 pc->allow32 = TRUE;
3600
3601 int base = (TGSI_SEMANTIC_POSITION ==
3602 p->info.input_semantic_name[0]) ? 0 : 1;
3603
3604 /* non-flat interpolants have to be mapped to
3605 * the lower hardware IDs, so sort them:
3606 */
3607 for (i = 0; i < pc->attr_nr; i++) {
3608 if (pc->interp_mode[i] == INTERP_FLAT)
3609 p->cfg.io[m++].id = i;
3610 else {
3611 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
3612 p->cfg.io[n].linear = TRUE;
3613 p->cfg.io[n++].id = i;
3614 }
3615 }
3616
3617 if (!base) /* set w-coordinate mask from perspective interp */
3618 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
3619
3620 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
3621 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
3622
3623 for (n = 0; n < pc->attr_nr; ++n) {
3624 p->cfg.io[n].hw = rid = aid;
3625 i = p->cfg.io[n].id;
3626
3627 if (p->info.input_semantic_name[n] ==
3628 TGSI_SEMANTIC_FACE) {
3629 load_frontfacing(pc, &pc->attr[i * 4]);
3630 continue;
3631 }
3632
3633 for (c = 0; c < 4; ++c) {
3634 if (!pc->attr[i * 4 + c].acc)
3635 continue;
3636 pc->attr[i * 4 + c].rhw = rid++;
3637 p->cfg.io[n].mask |= 1 << c;
3638
3639 load_interpolant(pc, &pc->attr[i * 4 + c]);
3640 }
3641 aid += popcnt4(p->cfg.io[n].mask);
3642 }
3643
3644 if (!base)
3645 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
3646
3647 m = popcnt4(p->cfg.regs[1] >> 24);
3648
3649 /* set count of non-position inputs and of non-flat
3650 * non-position inputs for FP_INTERPOLANT_CTRL
3651 */
3652 p->cfg.regs[1] |= aid - m;
3653
3654 if (flat_nr) {
3655 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
3656 p->cfg.regs[1] |= (i - m) << 16;
3657 } else
3658 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
3659
3660 /* mark color semantic for light-twoside */
3661 n = 0x40;
3662 for (i = 0; i < pc->attr_nr; i++) {
3663 ubyte si, sn;
3664
3665 sn = p->info.input_semantic_name[p->cfg.io[i].id];
3666 si = p->info.input_semantic_index[p->cfg.io[i].id];
3667
3668 if (sn == TGSI_SEMANTIC_COLOR) {
3669 p->cfg.two_side[si] = p->cfg.io[i];
3670
3671 /* increase colour count */
3672 p->cfg.regs[0] += popcnt4(
3673 p->cfg.two_side[si].mask) << 16;
3674
3675 n = MIN2(n, p->cfg.io[i].hw - m);
3676 }
3677 }
3678 if (n < 0x40)
3679 p->cfg.regs[0] += n;
3680
3681 /* Initialize FP results:
3682 * FragDepth is always first TGSI and last hw output
3683 */
3684 i = p->info.writes_z ? 4 : 0;
3685 for (rid = 0; i < pc->result_nr * 4; i++)
3686 pc->result[i].rhw = rid++;
3687 if (p->info.writes_z)
3688 pc->result[2].rhw = rid;
3689
3690 p->cfg.high_result = rid;
3691
3692 /* separate/different colour results for MRTs ? */
3693 if (pc->result_nr - (p->info.writes_z ? 1 : 0) > 1)
3694 p->cfg.regs[2] |= 1;
3695 }
3696
3697 if (pc->immd_nr) {
3698 int rid = 0;
3699
3700 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
3701 if (!pc->immd)
3702 goto out_err;
3703
3704 for (i = 0; i < pc->immd_nr; i++) {
3705 for (c = 0; c < 4; c++, rid++)
3706 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
3707 }
3708 }
3709
3710 ret = TRUE;
3711 out_err:
3712 if (pc->iv_p)
3713 free_temp(pc, pc->iv_p);
3714 if (pc->iv_c)
3715 free_temp(pc, pc->iv_c);
3716
3717 tgsi_parse_free(&tp);
3718 return ret;
3719 }
3720
3721 static void
3722 free_nv50_pc(struct nv50_pc *pc)
3723 {
3724 if (pc->immd)
3725 FREE(pc->immd);
3726 if (pc->param)
3727 FREE(pc->param);
3728 if (pc->result)
3729 FREE(pc->result);
3730 if (pc->attr)
3731 FREE(pc->attr);
3732 if (pc->temp)
3733 FREE(pc->temp);
3734 if (pc->insn_pos)
3735 FREE(pc->insn_pos);
3736
3737 FREE(pc);
3738 }
3739
3740 static boolean
3741 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
3742 {
3743 int i, c;
3744 unsigned rtype[2] = { P_ATTR, P_RESULT };
3745
3746 pc->p = p;
3747 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
3748 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
3749 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
3750 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
3751 pc->addr_nr = p->info.file_max[TGSI_FILE_ADDRESS] + 1;
3752 assert(pc->addr_nr <= 2);
3753
3754 p->cfg.high_temp = 4;
3755
3756 p->cfg.two_side[0].hw = 0x40;
3757 p->cfg.two_side[1].hw = 0x40;
3758
3759 p->cfg.edgeflag_in = pc->edgeflag_out = 0xff;
3760
3761 switch (p->type) {
3762 case PIPE_SHADER_VERTEX:
3763 p->cfg.psiz = 0x40;
3764 p->cfg.clpd = 0x40;
3765 p->cfg.io_nr = pc->result_nr;
3766 break;
3767 case PIPE_SHADER_FRAGMENT:
3768 rtype[0] = rtype[1] = P_TEMP;
3769
3770 p->cfg.regs[0] = 0x01000004;
3771 p->cfg.io_nr = pc->attr_nr;
3772
3773 if (p->info.writes_z) {
3774 p->cfg.regs[2] |= 0x00000100;
3775 p->cfg.regs[3] |= 0x00000011;
3776 }
3777 if (p->info.uses_kill)
3778 p->cfg.regs[2] |= 0x00100000;
3779 break;
3780 }
3781
3782 if (pc->temp_nr) {
3783 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
3784 if (!pc->temp)
3785 return FALSE;
3786
3787 for (i = 0; i < pc->temp_nr * 4; ++i)
3788 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
3789 }
3790
3791 if (pc->attr_nr) {
3792 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
3793 if (!pc->attr)
3794 return FALSE;
3795
3796 for (i = 0; i < pc->attr_nr * 4; ++i)
3797 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
3798 }
3799
3800 if (pc->result_nr) {
3801 unsigned nr = pc->result_nr * 4;
3802
3803 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
3804 if (!pc->result)
3805 return FALSE;
3806
3807 for (i = 0; i < nr; ++i)
3808 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
3809 }
3810
3811 if (pc->param_nr) {
3812 int rid = 0;
3813
3814 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
3815 if (!pc->param)
3816 return FALSE;
3817
3818 for (i = 0; i < pc->param_nr; ++i)
3819 for (c = 0; c < 4; ++c, ++rid)
3820 ctor_reg(&pc->param[rid], P_CONST, i, rid);
3821 }
3822
3823 if (pc->addr_nr) {
3824 pc->addr = CALLOC(pc->addr_nr * 4, sizeof(struct nv50_reg *));
3825 if (!pc->addr)
3826 return FALSE;
3827 }
3828 for (i = 0; i < NV50_SU_MAX_ADDR; ++i)
3829 ctor_reg(&pc->r_addr[i], P_ADDR, -1, i + 1);
3830
3831 return TRUE;
3832 }
3833
3834 static void
3835 nv50_program_fixup_insns(struct nv50_pc *pc)
3836 {
3837 struct nv50_program_exec *e, **bra_list;
3838 unsigned i, n, pos;
3839
3840 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
3841
3842 /* Collect branch instructions, we need to adjust their offsets
3843 * when converting 32 bit instructions to 64 bit ones
3844 */
3845 for (n = 0, e = pc->p->exec_head; e; e = e->next)
3846 if (e->param.index >= 0 && !e->param.mask)
3847 bra_list[n++] = e;
3848
3849 /* Make sure we don't have any single 32 bit instructions. */
3850 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
3851 pos += is_long(e) ? 2 : 1;
3852
3853 if ((pos & 1) && (!e->next || is_long(e->next))) {
3854 for (i = 0; i < n; ++i)
3855 if (bra_list[i]->param.index >= pos)
3856 bra_list[i]->param.index += 1;
3857 for (i = 0; i < pc->insn_nr; ++i)
3858 if (pc->insn_pos[i] >= pos)
3859 pc->insn_pos[i] += 1;
3860 convert_to_long(pc, e);
3861 ++pos;
3862 }
3863 }
3864
3865 FREE(bra_list);
3866
3867 if (!pc->p->info.opcode_count[TGSI_OPCODE_CAL])
3868 return;
3869
3870 /* fill in CALL offsets */
3871 for (e = pc->p->exec_head; e; e = e->next) {
3872 if ((e->inst[0] & 2) && (e->inst[0] >> 28) == 0x2)
3873 e->param.index = pc->insn_pos[e->param.index];
3874 }
3875 }
3876
3877 static boolean
3878 nv50_program_tx(struct nv50_program *p)
3879 {
3880 struct tgsi_parse_context parse;
3881 struct nv50_pc *pc;
3882 boolean ret;
3883
3884 pc = CALLOC_STRUCT(nv50_pc);
3885 if (!pc)
3886 return FALSE;
3887
3888 ret = ctor_nv50_pc(pc, p);
3889 if (ret == FALSE)
3890 goto out_cleanup;
3891
3892 ret = nv50_program_tx_prep(pc);
3893 if (ret == FALSE)
3894 goto out_cleanup;
3895
3896 pc->insn_pos = MALLOC(pc->insn_nr * sizeof(unsigned));
3897
3898 tgsi_parse_init(&parse, pc->p->pipe.tokens);
3899 while (!tgsi_parse_end_of_tokens(&parse)) {
3900 const union tgsi_full_token *tok = &parse.FullToken;
3901
3902 /* previously allow32 was FALSE for first & last instruction */
3903 pc->allow32 = TRUE;
3904
3905 tgsi_parse_token(&parse);
3906
3907 switch (tok->Token.Type) {
3908 case TGSI_TOKEN_TYPE_INSTRUCTION:
3909 pc->insn_pos[pc->insn_cur] = pc->p->exec_size;
3910 ++pc->insn_cur;
3911 ret = nv50_tgsi_insn(pc, tok);
3912 if (ret == FALSE)
3913 goto out_err;
3914 break;
3915 default:
3916 break;
3917 }
3918 }
3919
3920 nv50_program_fixup_insns(pc);
3921
3922 p->param_nr = pc->param_nr * 4;
3923 p->immd_nr = pc->immd_nr * 4;
3924 p->immd = pc->immd_buf;
3925
3926 out_err:
3927 tgsi_parse_free(&parse);
3928
3929 out_cleanup:
3930 free_nv50_pc(pc);
3931 return ret;
3932 }
3933
3934 static void
3935 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
3936 {
3937 if (nv50_program_tx(p) == FALSE)
3938 assert(0);
3939 p->translated = TRUE;
3940 }
3941
3942 static void
3943 nv50_program_upload_data(struct nv50_context *nv50, uint32_t *map,
3944 unsigned start, unsigned count, unsigned cbuf)
3945 {
3946 struct nouveau_channel *chan = nv50->screen->base.channel;
3947 struct nouveau_grobj *tesla = nv50->screen->tesla;
3948
3949 while (count) {
3950 unsigned nr = count > 2047 ? 2047 : count;
3951
3952 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
3953 OUT_RING (chan, (cbuf << 0) | (start << 8));
3954 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
3955 OUT_RINGp (chan, map, nr);
3956
3957 map += nr;
3958 start += nr;
3959 count -= nr;
3960 }
3961 }
3962
3963 static void
3964 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
3965 {
3966 struct pipe_screen *pscreen = nv50->pipe.screen;
3967
3968 if (!p->data[0] && p->immd_nr) {
3969 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
3970
3971 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
3972 while (heap->next && heap->size < p->immd_nr) {
3973 struct nv50_program *evict = heap->next->priv;
3974 nouveau_resource_free(&evict->data[0]);
3975 }
3976
3977 if (nouveau_resource_alloc(heap, p->immd_nr, p,
3978 &p->data[0]))
3979 assert(0);
3980 }
3981
3982 /* immediates only need to be uploaded again when freed */
3983 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
3984 p->immd_nr, NV50_CB_PMISC);
3985 }
3986
3987 assert(p->param_nr <= 512);
3988
3989 if (p->param_nr) {
3990 unsigned cb;
3991 uint32_t *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
3992 PIPE_BUFFER_USAGE_CPU_READ);
3993
3994 if (p->type == PIPE_SHADER_VERTEX)
3995 cb = NV50_CB_PVP;
3996 else
3997 cb = NV50_CB_PFP;
3998
3999 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
4000 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
4001 }
4002 }
4003
4004 static void
4005 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
4006 {
4007 struct nouveau_channel *chan = nv50->screen->base.channel;
4008 struct nv50_program_exec *e;
4009 uint32_t *up, i;
4010 boolean upload = FALSE;
4011
4012 if (!p->bo) {
4013 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
4014 p->exec_size * 4, &p->bo);
4015 upload = TRUE;
4016 }
4017
4018 if (p->data[0] && p->data[0]->start != p->data_start[0])
4019 upload = TRUE;
4020
4021 if (!upload)
4022 return;
4023
4024 up = MALLOC(p->exec_size * 4);
4025
4026 for (i = 0, e = p->exec_head; e; e = e->next) {
4027 unsigned ei, ci, bs;
4028
4029 if (e->param.index >= 0 && e->param.mask) {
4030 bs = (e->inst[1] >> 22) & 0x07;
4031 assert(bs < 2);
4032 ei = e->param.shift >> 5;
4033 ci = e->param.index;
4034 if (bs == 0)
4035 ci += p->data[bs]->start;
4036
4037 e->inst[ei] &= ~e->param.mask;
4038 e->inst[ei] |= (ci << e->param.shift);
4039 } else
4040 if (e->param.index >= 0) {
4041 /* zero mask means param is a jump/branch offset */
4042 assert(!(e->param.index & 1));
4043 /* seem to be 8 byte steps */
4044 ei = (e->param.index >> 1) + 0 /* START_ID */;
4045
4046 e->inst[0] &= 0xf0000fff;
4047 e->inst[0] |= ei << 12;
4048 }
4049
4050 up[i++] = e->inst[0];
4051 if (is_long(e))
4052 up[i++] = e->inst[1];
4053 }
4054 assert(i == p->exec_size);
4055
4056 if (p->data[0])
4057 p->data_start[0] = p->data[0]->start;
4058
4059 #ifdef NV50_PROGRAM_DUMP
4060 NOUVEAU_ERR("-------\n");
4061 for (e = p->exec_head; e; e = e->next) {
4062 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
4063 if (is_long(e))
4064 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
4065 }
4066 #endif
4067 nv50_upload_sifc(nv50, p->bo, 0, NOUVEAU_BO_VRAM,
4068 NV50_2D_DST_FORMAT_R8_UNORM, 65536, 1, 262144,
4069 up, NV50_2D_SIFC_FORMAT_R8_UNORM, 0,
4070 0, 0, p->exec_size * 4, 1, 1);
4071
4072 FREE(up);
4073 }
4074
4075 void
4076 nv50_vertprog_validate(struct nv50_context *nv50)
4077 {
4078 struct nouveau_grobj *tesla = nv50->screen->tesla;
4079 struct nv50_program *p = nv50->vertprog;
4080 struct nouveau_stateobj *so;
4081
4082 if (!p->translated) {
4083 nv50_program_validate(nv50, p);
4084 if (!p->translated)
4085 assert(0);
4086 }
4087
4088 nv50_program_validate_data(nv50, p);
4089 nv50_program_validate_code(nv50, p);
4090
4091 so = so_new(5, 8, 2);
4092 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
4093 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4094 NOUVEAU_BO_HIGH, 0, 0);
4095 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4096 NOUVEAU_BO_LOW, 0, 0);
4097 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
4098 so_data (so, p->cfg.attr[0]);
4099 so_data (so, p->cfg.attr[1]);
4100 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
4101 so_data (so, p->cfg.high_result);
4102 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
4103 so_data (so, p->cfg.high_result); //8);
4104 so_data (so, p->cfg.high_temp);
4105 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
4106 so_data (so, 0); /* program start offset */
4107 so_ref(so, &nv50->state.vertprog);
4108 so_ref(NULL, &so);
4109 }
4110
4111 void
4112 nv50_fragprog_validate(struct nv50_context *nv50)
4113 {
4114 struct nouveau_grobj *tesla = nv50->screen->tesla;
4115 struct nv50_program *p = nv50->fragprog;
4116 struct nouveau_stateobj *so;
4117
4118 if (!p->translated) {
4119 nv50_program_validate(nv50, p);
4120 if (!p->translated)
4121 assert(0);
4122 }
4123
4124 nv50_program_validate_data(nv50, p);
4125 nv50_program_validate_code(nv50, p);
4126
4127 so = so_new(6, 7, 2);
4128 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
4129 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4130 NOUVEAU_BO_HIGH, 0, 0);
4131 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
4132 NOUVEAU_BO_LOW, 0, 0);
4133 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
4134 so_data (so, p->cfg.high_temp);
4135 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
4136 so_data (so, p->cfg.high_result);
4137 so_method(so, tesla, NV50TCL_FP_CONTROL, 1);
4138 so_data (so, p->cfg.regs[2]);
4139 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
4140 so_data (so, p->cfg.regs[3]);
4141 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
4142 so_data (so, 0); /* program start offset */
4143 so_ref(so, &nv50->state.fragprog);
4144 so_ref(NULL, &so);
4145 }
4146
4147 static uint32_t
4148 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
4149 {
4150 struct nv50_program *fp = nv50->fragprog;
4151 struct nv50_program *vp = nv50->vertprog;
4152 unsigned i, c, m = base;
4153 uint32_t origin = 0x00000010;
4154
4155 /* XXX: this might not work correctly in all cases yet - we'll
4156 * just assume that an FP generic input that is not written in
4157 * the VP is PointCoord.
4158 */
4159 memset(pntc, 0, 8 * sizeof(uint32_t));
4160
4161 for (i = 0; i < fp->cfg.io_nr; i++) {
4162 uint8_t sn, si;
4163 uint8_t j, k = fp->cfg.io[i].id;
4164 unsigned n = popcnt4(fp->cfg.io[i].mask);
4165
4166 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
4167 m += n;
4168 continue;
4169 }
4170
4171 for (j = 0; j < vp->info.num_outputs; ++j) {
4172 sn = vp->info.output_semantic_name[j];
4173 si = vp->info.output_semantic_index[j];
4174
4175 if (sn == fp->info.input_semantic_name[k] &&
4176 si == fp->info.input_semantic_index[k])
4177 break;
4178 }
4179
4180 if (j < vp->info.num_outputs) {
4181 ubyte mode =
4182 nv50->rasterizer->pipe.sprite_coord_mode[si];
4183
4184 if (mode == PIPE_SPRITE_COORD_NONE) {
4185 m += n;
4186 continue;
4187 } else
4188 if (mode == PIPE_SPRITE_COORD_LOWER_LEFT)
4189 origin = 0;
4190 }
4191
4192 /* this is either PointCoord or replaced by sprite coords */
4193 for (c = 0; c < 4; c++) {
4194 if (!(fp->cfg.io[i].mask & (1 << c)))
4195 continue;
4196 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
4197 ++m;
4198 }
4199 }
4200 return origin;
4201 }
4202
4203 static int
4204 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
4205 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
4206 {
4207 int c;
4208 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
4209 uint8_t *map = (uint8_t *)p_map;
4210
4211 for (c = 0; c < 4; ++c) {
4212 if (mf & 1) {
4213 if (fpi->linear == TRUE)
4214 lin[mid / 32] |= 1 << (mid % 32);
4215 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
4216 }
4217
4218 oid += mv & 1;
4219 mf >>= 1;
4220 mv >>= 1;
4221 }
4222
4223 return mid;
4224 }
4225
4226 void
4227 nv50_linkage_validate(struct nv50_context *nv50)
4228 {
4229 struct nouveau_grobj *tesla = nv50->screen->tesla;
4230 struct nv50_program *vp = nv50->vertprog;
4231 struct nv50_program *fp = nv50->fragprog;
4232 struct nouveau_stateobj *so;
4233 struct nv50_sreg4 dummy, *vpo;
4234 int i, n, c, m = 0;
4235 uint32_t map[16], lin[4], reg[5], pcrd[8];
4236
4237 memset(map, 0, sizeof(map));
4238 memset(lin, 0, sizeof(lin));
4239
4240 reg[1] = 0x00000004; /* low and high clip distance map ids */
4241 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
4242 reg[3] = 0x00000000; /* point size map id & enable */
4243 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
4244 reg[4] = fp->cfg.regs[1]; /* interpolant info */
4245
4246 dummy.linear = FALSE;
4247 dummy.mask = 0xf; /* map all components of HPOS */
4248 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
4249
4250 dummy.mask = 0x0;
4251
4252 if (vp->cfg.clpd < 0x40) {
4253 for (c = 0; c < vp->cfg.clpd_nr; ++c)
4254 map[m++] = vp->cfg.clpd + c;
4255 reg[1] = (m << 8);
4256 }
4257
4258 reg[0] |= m << 8; /* adjust BFC0 id */
4259
4260 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
4261 if (nv50->rasterizer->pipe.light_twoside) {
4262 vpo = &vp->cfg.two_side[0];
4263
4264 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
4265 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
4266 }
4267
4268 reg[0] += m - 4; /* adjust FFC0 id */
4269 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
4270
4271 for (i = 0; i < fp->cfg.io_nr; i++) {
4272 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id];
4273 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id];
4274
4275 /* position must be mapped first */
4276 assert(i == 0 || sn != TGSI_SEMANTIC_POSITION);
4277
4278 /* maybe even remove these from cfg.io */
4279 if (sn == TGSI_SEMANTIC_POSITION || sn == TGSI_SEMANTIC_FACE)
4280 continue;
4281
4282 /* VP outputs and vp->cfg.io are in the same order */
4283 for (n = 0; n < vp->info.num_outputs; ++n) {
4284 if (vp->info.output_semantic_name[n] == sn &&
4285 vp->info.output_semantic_index[n] == si)
4286 break;
4287 }
4288 vpo = (n < vp->info.num_outputs) ? &vp->cfg.io[n] : &dummy;
4289
4290 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
4291 }
4292
4293 if (nv50->rasterizer->pipe.point_size_per_vertex) {
4294 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
4295 reg[3] = (m++ << 4) | 1;
4296 }
4297
4298 /* now fill the stateobj */
4299 so = so_new(7, 57, 0);
4300
4301 n = (m + 3) / 4;
4302 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
4303 so_data (so, m);
4304 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
4305 so_datap (so, map, n);
4306
4307 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
4308 so_datap (so, reg, 4);
4309
4310 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
4311 so_data (so, reg[4]);
4312
4313 so_method(so, tesla, NV50TCL_NOPERSPECTIVE_BITMAP(0), 4);
4314 so_datap (so, lin, 4);
4315
4316 if (nv50->rasterizer->pipe.point_sprite) {
4317 so_method(so, tesla, NV50TCL_POINT_SPRITE_CTRL, 1);
4318 so_data (so,
4319 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff));
4320
4321 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
4322 so_datap (so, pcrd, 8);
4323 }
4324
4325 so_ref(so, &nv50->state.programs);
4326 so_ref(NULL, &so);
4327 }
4328
4329 void
4330 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
4331 {
4332 while (p->exec_head) {
4333 struct nv50_program_exec *e = p->exec_head;
4334
4335 p->exec_head = e->next;
4336 FREE(e);
4337 }
4338 p->exec_tail = NULL;
4339 p->exec_size = 0;
4340
4341 nouveau_bo_ref(NULL, &p->bo);
4342
4343 nouveau_resource_free(&p->data[0]);
4344
4345 p->translated = 0;
4346 }