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nv50: fix CEIL and TRUNC
[mesa.git] / src / gallium / drivers / nv50 / nv50_program.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_defines.h"
25 #include "pipe/p_state.h"
26 #include "pipe/p_inlines.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_util.h"
31
32 #include "nv50_context.h"
33
34 #define NV50_SU_MAX_TEMP 64
35 //#define NV50_PROGRAM_DUMP
36
37 /* ARL - gallium craps itself on progs/vp/arl.txt
38 *
39 * MSB - Like MAD, but MUL+SUB
40 * - Fuck it off, introduce a way to negate args for ops that
41 * support it.
42 *
43 * Look into inlining IMMD for ops other than MOV (make it general?)
44 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
45 * but can emit to P_TEMP first - then MOV later. NVIDIA does this
46 *
47 * In ops such as ADD it's possible to construct a bad opcode in the !is_long()
48 * case, if the emit_src() causes the inst to suddenly become long.
49 *
50 * Verify half-insns work where expected - and force disable them where they
51 * don't work - MUL has it forcibly disabled atm as it fixes POW..
52 *
53 * FUCK! watch dst==src vectors, can overwrite components that are needed.
54 * ie. SUB R0, R0.yzxw, R0
55 *
56 * Things to check with renouveau:
57 * FP attr/result assignment - how?
58 * attrib
59 * - 0x16bc maps vp output onto fp hpos
60 * - 0x16c0 maps vp output onto fp col0
61 * result
62 * - colr always 0-3
63 * - depr always 4
64 * 0x16bc->0x16e8 --> some binding between vp/fp regs
65 * 0x16b8 --> VP output count
66 *
67 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005
68 * "MOV rcol.x, fcol.y" = 0x00000004
69 * 0x19a8 --> as above but 0x00000100 and 0x00000000
70 * - 0x00100000 used when KIL used
71 * 0x196c --> as above but 0x00000011 and 0x00000000
72 *
73 * 0x1988 --> 0xXXNNNNNN
74 * - XX == FP high something
75 */
76 struct nv50_reg {
77 enum {
78 P_TEMP,
79 P_ATTR,
80 P_RESULT,
81 P_CONST,
82 P_IMMD
83 } type;
84 int index;
85
86 int hw;
87 int neg;
88
89 int rhw; /* result hw for FP outputs, or interpolant index */
90 int acc; /* instruction where this reg is last read (first insn == 1) */
91 };
92
93 /* arbitrary limits */
94 #define MAX_IF_DEPTH 4
95 #define MAX_LOOP_DEPTH 4
96
97 struct nv50_pc {
98 struct nv50_program *p;
99
100 /* hw resources */
101 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP];
102
103 /* tgsi resources */
104 struct nv50_reg *temp;
105 int temp_nr;
106 struct nv50_reg *attr;
107 int attr_nr;
108 struct nv50_reg *result;
109 int result_nr;
110 struct nv50_reg *param;
111 int param_nr;
112 struct nv50_reg *immd;
113 float *immd_buf;
114 int immd_nr;
115
116 struct nv50_reg *temp_temp[16];
117 unsigned temp_temp_nr;
118
119 /* broadcast and destination replacement regs */
120 struct nv50_reg *r_brdc;
121 struct nv50_reg *r_dst[4];
122
123 unsigned interp_mode[32];
124 /* perspective interpolation registers */
125 struct nv50_reg *iv_p;
126 struct nv50_reg *iv_c;
127
128 struct nv50_program_exec *if_cond;
129 struct nv50_program_exec *if_insn[MAX_IF_DEPTH];
130 struct nv50_program_exec *br_join[MAX_IF_DEPTH];
131 struct nv50_program_exec *br_loop[MAX_LOOP_DEPTH]; /* for BRK branch */
132 int if_lvl, loop_lvl;
133 unsigned loop_pos[MAX_LOOP_DEPTH];
134
135 /* current instruction and total number of insns */
136 unsigned insn_cur;
137 unsigned insn_nr;
138
139 boolean allow32;
140 };
141
142 static INLINE void
143 ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw)
144 {
145 reg->type = type;
146 reg->index = index;
147 reg->hw = hw;
148 reg->neg = 0;
149 reg->rhw = -1;
150 reg->acc = 0;
151 }
152
153 static INLINE unsigned
154 popcnt4(uint32_t val)
155 {
156 static const unsigned cnt[16]
157 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 };
158 return cnt[val & 0xf];
159 }
160
161 static void
162 alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg)
163 {
164 int i = 0;
165
166 if (reg->type == P_RESULT) {
167 if (pc->p->cfg.high_result < (reg->hw + 1))
168 pc->p->cfg.high_result = reg->hw + 1;
169 }
170
171 if (reg->type != P_TEMP)
172 return;
173
174 if (reg->hw >= 0) {
175 /*XXX: do this here too to catch FP temp-as-attr usage..
176 * not clean, but works */
177 if (pc->p->cfg.high_temp < (reg->hw + 1))
178 pc->p->cfg.high_temp = reg->hw + 1;
179 return;
180 }
181
182 if (reg->rhw != -1) {
183 /* try to allocate temporary with index rhw first */
184 if (!(pc->r_temp[reg->rhw])) {
185 pc->r_temp[reg->rhw] = reg;
186 reg->hw = reg->rhw;
187 if (pc->p->cfg.high_temp < (reg->rhw + 1))
188 pc->p->cfg.high_temp = reg->rhw + 1;
189 return;
190 }
191 /* make sure we don't get things like $r0 needs to go
192 * in $r1 and $r1 in $r0
193 */
194 i = pc->result_nr * 4;
195 }
196
197 for (; i < NV50_SU_MAX_TEMP; i++) {
198 if (!(pc->r_temp[i])) {
199 pc->r_temp[i] = reg;
200 reg->hw = i;
201 if (pc->p->cfg.high_temp < (i + 1))
202 pc->p->cfg.high_temp = i + 1;
203 return;
204 }
205 }
206
207 assert(0);
208 }
209
210 /* XXX: For shaders that aren't executed linearly (e.g. shaders that
211 * contain loops), we need to assign all hw regs to TGSI TEMPs early,
212 * lest we risk temp_temps overwriting regs alloc'd "later".
213 */
214 static struct nv50_reg *
215 alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
216 {
217 struct nv50_reg *r;
218 int i;
219
220 if (dst && dst->type == P_TEMP && dst->hw == -1)
221 return dst;
222
223 for (i = 0; i < NV50_SU_MAX_TEMP; i++) {
224 if (!pc->r_temp[i]) {
225 r = MALLOC_STRUCT(nv50_reg);
226 ctor_reg(r, P_TEMP, -1, i);
227 pc->r_temp[i] = r;
228 return r;
229 }
230 }
231
232 assert(0);
233 return NULL;
234 }
235
236 /* Assign the hw of the discarded temporary register src
237 * to the tgsi register dst and free src.
238 */
239 static void
240 assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
241 {
242 assert(src->index == -1 && src->hw != -1);
243
244 if (dst->hw != -1)
245 pc->r_temp[dst->hw] = NULL;
246 pc->r_temp[src->hw] = dst;
247 dst->hw = src->hw;
248
249 FREE(src);
250 }
251
252 /* release the hardware resource held by r */
253 static void
254 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
255 {
256 assert(r->type == P_TEMP);
257 if (r->hw == -1)
258 return;
259
260 assert(pc->r_temp[r->hw] == r);
261 pc->r_temp[r->hw] = NULL;
262
263 r->acc = 0;
264 if (r->index == -1)
265 FREE(r);
266 }
267
268 static void
269 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
270 {
271 if (r->index == -1) {
272 unsigned hw = r->hw;
273
274 FREE(pc->r_temp[hw]);
275 pc->r_temp[hw] = NULL;
276 }
277 }
278
279 static int
280 alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx)
281 {
282 int i;
283
284 if ((idx + 4) >= NV50_SU_MAX_TEMP)
285 return 1;
286
287 if (pc->r_temp[idx] || pc->r_temp[idx + 1] ||
288 pc->r_temp[idx + 2] || pc->r_temp[idx + 3])
289 return alloc_temp4(pc, dst, idx + 4);
290
291 for (i = 0; i < 4; i++) {
292 dst[i] = MALLOC_STRUCT(nv50_reg);
293 ctor_reg(dst[i], P_TEMP, -1, idx + i);
294 pc->r_temp[idx + i] = dst[i];
295 }
296
297 return 0;
298 }
299
300 static void
301 free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4])
302 {
303 int i;
304
305 for (i = 0; i < 4; i++)
306 free_temp(pc, reg[i]);
307 }
308
309 static struct nv50_reg *
310 temp_temp(struct nv50_pc *pc)
311 {
312 if (pc->temp_temp_nr >= 16)
313 assert(0);
314
315 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL);
316 return pc->temp_temp[pc->temp_temp_nr++];
317 }
318
319 static void
320 kill_temp_temp(struct nv50_pc *pc)
321 {
322 int i;
323
324 for (i = 0; i < pc->temp_temp_nr; i++)
325 free_temp(pc, pc->temp_temp[i]);
326 pc->temp_temp_nr = 0;
327 }
328
329 static int
330 ctor_immd(struct nv50_pc *pc, float x, float y, float z, float w)
331 {
332 pc->immd_buf = REALLOC(pc->immd_buf, (pc->immd_nr * 4 * sizeof(float)),
333 (pc->immd_nr + 1) * 4 * sizeof(float));
334 pc->immd_buf[(pc->immd_nr * 4) + 0] = x;
335 pc->immd_buf[(pc->immd_nr * 4) + 1] = y;
336 pc->immd_buf[(pc->immd_nr * 4) + 2] = z;
337 pc->immd_buf[(pc->immd_nr * 4) + 3] = w;
338
339 return pc->immd_nr++;
340 }
341
342 static struct nv50_reg *
343 alloc_immd(struct nv50_pc *pc, float f)
344 {
345 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg);
346 unsigned hw;
347
348 for (hw = 0; hw < pc->immd_nr * 4; hw++)
349 if (pc->immd_buf[hw] == f)
350 break;
351
352 if (hw == pc->immd_nr * 4)
353 hw = ctor_immd(pc, f, -f, 0.5 * f, 0) * 4;
354
355 ctor_reg(r, P_IMMD, -1, hw);
356 return r;
357 }
358
359 static struct nv50_program_exec *
360 exec(struct nv50_pc *pc)
361 {
362 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec);
363
364 e->param.index = -1;
365 return e;
366 }
367
368 static void
369 emit(struct nv50_pc *pc, struct nv50_program_exec *e)
370 {
371 struct nv50_program *p = pc->p;
372
373 if (p->exec_tail)
374 p->exec_tail->next = e;
375 if (!p->exec_head)
376 p->exec_head = e;
377 p->exec_tail = e;
378 p->exec_size += (e->inst[0] & 1) ? 2 : 1;
379 }
380
381 static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *);
382
383 static boolean
384 is_long(struct nv50_program_exec *e)
385 {
386 if (e->inst[0] & 1)
387 return TRUE;
388 return FALSE;
389 }
390
391 static boolean
392 is_immd(struct nv50_program_exec *e)
393 {
394 if (is_long(e) && (e->inst[1] & 3) == 3)
395 return TRUE;
396 return FALSE;
397 }
398
399 static INLINE void
400 set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx,
401 struct nv50_program_exec *e)
402 {
403 set_long(pc, e);
404 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12));
405 e->inst[1] |= (pred << 7) | (idx << 12);
406 }
407
408 static INLINE void
409 set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx,
410 struct nv50_program_exec *e)
411 {
412 set_long(pc, e);
413 e->inst[1] &= ~((0x3 << 4) | (1 << 6));
414 e->inst[1] |= (idx << 4) | (on << 6);
415 }
416
417 static INLINE void
418 set_long(struct nv50_pc *pc, struct nv50_program_exec *e)
419 {
420 if (is_long(e))
421 return;
422
423 e->inst[0] |= 1;
424 set_pred(pc, 0xf, 0, e);
425 set_pred_wr(pc, 0, 0, e);
426 }
427
428 static INLINE void
429 set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e)
430 {
431 if (dst->type == P_RESULT) {
432 set_long(pc, e);
433 e->inst[1] |= 0x00000008;
434 }
435
436 alloc_reg(pc, dst);
437 e->inst[0] |= (dst->hw << 2);
438 }
439
440 static INLINE void
441 set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
442 {
443 float f = pc->immd_buf[imm->hw];
444 unsigned val = fui(imm->neg ? -f : f);
445
446 set_long(pc, e);
447 /*XXX: can't be predicated - bits overlap.. catch cases where both
448 * are required and avoid them. */
449 set_pred(pc, 0, 0, e);
450 set_pred_wr(pc, 0, 0, e);
451
452 e->inst[1] |= 0x00000002 | 0x00000001;
453 e->inst[0] |= (val & 0x3f) << 16;
454 e->inst[1] |= (val >> 6) << 2;
455 }
456
457
458 #define INTERP_LINEAR 0
459 #define INTERP_FLAT 1
460 #define INTERP_PERSPECTIVE 2
461 #define INTERP_CENTROID 4
462
463 /* interpolant index has been stored in dst->rhw */
464 static void
465 emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv,
466 unsigned mode)
467 {
468 assert(dst->rhw != -1);
469 struct nv50_program_exec *e = exec(pc);
470
471 e->inst[0] |= 0x80000000;
472 set_dst(pc, dst, e);
473 e->inst[0] |= (dst->rhw << 16);
474
475 if (mode & INTERP_FLAT) {
476 e->inst[0] |= (1 << 8);
477 } else {
478 if (mode & INTERP_PERSPECTIVE) {
479 e->inst[0] |= (1 << 25);
480 alloc_reg(pc, iv);
481 e->inst[0] |= (iv->hw << 9);
482 }
483
484 if (mode & INTERP_CENTROID)
485 e->inst[0] |= (1 << 24);
486 }
487
488 emit(pc, e);
489 }
490
491 static void
492 set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s,
493 struct nv50_program_exec *e)
494 {
495 set_long(pc, e);
496
497 e->param.index = src->hw;
498 e->param.shift = s;
499 e->param.mask = m << (s % 32);
500
501 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22);
502 }
503
504 static void
505 emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
506 {
507 struct nv50_program_exec *e = exec(pc);
508
509 e->inst[0] |= 0x10000000;
510
511 set_dst(pc, dst, e);
512
513 if (pc->allow32 && dst->type != P_RESULT && src->type == P_IMMD) {
514 set_immd(pc, src, e);
515 /*XXX: 32-bit, but steals part of "half" reg space - need to
516 * catch and handle this case if/when we do half-regs
517 */
518 } else
519 if (src->type == P_IMMD || src->type == P_CONST) {
520 set_long(pc, e);
521 set_data(pc, src, 0x7f, 9, e);
522 e->inst[1] |= 0x20000000; /* src0 const? */
523 } else {
524 if (src->type == P_ATTR) {
525 set_long(pc, e);
526 e->inst[1] |= 0x00200000;
527 }
528
529 alloc_reg(pc, src);
530 e->inst[0] |= (src->hw << 9);
531 }
532
533 if (is_long(e) && !is_immd(e)) {
534 e->inst[1] |= 0x04000000; /* 32-bit */
535 e->inst[1] |= 0x0000c000; /* "subsubop" 0x3 */
536 if (!(e->inst[1] & 0x20000000))
537 e->inst[1] |= 0x00030000; /* "subsubop" 0xf */
538 } else
539 e->inst[0] |= 0x00008000;
540
541 emit(pc, e);
542 }
543
544 static INLINE void
545 emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f)
546 {
547 struct nv50_reg *imm = alloc_immd(pc, f);
548 emit_mov(pc, dst, imm);
549 FREE(imm);
550 }
551
552 static boolean
553 check_swap_src_0_1(struct nv50_pc *pc,
554 struct nv50_reg **s0, struct nv50_reg **s1)
555 {
556 struct nv50_reg *src0 = *s0, *src1 = *s1;
557
558 if (src0->type == P_CONST) {
559 if (src1->type != P_CONST) {
560 *s0 = src1;
561 *s1 = src0;
562 return TRUE;
563 }
564 } else
565 if (src1->type == P_ATTR) {
566 if (src0->type != P_ATTR) {
567 *s0 = src1;
568 *s1 = src0;
569 return TRUE;
570 }
571 }
572
573 return FALSE;
574 }
575
576 static void
577 set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
578 {
579 if (src->type == P_ATTR) {
580 set_long(pc, e);
581 e->inst[1] |= 0x00200000;
582 } else
583 if (src->type == P_CONST || src->type == P_IMMD) {
584 struct nv50_reg *temp = temp_temp(pc);
585
586 emit_mov(pc, temp, src);
587 src = temp;
588 }
589
590 alloc_reg(pc, src);
591 e->inst[0] |= (src->hw << 9);
592 }
593
594 static void
595 set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
596 {
597 if (src->type == P_ATTR) {
598 struct nv50_reg *temp = temp_temp(pc);
599
600 emit_mov(pc, temp, src);
601 src = temp;
602 } else
603 if (src->type == P_CONST || src->type == P_IMMD) {
604 assert(!(e->inst[0] & 0x00800000));
605 if (e->inst[0] & 0x01000000) {
606 struct nv50_reg *temp = temp_temp(pc);
607
608 emit_mov(pc, temp, src);
609 src = temp;
610 } else {
611 set_data(pc, src, 0x7f, 16, e);
612 e->inst[0] |= 0x00800000;
613 }
614 }
615
616 alloc_reg(pc, src);
617 e->inst[0] |= (src->hw << 16);
618 }
619
620 static void
621 set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e)
622 {
623 set_long(pc, e);
624
625 if (src->type == P_ATTR) {
626 struct nv50_reg *temp = temp_temp(pc);
627
628 emit_mov(pc, temp, src);
629 src = temp;
630 } else
631 if (src->type == P_CONST || src->type == P_IMMD) {
632 assert(!(e->inst[0] & 0x01000000));
633 if (e->inst[0] & 0x00800000) {
634 struct nv50_reg *temp = temp_temp(pc);
635
636 emit_mov(pc, temp, src);
637 src = temp;
638 } else {
639 set_data(pc, src, 0x7f, 32+14, e);
640 e->inst[0] |= 0x01000000;
641 }
642 }
643
644 alloc_reg(pc, src);
645 e->inst[1] |= (src->hw << 14);
646 }
647
648 static void
649 emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
650 struct nv50_reg *src1)
651 {
652 struct nv50_program_exec *e = exec(pc);
653
654 e->inst[0] |= 0xc0000000;
655
656 if (!pc->allow32)
657 set_long(pc, e);
658
659 check_swap_src_0_1(pc, &src0, &src1);
660 set_dst(pc, dst, e);
661 set_src_0(pc, src0, e);
662 if (src1->type == P_IMMD && !is_long(e)) {
663 if (src0->neg)
664 e->inst[0] |= 0x00008000;
665 set_immd(pc, src1, e);
666 } else {
667 set_src_1(pc, src1, e);
668 if (src0->neg ^ src1->neg) {
669 if (is_long(e))
670 e->inst[1] |= 0x08000000;
671 else
672 e->inst[0] |= 0x00008000;
673 }
674 }
675
676 emit(pc, e);
677 }
678
679 static void
680 emit_add(struct nv50_pc *pc, struct nv50_reg *dst,
681 struct nv50_reg *src0, struct nv50_reg *src1)
682 {
683 struct nv50_program_exec *e = exec(pc);
684
685 e->inst[0] |= 0xb0000000;
686
687 check_swap_src_0_1(pc, &src0, &src1);
688
689 if (!pc->allow32 || src0->neg || src1->neg) {
690 set_long(pc, e);
691 e->inst[1] |= (src0->neg << 26) | (src1->neg << 27);
692 }
693
694 set_dst(pc, dst, e);
695 set_src_0(pc, src0, e);
696 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e))
697 set_src_2(pc, src1, e);
698 else
699 if (src1->type == P_IMMD)
700 set_immd(pc, src1, e);
701 else
702 set_src_1(pc, src1, e);
703
704 emit(pc, e);
705 }
706
707 static void
708 emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst,
709 struct nv50_reg *src0, struct nv50_reg *src1)
710 {
711 struct nv50_program_exec *e = exec(pc);
712
713 set_long(pc, e);
714 e->inst[0] |= 0xb0000000;
715 e->inst[1] |= (sub << 29);
716
717 check_swap_src_0_1(pc, &src0, &src1);
718 set_dst(pc, dst, e);
719 set_src_0(pc, src0, e);
720 set_src_1(pc, src1, e);
721
722 emit(pc, e);
723 }
724
725 static INLINE void
726 emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
727 struct nv50_reg *src1)
728 {
729 src1->neg ^= 1;
730 emit_add(pc, dst, src0, src1);
731 src1->neg ^= 1;
732 }
733
734 static void
735 emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
736 struct nv50_reg *src1, struct nv50_reg *src2)
737 {
738 struct nv50_program_exec *e = exec(pc);
739
740 e->inst[0] |= 0xe0000000;
741
742 check_swap_src_0_1(pc, &src0, &src1);
743 set_dst(pc, dst, e);
744 set_src_0(pc, src0, e);
745 set_src_1(pc, src1, e);
746 set_src_2(pc, src2, e);
747
748 if (src0->neg ^ src1->neg)
749 e->inst[1] |= 0x04000000;
750 if (src2->neg)
751 e->inst[1] |= 0x08000000;
752
753 emit(pc, e);
754 }
755
756 static INLINE void
757 emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0,
758 struct nv50_reg *src1, struct nv50_reg *src2)
759 {
760 src2->neg ^= 1;
761 emit_mad(pc, dst, src0, src1, src2);
762 src2->neg ^= 1;
763 }
764
765 static void
766 emit_flop(struct nv50_pc *pc, unsigned sub,
767 struct nv50_reg *dst, struct nv50_reg *src)
768 {
769 struct nv50_program_exec *e = exec(pc);
770
771 e->inst[0] |= 0x90000000;
772 if (sub) {
773 set_long(pc, e);
774 e->inst[1] |= (sub << 29);
775 }
776
777 set_dst(pc, dst, e);
778 set_src_0(pc, src, e);
779
780 emit(pc, e);
781 }
782
783 static void
784 emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
785 {
786 struct nv50_program_exec *e = exec(pc);
787
788 e->inst[0] |= 0xb0000000;
789
790 set_dst(pc, dst, e);
791 set_src_0(pc, src, e);
792 set_long(pc, e);
793 e->inst[1] |= (6 << 29) | 0x00004000;
794
795 emit(pc, e);
796 }
797
798 static void
799 emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
800 {
801 struct nv50_program_exec *e = exec(pc);
802
803 e->inst[0] |= 0xb0000000;
804
805 set_dst(pc, dst, e);
806 set_src_0(pc, src, e);
807 set_long(pc, e);
808 e->inst[1] |= (6 << 29);
809
810 emit(pc, e);
811 }
812
813 #define CVTOP_RN 0x01
814 #define CVTOP_FLOOR 0x03
815 #define CVTOP_CEIL 0x05
816 #define CVTOP_TRUNC 0x07
817 #define CVTOP_SAT 0x08
818 #define CVTOP_ABS 0x10
819
820 /* 0x04 == 32 bit */
821 /* 0x40 == dst is float */
822 /* 0x80 == src is float */
823 #define CVT_F32_F32 0xc4
824 #define CVT_F32_S32 0x44
825 #define CVT_F32_U32 0x64
826 #define CVT_S32_F32 0x8c
827 #define CVT_S32_S32 0x0c
828 #define CVT_NEG 0x20
829 #define CVT_RI 0x08
830
831 static void
832 emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src,
833 int wp, unsigned cvn, unsigned fmt)
834 {
835 struct nv50_program_exec *e;
836
837 e = exec(pc);
838 set_long(pc, e);
839
840 e->inst[0] |= 0xa0000000;
841 e->inst[1] |= 0x00004000;
842 e->inst[1] |= (cvn << 16);
843 e->inst[1] |= (fmt << 24);
844 set_src_0(pc, src, e);
845
846 if (wp >= 0)
847 set_pred_wr(pc, 1, wp, e);
848
849 if (dst)
850 set_dst(pc, dst, e);
851 else {
852 e->inst[0] |= 0x000001fc;
853 e->inst[1] |= 0x00000008;
854 }
855
856 emit(pc, e);
857 }
858
859 /* nv50 Condition codes:
860 * 0x1 = LT
861 * 0x2 = EQ
862 * 0x3 = LE
863 * 0x4 = GT
864 * 0x5 = NE
865 * 0x6 = GE
866 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge)
867 * 0x8 = unordered bit (allows NaN)
868 */
869 static void
870 emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp,
871 struct nv50_reg *src0, struct nv50_reg *src1)
872 {
873 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 };
874
875 struct nv50_program_exec *e = exec(pc);
876 struct nv50_reg *rdst;
877
878 assert(ccode < 16);
879 if (check_swap_src_0_1(pc, &src0, &src1))
880 ccode = cc_swapped[ccode & 7] | (ccode & 8);
881
882 rdst = dst;
883 if (dst && dst->type != P_TEMP)
884 dst = alloc_temp(pc, NULL);
885
886 /* set.u32 */
887 set_long(pc, e);
888 e->inst[0] |= 0xb0000000;
889 e->inst[1] |= 0x60000000 | (ccode << 14);
890
891 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
892 * that doesn't seem to match what the hw actually does
893 e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
894 */
895
896 if (wp >= 0)
897 set_pred_wr(pc, 1, wp, e);
898 if (dst)
899 set_dst(pc, dst, e);
900 else {
901 e->inst[0] |= 0x000001fc;
902 e->inst[1] |= 0x00000008;
903 }
904
905 set_src_0(pc, src0, e);
906 set_src_1(pc, src1, e);
907
908 emit(pc, e);
909 pc->if_cond = pc->p->exec_tail; /* record for OPCODE_IF */
910
911 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */
912 if (rdst)
913 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32);
914 if (rdst && rdst != dst)
915 free_temp(pc, dst);
916 }
917
918 static INLINE unsigned
919 map_tgsi_setop_cc(unsigned op)
920 {
921 switch (op) {
922 case TGSI_OPCODE_SLT: return 0x1;
923 case TGSI_OPCODE_SGE: return 0x6;
924 case TGSI_OPCODE_SEQ: return 0x2;
925 case TGSI_OPCODE_SGT: return 0x4;
926 case TGSI_OPCODE_SLE: return 0x3;
927 case TGSI_OPCODE_SNE: return 0xd;
928 default:
929 assert(0);
930 return 0;
931 }
932 }
933
934 static INLINE void
935 emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
936 {
937 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI);
938 }
939
940 static void
941 emit_pow(struct nv50_pc *pc, struct nv50_reg *dst,
942 struct nv50_reg *v, struct nv50_reg *e)
943 {
944 struct nv50_reg *temp = alloc_temp(pc, NULL);
945
946 emit_flop(pc, 3, temp, v);
947 emit_mul(pc, temp, temp, e);
948 emit_preex2(pc, temp, temp);
949 emit_flop(pc, 6, dst, temp);
950
951 free_temp(pc, temp);
952 }
953
954 static INLINE void
955 emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
956 {
957 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32);
958 }
959
960 static INLINE void
961 emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
962 {
963 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32);
964 }
965
966 static void
967 emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
968 struct nv50_reg **src)
969 {
970 struct nv50_reg *one = alloc_immd(pc, 1.0);
971 struct nv50_reg *zero = alloc_immd(pc, 0.0);
972 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999);
973 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999);
974 struct nv50_reg *tmp[4];
975 boolean allow32 = pc->allow32;
976
977 pc->allow32 = FALSE;
978
979 if (mask & (3 << 1)) {
980 tmp[0] = alloc_temp(pc, NULL);
981 emit_minmax(pc, 4, tmp[0], src[0], zero);
982 }
983
984 if (mask & (1 << 2)) {
985 set_pred_wr(pc, 1, 0, pc->p->exec_tail);
986
987 tmp[1] = temp_temp(pc);
988 emit_minmax(pc, 4, tmp[1], src[1], zero);
989
990 tmp[3] = temp_temp(pc);
991 emit_minmax(pc, 4, tmp[3], src[3], neg128);
992 emit_minmax(pc, 5, tmp[3], tmp[3], pos128);
993
994 emit_pow(pc, dst[2], tmp[1], tmp[3]);
995 emit_mov(pc, dst[2], zero);
996 set_pred(pc, 3, 0, pc->p->exec_tail);
997 }
998
999 if (mask & (1 << 1))
1000 assimilate_temp(pc, dst[1], tmp[0]);
1001 else
1002 if (mask & (1 << 2))
1003 free_temp(pc, tmp[0]);
1004
1005 pc->allow32 = allow32;
1006
1007 /* do this last, in case src[i,j] == dst[0,3] */
1008 if (mask & (1 << 0))
1009 emit_mov(pc, dst[0], one);
1010
1011 if (mask & (1 << 3))
1012 emit_mov(pc, dst[3], one);
1013
1014 FREE(pos128);
1015 FREE(neg128);
1016 FREE(zero);
1017 FREE(one);
1018 }
1019
1020 static void
1021 emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
1022 {
1023 struct nv50_program_exec *e = exec(pc);
1024
1025 set_long(pc, e);
1026 e->inst[0] |= 0xa0000000; /* delta */
1027 e->inst[1] |= (7 << 29); /* delta */
1028 e->inst[1] |= 0x04000000; /* negate arg0? probably not */
1029 e->inst[1] |= (1 << 14); /* src .f32 */
1030 set_dst(pc, dst, e);
1031 set_src_0(pc, src, e);
1032
1033 emit(pc, e);
1034 }
1035
1036 static void
1037 emit_kil(struct nv50_pc *pc, struct nv50_reg *src)
1038 {
1039 struct nv50_program_exec *e;
1040 const int r_pred = 1;
1041
1042 /* Sets predicate reg ? */
1043 e = exec(pc);
1044 e->inst[0] = 0xa00001fd;
1045 e->inst[1] = 0xc4014788;
1046 set_src_0(pc, src, e);
1047 set_pred_wr(pc, 1, r_pred, e);
1048 if (src->neg)
1049 e->inst[1] |= 0x20000000;
1050 emit(pc, e);
1051
1052 /* This is probably KILP */
1053 e = exec(pc);
1054 e->inst[0] = 0x000001fe;
1055 set_long(pc, e);
1056 set_pred(pc, 1 /* LT? */, r_pred, e);
1057 emit(pc, e);
1058 }
1059
1060 static void
1061 emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask,
1062 struct nv50_reg **src, unsigned unit, unsigned type, boolean proj)
1063 {
1064 struct nv50_reg *temp, *t[4];
1065 struct nv50_program_exec *e;
1066
1067 unsigned c, mode, dim;
1068
1069 switch (type) {
1070 case TGSI_TEXTURE_1D:
1071 dim = 1;
1072 break;
1073 case TGSI_TEXTURE_UNKNOWN:
1074 case TGSI_TEXTURE_2D:
1075 case TGSI_TEXTURE_SHADOW1D: /* XXX: x, z */
1076 case TGSI_TEXTURE_RECT:
1077 dim = 2;
1078 break;
1079 case TGSI_TEXTURE_3D:
1080 case TGSI_TEXTURE_CUBE:
1081 case TGSI_TEXTURE_SHADOW2D:
1082 case TGSI_TEXTURE_SHADOWRECT: /* XXX */
1083 dim = 3;
1084 break;
1085 default:
1086 assert(0);
1087 break;
1088 }
1089
1090 /* some cards need t[0]'s hw index to be a multiple of 4 */
1091 alloc_temp4(pc, t, 0);
1092
1093 if (proj) {
1094 if (src[0]->type == P_TEMP && src[0]->rhw != -1) {
1095 mode = pc->interp_mode[src[0]->index];
1096
1097 t[3]->rhw = src[3]->rhw;
1098 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID));
1099 emit_flop(pc, 0, t[3], t[3]);
1100
1101 for (c = 0; c < dim; c++) {
1102 t[c]->rhw = src[c]->rhw;
1103 emit_interp(pc, t[c], t[3],
1104 (mode | INTERP_PERSPECTIVE));
1105 }
1106 } else {
1107 emit_flop(pc, 0, t[3], src[3]);
1108 for (c = 0; c < dim; c++)
1109 emit_mul(pc, t[c], src[c], t[3]);
1110
1111 /* XXX: for some reason the blob sometimes uses MAD:
1112 * emit_mad(pc, t[c], src[0][c], t[3], t[3])
1113 * pc->p->exec_tail->inst[1] |= 0x080fc000;
1114 */
1115 }
1116 } else {
1117 if (type == TGSI_TEXTURE_CUBE) {
1118 temp = temp_temp(pc);
1119 emit_minmax(pc, 4, temp, src[0], src[1]);
1120 emit_minmax(pc, 4, temp, temp, src[2]);
1121 emit_flop(pc, 0, temp, temp);
1122 for (c = 0; c < 3; c++)
1123 emit_mul(pc, t[c], src[c], temp);
1124 } else {
1125 for (c = 0; c < dim; c++)
1126 emit_mov(pc, t[c], src[c]);
1127 }
1128 }
1129
1130 e = exec(pc);
1131 set_long(pc, e);
1132 e->inst[0] |= 0xf0000000;
1133 e->inst[1] |= 0x00000004;
1134 set_dst(pc, t[0], e);
1135 e->inst[0] |= (unit << 9);
1136
1137 if (dim == 2)
1138 e->inst[0] |= 0x00400000;
1139 else
1140 if (dim == 3)
1141 e->inst[0] |= 0x00800000;
1142
1143 e->inst[0] |= (mask & 0x3) << 25;
1144 e->inst[1] |= (mask & 0xc) << 12;
1145
1146 emit(pc, e);
1147
1148 #if 1
1149 if (mask & 1) emit_mov(pc, dst[0], t[0]);
1150 if (mask & 2) emit_mov(pc, dst[1], t[1]);
1151 if (mask & 4) emit_mov(pc, dst[2], t[2]);
1152 if (mask & 8) emit_mov(pc, dst[3], t[3]);
1153
1154 free_temp4(pc, t);
1155 #else
1156 /* XXX: if p.e. MUL is used directly after TEX, it would still use
1157 * the texture coordinates, not the fetched values: latency ? */
1158
1159 for (c = 0; c < 4; c++) {
1160 if (mask & (1 << c))
1161 assimilate_temp(pc, dst[c], t[c]);
1162 else
1163 free_temp(pc, t[c]);
1164 }
1165 #endif
1166 }
1167
1168 static void
1169 emit_branch(struct nv50_pc *pc, int pred, unsigned cc,
1170 struct nv50_program_exec **join)
1171 {
1172 struct nv50_program_exec *e = exec(pc);
1173
1174 if (join) {
1175 set_long(pc, e);
1176 e->inst[0] |= 0xa0000002;
1177 emit(pc, e);
1178 *join = e;
1179 e = exec(pc);
1180 }
1181
1182 set_long(pc, e);
1183 e->inst[0] |= 0x10000002;
1184 if (pred >= 0)
1185 set_pred(pc, cc, pred, e);
1186 emit(pc, e);
1187 }
1188
1189 static void
1190 emit_nop(struct nv50_pc *pc)
1191 {
1192 struct nv50_program_exec *e = exec(pc);
1193
1194 e->inst[0] = 0xf0000000;
1195 set_long(pc, e);
1196 e->inst[1] = 0xe0000000;
1197 emit(pc, e);
1198 }
1199
1200 static void
1201 convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e)
1202 {
1203 unsigned q = 0, m = ~0;
1204
1205 assert(!is_long(e));
1206
1207 switch (e->inst[0] >> 28) {
1208 case 0x1:
1209 /* MOV */
1210 q = 0x0403c000;
1211 m = 0xffff7fff;
1212 break;
1213 case 0x8:
1214 /* INTERP (move centroid, perspective and flat bits) */
1215 m = ~0x03000100;
1216 q = (e->inst[0] & (3 << 24)) >> (24 - 16);
1217 q |= (e->inst[0] & (1 << 8)) << (18 - 8);
1218 break;
1219 case 0x9:
1220 /* RCP */
1221 break;
1222 case 0xB:
1223 /* ADD */
1224 m = ~(127 << 16);
1225 q = ((e->inst[0] & (~m)) >> 2);
1226 break;
1227 case 0xC:
1228 /* MUL */
1229 m = ~0x00008000;
1230 q = ((e->inst[0] & (~m)) << 12);
1231 break;
1232 case 0xE:
1233 /* MAD (if src2 == dst) */
1234 q = ((e->inst[0] & 0x1fc) << 12);
1235 break;
1236 default:
1237 assert(0);
1238 break;
1239 }
1240
1241 set_long(pc, e);
1242 pc->p->exec_size++;
1243
1244 e->inst[0] &= m;
1245 e->inst[1] |= q;
1246 }
1247
1248 static boolean
1249 negate_supported(const struct tgsi_full_instruction *insn, int i)
1250 {
1251 switch (insn->Instruction.Opcode) {
1252 case TGSI_OPCODE_DP3:
1253 case TGSI_OPCODE_DP4:
1254 case TGSI_OPCODE_MUL:
1255 case TGSI_OPCODE_KIL:
1256 case TGSI_OPCODE_ADD:
1257 case TGSI_OPCODE_SUB:
1258 case TGSI_OPCODE_MAD:
1259 return TRUE;
1260 case TGSI_OPCODE_POW:
1261 return (i == 1) ? TRUE : FALSE;
1262 default:
1263 return FALSE;
1264 }
1265 }
1266
1267 /* Return a read mask for source registers deduced from opcode & write mask. */
1268 static unsigned
1269 nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
1270 {
1271 unsigned x, mask = insn->FullDstRegisters[0].DstRegister.WriteMask;
1272
1273 switch (insn->Instruction.Opcode) {
1274 case TGSI_OPCODE_COS:
1275 case TGSI_OPCODE_SIN:
1276 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0);
1277 case TGSI_OPCODE_DP3:
1278 return 0x7;
1279 case TGSI_OPCODE_DP4:
1280 case TGSI_OPCODE_DPH:
1281 case TGSI_OPCODE_KIL: /* WriteMask ignored */
1282 return 0xf;
1283 case TGSI_OPCODE_DST:
1284 return mask & (c ? 0xa : 0x6);
1285 case TGSI_OPCODE_EX2:
1286 case TGSI_OPCODE_LG2:
1287 case TGSI_OPCODE_POW:
1288 case TGSI_OPCODE_RCP:
1289 case TGSI_OPCODE_RSQ:
1290 case TGSI_OPCODE_SCS:
1291 return 0x1;
1292 case TGSI_OPCODE_LIT:
1293 return 0xb;
1294 case TGSI_OPCODE_TEX:
1295 case TGSI_OPCODE_TXP:
1296 {
1297 const struct tgsi_instruction_ext_texture *tex;
1298
1299 assert(insn->Instruction.Extended);
1300 tex = &insn->InstructionExtTexture;
1301
1302 mask = 0x7;
1303 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP)
1304 mask |= 0x8;
1305
1306 switch (tex->Texture) {
1307 case TGSI_TEXTURE_1D:
1308 mask &= 0x9;
1309 break;
1310 case TGSI_TEXTURE_2D:
1311 mask &= 0xb;
1312 break;
1313 default:
1314 break;
1315 }
1316 }
1317 return mask;
1318 case TGSI_OPCODE_XPD:
1319 x = 0;
1320 if (mask & 1) x |= 0x6;
1321 if (mask & 2) x |= 0x5;
1322 if (mask & 4) x |= 0x3;
1323 return x;
1324 default:
1325 break;
1326 }
1327
1328 return mask;
1329 }
1330
1331 static struct nv50_reg *
1332 tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst)
1333 {
1334 switch (dst->DstRegister.File) {
1335 case TGSI_FILE_TEMPORARY:
1336 return &pc->temp[dst->DstRegister.Index * 4 + c];
1337 case TGSI_FILE_OUTPUT:
1338 return &pc->result[dst->DstRegister.Index * 4 + c];
1339 case TGSI_FILE_NULL:
1340 return NULL;
1341 default:
1342 break;
1343 }
1344
1345 return NULL;
1346 }
1347
1348 static struct nv50_reg *
1349 tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src,
1350 boolean neg)
1351 {
1352 struct nv50_reg *r = NULL;
1353 struct nv50_reg *temp;
1354 unsigned sgn, c;
1355
1356 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan);
1357
1358 c = tgsi_util_get_full_src_register_extswizzle(src, chan);
1359 switch (c) {
1360 case TGSI_EXTSWIZZLE_X:
1361 case TGSI_EXTSWIZZLE_Y:
1362 case TGSI_EXTSWIZZLE_Z:
1363 case TGSI_EXTSWIZZLE_W:
1364 switch (src->SrcRegister.File) {
1365 case TGSI_FILE_INPUT:
1366 r = &pc->attr[src->SrcRegister.Index * 4 + c];
1367 break;
1368 case TGSI_FILE_TEMPORARY:
1369 r = &pc->temp[src->SrcRegister.Index * 4 + c];
1370 break;
1371 case TGSI_FILE_CONSTANT:
1372 r = &pc->param[src->SrcRegister.Index * 4 + c];
1373 break;
1374 case TGSI_FILE_IMMEDIATE:
1375 r = &pc->immd[src->SrcRegister.Index * 4 + c];
1376 break;
1377 case TGSI_FILE_SAMPLER:
1378 break;
1379 default:
1380 assert(0);
1381 break;
1382 }
1383 break;
1384 case TGSI_EXTSWIZZLE_ZERO:
1385 r = alloc_immd(pc, 0.0);
1386 return r;
1387 case TGSI_EXTSWIZZLE_ONE:
1388 if (sgn == TGSI_UTIL_SIGN_TOGGLE || sgn == TGSI_UTIL_SIGN_SET)
1389 return alloc_immd(pc, -1.0);
1390 return alloc_immd(pc, 1.0);
1391 default:
1392 assert(0);
1393 break;
1394 }
1395
1396 switch (sgn) {
1397 case TGSI_UTIL_SIGN_KEEP:
1398 break;
1399 case TGSI_UTIL_SIGN_CLEAR:
1400 temp = temp_temp(pc);
1401 emit_abs(pc, temp, r);
1402 r = temp;
1403 break;
1404 case TGSI_UTIL_SIGN_TOGGLE:
1405 if (neg)
1406 r->neg = 1;
1407 else {
1408 temp = temp_temp(pc);
1409 emit_neg(pc, temp, r);
1410 r = temp;
1411 }
1412 break;
1413 case TGSI_UTIL_SIGN_SET:
1414 temp = temp_temp(pc);
1415 emit_abs(pc, temp, r);
1416 if (neg)
1417 temp->neg = 1;
1418 else
1419 emit_neg(pc, temp, temp);
1420 r = temp;
1421 break;
1422 default:
1423 assert(0);
1424 break;
1425 }
1426
1427 return r;
1428 }
1429
1430 /* return TRUE for ops that produce only a single result */
1431 static boolean
1432 is_scalar_op(unsigned op)
1433 {
1434 switch (op) {
1435 case TGSI_OPCODE_COS:
1436 case TGSI_OPCODE_DP2:
1437 case TGSI_OPCODE_DP3:
1438 case TGSI_OPCODE_DP4:
1439 case TGSI_OPCODE_DPH:
1440 case TGSI_OPCODE_EX2:
1441 case TGSI_OPCODE_LG2:
1442 case TGSI_OPCODE_POW:
1443 case TGSI_OPCODE_RCP:
1444 case TGSI_OPCODE_RSQ:
1445 case TGSI_OPCODE_SIN:
1446 /*
1447 case TGSI_OPCODE_KIL:
1448 case TGSI_OPCODE_LIT:
1449 case TGSI_OPCODE_SCS:
1450 */
1451 return TRUE;
1452 default:
1453 return FALSE;
1454 }
1455 }
1456
1457 /* Returns a bitmask indicating which dst components depend
1458 * on source s, component c (reverse of nv50_tgsi_src_mask).
1459 */
1460 static unsigned
1461 nv50_tgsi_dst_revdep(unsigned op, int s, int c)
1462 {
1463 if (is_scalar_op(op))
1464 return 0x1;
1465
1466 switch (op) {
1467 case TGSI_OPCODE_DST:
1468 return (1 << c) & (s ? 0xa : 0x6);
1469 case TGSI_OPCODE_XPD:
1470 switch (c) {
1471 case 0: return 0x6;
1472 case 1: return 0x5;
1473 case 2: return 0x3;
1474 case 3: return 0x0;
1475 default:
1476 assert(0);
1477 return 0x0;
1478 }
1479 case TGSI_OPCODE_LIT:
1480 case TGSI_OPCODE_SCS:
1481 case TGSI_OPCODE_TEX:
1482 case TGSI_OPCODE_TXP:
1483 /* these take care of dangerous swizzles themselves */
1484 return 0x0;
1485 case TGSI_OPCODE_IF:
1486 case TGSI_OPCODE_KIL:
1487 /* don't call this function for these ops */
1488 assert(0);
1489 return 0;
1490 default:
1491 /* linear vector instruction */
1492 return (1 << c);
1493 }
1494 }
1495
1496 static INLINE boolean
1497 has_pred(struct nv50_program_exec *e, unsigned cc)
1498 {
1499 if (!is_long(e) || is_immd(e))
1500 return FALSE;
1501 return ((e->inst[1] & 0x780) == (cc << 7));
1502 }
1503
1504 /* on ENDIF see if we can do "@p0.neu single_op" instead of:
1505 * join_at ENDIF
1506 * @p0.eq bra ENDIF
1507 * single_op
1508 * ENDIF: nop.join
1509 */
1510 static boolean
1511 nv50_kill_branch(struct nv50_pc *pc)
1512 {
1513 int lvl = pc->if_lvl;
1514
1515 if (pc->if_insn[lvl]->next != pc->p->exec_tail)
1516 return FALSE;
1517
1518 /* if ccode == 'true', the BRA is from an ELSE and the predicate
1519 * reg may no longer be valid, since we currently always use $p0
1520 */
1521 if (has_pred(pc->if_insn[lvl], 0xf))
1522 return FALSE;
1523 assert(pc->if_insn[lvl] && pc->br_join[lvl]);
1524
1525 /* We'll use the exec allocated for JOIN_AT (as we can't easily
1526 * update prev's next); if exec_tail is BRK, update the pointer.
1527 */
1528 if (pc->loop_lvl && pc->br_loop[pc->loop_lvl - 1] == pc->p->exec_tail)
1529 pc->br_loop[pc->loop_lvl - 1] = pc->br_join[lvl];
1530
1531 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */
1532
1533 *pc->br_join[lvl] = *pc->p->exec_tail;
1534
1535 FREE(pc->if_insn[lvl]);
1536 FREE(pc->p->exec_tail);
1537
1538 pc->p->exec_tail = pc->br_join[lvl];
1539 pc->p->exec_tail->next = NULL;
1540 set_pred(pc, 0xd, 0, pc->p->exec_tail);
1541
1542 return TRUE;
1543 }
1544
1545 static boolean
1546 nv50_program_tx_insn(struct nv50_pc *pc,
1547 const struct tgsi_full_instruction *inst)
1548 {
1549 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp;
1550 unsigned mask, sat, unit;
1551 int i, c;
1552
1553 mask = inst->FullDstRegisters[0].DstRegister.WriteMask;
1554 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
1555
1556 memset(src, 0, sizeof(src));
1557
1558 for (c = 0; c < 4; c++) {
1559 if ((mask & (1 << c)) && !pc->r_dst[c])
1560 dst[c] = tgsi_dst(pc, c, &inst->FullDstRegisters[0]);
1561 else
1562 dst[c] = pc->r_dst[c];
1563 rdst[c] = dst[c];
1564 }
1565
1566 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1567 const struct tgsi_full_src_register *fs = &inst->FullSrcRegisters[i];
1568 unsigned src_mask;
1569 boolean neg_supp;
1570
1571 src_mask = nv50_tgsi_src_mask(inst, i);
1572 neg_supp = negate_supported(inst, i);
1573
1574 if (fs->SrcRegister.File == TGSI_FILE_SAMPLER)
1575 unit = fs->SrcRegister.Index;
1576
1577 for (c = 0; c < 4; c++)
1578 if (src_mask & (1 << c))
1579 src[i][c] = tgsi_src(pc, c, fs, neg_supp);
1580 }
1581
1582 brdc = temp = pc->r_brdc;
1583 if (brdc && brdc->type != P_TEMP) {
1584 temp = temp_temp(pc);
1585 if (sat)
1586 brdc = temp;
1587 } else
1588 if (sat) {
1589 for (c = 0; c < 4; c++) {
1590 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP)
1591 continue;
1592 rdst[c] = dst[c];
1593 dst[c] = temp_temp(pc);
1594 }
1595 }
1596
1597 assert(brdc || !is_scalar_op(inst->Instruction.Opcode));
1598
1599 switch (inst->Instruction.Opcode) {
1600 case TGSI_OPCODE_ABS:
1601 for (c = 0; c < 4; c++) {
1602 if (!(mask & (1 << c)))
1603 continue;
1604 emit_abs(pc, dst[c], src[0][c]);
1605 }
1606 break;
1607 case TGSI_OPCODE_ADD:
1608 for (c = 0; c < 4; c++) {
1609 if (!(mask & (1 << c)))
1610 continue;
1611 emit_add(pc, dst[c], src[0][c], src[1][c]);
1612 }
1613 break;
1614 case TGSI_OPCODE_BGNLOOP:
1615 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size;
1616 break;
1617 case TGSI_OPCODE_BRK:
1618 emit_branch(pc, -1, 0, NULL);
1619 assert(pc->loop_lvl > 0);
1620 pc->br_loop[pc->loop_lvl - 1] = pc->p->exec_tail;
1621 break;
1622 case TGSI_OPCODE_CEIL:
1623 for (c = 0; c < 4; c++) {
1624 if (!(mask & (1 << c)))
1625 continue;
1626 emit_cvt(pc, dst[c], src[0][c], -1,
1627 CVTOP_CEIL, CVT_F32_F32 | CVT_RI);
1628 }
1629 break;
1630 case TGSI_OPCODE_COS:
1631 if (mask & 8) {
1632 emit_precossin(pc, temp, src[0][3]);
1633 emit_flop(pc, 5, dst[3], temp);
1634 if (!(mask &= 7))
1635 break;
1636 if (temp == dst[3])
1637 temp = brdc = temp_temp(pc);
1638 }
1639 emit_precossin(pc, temp, src[0][0]);
1640 emit_flop(pc, 5, brdc, temp);
1641 break;
1642 case TGSI_OPCODE_DP3:
1643 emit_mul(pc, temp, src[0][0], src[1][0]);
1644 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1645 emit_mad(pc, brdc, src[0][2], src[1][2], temp);
1646 break;
1647 case TGSI_OPCODE_DP4:
1648 emit_mul(pc, temp, src[0][0], src[1][0]);
1649 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1650 emit_mad(pc, temp, src[0][2], src[1][2], temp);
1651 emit_mad(pc, brdc, src[0][3], src[1][3], temp);
1652 break;
1653 case TGSI_OPCODE_DPH:
1654 emit_mul(pc, temp, src[0][0], src[1][0]);
1655 emit_mad(pc, temp, src[0][1], src[1][1], temp);
1656 emit_mad(pc, temp, src[0][2], src[1][2], temp);
1657 emit_add(pc, brdc, src[1][3], temp);
1658 break;
1659 case TGSI_OPCODE_DST:
1660 if (mask & (1 << 1))
1661 emit_mul(pc, dst[1], src[0][1], src[1][1]);
1662 if (mask & (1 << 2))
1663 emit_mov(pc, dst[2], src[0][2]);
1664 if (mask & (1 << 3))
1665 emit_mov(pc, dst[3], src[1][3]);
1666 if (mask & (1 << 0))
1667 emit_mov_immdval(pc, dst[0], 1.0f);
1668 break;
1669 case TGSI_OPCODE_ELSE:
1670 emit_branch(pc, -1, 0, NULL);
1671 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
1672 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
1673 break;
1674 case TGSI_OPCODE_ENDIF:
1675 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size;
1676
1677 /* try to replace branch over 1 insn with a predicated insn */
1678 if (nv50_kill_branch(pc) == TRUE)
1679 break;
1680
1681 if (pc->br_join[pc->if_lvl]) {
1682 pc->br_join[pc->if_lvl]->param.index = pc->p->exec_size;
1683 pc->br_join[pc->if_lvl] = NULL;
1684 }
1685 /* emit a NOP as join point, we could set it on the next
1686 * one, but would have to make sure it is long and !immd
1687 */
1688 emit_nop(pc);
1689 pc->p->exec_tail->inst[1] |= 2;
1690 break;
1691 case TGSI_OPCODE_ENDLOOP:
1692 emit_branch(pc, -1, 0, NULL);
1693 pc->p->exec_tail->param.index = pc->loop_pos[--pc->loop_lvl];
1694 pc->br_loop[pc->loop_lvl]->param.index = pc->p->exec_size;
1695 break;
1696 case TGSI_OPCODE_EX2:
1697 emit_preex2(pc, temp, src[0][0]);
1698 emit_flop(pc, 6, brdc, temp);
1699 break;
1700 case TGSI_OPCODE_FLR:
1701 for (c = 0; c < 4; c++) {
1702 if (!(mask & (1 << c)))
1703 continue;
1704 emit_flr(pc, dst[c], src[0][c]);
1705 }
1706 break;
1707 case TGSI_OPCODE_FRC:
1708 temp = temp_temp(pc);
1709 for (c = 0; c < 4; c++) {
1710 if (!(mask & (1 << c)))
1711 continue;
1712 emit_flr(pc, temp, src[0][c]);
1713 emit_sub(pc, dst[c], src[0][c], temp);
1714 }
1715 break;
1716 case TGSI_OPCODE_IF:
1717 /* emitting a join_at may not be necessary */
1718 assert(pc->if_lvl < MAX_IF_DEPTH);
1719 set_pred_wr(pc, 1, 0, pc->if_cond);
1720 emit_branch(pc, 0, 2, &pc->br_join[pc->if_lvl]);
1721 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail;
1722 break;
1723 case TGSI_OPCODE_KIL:
1724 emit_kil(pc, src[0][0]);
1725 emit_kil(pc, src[0][1]);
1726 emit_kil(pc, src[0][2]);
1727 emit_kil(pc, src[0][3]);
1728 break;
1729 case TGSI_OPCODE_LIT:
1730 emit_lit(pc, &dst[0], mask, &src[0][0]);
1731 break;
1732 case TGSI_OPCODE_LG2:
1733 emit_flop(pc, 3, brdc, src[0][0]);
1734 break;
1735 case TGSI_OPCODE_LRP:
1736 temp = temp_temp(pc);
1737 for (c = 0; c < 4; c++) {
1738 if (!(mask & (1 << c)))
1739 continue;
1740 emit_sub(pc, temp, src[1][c], src[2][c]);
1741 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]);
1742 }
1743 break;
1744 case TGSI_OPCODE_MAD:
1745 for (c = 0; c < 4; c++) {
1746 if (!(mask & (1 << c)))
1747 continue;
1748 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]);
1749 }
1750 break;
1751 case TGSI_OPCODE_MAX:
1752 for (c = 0; c < 4; c++) {
1753 if (!(mask & (1 << c)))
1754 continue;
1755 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]);
1756 }
1757 break;
1758 case TGSI_OPCODE_MIN:
1759 for (c = 0; c < 4; c++) {
1760 if (!(mask & (1 << c)))
1761 continue;
1762 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]);
1763 }
1764 break;
1765 case TGSI_OPCODE_MOV:
1766 case TGSI_OPCODE_SWZ:
1767 for (c = 0; c < 4; c++) {
1768 if (!(mask & (1 << c)))
1769 continue;
1770 emit_mov(pc, dst[c], src[0][c]);
1771 }
1772 break;
1773 case TGSI_OPCODE_MUL:
1774 for (c = 0; c < 4; c++) {
1775 if (!(mask & (1 << c)))
1776 continue;
1777 emit_mul(pc, dst[c], src[0][c], src[1][c]);
1778 }
1779 break;
1780 case TGSI_OPCODE_POW:
1781 emit_pow(pc, brdc, src[0][0], src[1][0]);
1782 break;
1783 case TGSI_OPCODE_RCP:
1784 emit_flop(pc, 0, brdc, src[0][0]);
1785 break;
1786 case TGSI_OPCODE_RSQ:
1787 emit_flop(pc, 2, brdc, src[0][0]);
1788 break;
1789 case TGSI_OPCODE_SCS:
1790 temp = temp_temp(pc);
1791 if (mask & 3)
1792 emit_precossin(pc, temp, src[0][0]);
1793 if (mask & (1 << 0))
1794 emit_flop(pc, 5, dst[0], temp);
1795 if (mask & (1 << 1))
1796 emit_flop(pc, 4, dst[1], temp);
1797 if (mask & (1 << 2))
1798 emit_mov_immdval(pc, dst[2], 0.0);
1799 if (mask & (1 << 3))
1800 emit_mov_immdval(pc, dst[3], 1.0);
1801 break;
1802 case TGSI_OPCODE_SIN:
1803 if (mask & 8) {
1804 emit_precossin(pc, temp, src[0][3]);
1805 emit_flop(pc, 4, dst[3], temp);
1806 if (!(mask &= 7))
1807 break;
1808 if (temp == dst[3])
1809 temp = brdc = temp_temp(pc);
1810 }
1811 emit_precossin(pc, temp, src[0][0]);
1812 emit_flop(pc, 4, brdc, temp);
1813 break;
1814 case TGSI_OPCODE_SLT:
1815 case TGSI_OPCODE_SGE:
1816 case TGSI_OPCODE_SEQ:
1817 case TGSI_OPCODE_SGT:
1818 case TGSI_OPCODE_SLE:
1819 case TGSI_OPCODE_SNE:
1820 i = map_tgsi_setop_cc(inst->Instruction.Opcode);
1821 for (c = 0; c < 4; c++) {
1822 if (!(mask & (1 << c)))
1823 continue;
1824 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]);
1825 }
1826 break;
1827 case TGSI_OPCODE_SUB:
1828 for (c = 0; c < 4; c++) {
1829 if (!(mask & (1 << c)))
1830 continue;
1831 emit_sub(pc, dst[c], src[0][c], src[1][c]);
1832 }
1833 break;
1834 case TGSI_OPCODE_TEX:
1835 emit_tex(pc, dst, mask, src[0], unit,
1836 inst->InstructionExtTexture.Texture, FALSE);
1837 break;
1838 case TGSI_OPCODE_TXP:
1839 emit_tex(pc, dst, mask, src[0], unit,
1840 inst->InstructionExtTexture.Texture, TRUE);
1841 break;
1842 case TGSI_OPCODE_TRUNC:
1843 for (c = 0; c < 4; c++) {
1844 if (!(mask & (1 << c)))
1845 continue;
1846 emit_cvt(pc, dst[c], src[0][c], -1,
1847 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI);
1848 }
1849 break;
1850 case TGSI_OPCODE_XPD:
1851 temp = temp_temp(pc);
1852 if (mask & (1 << 0)) {
1853 emit_mul(pc, temp, src[0][2], src[1][1]);
1854 emit_msb(pc, dst[0], src[0][1], src[1][2], temp);
1855 }
1856 if (mask & (1 << 1)) {
1857 emit_mul(pc, temp, src[0][0], src[1][2]);
1858 emit_msb(pc, dst[1], src[0][2], src[1][0], temp);
1859 }
1860 if (mask & (1 << 2)) {
1861 emit_mul(pc, temp, src[0][1], src[1][0]);
1862 emit_msb(pc, dst[2], src[0][0], src[1][1], temp);
1863 }
1864 if (mask & (1 << 3))
1865 emit_mov_immdval(pc, dst[3], 1.0);
1866 break;
1867 case TGSI_OPCODE_END:
1868 break;
1869 default:
1870 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode);
1871 return FALSE;
1872 }
1873
1874 if (brdc) {
1875 if (sat)
1876 emit_sat(pc, brdc, brdc);
1877 for (c = 0; c < 4; c++)
1878 if ((mask & (1 << c)) && dst[c] != brdc)
1879 emit_mov(pc, dst[c], brdc);
1880 } else
1881 if (sat) {
1882 for (c = 0; c < 4; c++) {
1883 if (!(mask & (1 << c)))
1884 continue;
1885 /* in this case we saturate later */
1886 if (dst[c]->type == P_TEMP && dst[c]->index < 0)
1887 continue;
1888 emit_sat(pc, rdst[c], dst[c]);
1889 }
1890 }
1891
1892 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1893 for (c = 0; c < 4; c++) {
1894 if (!src[i][c])
1895 continue;
1896 if (src[i][c]->index == -1 && src[i][c]->type == P_IMMD)
1897 FREE(src[i][c]);
1898 }
1899 }
1900
1901 kill_temp_temp(pc);
1902 return TRUE;
1903 }
1904
1905 static void
1906 prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn)
1907 {
1908 struct nv50_reg *reg = NULL;
1909 const struct tgsi_full_src_register *src;
1910 const struct tgsi_dst_register *dst;
1911 unsigned i, c, k, mask;
1912
1913 dst = &insn->FullDstRegisters[0].DstRegister;
1914 mask = dst->WriteMask;
1915
1916 if (dst->File == TGSI_FILE_TEMPORARY)
1917 reg = pc->temp;
1918 else
1919 if (dst->File == TGSI_FILE_OUTPUT)
1920 reg = pc->result;
1921
1922 if (reg) {
1923 for (c = 0; c < 4; c++) {
1924 if (!(mask & (1 << c)))
1925 continue;
1926 reg[dst->Index * 4 + c].acc = pc->insn_nr;
1927 }
1928 }
1929
1930 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
1931 src = &insn->FullSrcRegisters[i];
1932
1933 if (src->SrcRegister.File == TGSI_FILE_TEMPORARY)
1934 reg = pc->temp;
1935 else
1936 if (src->SrcRegister.File == TGSI_FILE_INPUT)
1937 reg = pc->attr;
1938 else
1939 continue;
1940
1941 mask = nv50_tgsi_src_mask(insn, i);
1942
1943 for (c = 0; c < 4; c++) {
1944 if (!(mask & (1 << c)))
1945 continue;
1946 k = tgsi_util_get_full_src_register_extswizzle(src, c);
1947
1948 if (k > TGSI_EXTSWIZZLE_W)
1949 continue;
1950
1951 reg[src->SrcRegister.Index * 4 + k].acc = pc->insn_nr;
1952 }
1953 }
1954 }
1955
1956 /* Returns a bitmask indicating which dst components need to be
1957 * written to temporaries first to avoid 'corrupting' sources.
1958 *
1959 * m[i] (out) indicate component to write in the i-th position
1960 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source
1961 */
1962 static unsigned
1963 nv50_revdep_reorder(unsigned m[4], unsigned rdep[4])
1964 {
1965 unsigned i, c, x, unsafe;
1966
1967 for (c = 0; c < 4; c++)
1968 m[c] = c;
1969
1970 /* Swap as long as a dst component written earlier is depended on
1971 * by one written later, but the next one isn't depended on by it.
1972 */
1973 for (c = 0; c < 3; c++) {
1974 if (rdep[m[c + 1]] & (1 << m[c]))
1975 continue; /* if next one is depended on by us */
1976 for (i = c + 1; i < 4; i++)
1977 /* if we are depended on by a later one */
1978 if (rdep[m[c]] & (1 << m[i]))
1979 break;
1980 if (i == 4)
1981 continue;
1982 /* now, swap */
1983 x = m[c];
1984 m[c] = m[c + 1];
1985 m[c + 1] = x;
1986
1987 /* restart */
1988 c = 0;
1989 }
1990
1991 /* mark dependencies that could not be resolved by reordering */
1992 for (i = 0; i < 3; ++i)
1993 for (c = i + 1; c < 4; ++c)
1994 if (rdep[m[i]] & (1 << m[c]))
1995 unsafe |= (1 << i);
1996
1997 /* NOTE: $unsafe is with respect to order, not component */
1998 return unsafe;
1999 }
2000
2001 /* Select a suitable dst register for broadcasting scalar results,
2002 * or return NULL if we have to allocate an extra TEMP.
2003 *
2004 * If e.g. only 1 component is written, we may also emit the final
2005 * result to a write-only register.
2006 */
2007 static struct nv50_reg *
2008 tgsi_broadcast_dst(struct nv50_pc *pc,
2009 const struct tgsi_full_dst_register *fd, unsigned mask)
2010 {
2011 if (fd->DstRegister.File == TGSI_FILE_TEMPORARY) {
2012 int c = ffs(~mask & fd->DstRegister.WriteMask);
2013 if (c)
2014 return tgsi_dst(pc, c - 1, fd);
2015 } else {
2016 int c = ffs(fd->DstRegister.WriteMask) - 1;
2017 if ((1 << c) == fd->DstRegister.WriteMask)
2018 return tgsi_dst(pc, c, fd);
2019 }
2020
2021 return NULL;
2022 }
2023
2024 /* Scan source swizzles and return a bitmask indicating dst regs that
2025 * also occur among the src regs, and fill rdep for nv50_revdep_reoder.
2026 */
2027 static unsigned
2028 nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
2029 unsigned rdep[4])
2030 {
2031 const struct tgsi_full_dst_register *fd = &insn->FullDstRegisters[0];
2032 const struct tgsi_full_src_register *fs;
2033 unsigned i, deqs = 0;
2034
2035 for (i = 0; i < 4; ++i)
2036 rdep[i] = 0;
2037
2038 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
2039 unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
2040 boolean neg_supp = negate_supported(insn, i);
2041
2042 fs = &insn->FullSrcRegisters[i];
2043 if (fs->SrcRegister.File != fd->DstRegister.File ||
2044 fs->SrcRegister.Index != fd->DstRegister.Index)
2045 continue;
2046
2047 for (chn = 0; chn < 4; ++chn) {
2048 unsigned s, c;
2049
2050 if (!(mask & (1 << chn))) /* src is not read */
2051 continue;
2052 c = tgsi_util_get_full_src_register_extswizzle(fs, chn);
2053 s = tgsi_util_get_full_src_register_sign_mode(fs, chn);
2054
2055 if (c > TGSI_EXTSWIZZLE_W ||
2056 !(fd->DstRegister.WriteMask & (1 << c)))
2057 continue;
2058
2059 /* no danger if src is copied to TEMP first */
2060 if ((s != TGSI_UTIL_SIGN_KEEP) &&
2061 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp))
2062 continue;
2063
2064 rdep[c] |= nv50_tgsi_dst_revdep(
2065 insn->Instruction.Opcode, i, chn);
2066 deqs |= (1 << c);
2067 }
2068 }
2069
2070 return deqs;
2071 }
2072
2073 static boolean
2074 nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok)
2075 {
2076 struct tgsi_full_instruction insn = tok->FullInstruction;
2077 const struct tgsi_full_dst_register *fd;
2078 unsigned i, deqs, rdep[4], m[4];
2079
2080 fd = &tok->FullInstruction.FullDstRegisters[0];
2081 deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
2082
2083 if (is_scalar_op(insn.Instruction.Opcode)) {
2084 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs);
2085 if (!pc->r_brdc)
2086 pc->r_brdc = temp_temp(pc);
2087 return nv50_program_tx_insn(pc, &insn);
2088 }
2089 pc->r_brdc = NULL;
2090
2091 if (!deqs)
2092 return nv50_program_tx_insn(pc, &insn);
2093
2094 deqs = nv50_revdep_reorder(m, rdep);
2095
2096 for (i = 0; i < 4; ++i) {
2097 assert(pc->r_dst[m[i]] == NULL);
2098
2099 insn.FullDstRegisters[0].DstRegister.WriteMask =
2100 fd->DstRegister.WriteMask & (1 << m[i]);
2101
2102 if (!insn.FullDstRegisters[0].DstRegister.WriteMask)
2103 continue;
2104
2105 if (deqs & (1 << i))
2106 pc->r_dst[m[i]] = alloc_temp(pc, NULL);
2107
2108 if (!nv50_program_tx_insn(pc, &insn))
2109 return FALSE;
2110 }
2111
2112 for (i = 0; i < 4; i++) {
2113 struct nv50_reg *reg = pc->r_dst[i];
2114 if (!reg)
2115 continue;
2116 pc->r_dst[i] = NULL;
2117
2118 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE)
2119 emit_sat(pc, tgsi_dst(pc, i, fd), reg);
2120 else
2121 emit_mov(pc, tgsi_dst(pc, i, fd), reg);
2122 free_temp(pc, reg);
2123 }
2124
2125 return TRUE;
2126 }
2127
2128 static void
2129 load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg)
2130 {
2131 struct nv50_reg *iv, **ppiv;
2132 unsigned mode = pc->interp_mode[reg->index];
2133
2134 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p;
2135 iv = *ppiv;
2136
2137 if ((mode & INTERP_PERSPECTIVE) && !iv) {
2138 iv = *ppiv = alloc_temp(pc, NULL);
2139 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1;
2140
2141 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID);
2142 emit_flop(pc, 0, iv, iv);
2143
2144 /* XXX: when loading interpolants dynamically, move these
2145 * to the program head, or make sure it can't be skipped.
2146 */
2147 }
2148
2149 emit_interp(pc, reg, iv, mode);
2150 }
2151
2152 static boolean
2153 nv50_program_tx_prep(struct nv50_pc *pc)
2154 {
2155 struct tgsi_parse_context tp;
2156 struct nv50_program *p = pc->p;
2157 boolean ret = FALSE;
2158 unsigned i, c, flat_nr = 0;
2159
2160 tgsi_parse_init(&tp, pc->p->pipe.tokens);
2161 while (!tgsi_parse_end_of_tokens(&tp)) {
2162 const union tgsi_full_token *tok = &tp.FullToken;
2163
2164 tgsi_parse_token(&tp);
2165 switch (tok->Token.Type) {
2166 case TGSI_TOKEN_TYPE_IMMEDIATE:
2167 {
2168 const struct tgsi_full_immediate *imm =
2169 &tp.FullToken.FullImmediate;
2170
2171 ctor_immd(pc, imm->u[0].Float,
2172 imm->u[1].Float,
2173 imm->u[2].Float,
2174 imm->u[3].Float);
2175 }
2176 break;
2177 case TGSI_TOKEN_TYPE_DECLARATION:
2178 {
2179 const struct tgsi_full_declaration *d;
2180 unsigned si, last, first, mode;
2181
2182 d = &tp.FullToken.FullDeclaration;
2183 first = d->DeclarationRange.First;
2184 last = d->DeclarationRange.Last;
2185
2186 switch (d->Declaration.File) {
2187 case TGSI_FILE_TEMPORARY:
2188 break;
2189 case TGSI_FILE_OUTPUT:
2190 if (!d->Declaration.Semantic ||
2191 p->type == PIPE_SHADER_FRAGMENT)
2192 break;
2193
2194 si = d->Semantic.SemanticIndex;
2195 switch (d->Semantic.SemanticName) {
2196 case TGSI_SEMANTIC_BCOLOR:
2197 p->cfg.two_side[si].hw = first;
2198 if (p->cfg.io_nr > first)
2199 p->cfg.io_nr = first;
2200 break;
2201 case TGSI_SEMANTIC_PSIZE:
2202 p->cfg.psiz = first;
2203 if (p->cfg.io_nr > first)
2204 p->cfg.io_nr = first;
2205 break;
2206 /*
2207 case TGSI_SEMANTIC_CLIP_DISTANCE:
2208 p->cfg.clpd = MIN2(p->cfg.clpd, first);
2209 break;
2210 */
2211 default:
2212 break;
2213 }
2214 break;
2215 case TGSI_FILE_INPUT:
2216 {
2217 if (p->type != PIPE_SHADER_FRAGMENT)
2218 break;
2219
2220 switch (d->Declaration.Interpolate) {
2221 case TGSI_INTERPOLATE_CONSTANT:
2222 mode = INTERP_FLAT;
2223 flat_nr++;
2224 break;
2225 case TGSI_INTERPOLATE_PERSPECTIVE:
2226 mode = INTERP_PERSPECTIVE;
2227 p->cfg.regs[1] |= 0x08 << 24;
2228 break;
2229 default:
2230 mode = INTERP_LINEAR;
2231 break;
2232 }
2233 if (d->Declaration.Centroid)
2234 mode |= INTERP_CENTROID;
2235
2236 assert(last < 32);
2237 for (i = first; i <= last; i++)
2238 pc->interp_mode[i] = mode;
2239 }
2240 break;
2241 case TGSI_FILE_CONSTANT:
2242 break;
2243 case TGSI_FILE_SAMPLER:
2244 break;
2245 default:
2246 NOUVEAU_ERR("bad decl file %d\n",
2247 d->Declaration.File);
2248 goto out_err;
2249 }
2250 }
2251 break;
2252 case TGSI_TOKEN_TYPE_INSTRUCTION:
2253 pc->insn_nr++;
2254 prep_inspect_insn(pc, &tok->FullInstruction);
2255 break;
2256 default:
2257 break;
2258 }
2259 }
2260
2261 if (p->type == PIPE_SHADER_VERTEX) {
2262 int rid = 0;
2263
2264 for (i = 0; i < pc->attr_nr * 4; ++i) {
2265 if (pc->attr[i].acc) {
2266 pc->attr[i].hw = rid++;
2267 p->cfg.attr[i / 32] |= 1 << (i % 32);
2268 }
2269 }
2270
2271 for (i = 0, rid = 0; i < pc->result_nr; ++i) {
2272 p->cfg.io[i].hw = rid;
2273 p->cfg.io[i].id_vp = i;
2274
2275 for (c = 0; c < 4; ++c) {
2276 int n = i * 4 + c;
2277 if (!pc->result[n].acc)
2278 continue;
2279 pc->result[n].hw = rid++;
2280 p->cfg.io[i].mask |= 1 << c;
2281 }
2282 }
2283
2284 for (c = 0; c < 2; ++c)
2285 if (p->cfg.two_side[c].hw < 0x40)
2286 p->cfg.two_side[c] = p->cfg.io[
2287 p->cfg.two_side[c].hw];
2288
2289 if (p->cfg.psiz < 0x40)
2290 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw;
2291 } else
2292 if (p->type == PIPE_SHADER_FRAGMENT) {
2293 int rid, aid;
2294 unsigned n = 0, m = pc->attr_nr - flat_nr;
2295
2296 int base = (TGSI_SEMANTIC_POSITION ==
2297 p->info.input_semantic_name[0]) ? 0 : 1;
2298
2299 /* non-flat interpolants have to be mapped to
2300 * the lower hardware IDs, so sort them:
2301 */
2302 for (i = 0; i < pc->attr_nr; i++) {
2303 if (pc->interp_mode[i] == INTERP_FLAT) {
2304 p->cfg.io[m].id_vp = i + base;
2305 p->cfg.io[m++].id_fp = i;
2306 } else {
2307 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE))
2308 p->cfg.io[n].linear = TRUE;
2309 p->cfg.io[n].id_vp = i + base;
2310 p->cfg.io[n++].id_fp = i;
2311 }
2312 }
2313
2314 if (!base) /* set w-coordinate mask from perspective interp */
2315 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24;
2316
2317 aid = popcnt4( /* if fcrd isn't contained in cfg.io */
2318 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask);
2319
2320 for (n = 0; n < pc->attr_nr; ++n) {
2321 p->cfg.io[n].hw = rid = aid;
2322 i = p->cfg.io[n].id_fp;
2323
2324 for (c = 0; c < 4; ++c) {
2325 if (!pc->attr[i * 4 + c].acc)
2326 continue;
2327 pc->attr[i * 4 + c].rhw = rid++;
2328 p->cfg.io[n].mask |= 1 << c;
2329
2330 load_interpolant(pc, &pc->attr[i * 4 + c]);
2331 }
2332 aid += popcnt4(p->cfg.io[n].mask);
2333 }
2334
2335 if (!base)
2336 p->cfg.regs[1] |= p->cfg.io[0].mask << 24;
2337
2338 m = popcnt4(p->cfg.regs[1] >> 24);
2339
2340 /* set count of non-position inputs and of non-flat
2341 * non-position inputs for FP_INTERPOLANT_CTRL
2342 */
2343 p->cfg.regs[1] |= aid - m;
2344
2345 if (flat_nr) {
2346 i = p->cfg.io[pc->attr_nr - flat_nr].hw;
2347 p->cfg.regs[1] |= (i - m) << 16;
2348 } else
2349 p->cfg.regs[1] |= p->cfg.regs[1] << 16;
2350
2351 /* mark color semantic for light-twoside */
2352 n = 0x40;
2353 for (i = 0; i < pc->attr_nr; i++) {
2354 ubyte si, sn;
2355
2356 sn = p->info.input_semantic_name[p->cfg.io[i].id_fp];
2357 si = p->info.input_semantic_index[p->cfg.io[i].id_fp];
2358
2359 if (sn == TGSI_SEMANTIC_COLOR) {
2360 p->cfg.two_side[si] = p->cfg.io[i];
2361
2362 /* increase colour count */
2363 p->cfg.regs[0] += popcnt4(
2364 p->cfg.two_side[si].mask) << 16;
2365
2366 n = MIN2(n, p->cfg.io[i].hw - m);
2367 }
2368 }
2369 if (n < 0x40)
2370 p->cfg.regs[0] += n;
2371
2372 /* Initialize FP results:
2373 * FragDepth is always first TGSI and last hw output
2374 */
2375 i = p->info.writes_z ? 4 : 0;
2376 for (rid = 0; i < pc->result_nr * 4; i++)
2377 pc->result[i].rhw = rid++;
2378 if (p->info.writes_z)
2379 pc->result[2].rhw = rid;
2380
2381 p->cfg.high_result = rid;
2382 }
2383
2384 if (pc->immd_nr) {
2385 int rid = 0;
2386
2387 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg));
2388 if (!pc->immd)
2389 goto out_err;
2390
2391 for (i = 0; i < pc->immd_nr; i++) {
2392 for (c = 0; c < 4; c++, rid++)
2393 ctor_reg(&pc->immd[rid], P_IMMD, i, rid);
2394 }
2395 }
2396
2397 ret = TRUE;
2398 out_err:
2399 if (pc->iv_p)
2400 free_temp(pc, pc->iv_p);
2401 if (pc->iv_c)
2402 free_temp(pc, pc->iv_c);
2403
2404 tgsi_parse_free(&tp);
2405 return ret;
2406 }
2407
2408 static void
2409 free_nv50_pc(struct nv50_pc *pc)
2410 {
2411 if (pc->immd)
2412 FREE(pc->immd);
2413 if (pc->param)
2414 FREE(pc->param);
2415 if (pc->result)
2416 FREE(pc->result);
2417 if (pc->attr)
2418 FREE(pc->attr);
2419 if (pc->temp)
2420 FREE(pc->temp);
2421
2422 FREE(pc);
2423 }
2424
2425 static boolean
2426 ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p)
2427 {
2428 int i, c;
2429 unsigned rtype[2] = { P_ATTR, P_RESULT };
2430
2431 pc->p = p;
2432 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1;
2433 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1;
2434 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1;
2435 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1;
2436
2437 p->cfg.high_temp = 4;
2438
2439 p->cfg.two_side[0].hw = 0x40;
2440 p->cfg.two_side[1].hw = 0x40;
2441
2442 switch (p->type) {
2443 case PIPE_SHADER_VERTEX:
2444 p->cfg.psiz = 0x40;
2445 p->cfg.clpd = 0x40;
2446 p->cfg.io_nr = pc->result_nr;
2447 break;
2448 case PIPE_SHADER_FRAGMENT:
2449 rtype[0] = rtype[1] = P_TEMP;
2450
2451 p->cfg.regs[0] = 0x01000004;
2452 p->cfg.io_nr = pc->attr_nr;
2453
2454 if (p->info.writes_z) {
2455 p->cfg.regs[2] |= 0x00000100;
2456 p->cfg.regs[3] |= 0x00000011;
2457 }
2458 if (p->info.uses_kill)
2459 p->cfg.regs[2] |= 0x00100000;
2460 break;
2461 }
2462
2463 if (pc->temp_nr) {
2464 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg));
2465 if (!pc->temp)
2466 return FALSE;
2467
2468 for (i = 0; i < pc->temp_nr * 4; ++i)
2469 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1);
2470 }
2471
2472 if (pc->attr_nr) {
2473 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg));
2474 if (!pc->attr)
2475 return FALSE;
2476
2477 for (i = 0; i < pc->attr_nr * 4; ++i)
2478 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1);
2479 }
2480
2481 if (pc->result_nr) {
2482 unsigned nr = pc->result_nr * 4;
2483
2484 pc->result = MALLOC(nr * sizeof(struct nv50_reg));
2485 if (!pc->result)
2486 return FALSE;
2487
2488 for (i = 0; i < nr; ++i)
2489 ctor_reg(&pc->result[i], rtype[1], i / 4, -1);
2490 }
2491
2492 if (pc->param_nr) {
2493 int rid = 0;
2494
2495 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
2496 if (!pc->param)
2497 return FALSE;
2498
2499 for (i = 0; i < pc->param_nr; ++i)
2500 for (c = 0; c < 4; ++c, ++rid)
2501 ctor_reg(&pc->param[rid], P_CONST, i, rid);
2502 }
2503
2504 return TRUE;
2505 }
2506
2507 static void
2508 nv50_fp_move_results(struct nv50_pc *pc)
2509 {
2510 struct nv50_reg reg;
2511 unsigned i;
2512
2513 ctor_reg(&reg, P_TEMP, -1, -1);
2514
2515 for (i = 0; i < pc->result_nr * 4; ++i) {
2516 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0)
2517 continue;
2518 if (pc->result[i].rhw != pc->result[i].hw) {
2519 reg.hw = pc->result[i].rhw;
2520 emit_mov(pc, &reg, &pc->result[i]);
2521 }
2522 }
2523 }
2524
2525 static void
2526 nv50_program_fixup_insns(struct nv50_pc *pc)
2527 {
2528 struct nv50_program_exec *e, *prev = NULL, **bra_list;
2529 unsigned i, n, pos;
2530
2531 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *));
2532
2533 /* Collect branch instructions, we need to adjust their offsets
2534 * when converting 32 bit instructions to 64 bit ones
2535 */
2536 for (n = 0, e = pc->p->exec_head; e; e = e->next)
2537 if (e->param.index >= 0 && !e->param.mask)
2538 bra_list[n++] = e;
2539
2540 /* Make sure we don't have any single 32 bit instructions. */
2541 for (e = pc->p->exec_head, pos = 0; e; e = e->next) {
2542 pos += is_long(e) ? 2 : 1;
2543
2544 if ((pos & 1) && (!e->next || is_long(e->next))) {
2545 for (i = 0; i < n; ++i)
2546 if (bra_list[i]->param.index >= pos)
2547 bra_list[i]->param.index += 1;
2548 convert_to_long(pc, e);
2549 ++pos;
2550 }
2551 if (e->next)
2552 prev = e;
2553 }
2554
2555 assert(!is_immd(pc->p->exec_head));
2556 assert(!is_immd(pc->p->exec_tail));
2557
2558 /* last instruction must be long so it can have the end bit set */
2559 if (!is_long(pc->p->exec_tail)) {
2560 convert_to_long(pc, pc->p->exec_tail);
2561 if (prev)
2562 convert_to_long(pc, prev);
2563 }
2564 assert(!(pc->p->exec_tail->inst[1] & 2));
2565 /* set the end-bit */
2566 pc->p->exec_tail->inst[1] |= 1;
2567
2568 FREE(bra_list);
2569 }
2570
2571 static boolean
2572 nv50_program_tx(struct nv50_program *p)
2573 {
2574 struct tgsi_parse_context parse;
2575 struct nv50_pc *pc;
2576 boolean ret;
2577
2578 pc = CALLOC_STRUCT(nv50_pc);
2579 if (!pc)
2580 return FALSE;
2581
2582 ret = ctor_nv50_pc(pc, p);
2583 if (ret == FALSE)
2584 goto out_cleanup;
2585
2586 ret = nv50_program_tx_prep(pc);
2587 if (ret == FALSE)
2588 goto out_cleanup;
2589
2590 tgsi_parse_init(&parse, pc->p->pipe.tokens);
2591 while (!tgsi_parse_end_of_tokens(&parse)) {
2592 const union tgsi_full_token *tok = &parse.FullToken;
2593
2594 /* don't allow half insn/immd on first and last instruction */
2595 pc->allow32 = TRUE;
2596 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr)
2597 pc->allow32 = FALSE;
2598
2599 tgsi_parse_token(&parse);
2600
2601 switch (tok->Token.Type) {
2602 case TGSI_TOKEN_TYPE_INSTRUCTION:
2603 ++pc->insn_cur;
2604 ret = nv50_tgsi_insn(pc, tok);
2605 if (ret == FALSE)
2606 goto out_err;
2607 break;
2608 default:
2609 break;
2610 }
2611 }
2612
2613 if (pc->p->type == PIPE_SHADER_FRAGMENT)
2614 nv50_fp_move_results(pc);
2615
2616 nv50_program_fixup_insns(pc);
2617
2618 p->param_nr = pc->param_nr * 4;
2619 p->immd_nr = pc->immd_nr * 4;
2620 p->immd = pc->immd_buf;
2621
2622 out_err:
2623 tgsi_parse_free(&parse);
2624
2625 out_cleanup:
2626 free_nv50_pc(pc);
2627 return ret;
2628 }
2629
2630 static void
2631 nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p)
2632 {
2633 if (nv50_program_tx(p) == FALSE)
2634 assert(0);
2635 p->translated = TRUE;
2636 }
2637
2638 static void
2639 nv50_program_upload_data(struct nv50_context *nv50, float *map,
2640 unsigned start, unsigned count, unsigned cbuf)
2641 {
2642 struct nouveau_channel *chan = nv50->screen->base.channel;
2643 struct nouveau_grobj *tesla = nv50->screen->tesla;
2644
2645 while (count) {
2646 unsigned nr = count > 2047 ? 2047 : count;
2647
2648 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
2649 OUT_RING (chan, (cbuf << 0) | (start << 8));
2650 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
2651 OUT_RINGp (chan, map, nr);
2652
2653 map += nr;
2654 start += nr;
2655 count -= nr;
2656 }
2657 }
2658
2659 static void
2660 nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p)
2661 {
2662 struct pipe_screen *pscreen = nv50->pipe.screen;
2663
2664 if (!p->data[0] && p->immd_nr) {
2665 struct nouveau_resource *heap = nv50->screen->immd_heap[0];
2666
2667 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) {
2668 while (heap->next && heap->size < p->immd_nr) {
2669 struct nv50_program *evict = heap->next->priv;
2670 nouveau_resource_free(&evict->data[0]);
2671 }
2672
2673 if (nouveau_resource_alloc(heap, p->immd_nr, p,
2674 &p->data[0]))
2675 assert(0);
2676 }
2677
2678 /* immediates only need to be uploaded again when freed */
2679 nv50_program_upload_data(nv50, p->immd, p->data[0]->start,
2680 p->immd_nr, NV50_CB_PMISC);
2681 }
2682
2683 assert(p->param_nr <= 128);
2684
2685 if (p->param_nr) {
2686 unsigned cb;
2687 float *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type],
2688 PIPE_BUFFER_USAGE_CPU_READ);
2689
2690 if (p->type == PIPE_SHADER_VERTEX)
2691 cb = NV50_CB_PVP;
2692 else
2693 cb = NV50_CB_PFP;
2694
2695 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb);
2696 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]);
2697 }
2698 }
2699
2700 static void
2701 nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p)
2702 {
2703 struct nouveau_channel *chan = nv50->screen->base.channel;
2704 struct nouveau_grobj *tesla = nv50->screen->tesla;
2705 struct nv50_program_exec *e;
2706 struct nouveau_stateobj *so;
2707 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_WR;
2708 unsigned start, count, *up, *ptr;
2709 boolean upload = FALSE;
2710
2711 if (!p->bo) {
2712 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100,
2713 p->exec_size * 4, &p->bo);
2714 upload = TRUE;
2715 }
2716
2717 if (p->data[0] && p->data[0]->start != p->data_start[0])
2718 upload = TRUE;
2719
2720 if (!upload)
2721 return;
2722
2723 for (e = p->exec_head; e; e = e->next) {
2724 unsigned ei, ci, bs;
2725
2726 if (e->param.index < 0)
2727 continue;
2728
2729 if (e->param.mask == 0) {
2730 assert(!(e->param.index & 1));
2731 /* seem to be 8 byte steps */
2732 ei = (e->param.index >> 1) + 0 /* START_ID */;
2733
2734 e->inst[0] &= 0xf0000fff;
2735 e->inst[0] |= ei << 12;
2736 continue;
2737 }
2738
2739 bs = (e->inst[1] >> 22) & 0x07;
2740 assert(bs < 2);
2741 ei = e->param.shift >> 5;
2742 ci = e->param.index;
2743 if (bs == 0)
2744 ci += p->data[bs]->start;
2745
2746 e->inst[ei] &= ~e->param.mask;
2747 e->inst[ei] |= (ci << e->param.shift);
2748 }
2749
2750 if (p->data[0])
2751 p->data_start[0] = p->data[0]->start;
2752
2753 #ifdef NV50_PROGRAM_DUMP
2754 NOUVEAU_ERR("-------\n");
2755 for (e = p->exec_head; e; e = e->next) {
2756 NOUVEAU_ERR("0x%08x\n", e->inst[0]);
2757 if (is_long(e))
2758 NOUVEAU_ERR("0x%08x\n", e->inst[1]);
2759 }
2760 #endif
2761
2762 up = ptr = MALLOC(p->exec_size * 4);
2763 for (e = p->exec_head; e; e = e->next) {
2764 *(ptr++) = e->inst[0];
2765 if (is_long(e))
2766 *(ptr++) = e->inst[1];
2767 }
2768
2769 so = so_new(4,2);
2770 so_method(so, nv50->screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
2771 so_reloc (so, p->bo, 0, flags | NOUVEAU_BO_HIGH, 0, 0);
2772 so_reloc (so, p->bo, 0, flags | NOUVEAU_BO_LOW, 0, 0);
2773 so_data (so, (NV50_CB_PUPLOAD << 16) | 0x0800); //(p->exec_size * 4));
2774
2775 start = 0; count = p->exec_size;
2776 while (count) {
2777 struct nouveau_channel *chan = nv50->screen->base.channel;
2778 unsigned nr;
2779
2780 so_emit(chan, so);
2781
2782 nr = MIN2(count, 2047);
2783 nr = MIN2(chan->pushbuf->remaining, nr);
2784 if (chan->pushbuf->remaining < (nr + 3)) {
2785 FIRE_RING(chan);
2786 continue;
2787 }
2788
2789 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1);
2790 OUT_RING (chan, (start << 8) | NV50_CB_PUPLOAD);
2791 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr);
2792 OUT_RINGp (chan, up + start, nr);
2793
2794 start += nr;
2795 count -= nr;
2796 }
2797
2798 FREE(up);
2799 so_ref(NULL, &so);
2800 }
2801
2802 void
2803 nv50_vertprog_validate(struct nv50_context *nv50)
2804 {
2805 struct nouveau_grobj *tesla = nv50->screen->tesla;
2806 struct nv50_program *p = nv50->vertprog;
2807 struct nouveau_stateobj *so;
2808
2809 if (!p->translated) {
2810 nv50_program_validate(nv50, p);
2811 if (!p->translated)
2812 assert(0);
2813 }
2814
2815 nv50_program_validate_data(nv50, p);
2816 nv50_program_validate_code(nv50, p);
2817
2818 so = so_new(13, 2);
2819 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2);
2820 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
2821 NOUVEAU_BO_HIGH, 0, 0);
2822 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
2823 NOUVEAU_BO_LOW, 0, 0);
2824 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2);
2825 so_data (so, p->cfg.attr[0]);
2826 so_data (so, p->cfg.attr[1]);
2827 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
2828 so_data (so, p->cfg.high_result);
2829 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2);
2830 so_data (so, p->cfg.high_result); //8);
2831 so_data (so, p->cfg.high_temp);
2832 so_method(so, tesla, NV50TCL_VP_START_ID, 1);
2833 so_data (so, 0); /* program start offset */
2834 so_ref(so, &nv50->state.vertprog);
2835 so_ref(NULL, &so);
2836 }
2837
2838 void
2839 nv50_fragprog_validate(struct nv50_context *nv50)
2840 {
2841 struct nouveau_grobj *tesla = nv50->screen->tesla;
2842 struct nv50_program *p = nv50->fragprog;
2843 struct nouveau_stateobj *so;
2844
2845 if (!p->translated) {
2846 nv50_program_validate(nv50, p);
2847 if (!p->translated)
2848 assert(0);
2849 }
2850
2851 nv50_program_validate_data(nv50, p);
2852 nv50_program_validate_code(nv50, p);
2853
2854 so = so_new(64, 2);
2855 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2);
2856 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
2857 NOUVEAU_BO_HIGH, 0, 0);
2858 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD |
2859 NOUVEAU_BO_LOW, 0, 0);
2860 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1);
2861 so_data (so, p->cfg.high_temp);
2862 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1);
2863 so_data (so, p->cfg.high_result);
2864 so_method(so, tesla, NV50TCL_FP_CTRL_UNK19A8, 1);
2865 so_data (so, p->cfg.regs[2]);
2866 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1);
2867 so_data (so, p->cfg.regs[3]);
2868 so_method(so, tesla, NV50TCL_FP_START_ID, 1);
2869 so_data (so, 0); /* program start offset */
2870 so_ref(so, &nv50->state.fragprog);
2871 so_ref(NULL, &so);
2872 }
2873
2874 static void
2875 nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base)
2876 {
2877 struct nv50_program *fp = nv50->fragprog;
2878 struct nv50_program *vp = nv50->vertprog;
2879 unsigned i, c, m = base;
2880
2881 /* XXX: This can't work correctly in all cases yet, we either
2882 * have to create TGSI_SEMANTIC_PNTC or sprite_coord_mode has
2883 * to be per FP input instead of per VP output
2884 */
2885 memset(pntc, 0, 8 * sizeof(uint32_t));
2886
2887 for (i = 0; i < fp->cfg.io_nr; i++) {
2888 uint8_t sn, si;
2889 uint8_t j = fp->cfg.io[i].id_vp, k = fp->cfg.io[i].id_fp;
2890 unsigned n = popcnt4(fp->cfg.io[i].mask);
2891
2892 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) {
2893 m += n;
2894 continue;
2895 }
2896
2897 sn = vp->info.input_semantic_name[j];
2898 si = vp->info.input_semantic_index[j];
2899
2900 if (j < fp->cfg.io_nr && sn == TGSI_SEMANTIC_GENERIC) {
2901 ubyte mode =
2902 nv50->rasterizer->pipe.sprite_coord_mode[si];
2903
2904 if (mode == PIPE_SPRITE_COORD_NONE) {
2905 m += n;
2906 continue;
2907 }
2908 }
2909
2910 /* this is either PointCoord or replaced by sprite coords */
2911 for (c = 0; c < 4; c++) {
2912 if (!(fp->cfg.io[i].mask & (1 << c)))
2913 continue;
2914 pntc[m / 8] |= (c + 1) << ((m % 8) * 4);
2915 ++m;
2916 }
2917 }
2918 }
2919
2920 static int
2921 nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4],
2922 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo)
2923 {
2924 int c;
2925 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw;
2926 uint8_t *map = (uint8_t *)p_map;
2927
2928 for (c = 0; c < 4; ++c) {
2929 if (mf & 1) {
2930 if (fpi->linear == TRUE)
2931 lin[mid / 32] |= 1 << (mid % 32);
2932 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40);
2933 }
2934
2935 oid += mv & 1;
2936 mf >>= 1;
2937 mv >>= 1;
2938 }
2939
2940 return mid;
2941 }
2942
2943 void
2944 nv50_linkage_validate(struct nv50_context *nv50)
2945 {
2946 struct nouveau_grobj *tesla = nv50->screen->tesla;
2947 struct nv50_program *vp = nv50->vertprog;
2948 struct nv50_program *fp = nv50->fragprog;
2949 struct nouveau_stateobj *so;
2950 struct nv50_sreg4 dummy, *vpo;
2951 int i, n, c, m = 0;
2952 uint32_t map[16], lin[4], reg[5], pcrd[8];
2953
2954 memset(map, 0, sizeof(map));
2955 memset(lin, 0, sizeof(lin));
2956
2957 reg[1] = 0x00000004; /* low and high clip distance map ids */
2958 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */
2959 reg[3] = 0x00000000; /* point size map id & enable */
2960 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */
2961 reg[4] = fp->cfg.regs[1]; /* interpolant info */
2962
2963 dummy.linear = FALSE;
2964 dummy.mask = 0xf; /* map all components of HPOS */
2965 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]);
2966
2967 dummy.mask = 0x0;
2968
2969 if (vp->cfg.clpd < 0x40) {
2970 for (c = 0; c < vp->cfg.clpd_nr; ++c)
2971 map[m++] = vp->cfg.clpd + c;
2972 reg[1] = (m << 8);
2973 }
2974
2975 reg[0] |= m << 8; /* adjust BFC0 id */
2976
2977 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */
2978 if (nv50->rasterizer->pipe.light_twoside) {
2979 vpo = &vp->cfg.two_side[0];
2980
2981 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]);
2982 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]);
2983 }
2984
2985 reg[0] += m - 4; /* adjust FFC0 id */
2986 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */
2987
2988 i = 0;
2989 if (fp->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION)
2990 i = 1;
2991 for (; i < fp->cfg.io_nr; i++) {
2992 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id_fp];
2993 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id_fp];
2994
2995 n = fp->cfg.io[i].id_vp;
2996 if (n >= vp->cfg.io_nr ||
2997 vp->info.output_semantic_name[n] != sn ||
2998 vp->info.output_semantic_index[n] != si)
2999 vpo = &dummy;
3000 else
3001 vpo = &vp->cfg.io[n];
3002
3003 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo);
3004 }
3005
3006 if (nv50->rasterizer->pipe.point_size_per_vertex) {
3007 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8);
3008 reg[3] = (m++ << 4) | 1;
3009 }
3010
3011 /* now fill the stateobj */
3012 so = so_new(64, 0);
3013
3014 n = (m + 3) / 4;
3015 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1);
3016 so_data (so, m);
3017 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n);
3018 so_datap (so, map, n);
3019
3020 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4);
3021 so_datap (so, reg, 4);
3022
3023 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1);
3024 so_data (so, reg[4]);
3025
3026 so_method(so, tesla, 0x1540, 4);
3027 so_datap (so, lin, 4);
3028
3029 if (nv50->rasterizer->pipe.point_sprite) {
3030 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff);
3031
3032 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8);
3033 so_datap (so, pcrd, 8);
3034 }
3035
3036 so_ref(so, &nv50->state.programs);
3037 so_ref(NULL, &so);
3038 }
3039
3040 void
3041 nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p)
3042 {
3043 while (p->exec_head) {
3044 struct nv50_program_exec *e = p->exec_head;
3045
3046 p->exec_head = e->next;
3047 FREE(e);
3048 }
3049 p->exec_tail = NULL;
3050 p->exec_size = 0;
3051
3052 nouveau_bo_ref(NULL, &p->bo);
3053
3054 nouveau_resource_free(&p->data[0]);
3055
3056 p->translated = 0;
3057 }