src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 extern int nouveau_device_get_param(struct nouveau_device *dev,
  37                                     uint64_t param, uint64_t *value);
  38
  39 static boolean
  40 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  47       return FALSE;
  48    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  49       return FALSE;
  50
  51    if (!util_format_is_supported(format, bindings))
  52       return FALSE;
  53
  54    switch (format) {
  55    case PIPE_FORMAT_Z16_UNORM:
  56       if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D)
  57          return FALSE;
  58       break;
  59    case PIPE_FORMAT_R8G8B8A8_UNORM:
  60    case PIPE_FORMAT_R8G8B8X8_UNORM:
  61       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  62       if (bindings & PIPE_BIND_RENDER_TARGET)
  63          return FALSE;
  64    default:
  65       break;
  66    }
  67
  68    /* transfers & shared are always supported */
  69    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  70                  PIPE_BIND_TRANSFER_WRITE |
  71                  PIPE_BIND_SHARED);
  72
  73    return (nv50_format_table[format].usage & bindings) == bindings;
  74 }
  75
  76 static int
  77 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  78 {
  79    switch (param) {
  80    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  81       return 64;
  82    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  83       return 14;
  84    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  85       return 12;
  86    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  87       return 14;
  88    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* shader support missing */
  89       return 0;
  90    case PIPE_CAP_MIN_TEXEL_OFFSET:
  91       return 0 /* -8, TODO */;
  92    case PIPE_CAP_MAX_TEXEL_OFFSET:
  93       return 0 /* +7, TODO */;
  94    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  95    case PIPE_CAP_TEXTURE_SWIZZLE:
  96    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  97    case PIPE_CAP_NPOT_TEXTURES:
  98    case PIPE_CAP_ANISOTROPIC_FILTER:
  99    case PIPE_CAP_SCALED_RESOLVE:
 100       return 1;
 101    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 102       return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
 103    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 104       return 0;
 105    case PIPE_CAP_TWO_SIDED_STENCIL:
 106    case PIPE_CAP_DEPTH_CLAMP:
 107    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 108    case PIPE_CAP_POINT_SPRITE:
 109       return 1;
 110    case PIPE_CAP_SM3:
 111       return 1;
 112    case PIPE_CAP_MAX_RENDER_TARGETS:
 113       return 8;
 114    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 115       return 1;
 116    case PIPE_CAP_TIMER_QUERY:
 117    case PIPE_CAP_OCCLUSION_QUERY:
 118       return 1;
 119    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 120       return 0;
 121    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 122    case PIPE_CAP_INDEP_BLEND_ENABLE:
 123       return 1;
 124    case PIPE_CAP_INDEP_BLEND_FUNC:
 125       return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D;
 126    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 127    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 128       return 1;
 129    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 130    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 131       return 0;
 132    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 133       return 0;
 134    case PIPE_CAP_PRIMITIVE_RESTART:
 135    case PIPE_CAP_TGSI_INSTANCEID:
 136    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 137    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 138    case PIPE_CAP_CONDITIONAL_RENDER:
 139    case PIPE_CAP_TEXTURE_BARRIER:
 140       return 1;
 141    default:
 142       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 143       return 0;
 144    }
 145 }
 146
 147 static int
 148 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 149                              enum pipe_shader_cap param)
 150 {
 151    switch (shader) {
 152    case PIPE_SHADER_VERTEX:
 153    case PIPE_SHADER_GEOMETRY:
 154    case PIPE_SHADER_FRAGMENT:
 155       break;
 156    default:
 157       return 0;
 158    }
 159
 160    switch (param) {
 161    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 162    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 163    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 164    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 165       return 16384;
 166    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 167       return 4;
 168    case PIPE_SHADER_CAP_MAX_INPUTS:
 169       if (shader == PIPE_SHADER_VERTEX)
 170          return 32;
 171       return 0x300 / 16;
 172    case PIPE_SHADER_CAP_MAX_CONSTS:
 173       return 65536 / 16;
 174    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 175       return 14;
 176    case PIPE_SHADER_CAP_MAX_ADDRS:
 177       return 1;
 178    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 179    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 180       return shader != PIPE_SHADER_FRAGMENT;
 181    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 182    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 183       return 1;
 184    case PIPE_SHADER_CAP_MAX_PREDS:
 185       return 0;
 186    case PIPE_SHADER_CAP_MAX_TEMPS:
 187       return NV50_CAP_MAX_PROGRAM_TEMPS;
 188    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 189       return 1;
 190    case PIPE_SHADER_CAP_SUBROUTINES:
 191       return 0; /* please inline, or provide function declarations */
 192    case PIPE_SHADER_CAP_INTEGERS:
 193       return 0;
 194    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 195       return 32;
 196    default:
 197       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 198       return 0;
 199    }
 200 }
 201
 202 static float
 203 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 204 {
 205    switch (param) {
 206    case PIPE_CAPF_MAX_LINE_WIDTH:
 207    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 208       return 10.0f;
 209    case PIPE_CAPF_MAX_POINT_WIDTH:
 210    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 211       return 64.0f;
 212    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 213       return 16.0f;
 214    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 215       return 4.0f;
 216    default:
 217       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 218       return 0.0f;
 219    }
 220 }
 221
 222 static void
 223 nv50_screen_destroy(struct pipe_screen *pscreen)
 224 {
 225    struct nv50_screen *screen = nv50_screen(pscreen);
 226
 227    if (screen->base.fence.current) {
 228       nouveau_fence_wait(screen->base.fence.current);
 229       nouveau_fence_ref (NULL, &screen->base.fence.current);
 230    }
 231    if (screen->base.channel)
 232       screen->base.channel->user_private = NULL;
 233    if (screen->blitctx)
 234       FREE(screen->blitctx);
 235
 236    nouveau_bo_ref(NULL, &screen->code);
 237    nouveau_bo_ref(NULL, &screen->tls_bo);
 238    nouveau_bo_ref(NULL, &screen->stack_bo);
 239    nouveau_bo_ref(NULL, &screen->txc);
 240    nouveau_bo_ref(NULL, &screen->uniforms);
 241    nouveau_bo_ref(NULL, &screen->fence.bo);
 242
 243    nouveau_resource_destroy(&screen->vp_code_heap);
 244    nouveau_resource_destroy(&screen->gp_code_heap);
 245    nouveau_resource_destroy(&screen->fp_code_heap);
 246
 247    if (screen->tic.entries)
 248       FREE(screen->tic.entries);
 249
 250    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 251
 252    nouveau_grobj_free(&screen->tesla);
 253    nouveau_grobj_free(&screen->eng2d);
 254    nouveau_grobj_free(&screen->m2mf);
 255
 256    nouveau_notifier_free(&screen->sync);
 257
 258    nouveau_screen_fini(&screen->base);
 259
 260    FREE(screen);
 261 }
 262
 263 static void
 264 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 265 {
 266    struct nv50_screen *screen = nv50_screen(pscreen);
 267    struct nouveau_channel *chan = screen->base.channel;
 268
 269    MARK_RING (chan, 5, 2);
 270
 271    /* we need to do it after possible flush in MARK_RING */
 272    *sequence = ++screen->base.fence.sequence;
 273
 274    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 275    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 276    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 277    OUT_RING  (chan, *sequence);
 278    OUT_RING  (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 279                     NV50_3D_QUERY_GET_UNK4 |
 280                     NV50_3D_QUERY_GET_UNIT_CROP |
 281                     NV50_3D_QUERY_GET_TYPE_QUERY |
 282                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 283                     NV50_3D_QUERY_GET_SHORT);
 284 }
 285
 286 static u32
 287 nv50_screen_fence_update(struct pipe_screen *pscreen)
 288 {
 289    struct nv50_screen *screen = nv50_screen(pscreen);
 290    return screen->fence.map[0];
 291 }
 292
 293 #define FAIL_SCREEN_INIT(str, err)                    \
 294    do {                                               \
 295       NOUVEAU_ERR(str, err);                          \
 296       nv50_screen_destroy(pscreen);                   \
 297       return NULL;                                    \
 298    } while(0)
 299
 300 struct pipe_screen *
 301 nv50_screen_create(struct nouveau_device *dev)
 302 {
 303    struct nv50_screen *screen;
 304    struct nouveau_channel *chan;
 305    struct pipe_screen *pscreen;
 306    uint64_t value;
 307    uint32_t tesla_class;
 308    unsigned stack_size, max_warps, tls_space;
 309    int ret;
 310    unsigned i, base;
 311
 312    screen = CALLOC_STRUCT(nv50_screen);
 313    if (!screen)
 314       return NULL;
 315    pscreen = &screen->base.base;
 316
 317    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 318
 319    ret = nouveau_screen_init(&screen->base, dev);
 320    if (ret)
 321       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 322
 323    chan = screen->base.channel;
 324    chan->user_private = screen;
 325
 326    pscreen->destroy = nv50_screen_destroy;
 327    pscreen->context_create = nv50_create;
 328    pscreen->is_format_supported = nv50_screen_is_format_supported;
 329    pscreen->get_param = nv50_screen_get_param;
 330    pscreen->get_shader_param = nv50_screen_get_shader_param;
 331    pscreen->get_paramf = nv50_screen_get_paramf;
 332
 333    nv50_screen_init_resource_functions(pscreen);
 334
 335    nouveau_screen_init_vdec(&screen->base);
 336
 337    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 338                         &screen->fence.bo);
 339    if (ret)
 340       goto fail;
 341    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 342    screen->fence.map = screen->fence.bo->map;
 343    nouveau_bo_unmap(screen->fence.bo);
 344    screen->base.fence.emit = nv50_screen_fence_emit;
 345    screen->base.fence.update = nv50_screen_fence_update;
 346
 347    ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 348    if (ret)
 349       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 350
 351    ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
 352    if (ret)
 353       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 354
 355    BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
 356    BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
 357    OUT_RING  (chan, screen->sync->handle);
 358    OUT_RING  (chan, chan->vram->handle);
 359    OUT_RING  (chan, chan->vram->handle);
 360
 361    ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 362    if (ret)
 363       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 364
 365    BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
 366    BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
 367    OUT_RING  (chan, screen->sync->handle);
 368    OUT_RING  (chan, chan->vram->handle);
 369    OUT_RING  (chan, chan->vram->handle);
 370    OUT_RING  (chan, chan->vram->handle);
 371    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 372    OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 373    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 374    OUT_RING  (chan, 0);
 375    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 376    OUT_RING  (chan, 0);
 377    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 378    OUT_RING  (chan, 1);
 379
 380    switch (dev->chipset & 0xf0) {
 381    case 0x50:
 382       tesla_class = NV50_3D;
 383       break;
 384    case 0x80:
 385    case 0x90:
 386       tesla_class = NV84_3D;
 387       break;
 388    case 0xa0:
 389       switch (dev->chipset) {
 390       case 0xa0:
 391       case 0xaa:
 392       case 0xac:
 393          tesla_class = NVA0_3D;
 394          break;
 395       case 0xaf:
 396          tesla_class = NVAF_3D;
 397          break;
 398       default:
 399          tesla_class = NVA3_3D;
 400          break;
 401       }
 402       break;
 403    default:
 404       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 405       break;
 406    }
 407
 408    ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
 409    if (ret)
 410       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 411
 412    BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
 413
 414    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 415    OUT_RING  (chan, NV50_3D_COND_MODE_ALWAYS);
 416
 417    BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
 418    OUT_RING  (chan, screen->sync->handle);
 419    BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
 420    for (i = 0; i < 11; ++i)
 421       OUT_RING(chan, chan->vram->handle);
 422    BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 423    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 424       OUT_RING(chan, chan->vram->handle);
 425
 426    BEGIN_RING(chan, RING_3D(REG_MODE), 1);
 427    OUT_RING  (chan, NV50_3D_REG_MODE_STRIPED);
 428    BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
 429    OUT_RING  (chan, 0xf);
 430
 431    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 432    OUT_RING  (chan, 1);
 433
 434    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 435    OUT_RING  (chan, 0);
 436    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 437    OUT_RING  (chan, 0);
 438    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 439    OUT_RING  (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
 440    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 441    OUT_RING  (chan, 0);
 442    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 443    OUT_RING  (chan, 0);
 444    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 445    OUT_RING  (chan, 1);
 446
 447    if (tesla_class >= NVA0_3D) {
 448       BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1);
 449       OUT_RING  (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 450    }
 451
 452    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 453    OUT_RING  (chan, 0);
 454    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 455    OUT_RING  (chan, 0);
 456    OUT_RING  (chan, 0);
 457    BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 458    OUT_RING  (chan, 0x3f);
 459
 460    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 461                         3 << NV50_CODE_BO_SIZE_LOG2, &screen->code);
 462    if (ret)
 463       goto fail;
 464
 465    nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 466    nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 467    nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 468
 469    base = 1 << NV50_CODE_BO_SIZE_LOG2;
 470
 471    BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
 472    OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 473    OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 474
 475    BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
 476    OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 477    OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 478
 479    BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
 480    OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 481    OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 482
 483    nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 484
 485    max_warps  = util_bitcount(value & 0xffff);
 486    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 487
 488    stack_size = max_warps * 64 * 8;
 489
 490    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
 491                         &screen->stack_bo);
 492    if (ret)
 493       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 494
 495    BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
 496    OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 497    OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 498    OUT_RING  (chan, 4);
 499
 500    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 501
 502    screen->tls_size = tls_space * max_warps * 32;
 503
 504    if (nouveau_mesa_debug)
 505       debug_printf("max_warps = %i, tls_size = %"PRIu64" KiB\n",
 506                      max_warps, screen->tls_size >> 10);
 507
 508    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
 509                         &screen->tls_bo);
 510    if (ret)
 511       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 512
 513    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
 514    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 515    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 516    OUT_RING  (chan, util_logbase2(tls_space / 8));
 517
 518    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
 519                         &screen->uniforms);
 520    if (ret)
 521       goto fail;
 522
 523    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 524    OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 525    OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 526    OUT_RING  (chan, (NV50_CB_PVP << 16) | 0x0000);
 527
 528    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 529    OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 530    OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 531    OUT_RING  (chan, (NV50_CB_PGP << 16) | 0x0000);
 532
 533    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 534    OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 535    OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 536    OUT_RING  (chan, (NV50_CB_PFP << 16) | 0x0000);
 537
 538    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 539    OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 540    OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 541    OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 542
 543    BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
 544    OUT_RING  (chan, (NV50_CB_PVP << 12) | 0x001);
 545    OUT_RING  (chan, (NV50_CB_PGP << 12) | 0x021);
 546    OUT_RING  (chan, (NV50_CB_PFP << 12) | 0x031);
 547    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf01);
 548    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf21);
 549    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf31);
 550
 551    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
 552                         &screen->txc);
 553    if (ret)
 554       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 555
 556    /* max TIC (bits 4:8) & TSC bindings, per program type */
 557    for (i = 0; i < 3; ++i) {
 558       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 559       OUT_RING  (chan, 0x54);
 560    }
 561
 562    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 563    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 564    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 565    OUT_RING  (chan, NV50_TIC_MAX_ENTRIES - 1);
 566
 567    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 568    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 569    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 570    OUT_RING  (chan, NV50_TSC_MAX_ENTRIES - 1);
 571
 572    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 573    OUT_RING  (chan, 0);
 574
 575    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 576    OUT_RING  (chan, 0);
 577    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 578    OUT_RING  (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 579    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 580    for (i = 0; i < 8 * 2; ++i)
 581       OUT_RING(chan, 0);
 582    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 583    OUT_RING  (chan, 0);
 584
 585    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 586    OUT_RING  (chan, 1);
 587    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 588    OUT_RINGf (chan, 0.0f);
 589    OUT_RINGf (chan, 1.0f);
 590
 591    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 592 #ifdef NV50_SCISSORS_CLIPPING
 593    OUT_RING  (chan, 0x0000);
 594 #else
 595    OUT_RING  (chan, 0x1080);
 596 #endif
 597
 598    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 599    OUT_RING  (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 600
 601    /* We use scissors instead of exact view volume clipping,
 602     * so they're always enabled.
 603     */
 604    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 605    OUT_RING  (chan, 1);
 606    OUT_RING  (chan, 8192 << 16);
 607    OUT_RING  (chan, 8192 << 16);
 608
 609    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 610    OUT_RING  (chan, 1);
 611    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 612    OUT_RING  (chan, NV50_3D_POINT_RASTER_RULES_OGL);
 613    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 614    OUT_RING  (chan, 0x11111111);
 615    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 616    OUT_RING  (chan, 1);
 617
 618    FIRE_RING (chan);
 619
 620    screen->tic.entries = CALLOC(4096, sizeof(void *));
 621    screen->tsc.entries = screen->tic.entries + 2048;
 622
 623    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 624
 625    if (!nv50_blitctx_create(screen))
 626       goto fail;
 627
 628    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 629
 630    return pscreen;
 631
 632 fail:
 633    nv50_screen_destroy(pscreen);
 634    return NULL;
 635 }
 636
 637 void
 638 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
 639 {
 640    struct nouveau_channel *chan = screen->base.channel;
 641
 642    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 643
 644    MARK_RING(chan, 0, 5);
 645    nouveau_bo_validate(chan, screen->code, flags);
 646    nouveau_bo_validate(chan, screen->uniforms, flags);
 647    nouveau_bo_validate(chan, screen->txc, flags);
 648    nouveau_bo_validate(chan, screen->tls_bo, flags);
 649    nouveau_bo_validate(chan, screen->stack_bo, flags);
 650 }
 651
 652 int
 653 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 654 {
 655    int i = screen->tic.next;
 656
 657    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 658       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 659
 660    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 661
 662    if (screen->tic.entries[i])
 663       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 664
 665    screen->tic.entries[i] = entry;
 666    return i;
 667 }
 668
 669 int
 670 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 671 {
 672    int i = screen->tsc.next;
 673
 674    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 675       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 676
 677    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 678
 679    if (screen->tsc.entries[i])
 680       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 681
 682    screen->tsc.entries[i] = entry;
 683    return i;
 684 }