src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nouveau_vp3_video.h"
  31
  32 #include "nouveau/nv_object.xml.h"
  33 #include <errno.h>
  34
  35 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  36 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  37 #endif
  38
  39 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  40 #define LOCAL_WARPS_ALLOC 32
  41 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  42 #define STACK_WARPS_ALLOC 32
  43
  44 #define THREADS_IN_WARP 32
  45
  46 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  47
  48 static boolean
  49 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  50                                 enum pipe_format format,
  51                                 enum pipe_texture_target target,
  52                                 unsigned sample_count,
  53                                 unsigned bindings)
  54 {
  55    if (sample_count > 8)
  56       return FALSE;
  57    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  58       return FALSE;
  59    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  60       return FALSE;
  61
  62    if (!util_format_is_supported(format, bindings))
  63       return FALSE;
  64
  65    switch (format) {
  66    case PIPE_FORMAT_Z16_UNORM:
  67       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  68          return FALSE;
  69       break;
  70    default:
  71       break;
  72    }
  73
  74    /* transfers & shared are always supported */
  75    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  76                  PIPE_BIND_TRANSFER_WRITE |
  77                  PIPE_BIND_SHARED);
  78
  79    return (nv50_format_table[format].usage & bindings) == bindings;
  80 }
  81
  82 static int
  83 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  84 {
  85    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  86
  87    switch (param) {
  88    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  89       return 64;
  90    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  91       return 14;
  92    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  93       return 12;
  94    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  95       return 14;
  96    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  97       return 512;
  98    case PIPE_CAP_MIN_TEXEL_OFFSET:
  99       return -8;
 100    case PIPE_CAP_MAX_TEXEL_OFFSET:
 101       return 7;
 102    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 103    case PIPE_CAP_TEXTURE_SWIZZLE:
 104    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 105    case PIPE_CAP_NPOT_TEXTURES:
 106    case PIPE_CAP_ANISOTROPIC_FILTER:
 107    case PIPE_CAP_SCALED_RESOLVE:
 108    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 109       return 1;
 110    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 111       return 65536;
 112    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 113       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 114    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 115       return 0;
 116    case PIPE_CAP_CUBE_MAP_ARRAY:
 117       return 0;
 118       /*
 119       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 120       */
 121    case PIPE_CAP_TWO_SIDED_STENCIL:
 122    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 123    case PIPE_CAP_POINT_SPRITE:
 124       return 1;
 125    case PIPE_CAP_SM3:
 126       return 1;
 127    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 128       return 140;
 129    case PIPE_CAP_MAX_RENDER_TARGETS:
 130       return 8;
 131    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 132       return 1;
 133    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 134    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 135    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 136       return 1;
 137    case PIPE_CAP_QUERY_TIMESTAMP:
 138    case PIPE_CAP_QUERY_TIME_ELAPSED:
 139    case PIPE_CAP_OCCLUSION_QUERY:
 140       return 1;
 141    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 142       return 4;
 143    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 145       return 64;
 146    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 147       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 148    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 149    case PIPE_CAP_INDEP_BLEND_ENABLE:
 150       return 1;
 151    case PIPE_CAP_INDEP_BLEND_FUNC:
 152       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 153    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 154    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 155       return 1;
 156    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 157    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 158       return 0;
 159    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 160       return 0;
 161    case PIPE_CAP_PRIMITIVE_RESTART:
 162    case PIPE_CAP_TGSI_INSTANCEID:
 163    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 164    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 165    case PIPE_CAP_CONDITIONAL_RENDER:
 166    case PIPE_CAP_TEXTURE_BARRIER:
 167    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 168    case PIPE_CAP_START_INSTANCE:
 169       return 1;
 170    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 171       return 0; /* state trackers will know better */
 172    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 173    case PIPE_CAP_USER_INDEX_BUFFERS:
 174    case PIPE_CAP_USER_VERTEX_BUFFERS:
 175       return 1;
 176    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 177       return 256;
 178    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 179       return 1; /* 256 for binding as RT, but that's not possible in GL */
 180    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 181       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 182    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 183    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 184    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 185    case PIPE_CAP_TGSI_TEXCOORD:
 186    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 187       return 0;
 188    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 189       return 1;
 190    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 191       return 0;
 192    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 193       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 194    case PIPE_CAP_ENDIANNESS:
 195       return PIPE_ENDIAN_LITTLE;
 196    default:
 197       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 198       return 0;
 199    }
 200 }
 201
 202 static int
 203 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 204                              enum pipe_shader_cap param)
 205 {
 206    switch (shader) {
 207    case PIPE_SHADER_VERTEX:
 208    case PIPE_SHADER_GEOMETRY:
 209    case PIPE_SHADER_FRAGMENT:
 210       break;
 211    default:
 212       return 0;
 213    }
 214
 215    switch (param) {
 216    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 217    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 218    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 219    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 220       return 16384;
 221    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 222       return 4;
 223    case PIPE_SHADER_CAP_MAX_INPUTS:
 224       if (shader == PIPE_SHADER_VERTEX)
 225          return 32;
 226       return 0x300 / 16;
 227    case PIPE_SHADER_CAP_MAX_CONSTS:
 228       return 65536 / 16;
 229    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 230       return NV50_MAX_PIPE_CONSTBUFS;
 231    case PIPE_SHADER_CAP_MAX_ADDRS:
 232       return 1;
 233    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 234    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 235       return shader != PIPE_SHADER_FRAGMENT;
 236    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 237    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 238       return 1;
 239    case PIPE_SHADER_CAP_MAX_PREDS:
 240       return 0;
 241    case PIPE_SHADER_CAP_MAX_TEMPS:
 242       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 243    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 244       return 1;
 245    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 246       return 0;
 247    case PIPE_SHADER_CAP_SUBROUTINES:
 248       return 0; /* please inline, or provide function declarations */
 249    case PIPE_SHADER_CAP_INTEGERS:
 250       return 1;
 251    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 252       return 32;
 253    default:
 254       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 255       return 0;
 256    }
 257 }
 258
 259 static float
 260 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 261 {
 262    switch (param) {
 263    case PIPE_CAPF_MAX_LINE_WIDTH:
 264    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 265       return 10.0f;
 266    case PIPE_CAPF_MAX_POINT_WIDTH:
 267    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 268       return 64.0f;
 269    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 270       return 16.0f;
 271    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 272       return 4.0f;
 273    default:
 274       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 275       return 0.0f;
 276    }
 277 }
 278
 279 static void
 280 nv50_screen_destroy(struct pipe_screen *pscreen)
 281 {
 282    struct nv50_screen *screen = nv50_screen(pscreen);
 283
 284    if (screen->base.fence.current) {
 285       nouveau_fence_wait(screen->base.fence.current);
 286       nouveau_fence_ref (NULL, &screen->base.fence.current);
 287    }
 288    if (screen->base.pushbuf)
 289       screen->base.pushbuf->user_priv = NULL;
 290
 291    if (screen->blitter)
 292       nv50_blitter_destroy(screen);
 293
 294    nouveau_bo_ref(NULL, &screen->code);
 295    nouveau_bo_ref(NULL, &screen->tls_bo);
 296    nouveau_bo_ref(NULL, &screen->stack_bo);
 297    nouveau_bo_ref(NULL, &screen->txc);
 298    nouveau_bo_ref(NULL, &screen->uniforms);
 299    nouveau_bo_ref(NULL, &screen->fence.bo);
 300
 301    nouveau_heap_destroy(&screen->vp_code_heap);
 302    nouveau_heap_destroy(&screen->gp_code_heap);
 303    nouveau_heap_destroy(&screen->fp_code_heap);
 304
 305    FREE(screen->tic.entries);
 306
 307    nouveau_object_del(&screen->tesla);
 308    nouveau_object_del(&screen->eng2d);
 309    nouveau_object_del(&screen->m2mf);
 310    nouveau_object_del(&screen->sync);
 311
 312    nouveau_screen_fini(&screen->base);
 313
 314    FREE(screen);
 315 }
 316
 317 static void
 318 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 319 {
 320    struct nv50_screen *screen = nv50_screen(pscreen);
 321    struct nouveau_pushbuf *push = screen->base.pushbuf;
 322
 323    /* we need to do it after possible flush in MARK_RING */
 324    *sequence = ++screen->base.fence.sequence;
 325
 326    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 327    PUSH_DATAh(push, screen->fence.bo->offset);
 328    PUSH_DATA (push, screen->fence.bo->offset);
 329    PUSH_DATA (push, *sequence);
 330    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 331                     NV50_3D_QUERY_GET_UNK4 |
 332                     NV50_3D_QUERY_GET_UNIT_CROP |
 333                     NV50_3D_QUERY_GET_TYPE_QUERY |
 334                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 335                     NV50_3D_QUERY_GET_SHORT);
 336 }
 337
 338 static u32
 339 nv50_screen_fence_update(struct pipe_screen *pscreen)
 340 {
 341    return nv50_screen(pscreen)->fence.map[0];
 342 }
 343
 344 static void
 345 nv50_screen_init_hwctx(struct nv50_screen *screen)
 346 {
 347    struct nouveau_pushbuf *push = screen->base.pushbuf;
 348    struct nv04_fifo *fifo;
 349    unsigned i;
 350
 351    fifo = (struct nv04_fifo *)screen->base.channel->data;
 352
 353    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 354    PUSH_DATA (push, screen->m2mf->handle);
 355    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 356    PUSH_DATA (push, screen->sync->handle);
 357    PUSH_DATA (push, fifo->vram);
 358    PUSH_DATA (push, fifo->vram);
 359
 360    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 361    PUSH_DATA (push, screen->eng2d->handle);
 362    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 363    PUSH_DATA (push, screen->sync->handle);
 364    PUSH_DATA (push, fifo->vram);
 365    PUSH_DATA (push, fifo->vram);
 366    PUSH_DATA (push, fifo->vram);
 367    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 368    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 369    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 370    PUSH_DATA (push, 0);
 371    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 372    PUSH_DATA (push, 0);
 373    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 374    PUSH_DATA (push, 1);
 375
 376    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 377    PUSH_DATA (push, screen->tesla->handle);
 378
 379    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 380    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 381
 382    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 383    PUSH_DATA (push, screen->sync->handle);
 384    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 385    for (i = 0; i < 11; ++i)
 386       PUSH_DATA(push, fifo->vram);
 387    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 388    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 389       PUSH_DATA(push, fifo->vram);
 390
 391    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 392    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 393    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 394    PUSH_DATA (push, 0xf);
 395
 396    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 397       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 398       PUSH_DATA (push, 0x18);
 399    }
 400
 401    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 402    PUSH_DATA (push, 1);
 403
 404    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 405    PUSH_DATA (push, 0);
 406    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 407    PUSH_DATA (push, 0);
 408    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 409    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 410    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 411    PUSH_DATA (push, 0);
 412    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 413    PUSH_DATA (push, 0);
 414    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 415    PUSH_DATA (push, 1);
 416
 417    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 418       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 419       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 420    }
 421
 422    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 423    PUSH_DATA (push, 0);
 424    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 425    PUSH_DATA (push, 0);
 426    PUSH_DATA (push, 0);
 427    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 428    PUSH_DATA (push, 0x3f);
 429
 430    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 431    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 432    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 433
 434    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 435    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 436    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 437
 438    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 439    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 440    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 441
 442    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 443    PUSH_DATAh(push, screen->tls_bo->offset);
 444    PUSH_DATA (push, screen->tls_bo->offset);
 445    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 446
 447    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 448    PUSH_DATAh(push, screen->stack_bo->offset);
 449    PUSH_DATA (push, screen->stack_bo->offset);
 450    PUSH_DATA (push, 4);
 451
 452    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 453    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 454    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 455    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 456
 457    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 458    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 459    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 460    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 461
 462    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 463    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 464    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 465    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 466
 467    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 468    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 469    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 470    PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
 471
 472    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 473    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 474    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 475    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 476
 477    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 478    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 479    PUSH_DATA (push, ((1 << 9) << 6) | NV50_CB_AUX);
 480    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 481    PUSH_DATAf(push, 0.0f);
 482    PUSH_DATAf(push, 0.0f);
 483    PUSH_DATAf(push, 0.0f);
 484    PUSH_DATAf(push, 0.0f);
 485    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 486    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 487    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 488
 489    /* max TIC (bits 4:8) & TSC bindings, per program type */
 490    for (i = 0; i < 3; ++i) {
 491       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 492       PUSH_DATA (push, 0x54);
 493    }
 494
 495    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 496    PUSH_DATAh(push, screen->txc->offset);
 497    PUSH_DATA (push, screen->txc->offset);
 498    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 499
 500    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 501    PUSH_DATAh(push, screen->txc->offset + 65536);
 502    PUSH_DATA (push, screen->txc->offset + 65536);
 503    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 504
 505    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 506    PUSH_DATA (push, 0);
 507
 508    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 509    PUSH_DATA (push, 0);
 510    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 511    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 512    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 513    for (i = 0; i < 8 * 2; ++i)
 514       PUSH_DATA(push, 0);
 515    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 516    PUSH_DATA (push, 0);
 517
 518    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 519    PUSH_DATA (push, 1);
 520    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 521    PUSH_DATAf(push, 0.0f);
 522    PUSH_DATAf(push, 1.0f);
 523
 524    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 525 #ifdef NV50_SCISSORS_CLIPPING
 526    PUSH_DATA (push, 0x0000);
 527 #else
 528    PUSH_DATA (push, 0x1080);
 529 #endif
 530
 531    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 532    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 533
 534    /* We use scissors instead of exact view volume clipping,
 535     * so they're always enabled.
 536     */
 537    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 538    PUSH_DATA (push, 1);
 539    PUSH_DATA (push, 8192 << 16);
 540    PUSH_DATA (push, 8192 << 16);
 541
 542    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 543    PUSH_DATA (push, 1);
 544    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 545    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 546    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 547    PUSH_DATA (push, 0x11111111);
 548    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 549    PUSH_DATA (push, 1);
 550
 551    PUSH_KICK (push);
 552 }
 553
 554 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 555       uint64_t *tls_size)
 556 {
 557    struct nouveau_device *dev = screen->base.device;
 558    int ret;
 559
 560    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 561          ONE_TEMP_SIZE;
 562    if (nouveau_mesa_debug)
 563       debug_printf("allocating space for %u temps\n",
 564             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 565    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 566          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 567
 568    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 569                         *tls_size, NULL, &screen->tls_bo);
 570    if (ret) {
 571       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 572       return ret;
 573    }
 574
 575    return 0;
 576 }
 577
 578 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 579 {
 580    struct nouveau_pushbuf *push = screen->base.pushbuf;
 581    int ret;
 582    uint64_t tls_size;
 583
 584    if (tls_space < screen->cur_tls_space)
 585       return 0;
 586    if (tls_space > screen->max_tls_space) {
 587       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 588        * LOCAL_WARPS_NO_CLAMP) */
 589       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 590             (unsigned)(tls_space / ONE_TEMP_SIZE),
 591             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 592       return -ENOMEM;
 593    }
 594
 595    nouveau_bo_ref(NULL, &screen->tls_bo);
 596    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 597    if (ret)
 598       return ret;
 599
 600    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 601    PUSH_DATAh(push, screen->tls_bo->offset);
 602    PUSH_DATA (push, screen->tls_bo->offset);
 603    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 604
 605    return 1;
 606 }
 607
 608 struct pipe_screen *
 609 nv50_screen_create(struct nouveau_device *dev)
 610 {
 611    struct nv50_screen *screen;
 612    struct pipe_screen *pscreen;
 613    struct nouveau_object *chan;
 614    uint64_t value;
 615    uint32_t tesla_class;
 616    unsigned stack_size;
 617    int ret;
 618
 619    screen = CALLOC_STRUCT(nv50_screen);
 620    if (!screen)
 621       return NULL;
 622    pscreen = &screen->base.base;
 623
 624    ret = nouveau_screen_init(&screen->base, dev);
 625    if (ret) {
 626       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 627       goto fail;
 628    }
 629
 630    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 631     *  admit them to VRAM.
 632     */
 633    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 634       PIPE_BIND_VERTEX_BUFFER;
 635    screen->base.sysmem_bindings |=
 636       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 637
 638    screen->base.pushbuf->user_priv = screen;
 639    screen->base.pushbuf->rsvd_kick = 5;
 640
 641    chan = screen->base.channel;
 642
 643    pscreen->destroy = nv50_screen_destroy;
 644    pscreen->context_create = nv50_create;
 645    pscreen->is_format_supported = nv50_screen_is_format_supported;
 646    pscreen->get_param = nv50_screen_get_param;
 647    pscreen->get_shader_param = nv50_screen_get_shader_param;
 648    pscreen->get_paramf = nv50_screen_get_paramf;
 649
 650    nv50_screen_init_resource_functions(pscreen);
 651
 652    if (screen->base.device->chipset < 0x84 ||
 653        debug_get_bool_option("NOUVEAU_PMPEG", FALSE)) {
 654       /* PMPEG */
 655       nouveau_screen_init_vdec(&screen->base);
 656    } else if (screen->base.device->chipset < 0x98 ||
 657               screen->base.device->chipset == 0xa0) {
 658       /* VP2 */
 659       screen->base.base.get_video_param = nv84_screen_get_video_param;
 660       screen->base.base.is_video_format_supported = nv84_screen_video_supported;
 661    } else {
 662       /* VP3/4 */
 663       screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
 664       screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
 665    }
 666
 667    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 668                         NULL, &screen->fence.bo);
 669    if (ret) {
 670       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 671       goto fail;
 672    }
 673
 674    nouveau_bo_map(screen->fence.bo, 0, NULL);
 675    screen->fence.map = screen->fence.bo->map;
 676    screen->base.fence.emit = nv50_screen_fence_emit;
 677    screen->base.fence.update = nv50_screen_fence_update;
 678
 679    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 680                             &(struct nv04_notify){ .length = 32 },
 681                             sizeof(struct nv04_notify), &screen->sync);
 682    if (ret) {
 683       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 684       goto fail;
 685    }
 686
 687    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 688                             NULL, 0, &screen->m2mf);
 689    if (ret) {
 690       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 691       goto fail;
 692    }
 693
 694    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 695                             NULL, 0, &screen->eng2d);
 696    if (ret) {
 697       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 698       goto fail;
 699    }
 700
 701    switch (dev->chipset & 0xf0) {
 702    case 0x50:
 703       tesla_class = NV50_3D_CLASS;
 704       break;
 705    case 0x80:
 706    case 0x90:
 707       tesla_class = NV84_3D_CLASS;
 708       break;
 709    case 0xa0:
 710       switch (dev->chipset) {
 711       case 0xa0:
 712       case 0xaa:
 713       case 0xac:
 714          tesla_class = NVA0_3D_CLASS;
 715          break;
 716       case 0xaf:
 717          tesla_class = NVAF_3D_CLASS;
 718          break;
 719       default:
 720          tesla_class = NVA3_3D_CLASS;
 721          break;
 722       }
 723       break;
 724    default:
 725       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 726       goto fail;
 727    }
 728    screen->base.class_3d = tesla_class;
 729
 730    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 731                             NULL, 0, &screen->tesla);
 732    if (ret) {
 733       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 734       goto fail;
 735    }
 736
 737    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 738                         3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 739    if (ret) {
 740       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 741       goto fail;
 742    }
 743
 744    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 745    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 746    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 747
 748    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 749
 750    screen->TPs = util_bitcount(value & 0xffff);
 751    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 752
 753    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 754          STACK_WARPS_ALLOC * 64 * 8;
 755
 756    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 757                         &screen->stack_bo);
 758    if (ret) {
 759       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 760       goto fail;
 761    }
 762
 763    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 764          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 765          ONE_TEMP_SIZE;
 766    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 767    screen->max_tls_space /= 2; /* half of vram */
 768
 769    /* hw can address max 64 KiB */
 770    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 771
 772    uint64_t tls_size;
 773    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 774    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 775    if (ret)
 776       goto fail;
 777
 778    if (nouveau_mesa_debug)
 779       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 780             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 781
 782    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 783                         &screen->uniforms);
 784    if (ret) {
 785       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 786       goto fail;
 787    }
 788
 789    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 790                         &screen->txc);
 791    if (ret) {
 792       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 793       goto fail;
 794    }
 795
 796    screen->tic.entries = CALLOC(4096, sizeof(void *));
 797    screen->tsc.entries = screen->tic.entries + 2048;
 798
 799    if (!nv50_blitter_create(screen))
 800       goto fail;
 801
 802    nv50_screen_init_hwctx(screen);
 803
 804    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 805
 806    return pscreen;
 807
 808 fail:
 809    nv50_screen_destroy(pscreen);
 810    return NULL;
 811 }
 812
 813 int
 814 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 815 {
 816    int i = screen->tic.next;
 817
 818    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 819       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 820
 821    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 822
 823    if (screen->tic.entries[i])
 824       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 825
 826    screen->tic.entries[i] = entry;
 827    return i;
 828 }
 829
 830 int
 831 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 832 {
 833    int i = screen->tsc.next;
 834
 835    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 836       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 837
 838    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 839
 840    if (screen->tsc.entries[i])
 841       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 842
 843    screen->tsc.entries[i] = entry;
 844    return i;
 845 }