src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nv50_context.h"
  27 #include "nv50_screen.h"
  28 #include "nv50_resource.h"
  29
  30 #include "nouveau/nouveau_stateobj.h"
  31
  32 static boolean
  33 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  34                                 enum pipe_format format,
  35                                 enum pipe_texture_target target,
  36                                 unsigned sample_count,
  37                                 unsigned tex_usage, unsigned geom_flags)
  38 {
  39         if (sample_count > 1)
  40                 return FALSE;
  41
  42         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
  43                 switch (format) {
  44                 case PIPE_FORMAT_B8G8R8X8_UNORM:
  45                 case PIPE_FORMAT_B8G8R8A8_UNORM:
  46                 case PIPE_FORMAT_B5G6R5_UNORM:
  47                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  48                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  49                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  50                 case PIPE_FORMAT_R16G16_SNORM:
  51                 case PIPE_FORMAT_R16G16_UNORM:
  52                         return TRUE;
  53                 default:
  54                         break;
  55                 }
  56         } else
  57         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
  58                 switch (format) {
  59                 case PIPE_FORMAT_Z32_FLOAT:
  60                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
  61                 case PIPE_FORMAT_Z24X8_UNORM:
  62                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
  63                         return TRUE;
  64                 default:
  65                         break;
  66                 }
  67         } else {
  68                 if (tex_usage & PIPE_BIND_SAMPLER_VIEW) {
  69                         switch (format) {
  70                         case PIPE_FORMAT_DXT1_RGB:
  71                         case PIPE_FORMAT_DXT1_RGBA:
  72                         case PIPE_FORMAT_DXT3_RGBA:
  73                         case PIPE_FORMAT_DXT5_RGBA:
  74                                 return util_format_s3tc_enabled;
  75                         default:
  76                                 break;
  77                         }
  78                 }
  79                 switch (format) {
  80                 case PIPE_FORMAT_B8G8R8A8_UNORM:
  81                 case PIPE_FORMAT_B8G8R8X8_UNORM:
  82                 case PIPE_FORMAT_B8G8R8A8_SRGB:
  83                 case PIPE_FORMAT_B8G8R8X8_SRGB:
  84                 case PIPE_FORMAT_B5G5R5A1_UNORM:
  85                 case PIPE_FORMAT_B4G4R4A4_UNORM:
  86                 case PIPE_FORMAT_B5G6R5_UNORM:
  87                 case PIPE_FORMAT_L8_UNORM:
  88                 case PIPE_FORMAT_A8_UNORM:
  89                 case PIPE_FORMAT_I8_UNORM:
  90                 case PIPE_FORMAT_L8A8_UNORM:
  91                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
  92                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
  93                 case PIPE_FORMAT_Z32_FLOAT:
  94                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  95                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  96                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  97                 case PIPE_FORMAT_R16G16_SNORM:
  98                 case PIPE_FORMAT_R16G16_UNORM:
  99                         return TRUE;
 100                 default:
 101                         break;
 102                 }
 103         }
 104
 105         return FALSE;
 106 }
 107
 108 static int
 109 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 110 {
 111         switch (param) {
 112         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 113                 return 32;
 114         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 115                 return 32;
 116         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 117                 return 64;
 118         case PIPE_CAP_NPOT_TEXTURES:
 119                 return 1;
 120         case PIPE_CAP_TWO_SIDED_STENCIL:
 121                 return 1;
 122         case PIPE_CAP_GLSL:
 123                 return 1;
 124         case PIPE_CAP_ANISOTROPIC_FILTER:
 125                 return 1;
 126         case PIPE_CAP_POINT_SPRITE:
 127                 return 1;
 128         case PIPE_CAP_MAX_RENDER_TARGETS:
 129                 return 8;
 130         case PIPE_CAP_OCCLUSION_QUERY:
 131                 return 1;
 132         case PIPE_CAP_TIMER_QUERY:
 133                 return 0;
 134         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 135                 return 1;
 136         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 137                 return 13;
 138         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 139                 return 10;
 140         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 141                 return 13;
 142         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 143         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
 144                 return 1;
 145         case PIPE_CAP_TGSI_CONT_SUPPORTED:
 146                 return 1;
 147         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 148                 return 1;
 149         case PIPE_CAP_INDEP_BLEND_ENABLE:
 150                 return 1;
 151         case PIPE_CAP_INDEP_BLEND_FUNC:
 152                 return 0;
 153         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 154                 return 1;
 155         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 156         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 157                 return 1;
 158         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 159         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 160                 return 0;
 161         case PIPE_CAP_MAX_VS_INSTRUCTIONS:
 162         case PIPE_CAP_MAX_FS_INSTRUCTIONS:
 163         case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS:
 164         case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS:
 165         case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS:
 166         case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS:
 167         case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS:
 168         case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: /* arbitrary limit */
 169                 return 16384;
 170         case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH:
 171         case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: /* need stack bo */
 172                 return 4;
 173         case PIPE_CAP_MAX_VS_INPUTS:
 174                 return 16;
 175         case PIPE_CAP_MAX_FS_INPUTS: /* 128 / 4 with GP */
 176                 return 64 / 4;
 177         case PIPE_CAP_MAX_VS_CONSTS:
 178         case PIPE_CAP_MAX_FS_CONSTS:
 179                 return 65536 / 16;
 180         case PIPE_CAP_MAX_VS_ADDRS:
 181         case PIPE_CAP_MAX_FS_ADDRS: /* no spilling atm */
 182                 return 1;
 183         case PIPE_CAP_MAX_VS_PREDS:
 184         case PIPE_CAP_MAX_FS_PREDS: /* not yet handled */
 185                 return 0;
 186         case PIPE_CAP_MAX_VS_TEMPS:
 187         case PIPE_CAP_MAX_FS_TEMPS: /* no spilling atm */
 188                 return 128 / 4;
 189         default:
 190                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 191                 return 0;
 192         }
 193 }
 194
 195 static float
 196 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 197 {
 198         switch (param) {
 199         case PIPE_CAP_MAX_LINE_WIDTH:
 200         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 201                 return 10.0;
 202         case PIPE_CAP_MAX_POINT_WIDTH:
 203         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 204                 return 64.0;
 205         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 206                 return 16.0;
 207         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 208                 return 4.0;
 209         default:
 210                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 211                 return 0.0;
 212         }
 213 }
 214
 215 static void
 216 nv50_screen_destroy(struct pipe_screen *pscreen)
 217 {
 218         struct nv50_screen *screen = nv50_screen(pscreen);
 219         unsigned i;
 220
 221         for (i = 0; i < 3; i++) {
 222                 if (screen->constbuf_parm[i])
 223                         nouveau_bo_ref(NULL, &screen->constbuf_parm[i]);
 224         }
 225
 226         if (screen->constbuf_misc[0])
 227                 nouveau_bo_ref(NULL, &screen->constbuf_misc[0]);
 228         if (screen->tic)
 229                 nouveau_bo_ref(NULL, &screen->tic);
 230         if (screen->tsc)
 231                 nouveau_bo_ref(NULL, &screen->tsc);
 232
 233         nouveau_notifier_free(&screen->sync);
 234         nouveau_grobj_free(&screen->tesla);
 235         nouveau_grobj_free(&screen->eng2d);
 236         nouveau_grobj_free(&screen->m2mf);
 237         nouveau_resource_destroy(&screen->immd_heap);
 238         nouveau_screen_fini(&screen->base);
 239         FREE(screen);
 240 }
 241
 242 #define BGN_RELOC(ch, bo, gr, m, n, fl) \
 243    OUT_RELOC(ch, bo, (n << 18) | (gr->subc << 13) | m, fl, 0, 0)
 244
 245 void
 246 nv50_screen_relocs(struct nv50_screen *screen)
 247 {
 248         struct nouveau_channel *chan = screen->base.channel;
 249         struct nouveau_grobj *tesla = screen->tesla;
 250         unsigned i;
 251         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
 252
 253         MARK_RING (chan, 28, 26);
 254
 255         /* cause grobj autobind */
 256         BEGIN_RING(chan, tesla, 0x0100, 1);
 257         OUT_RING  (chan, 0);
 258
 259         BGN_RELOC (chan, screen->tic, tesla, NV50TCL_TIC_ADDRESS_HIGH, 2, rl);
 260         OUT_RELOCh(chan, screen->tic, 0, rl);
 261         OUT_RELOCl(chan, screen->tic, 0, rl);
 262
 263         BGN_RELOC (chan, screen->tsc, tesla, NV50TCL_TSC_ADDRESS_HIGH, 2, rl);
 264         OUT_RELOCh(chan, screen->tsc, 0, rl);
 265         OUT_RELOCl(chan, screen->tsc, 0, rl);
 266
 267         BGN_RELOC (chan, screen->constbuf_misc[0],
 268                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 269         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 270         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 271         OUT_RELOC (chan, screen->constbuf_misc[0],
 272                    (NV50_CB_PMISC << 16) | 0x0200, rl, 0, 0);
 273
 274         BGN_RELOC (chan, screen->constbuf_misc[0],
 275                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 276         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 277         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 278         OUT_RELOC (chan, screen->constbuf_misc[0],
 279                    (NV50_CB_AUX << 16) | 0x0200, rl, 0, 0);
 280
 281         for (i = 0; i < 3; ++i) {
 282                 BGN_RELOC (chan, screen->constbuf_parm[i],
 283                            tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 284                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 285                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 286                 OUT_RELOC (chan, screen->constbuf_parm[i],
 287                            ((NV50_CB_PVP + i) << 16) | 0x0000, rl, 0, 0);
 288         }
 289 }
 290
 291 struct pipe_screen *
 292 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 293 {
 294         struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen);
 295         struct nouveau_channel *chan;
 296         struct pipe_screen *pscreen;
 297         unsigned chipset = dev->chipset;
 298         unsigned tesla_class = 0;
 299         int ret, i;
 300         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 301
 302         if (!screen)
 303                 return NULL;
 304         pscreen = &screen->base.base;
 305
 306         ret = nouveau_screen_init(&screen->base, dev);
 307         if (ret) {
 308                 nv50_screen_destroy(pscreen);
 309                 return NULL;
 310         }
 311         chan = screen->base.channel;
 312
 313         pscreen->winsys = ws;
 314         pscreen->destroy = nv50_screen_destroy;
 315         pscreen->get_param = nv50_screen_get_param;
 316         pscreen->get_paramf = nv50_screen_get_paramf;
 317         pscreen->is_format_supported = nv50_screen_is_format_supported;
 318         pscreen->context_create = nv50_create;
 319
 320         nv50_screen_init_resource_functions(pscreen);
 321
 322         /* DMA engine object */
 323         ret = nouveau_grobj_alloc(chan, 0xbeef5039,
 324                 NV50_MEMORY_TO_MEMORY_FORMAT, &screen->m2mf);
 325         if (ret) {
 326                 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret);
 327                 nv50_screen_destroy(pscreen);
 328                 return NULL;
 329         }
 330
 331         /* 2D object */
 332         ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 333         if (ret) {
 334                 NOUVEAU_ERR("Error creating 2D object: %d\n", ret);
 335                 nv50_screen_destroy(pscreen);
 336                 return NULL;
 337         }
 338
 339         /* 3D object */
 340         switch (chipset & 0xf0) {
 341         case 0x50:
 342                 tesla_class = NV50TCL;
 343                 break;
 344         case 0x80:
 345         case 0x90:
 346                 tesla_class = NV84TCL;
 347                 break;
 348         case 0xa0:
 349                 switch (chipset) {
 350                 case 0xa0:
 351                 case 0xaa:
 352                 case 0xac:
 353                         tesla_class = NVA0TCL;
 354                         break;
 355                 default:
 356                         tesla_class = NVA8TCL;
 357                         break;
 358                 }
 359                 break;
 360         default:
 361                 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset);
 362                 nv50_screen_destroy(pscreen);
 363                 return NULL;
 364         }
 365
 366         ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class,
 367                 &screen->tesla);
 368         if (ret) {
 369                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 370                 nv50_screen_destroy(pscreen);
 371                 return NULL;
 372         }
 373
 374         /* this is necessary for the new RING_3D / statebuffer code */
 375         BIND_RING(chan, screen->tesla, 7);
 376
 377         /* Sync notifier */
 378         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 379         if (ret) {
 380                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 381                 nv50_screen_destroy(pscreen);
 382                 return NULL;
 383         }
 384
 385         /* Static M2MF init */
 386         BEGIN_RING(chan, screen->m2mf,
 387                    NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 388         OUT_RING  (chan, screen->sync->handle);
 389         OUT_RING  (chan, chan->vram->handle);
 390         OUT_RING  (chan, chan->vram->handle);
 391
 392         /* Static 2D init */
 393         BEGIN_RING(chan, screen->eng2d, NV50_2D_DMA_NOTIFY, 4);
 394         OUT_RING  (chan, screen->sync->handle);
 395         OUT_RING  (chan, chan->vram->handle);
 396         OUT_RING  (chan, chan->vram->handle);
 397         OUT_RING  (chan, chan->vram->handle);
 398         BEGIN_RING(chan, screen->eng2d, NV50_2D_OPERATION, 1);
 399         OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 400         BEGIN_RING(chan, screen->eng2d, NV50_2D_CLIP_ENABLE, 1);
 401         OUT_RING  (chan, 0);
 402         BEGIN_RING(chan, screen->eng2d, 0x0888, 1);
 403         OUT_RING  (chan, 1);
 404
 405         /* Static tesla init */
 406         BEGIN_RING(chan, screen->tesla, NV50TCL_COND_MODE, 1);
 407         OUT_RING  (chan, NV50TCL_COND_MODE_ALWAYS);
 408         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
 409         OUT_RING  (chan, screen->sync->handle);
 410         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_ZETA, 11);
 411         for (i = 0; i < 11; i++)
 412                 OUT_RING  (chan, chan->vram->handle);
 413         BEGIN_RING(chan, screen->tesla,
 414                    NV50TCL_DMA_COLOR(0), NV50TCL_DMA_COLOR__SIZE);
 415         for (i = 0; i < NV50TCL_DMA_COLOR__SIZE; i++)
 416                 OUT_RING  (chan, chan->vram->handle);
 417
 418         BEGIN_RING(chan, screen->tesla, NV50TCL_RT_CONTROL, 1);
 419         OUT_RING  (chan, 1);
 420
 421         /* activate all 32 lanes (threads) in a warp */
 422         BEGIN_RING(chan, screen->tesla, NV50TCL_REG_MODE, 1);
 423         OUT_RING  (chan, NV50TCL_REG_MODE_STRIPED);
 424         BEGIN_RING(chan, screen->tesla, 0x1400, 1);
 425         OUT_RING  (chan, 0xf);
 426
 427         /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
 428         for (i = 0; i < 3; ++i) {
 429                 BEGIN_RING(chan, screen->tesla, NV50TCL_TEX_LIMITS(i), 1);
 430                 OUT_RING  (chan, 0x54);
 431         }
 432
 433         /* origin is top left (set to 1 for bottom left) */
 434         BEGIN_RING(chan, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1);
 435         OUT_RING  (chan, 0);
 436         BEGIN_RING(chan, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
 437         OUT_RING  (chan, 8);
 438
 439         /* constant buffers for immediates and VP/FP parameters */
 440         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (32 * 4) * 4,
 441                              &screen->constbuf_misc[0]);
 442         if (ret) {
 443                 nv50_screen_destroy(pscreen);
 444                 return NULL;
 445         }
 446         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 447         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 448         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 449         OUT_RING  (chan, (NV50_CB_PMISC << 16) | 0x0200);
 450         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 451         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 452         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 453         OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 454
 455         for (i = 0; i < 3; i++) {
 456                 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (4096 * 4) * 4,
 457                                      &screen->constbuf_parm[i]);
 458                 if (ret) {
 459                         nv50_screen_destroy(pscreen);
 460                         return NULL;
 461                 }
 462                 BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 463                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 464                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 465                 /* CB_DEF_SET_SIZE value of 0x0000 means 65536 */
 466                 OUT_RING  (chan, ((NV50_CB_PVP + i) << 16) | 0x0000);
 467         }
 468
 469         if (nouveau_resource_init(&screen->immd_heap, 0, 128)) {
 470                 NOUVEAU_ERR("Error initialising shader immediates heap.\n");
 471                 nv50_screen_destroy(pscreen);
 472                 return NULL;
 473         }
 474
 475         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 476                              &screen->tic);
 477         if (ret) {
 478                 nv50_screen_destroy(pscreen);
 479                 return NULL;
 480         }
 481         BEGIN_RING(chan, screen->tesla, NV50TCL_TIC_ADDRESS_HIGH, 3);
 482         OUT_RELOCh(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 483         OUT_RELOCl(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 484         OUT_RING  (chan, 3 * 32 - 1);
 485
 486         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 487                              &screen->tsc);
 488         if (ret) {
 489                 nv50_screen_destroy(pscreen);
 490                 return NULL;
 491         }
 492         BEGIN_RING(chan, screen->tesla, NV50TCL_TSC_ADDRESS_HIGH, 3);
 493         OUT_RELOCh(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 494         OUT_RELOCl(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 495         OUT_RING  (chan, 0); /* ignored if TSC_LINKED (0x1234) == 1 */
 496
 497         /* map constant buffers:
 498          *  B = buffer ID (maybe more than 1 byte)
 499          *  N = CB index used in shader instruction
 500          *  P = program type (0 = VP, 2 = GP, 3 = FP)
 501          * SET_PROGRAM_CB = 0x000BBNP1
 502          */
 503         BEGIN_RING_NI(chan, screen->tesla, NV50TCL_SET_PROGRAM_CB, 8);
 504         /* bind immediate buffer */
 505         OUT_RING  (chan, 0x001 | (NV50_CB_PMISC << 12));
 506         OUT_RING  (chan, 0x021 | (NV50_CB_PMISC << 12));
 507         OUT_RING  (chan, 0x031 | (NV50_CB_PMISC << 12));
 508         /* bind auxiliary constbuf to immediate data bo */
 509         OUT_RING  (chan, 0x201 | (NV50_CB_AUX << 12));
 510         OUT_RING  (chan, 0x221 | (NV50_CB_AUX << 12));
 511         /* bind parameter buffers */
 512         OUT_RING  (chan, 0x101 | (NV50_CB_PVP << 12));
 513         OUT_RING  (chan, 0x121 | (NV50_CB_PGP << 12));
 514         OUT_RING  (chan, 0x131 | (NV50_CB_PFP << 12));
 515
 516         /* Vertex array limits - max them out */
 517         for (i = 0; i < 16; i++) {
 518                 BEGIN_RING(chan, screen->tesla,
 519                            NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
 520                 OUT_RING  (chan, 0x000000ff);
 521                 OUT_RING  (chan, 0xffffffff);
 522         }
 523
 524         BEGIN_RING(chan, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
 525         OUT_RINGf (chan, 0.0f);
 526         OUT_RINGf (chan, 1.0f);
 527
 528         /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
 529         BEGIN_RING(chan, screen->tesla, NV50TCL_LINKED_TSC, 1);
 530         OUT_RING  (chan, 1);
 531
 532         BEGIN_RING(chan, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
 533         OUT_RING  (chan, 1); /* default edgeflag to TRUE */
 534
 535         FIRE_RING (chan);
 536
 537         screen->force_push = debug_get_bool_option("NV50_ALWAYS_PUSH", FALSE);
 538         if(!screen->force_push)
 539                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = NOUVEAU_BO_GART;
 540         return pscreen;
 541 }
 542