src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 extern int nouveau_device_get_param(struct nouveau_device *dev,
  37                                     uint64_t param, uint64_t *value);
  38
  39 static boolean
  40 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  47       return FALSE;
  48    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  49       return FALSE;
  50
  51    if (!util_format_is_supported(format, bindings))
  52       return FALSE;
  53
  54    switch (format) {
  55    case PIPE_FORMAT_Z16_UNORM:
  56       if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D)
  57          return FALSE;
  58       break;
  59    case PIPE_FORMAT_R8G8B8A8_UNORM:
  60    case PIPE_FORMAT_R8G8B8X8_UNORM:
  61       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  62       if (bindings & PIPE_BIND_RENDER_TARGET)
  63          return FALSE;
  64    default:
  65       break;
  66    }
  67
  68    /* transfers & shared are always supported */
  69    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  70                  PIPE_BIND_TRANSFER_WRITE |
  71                  PIPE_BIND_SHARED);
  72
  73    return (nv50_format_table[format].usage & bindings) == bindings;
  74 }
  75
  76 static int
  77 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  78 {
  79    switch (param) {
  80    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  81       return 64;
  82    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  83       return 14;
  84    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  85       return 12;
  86    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  87       return 14;
  88    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* shader support missing */
  89       return 0;
  90    case PIPE_CAP_MIN_TEXEL_OFFSET:
  91       return 0 /* -8, TODO */;
  92    case PIPE_CAP_MAX_TEXEL_OFFSET:
  93       return 0 /* +7, TODO */;
  94    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  95    case PIPE_CAP_TEXTURE_SWIZZLE:
  96    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  97    case PIPE_CAP_NPOT_TEXTURES:
  98    case PIPE_CAP_ANISOTROPIC_FILTER:
  99    case PIPE_CAP_SCALED_RESOLVE:
 100       return 1;
 101    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 102    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 103       return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
 104    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 105       return 0;
 106    case PIPE_CAP_TWO_SIDED_STENCIL:
 107    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 108    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 109    case PIPE_CAP_POINT_SPRITE:
 110       return 1;
 111    case PIPE_CAP_SM3:
 112       return 1;
 113    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 114       return 120;
 115    case PIPE_CAP_MAX_RENDER_TARGETS:
 116       return 8;
 117    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 118    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 119    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 120       return 1;
 121    case PIPE_CAP_TIMER_QUERY:
 122    case PIPE_CAP_OCCLUSION_QUERY:
 123       return 1;
 124    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 125       return 0;
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127       return 128;
 128    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 129       return 32;
 130    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 131    case PIPE_CAP_INDEP_BLEND_ENABLE:
 132       return 1;
 133    case PIPE_CAP_INDEP_BLEND_FUNC:
 134       return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D;
 135    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 136    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 137       return 1;
 138    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 139    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 140       return 0;
 141    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 142       return 0;
 143    case PIPE_CAP_PRIMITIVE_RESTART:
 144    case PIPE_CAP_TGSI_INSTANCEID:
 145    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 146    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 147    case PIPE_CAP_CONDITIONAL_RENDER:
 148    case PIPE_CAP_TEXTURE_BARRIER:
 149    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 150       return 1;
 151    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 152    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 153       return 0; /* state trackers will know better */
 154    default:
 155       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 156       return 0;
 157    }
 158 }
 159
 160 static int
 161 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 162                              enum pipe_shader_cap param)
 163 {
 164    switch (shader) {
 165    case PIPE_SHADER_VERTEX:
 166    case PIPE_SHADER_GEOMETRY:
 167    case PIPE_SHADER_FRAGMENT:
 168       break;
 169    default:
 170       return 0;
 171    }
 172
 173    switch (param) {
 174    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 175    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 176    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 177    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 178       return 16384;
 179    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 180       return 4;
 181    case PIPE_SHADER_CAP_MAX_INPUTS:
 182       if (shader == PIPE_SHADER_VERTEX)
 183          return 32;
 184       return 0x300 / 16;
 185    case PIPE_SHADER_CAP_MAX_CONSTS:
 186       return 65536 / 16;
 187    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 188       return 14;
 189    case PIPE_SHADER_CAP_MAX_ADDRS:
 190       return 1;
 191    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 192    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 193       return shader != PIPE_SHADER_FRAGMENT;
 194    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 195    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 196       return 1;
 197    case PIPE_SHADER_CAP_MAX_PREDS:
 198       return 0;
 199    case PIPE_SHADER_CAP_MAX_TEMPS:
 200       return NV50_CAP_MAX_PROGRAM_TEMPS;
 201    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 202       return 1;
 203    case PIPE_SHADER_CAP_SUBROUTINES:
 204       return 0; /* please inline, or provide function declarations */
 205    case PIPE_SHADER_CAP_INTEGERS:
 206       return 0;
 207    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 208       return 32;
 209    default:
 210       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 211       return 0;
 212    }
 213 }
 214
 215 static float
 216 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 217 {
 218    switch (param) {
 219    case PIPE_CAPF_MAX_LINE_WIDTH:
 220    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 221       return 10.0f;
 222    case PIPE_CAPF_MAX_POINT_WIDTH:
 223    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 224       return 64.0f;
 225    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 226       return 16.0f;
 227    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 228       return 4.0f;
 229    default:
 230       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 231       return 0.0f;
 232    }
 233 }
 234
 235 static void
 236 nv50_screen_destroy(struct pipe_screen *pscreen)
 237 {
 238    struct nv50_screen *screen = nv50_screen(pscreen);
 239
 240    if (screen->base.fence.current) {
 241       nouveau_fence_wait(screen->base.fence.current);
 242       nouveau_fence_ref (NULL, &screen->base.fence.current);
 243    }
 244    if (screen->base.channel)
 245       screen->base.channel->user_private = NULL;
 246    if (screen->blitctx)
 247       FREE(screen->blitctx);
 248
 249    nouveau_bo_ref(NULL, &screen->code);
 250    nouveau_bo_ref(NULL, &screen->tls_bo);
 251    nouveau_bo_ref(NULL, &screen->stack_bo);
 252    nouveau_bo_ref(NULL, &screen->txc);
 253    nouveau_bo_ref(NULL, &screen->uniforms);
 254    nouveau_bo_ref(NULL, &screen->fence.bo);
 255
 256    nouveau_resource_destroy(&screen->vp_code_heap);
 257    nouveau_resource_destroy(&screen->gp_code_heap);
 258    nouveau_resource_destroy(&screen->fp_code_heap);
 259
 260    if (screen->tic.entries)
 261       FREE(screen->tic.entries);
 262
 263    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 264
 265    nouveau_grobj_free(&screen->tesla);
 266    nouveau_grobj_free(&screen->eng2d);
 267    nouveau_grobj_free(&screen->m2mf);
 268
 269    nouveau_notifier_free(&screen->sync);
 270
 271    nouveau_screen_fini(&screen->base);
 272
 273    FREE(screen);
 274 }
 275
 276 static void
 277 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 278 {
 279    struct nv50_screen *screen = nv50_screen(pscreen);
 280    struct nouveau_channel *chan = screen->base.channel;
 281
 282    MARK_RING (chan, 5, 2);
 283
 284    /* we need to do it after possible flush in MARK_RING */
 285    *sequence = ++screen->base.fence.sequence;
 286
 287    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 288    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 289    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 290    OUT_RING  (chan, *sequence);
 291    OUT_RING  (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 292                     NV50_3D_QUERY_GET_UNK4 |
 293                     NV50_3D_QUERY_GET_UNIT_CROP |
 294                     NV50_3D_QUERY_GET_TYPE_QUERY |
 295                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 296                     NV50_3D_QUERY_GET_SHORT);
 297 }
 298
 299 static u32
 300 nv50_screen_fence_update(struct pipe_screen *pscreen)
 301 {
 302    struct nv50_screen *screen = nv50_screen(pscreen);
 303    return screen->fence.map[0];
 304 }
 305
 306 #define FAIL_SCREEN_INIT(str, err)                    \
 307    do {                                               \
 308       NOUVEAU_ERR(str, err);                          \
 309       nv50_screen_destroy(pscreen);                   \
 310       return NULL;                                    \
 311    } while(0)
 312
 313 struct pipe_screen *
 314 nv50_screen_create(struct nouveau_device *dev)
 315 {
 316    struct nv50_screen *screen;
 317    struct nouveau_channel *chan;
 318    struct pipe_screen *pscreen;
 319    uint64_t value;
 320    uint32_t tesla_class;
 321    unsigned stack_size, max_warps, tls_space;
 322    int ret;
 323    unsigned i, base;
 324
 325    screen = CALLOC_STRUCT(nv50_screen);
 326    if (!screen)
 327       return NULL;
 328    pscreen = &screen->base.base;
 329
 330    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 331
 332    ret = nouveau_screen_init(&screen->base, dev);
 333    if (ret)
 334       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 335
 336    chan = screen->base.channel;
 337    chan->user_private = screen;
 338
 339    pscreen->destroy = nv50_screen_destroy;
 340    pscreen->context_create = nv50_create;
 341    pscreen->is_format_supported = nv50_screen_is_format_supported;
 342    pscreen->get_param = nv50_screen_get_param;
 343    pscreen->get_shader_param = nv50_screen_get_shader_param;
 344    pscreen->get_paramf = nv50_screen_get_paramf;
 345
 346    nv50_screen_init_resource_functions(pscreen);
 347
 348    nouveau_screen_init_vdec(&screen->base);
 349
 350    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 351                         &screen->fence.bo);
 352    if (ret)
 353       goto fail;
 354    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 355    screen->fence.map = screen->fence.bo->map;
 356    nouveau_bo_unmap(screen->fence.bo);
 357    screen->base.fence.emit = nv50_screen_fence_emit;
 358    screen->base.fence.update = nv50_screen_fence_update;
 359
 360    ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 361    if (ret)
 362       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 363
 364    ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
 365    if (ret)
 366       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 367
 368    BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
 369    BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
 370    OUT_RING  (chan, screen->sync->handle);
 371    OUT_RING  (chan, chan->vram->handle);
 372    OUT_RING  (chan, chan->vram->handle);
 373
 374    ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 375    if (ret)
 376       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 377
 378    BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
 379    BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
 380    OUT_RING  (chan, screen->sync->handle);
 381    OUT_RING  (chan, chan->vram->handle);
 382    OUT_RING  (chan, chan->vram->handle);
 383    OUT_RING  (chan, chan->vram->handle);
 384    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 385    OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 386    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 387    OUT_RING  (chan, 0);
 388    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 389    OUT_RING  (chan, 0);
 390    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 391    OUT_RING  (chan, 1);
 392
 393    switch (dev->chipset & 0xf0) {
 394    case 0x50:
 395       tesla_class = NV50_3D;
 396       break;
 397    case 0x80:
 398    case 0x90:
 399       tesla_class = NV84_3D;
 400       break;
 401    case 0xa0:
 402       switch (dev->chipset) {
 403       case 0xa0:
 404       case 0xaa:
 405       case 0xac:
 406          tesla_class = NVA0_3D;
 407          break;
 408       case 0xaf:
 409          tesla_class = NVAF_3D;
 410          break;
 411       default:
 412          tesla_class = NVA3_3D;
 413          break;
 414       }
 415       break;
 416    default:
 417       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 418       break;
 419    }
 420
 421    ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
 422    if (ret)
 423       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 424
 425    BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
 426
 427    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 428    OUT_RING  (chan, NV50_3D_COND_MODE_ALWAYS);
 429
 430    BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
 431    OUT_RING  (chan, screen->sync->handle);
 432    BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
 433    for (i = 0; i < 11; ++i)
 434       OUT_RING(chan, chan->vram->handle);
 435    BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 436    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 437       OUT_RING(chan, chan->vram->handle);
 438
 439    BEGIN_RING(chan, RING_3D(REG_MODE), 1);
 440    OUT_RING  (chan, NV50_3D_REG_MODE_STRIPED);
 441    BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
 442    OUT_RING  (chan, 0xf);
 443
 444    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 445    OUT_RING  (chan, 1);
 446
 447    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 448    OUT_RING  (chan, 0);
 449    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 450    OUT_RING  (chan, 0);
 451    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 452    OUT_RING  (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
 453    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 454    OUT_RING  (chan, 0);
 455    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 456    OUT_RING  (chan, 0);
 457    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 458    OUT_RING  (chan, 1);
 459
 460    if (tesla_class >= NVA0_3D) {
 461       BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1);
 462       OUT_RING  (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 463    }
 464
 465    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 466    OUT_RING  (chan, 0);
 467    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 468    OUT_RING  (chan, 0);
 469    OUT_RING  (chan, 0);
 470    BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 471    OUT_RING  (chan, 0x3f);
 472
 473    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 474                         3 << NV50_CODE_BO_SIZE_LOG2, &screen->code);
 475    if (ret)
 476       goto fail;
 477
 478    nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 479    nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 480    nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 481
 482    base = 1 << NV50_CODE_BO_SIZE_LOG2;
 483
 484    BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
 485    OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 486    OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 487
 488    BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
 489    OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 490    OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 491
 492    BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
 493    OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 494    OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 495
 496    nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 497
 498    max_warps  = util_bitcount(value & 0xffff);
 499    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 500
 501    stack_size = max_warps * 64 * 8;
 502
 503    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
 504                         &screen->stack_bo);
 505    if (ret)
 506       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 507
 508    BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
 509    OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 510    OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 511    OUT_RING  (chan, 4);
 512
 513    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 514
 515    screen->tls_size = tls_space * max_warps * 32;
 516
 517    if (nouveau_mesa_debug)
 518       debug_printf("max_warps = %i, tls_size = %"PRIu64" KiB\n",
 519                      max_warps, screen->tls_size >> 10);
 520
 521    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
 522                         &screen->tls_bo);
 523    if (ret)
 524       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 525
 526    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
 527    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 528    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 529    OUT_RING  (chan, util_logbase2(tls_space / 8));
 530
 531    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
 532                         &screen->uniforms);
 533    if (ret)
 534       goto fail;
 535
 536    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 537    OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 538    OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 539    OUT_RING  (chan, (NV50_CB_PVP << 16) | 0x0000);
 540
 541    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 542    OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 543    OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 544    OUT_RING  (chan, (NV50_CB_PGP << 16) | 0x0000);
 545
 546    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 547    OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 548    OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 549    OUT_RING  (chan, (NV50_CB_PFP << 16) | 0x0000);
 550
 551    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 552    OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 553    OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 554    OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 555
 556    BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
 557    OUT_RING  (chan, (NV50_CB_PVP << 12) | 0x001);
 558    OUT_RING  (chan, (NV50_CB_PGP << 12) | 0x021);
 559    OUT_RING  (chan, (NV50_CB_PFP << 12) | 0x031);
 560    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf01);
 561    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf21);
 562    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf31);
 563
 564    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
 565                         &screen->txc);
 566    if (ret)
 567       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 568
 569    /* max TIC (bits 4:8) & TSC bindings, per program type */
 570    for (i = 0; i < 3; ++i) {
 571       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 572       OUT_RING  (chan, 0x54);
 573    }
 574
 575    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 576    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 577    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 578    OUT_RING  (chan, NV50_TIC_MAX_ENTRIES - 1);
 579
 580    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 581    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 582    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 583    OUT_RING  (chan, NV50_TSC_MAX_ENTRIES - 1);
 584
 585    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 586    OUT_RING  (chan, 0);
 587
 588    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 589    OUT_RING  (chan, 0);
 590    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 591    OUT_RING  (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 592    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 593    for (i = 0; i < 8 * 2; ++i)
 594       OUT_RING(chan, 0);
 595    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 596    OUT_RING  (chan, 0);
 597
 598    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 599    OUT_RING  (chan, 1);
 600    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 601    OUT_RINGf (chan, 0.0f);
 602    OUT_RINGf (chan, 1.0f);
 603
 604    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 605 #ifdef NV50_SCISSORS_CLIPPING
 606    OUT_RING  (chan, 0x0000);
 607 #else
 608    OUT_RING  (chan, 0x1080);
 609 #endif
 610
 611    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 612    OUT_RING  (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 613
 614    /* We use scissors instead of exact view volume clipping,
 615     * so they're always enabled.
 616     */
 617    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 618    OUT_RING  (chan, 1);
 619    OUT_RING  (chan, 8192 << 16);
 620    OUT_RING  (chan, 8192 << 16);
 621
 622    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 623    OUT_RING  (chan, 1);
 624    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 625    OUT_RING  (chan, NV50_3D_POINT_RASTER_RULES_OGL);
 626    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 627    OUT_RING  (chan, 0x11111111);
 628    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 629    OUT_RING  (chan, 1);
 630
 631    FIRE_RING (chan);
 632
 633    screen->tic.entries = CALLOC(4096, sizeof(void *));
 634    screen->tsc.entries = screen->tic.entries + 2048;
 635
 636    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 637
 638    if (!nv50_blitctx_create(screen))
 639       goto fail;
 640
 641    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 642
 643    return pscreen;
 644
 645 fail:
 646    nv50_screen_destroy(pscreen);
 647    return NULL;
 648 }
 649
 650 void
 651 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
 652 {
 653    struct nouveau_channel *chan = screen->base.channel;
 654
 655    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 656
 657    MARK_RING(chan, 0, 5);
 658    nouveau_bo_validate(chan, screen->code, flags);
 659    nouveau_bo_validate(chan, screen->uniforms, flags);
 660    nouveau_bo_validate(chan, screen->txc, flags);
 661    nouveau_bo_validate(chan, screen->tls_bo, flags);
 662    nouveau_bo_validate(chan, screen->stack_bo, flags);
 663 }
 664
 665 int
 666 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 667 {
 668    int i = screen->tic.next;
 669
 670    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 671       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 672
 673    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 674
 675    if (screen->tic.entries[i])
 676       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 677
 678    screen->tic.entries[i] = entry;
 679    return i;
 680 }
 681
 682 int
 683 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 684 {
 685    int i = screen->tsc.next;
 686
 687    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 688       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 689
 690    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 691
 692    if (screen->tsc.entries[i])
 693       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 694
 695    screen->tsc.entries[i] = entry;
 696    return i;
 697 }