2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_screen.h"
25 #include "nv50_context.h"
26 #include "nv50_screen.h"
28 #include "nouveau/nouveau_stateobj.h"
31 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
32 enum pipe_format format
,
33 enum pipe_texture_target target
,
34 unsigned tex_usage
, unsigned geom_flags
)
36 if (tex_usage
& PIPE_TEXTURE_USAGE_RENDER_TARGET
) {
38 case PIPE_FORMAT_A8R8G8B8_UNORM
:
39 case PIPE_FORMAT_R5G6B5_UNORM
:
45 if (tex_usage
& PIPE_TEXTURE_USAGE_DEPTH_STENCIL
) {
47 case PIPE_FORMAT_Z32_FLOAT
:
48 case PIPE_FORMAT_Z24S8_UNORM
:
49 case PIPE_FORMAT_X8Z24_UNORM
:
50 case PIPE_FORMAT_S8Z24_UNORM
:
57 case PIPE_FORMAT_A8R8G8B8_UNORM
:
58 case PIPE_FORMAT_A1R5G5B5_UNORM
:
59 case PIPE_FORMAT_A4R4G4B4_UNORM
:
60 case PIPE_FORMAT_R5G6B5_UNORM
:
61 case PIPE_FORMAT_L8_UNORM
:
62 case PIPE_FORMAT_A8_UNORM
:
63 case PIPE_FORMAT_I8_UNORM
:
64 case PIPE_FORMAT_A8L8_UNORM
:
65 case PIPE_FORMAT_DXT1_RGB
:
66 case PIPE_FORMAT_DXT1_RGBA
:
67 case PIPE_FORMAT_DXT3_RGBA
:
68 case PIPE_FORMAT_DXT5_RGBA
:
79 nv50_screen_get_param(struct pipe_screen
*pscreen
, int param
)
82 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
84 case PIPE_CAP_NPOT_TEXTURES
:
86 case PIPE_CAP_TWO_SIDED_STENCIL
:
90 case PIPE_CAP_ANISOTROPIC_FILTER
:
92 case PIPE_CAP_POINT_SPRITE
:
94 case PIPE_CAP_MAX_RENDER_TARGETS
:
96 case PIPE_CAP_OCCLUSION_QUERY
:
98 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
100 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
102 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
104 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
106 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
107 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
109 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
111 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
113 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
115 case NOUVEAU_CAP_HW_VTXBUF
:
117 case NOUVEAU_CAP_HW_IDXBUF
:
120 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
126 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
129 case PIPE_CAP_MAX_LINE_WIDTH
:
130 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
132 case PIPE_CAP_MAX_POINT_WIDTH
:
133 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
135 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
137 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
140 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
146 nv50_screen_destroy(struct pipe_screen
*pscreen
)
148 struct nv50_screen
*screen
= nv50_screen(pscreen
);
150 nouveau_notifier_free(&screen
->sync
);
151 nouveau_grobj_free(&screen
->tesla
);
152 nouveau_grobj_free(&screen
->eng2d
);
153 nouveau_grobj_free(&screen
->m2mf
);
154 nouveau_screen_fini(&screen
->base
);
159 nv50_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
161 struct nv50_screen
*screen
= CALLOC_STRUCT(nv50_screen
);
162 struct nouveau_channel
*chan
;
163 struct pipe_screen
*pscreen
;
164 struct nouveau_stateobj
*so
;
165 unsigned chipset
= dev
->chipset
;
166 unsigned tesla_class
= 0;
171 pscreen
= &screen
->base
.base
;
173 ret
= nouveau_screen_init(&screen
->base
, dev
);
175 nv50_screen_destroy(pscreen
);
178 chan
= screen
->base
.channel
;
180 pscreen
->winsys
= ws
;
181 pscreen
->destroy
= nv50_screen_destroy
;
182 pscreen
->get_param
= nv50_screen_get_param
;
183 pscreen
->get_paramf
= nv50_screen_get_paramf
;
184 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
186 nv50_screen_init_miptree_functions(pscreen
);
187 nv50_transfer_init_screen_functions(pscreen
);
189 /* DMA engine object */
190 ret
= nouveau_grobj_alloc(chan
, 0xbeef5039,
191 NV50_MEMORY_TO_MEMORY_FORMAT
, &screen
->m2mf
);
193 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret
);
194 nv50_screen_destroy(pscreen
);
197 BIND_RING(chan
, screen
->m2mf
, 1);
200 ret
= nouveau_grobj_alloc(chan
, 0xbeef502d, NV50_2D
, &screen
->eng2d
);
202 NOUVEAU_ERR("Error creating 2D object: %d\n", ret
);
203 nv50_screen_destroy(pscreen
);
206 BIND_RING(chan
, screen
->eng2d
, 2);
209 switch (chipset
& 0xf0) {
211 tesla_class
= NV50TCL
;
215 /* this stupid name should be corrected. */
216 tesla_class
= NV54TCL
;
219 tesla_class
= NVA0TCL
;
222 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset
);
223 nv50_screen_destroy(pscreen
);
227 if (tesla_class
== 0) {
228 NOUVEAU_ERR("Unknown G8x chipset: NV%02x\n", chipset
);
229 nv50_screen_destroy(pscreen
);
233 ret
= nouveau_grobj_alloc(chan
, 0xbeef5097, tesla_class
,
236 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
237 nv50_screen_destroy(pscreen
);
240 BIND_RING(chan
, screen
->tesla
, 3);
243 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
245 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
246 nv50_screen_destroy(pscreen
);
250 /* Static M2MF init */
252 so_method(so
, screen
->m2mf
, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY
, 3);
253 so_data (so
, screen
->sync
->handle
);
254 so_data (so
, chan
->vram
->handle
);
255 so_data (so
, chan
->vram
->handle
);
261 so_method(so
, screen
->eng2d
, NV50_2D_DMA_NOTIFY
, 4);
262 so_data (so
, screen
->sync
->handle
);
263 so_data (so
, chan
->vram
->handle
);
264 so_data (so
, chan
->vram
->handle
);
265 so_data (so
, chan
->vram
->handle
);
266 so_method(so
, screen
->eng2d
, NV50_2D_OPERATION
, 1);
267 so_data (so
, NV50_2D_OPERATION_SRCCOPY
);
268 so_method(so
, screen
->eng2d
, 0x0290, 1);
270 so_method(so
, screen
->eng2d
, 0x0888, 1);
275 /* Static tesla init */
276 so
= so_new(256, 20);
278 so_method(so
, screen
->tesla
, 0x1558, 1);
280 so_method(so
, screen
->tesla
, NV50TCL_DMA_NOTIFY
, 1);
281 so_data (so
, screen
->sync
->handle
);
282 so_method(so
, screen
->tesla
, NV50TCL_DMA_UNK0(0),
283 NV50TCL_DMA_UNK0__SIZE
);
284 for (i
= 0; i
< NV50TCL_DMA_UNK0__SIZE
; i
++)
285 so_data(so
, chan
->vram
->handle
);
286 so_method(so
, screen
->tesla
, NV50TCL_DMA_UNK1(0),
287 NV50TCL_DMA_UNK1__SIZE
);
288 for (i
= 0; i
< NV50TCL_DMA_UNK1__SIZE
; i
++)
289 so_data(so
, chan
->vram
->handle
);
290 so_method(so
, screen
->tesla
, 0x121c, 1);
293 so_method(so
, screen
->tesla
, 0x13bc, 1);
295 /* origin is top left (set to 1 for bottom left) */
296 so_method(so
, screen
->tesla
, 0x13ac, 1);
298 so_method(so
, screen
->tesla
, NV50TCL_VP_REG_ALLOC_RESULT
, 1);
301 /* constant buffers for immediates and VP/FP parameters */
302 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, 128*4*4,
303 &screen
->constbuf_misc
[0]);
305 nv50_screen_destroy(pscreen
);
309 for (i
= 0; i
< 2; i
++) {
310 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, 128*4*4,
311 &screen
->constbuf_parm
[i
]);
313 nv50_screen_destroy(pscreen
);
318 if (nouveau_resource_init(&screen
->immd_heap
[0], 0, 128) ||
319 nouveau_resource_init(&screen
->parm_heap
[0], 0, 128) ||
320 nouveau_resource_init(&screen
->parm_heap
[1], 0, 128))
322 NOUVEAU_ERR("Error initialising constant buffers.\n");
323 nv50_screen_destroy(pscreen
);
328 // map constant buffers:
329 // B = buffer ID (maybe more than 1 byte)
330 // N = CB index used in shader instruction
331 // P = program type (0 = VP, 2 = GP, 3 = FP)
332 so_method(so, screen->tesla, 0x1694, 1);
333 so_data (so, 0x000BBNP1);
336 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
337 so_reloc (so
, screen
->constbuf_misc
[0], 0, NOUVEAU_BO_VRAM
|
338 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
339 so_reloc (so
, screen
->constbuf_misc
[0], 0, NOUVEAU_BO_VRAM
|
340 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
341 so_data (so
, (NV50_CB_PMISC
<< 16) | 0x00000800);
342 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
343 so_data (so
, 0x00000001 | (NV50_CB_PMISC
<< 12));
344 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
345 so_data (so
, 0x00000031 | (NV50_CB_PMISC
<< 12));
347 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
348 so_reloc (so
, screen
->constbuf_parm
[0], 0, NOUVEAU_BO_VRAM
|
349 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
350 so_reloc (so
, screen
->constbuf_parm
[0], 0, NOUVEAU_BO_VRAM
|
351 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
352 so_data (so
, (NV50_CB_PVP
<< 16) | 0x00000800);
353 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
354 so_data (so
, 0x00000101 | (NV50_CB_PVP
<< 12));
356 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
357 so_reloc (so
, screen
->constbuf_parm
[1], 0, NOUVEAU_BO_VRAM
|
358 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
359 so_reloc (so
, screen
->constbuf_parm
[1], 0, NOUVEAU_BO_VRAM
|
360 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
361 so_data (so
, (NV50_CB_PFP
<< 16) | 0x00000800);
362 so_method(so
, screen
->tesla
, NV50TCL_SET_PROGRAM_CB
, 1);
363 so_data (so
, 0x00000131 | (NV50_CB_PFP
<< 12));
365 /* Texture sampler/image unit setup - we abuse the constant buffer
366 * upload mechanism for the moment to upload data to the tex config
367 * blocks. At some point we *may* want to go the NVIDIA way of doing
370 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, 32*8*4, &screen
->tic
);
372 nv50_screen_destroy(pscreen
);
376 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
377 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
378 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
379 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
380 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
381 so_data (so
, (NV50_CB_TIC
<< 16) | 0x0800);
382 so_method(so
, screen
->tesla
, NV50TCL_TIC_ADDRESS_HIGH
, 3);
383 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
384 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
385 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
386 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
387 so_data (so
, 0x00000800);
389 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 0, 32*8*4, &screen
->tsc
);
391 nv50_screen_destroy(pscreen
);
395 so_method(so
, screen
->tesla
, NV50TCL_CB_DEF_ADDRESS_HIGH
, 3);
396 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
397 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
398 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
399 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
400 so_data (so
, (NV50_CB_TSC
<< 16) | 0x0800);
401 so_method(so
, screen
->tesla
, NV50TCL_TSC_ADDRESS_HIGH
, 3);
402 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
403 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
404 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
405 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
406 so_data (so
, 0x00000800);
409 /* Vertex array limits - max them out */
410 for (i
= 0; i
< 16; i
++) {
411 so_method(so
, screen
->tesla
, NV50TCL_UNK1080_OFFSET_HIGH(i
), 2);
412 so_data (so
, 0x000000ff);
413 so_data (so
, 0xffffffff);
416 so_method(so
, screen
->tesla
, NV50TCL_DEPTH_RANGE_NEAR
, 2);
417 so_data (so
, fui(0.0));
418 so_data (so
, fui(1.0));
420 so_method(so
, screen
->tesla
, 0x1234, 1);
423 /* activate first scissor rectangle */
424 so_method(so
, screen
->tesla
, NV50TCL_SCISSOR_ENABLE
, 1);
428 so_ref (so
, &screen
->static_init
);
430 nouveau_pushbuf_flush(chan
, 0);