src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31 #include <errno.h>
  32
  33 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  34 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  35 #endif
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  45
  46 static boolean
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return FALSE;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return FALSE;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return FALSE;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return FALSE;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return FALSE;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    /* transfers & shared are always supported */
  73    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  74                  PIPE_BIND_TRANSFER_WRITE |
  75                  PIPE_BIND_SHARED);
  76
  77    return (nv50_format_table[format].usage & bindings) == bindings;
  78 }
  79
  80 static int
  81 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  82 {
  83    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  84
  85    switch (param) {
  86    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  87       return 64;
  88    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  89       return 14;
  90    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  91       return 12;
  92    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  93       return 14;
  94    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  95       return 512;
  96    case PIPE_CAP_MIN_TEXEL_OFFSET:
  97       return -8;
  98    case PIPE_CAP_MAX_TEXEL_OFFSET:
  99       return 7;
 100    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 101    case PIPE_CAP_TEXTURE_SWIZZLE:
 102    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 103    case PIPE_CAP_NPOT_TEXTURES:
 104    case PIPE_CAP_ANISOTROPIC_FILTER:
 105    case PIPE_CAP_SCALED_RESOLVE:
 106    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 107       return 1;
 108    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 109       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 110    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 111       return 0;
 112    case PIPE_CAP_CUBE_MAP_ARRAY:
 113       return 0;
 114       /*
 115       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 116       */
 117    case PIPE_CAP_TWO_SIDED_STENCIL:
 118    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 119    case PIPE_CAP_POINT_SPRITE:
 120       return 1;
 121    case PIPE_CAP_SM3:
 122       return 1;
 123    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 124       return 140;
 125    case PIPE_CAP_MAX_RENDER_TARGETS:
 126       return 8;
 127    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 128       return 1;
 129    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 130    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 131    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 132       return 1;
 133    case PIPE_CAP_QUERY_TIMESTAMP:
 134    case PIPE_CAP_QUERY_TIME_ELAPSED:
 135    case PIPE_CAP_OCCLUSION_QUERY:
 136       return 1;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 138       return 4;
 139    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 140    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 141       return 64;
 142    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 143       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 144    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 145    case PIPE_CAP_INDEP_BLEND_ENABLE:
 146       return 1;
 147    case PIPE_CAP_INDEP_BLEND_FUNC:
 148       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 149    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 150    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 151       return 1;
 152    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 153    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 154       return 0;
 155    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 156       return 0;
 157    case PIPE_CAP_PRIMITIVE_RESTART:
 158    case PIPE_CAP_TGSI_INSTANCEID:
 159    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 160    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 161    case PIPE_CAP_CONDITIONAL_RENDER:
 162    case PIPE_CAP_TEXTURE_BARRIER:
 163    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 164    case PIPE_CAP_START_INSTANCE:
 165       return 1;
 166    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 167    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 168       return 0; /* state trackers will know better */
 169    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 170    case PIPE_CAP_USER_INDEX_BUFFERS:
 171    case PIPE_CAP_USER_VERTEX_BUFFERS:
 172       return 1;
 173    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 174       return 256;
 175    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 176       return 1; /* 256 for binding as RT, but that's not possible in GL */
 177    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 178       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 179    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 180    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 181    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 182    case PIPE_CAP_TGSI_TEXCOORD:
 183    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 184       return 0;
 185    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 186       return 1;
 187    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 188       return 0;
 189    default:
 190       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 191       return 0;
 192    }
 193 }
 194
 195 static int
 196 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 197                              enum pipe_shader_cap param)
 198 {
 199    switch (shader) {
 200    case PIPE_SHADER_VERTEX:
 201    case PIPE_SHADER_GEOMETRY:
 202    case PIPE_SHADER_FRAGMENT:
 203       break;
 204    default:
 205       return 0;
 206    }
 207
 208    switch (param) {
 209    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 210    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 211    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 212    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 213       return 16384;
 214    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 215       return 4;
 216    case PIPE_SHADER_CAP_MAX_INPUTS:
 217       if (shader == PIPE_SHADER_VERTEX)
 218          return 32;
 219       return 0x300 / 16;
 220    case PIPE_SHADER_CAP_MAX_CONSTS:
 221       return 65536 / 16;
 222    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 223       return NV50_MAX_PIPE_CONSTBUFS;
 224    case PIPE_SHADER_CAP_MAX_ADDRS:
 225       return 1;
 226    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 227    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 228       return shader != PIPE_SHADER_FRAGMENT;
 229    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 230    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 231       return 1;
 232    case PIPE_SHADER_CAP_MAX_PREDS:
 233       return 0;
 234    case PIPE_SHADER_CAP_MAX_TEMPS:
 235       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 236    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 237       return 1;
 238    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 239       return 0;
 240    case PIPE_SHADER_CAP_SUBROUTINES:
 241       return 0; /* please inline, or provide function declarations */
 242    case PIPE_SHADER_CAP_INTEGERS:
 243       return 1;
 244    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 245       return 32;
 246    default:
 247       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 248       return 0;
 249    }
 250 }
 251
 252 static float
 253 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 254 {
 255    switch (param) {
 256    case PIPE_CAPF_MAX_LINE_WIDTH:
 257    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 258       return 10.0f;
 259    case PIPE_CAPF_MAX_POINT_WIDTH:
 260    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 261       return 64.0f;
 262    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 263       return 16.0f;
 264    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 265       return 4.0f;
 266    default:
 267       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 268       return 0.0f;
 269    }
 270 }
 271
 272 static void
 273 nv50_screen_destroy(struct pipe_screen *pscreen)
 274 {
 275    struct nv50_screen *screen = nv50_screen(pscreen);
 276
 277    if (screen->base.fence.current) {
 278       nouveau_fence_wait(screen->base.fence.current);
 279       nouveau_fence_ref (NULL, &screen->base.fence.current);
 280    }
 281    if (screen->base.pushbuf)
 282       screen->base.pushbuf->user_priv = NULL;
 283
 284    if (screen->blitter)
 285       nv50_blitter_destroy(screen);
 286
 287    nouveau_bo_ref(NULL, &screen->code);
 288    nouveau_bo_ref(NULL, &screen->tls_bo);
 289    nouveau_bo_ref(NULL, &screen->stack_bo);
 290    nouveau_bo_ref(NULL, &screen->txc);
 291    nouveau_bo_ref(NULL, &screen->uniforms);
 292    nouveau_bo_ref(NULL, &screen->fence.bo);
 293
 294    nouveau_heap_destroy(&screen->vp_code_heap);
 295    nouveau_heap_destroy(&screen->gp_code_heap);
 296    nouveau_heap_destroy(&screen->fp_code_heap);
 297
 298    FREE(screen->tic.entries);
 299
 300    nouveau_object_del(&screen->tesla);
 301    nouveau_object_del(&screen->eng2d);
 302    nouveau_object_del(&screen->m2mf);
 303    nouveau_object_del(&screen->sync);
 304
 305    nouveau_screen_fini(&screen->base);
 306
 307    FREE(screen);
 308 }
 309
 310 static void
 311 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 312 {
 313    struct nv50_screen *screen = nv50_screen(pscreen);
 314    struct nouveau_pushbuf *push = screen->base.pushbuf;
 315
 316    /* we need to do it after possible flush in MARK_RING */
 317    *sequence = ++screen->base.fence.sequence;
 318
 319    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 320    PUSH_DATAh(push, screen->fence.bo->offset);
 321    PUSH_DATA (push, screen->fence.bo->offset);
 322    PUSH_DATA (push, *sequence);
 323    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 324                     NV50_3D_QUERY_GET_UNK4 |
 325                     NV50_3D_QUERY_GET_UNIT_CROP |
 326                     NV50_3D_QUERY_GET_TYPE_QUERY |
 327                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 328                     NV50_3D_QUERY_GET_SHORT);
 329 }
 330
 331 static u32
 332 nv50_screen_fence_update(struct pipe_screen *pscreen)
 333 {
 334    return nv50_screen(pscreen)->fence.map[0];
 335 }
 336
 337 static void
 338 nv50_screen_init_hwctx(struct nv50_screen *screen)
 339 {
 340    struct nouveau_pushbuf *push = screen->base.pushbuf;
 341    struct nv04_fifo *fifo;
 342    unsigned i;
 343
 344    fifo = (struct nv04_fifo *)screen->base.channel->data;
 345
 346    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 347    PUSH_DATA (push, screen->m2mf->handle);
 348    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 349    PUSH_DATA (push, screen->sync->handle);
 350    PUSH_DATA (push, fifo->vram);
 351    PUSH_DATA (push, fifo->vram);
 352
 353    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 354    PUSH_DATA (push, screen->eng2d->handle);
 355    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 356    PUSH_DATA (push, screen->sync->handle);
 357    PUSH_DATA (push, fifo->vram);
 358    PUSH_DATA (push, fifo->vram);
 359    PUSH_DATA (push, fifo->vram);
 360    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 361    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 362    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 363    PUSH_DATA (push, 0);
 364    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 365    PUSH_DATA (push, 0);
 366    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 367    PUSH_DATA (push, 1);
 368
 369    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 370    PUSH_DATA (push, screen->tesla->handle);
 371
 372    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 373    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 374
 375    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 376    PUSH_DATA (push, screen->sync->handle);
 377    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 378    for (i = 0; i < 11; ++i)
 379       PUSH_DATA(push, fifo->vram);
 380    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 381    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 382       PUSH_DATA(push, fifo->vram);
 383
 384    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 385    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 386    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 387    PUSH_DATA (push, 0xf);
 388
 389    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 390       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 391       PUSH_DATA (push, 0x18);
 392    }
 393
 394    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 395    PUSH_DATA (push, 1);
 396
 397    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 398    PUSH_DATA (push, 0);
 399    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 400    PUSH_DATA (push, 0);
 401    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 402    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 403    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 404    PUSH_DATA (push, 0);
 405    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 406    PUSH_DATA (push, 0);
 407    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 408    PUSH_DATA (push, 1);
 409
 410    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 411       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 412       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 413    }
 414
 415    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 416    PUSH_DATA (push, 0);
 417    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 418    PUSH_DATA (push, 0);
 419    PUSH_DATA (push, 0);
 420    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 421    PUSH_DATA (push, 0x3f);
 422
 423    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 424    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 425    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 426
 427    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 428    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 429    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 430
 431    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 432    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 433    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 434
 435    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 436    PUSH_DATAh(push, screen->tls_bo->offset);
 437    PUSH_DATA (push, screen->tls_bo->offset);
 438    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 439
 440    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 441    PUSH_DATAh(push, screen->stack_bo->offset);
 442    PUSH_DATA (push, screen->stack_bo->offset);
 443    PUSH_DATA (push, 4);
 444
 445    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 446    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 447    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 448    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 449
 450    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 451    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 452    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 453    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 454
 455    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 456    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 457    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 458    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 459
 460    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 461    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 462    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 463    PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
 464
 465    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 466    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 467    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 468    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 469
 470    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 471    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 472    PUSH_DATA (push, ((1 << 9) << 6) | NV50_CB_AUX);
 473    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 474    PUSH_DATAf(push, 0.0f);
 475    PUSH_DATAf(push, 0.0f);
 476    PUSH_DATAf(push, 0.0f);
 477    PUSH_DATAf(push, 0.0f);
 478    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 479    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 480    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 481
 482    /* max TIC (bits 4:8) & TSC bindings, per program type */
 483    for (i = 0; i < 3; ++i) {
 484       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 485       PUSH_DATA (push, 0x54);
 486    }
 487
 488    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 489    PUSH_DATAh(push, screen->txc->offset);
 490    PUSH_DATA (push, screen->txc->offset);
 491    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 492
 493    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 494    PUSH_DATAh(push, screen->txc->offset + 65536);
 495    PUSH_DATA (push, screen->txc->offset + 65536);
 496    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 497
 498    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 499    PUSH_DATA (push, 0);
 500
 501    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 502    PUSH_DATA (push, 0);
 503    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 504    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 505    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 506    for (i = 0; i < 8 * 2; ++i)
 507       PUSH_DATA(push, 0);
 508    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 509    PUSH_DATA (push, 0);
 510
 511    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 512    PUSH_DATA (push, 1);
 513    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 514    PUSH_DATAf(push, 0.0f);
 515    PUSH_DATAf(push, 1.0f);
 516
 517    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 518 #ifdef NV50_SCISSORS_CLIPPING
 519    PUSH_DATA (push, 0x0000);
 520 #else
 521    PUSH_DATA (push, 0x1080);
 522 #endif
 523
 524    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 525    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 526
 527    /* We use scissors instead of exact view volume clipping,
 528     * so they're always enabled.
 529     */
 530    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 531    PUSH_DATA (push, 1);
 532    PUSH_DATA (push, 8192 << 16);
 533    PUSH_DATA (push, 8192 << 16);
 534
 535    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 536    PUSH_DATA (push, 1);
 537    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 538    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 539    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 540    PUSH_DATA (push, 0x11111111);
 541    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 542    PUSH_DATA (push, 1);
 543
 544    PUSH_KICK (push);
 545 }
 546
 547 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 548       uint64_t *tls_size)
 549 {
 550    struct nouveau_device *dev = screen->base.device;
 551    int ret;
 552
 553    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 554          ONE_TEMP_SIZE;
 555    if (nouveau_mesa_debug)
 556       debug_printf("allocating space for %u temps\n",
 557             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 558    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 559          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 560
 561    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 562                         *tls_size, NULL, &screen->tls_bo);
 563    if (ret) {
 564       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 565       return ret;
 566    }
 567
 568    return 0;
 569 }
 570
 571 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 572 {
 573    struct nouveau_pushbuf *push = screen->base.pushbuf;
 574    int ret;
 575    uint64_t tls_size;
 576
 577    if (tls_space < screen->cur_tls_space)
 578       return 0;
 579    if (tls_space > screen->max_tls_space) {
 580       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 581        * LOCAL_WARPS_NO_CLAMP) */
 582       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 583             (unsigned)(tls_space / ONE_TEMP_SIZE),
 584             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 585       return -ENOMEM;
 586    }
 587
 588    nouveau_bo_ref(NULL, &screen->tls_bo);
 589    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 590    if (ret)
 591       return ret;
 592
 593    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 594    PUSH_DATAh(push, screen->tls_bo->offset);
 595    PUSH_DATA (push, screen->tls_bo->offset);
 596    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 597
 598    return 1;
 599 }
 600
 601 struct pipe_screen *
 602 nv50_screen_create(struct nouveau_device *dev)
 603 {
 604    struct nv50_screen *screen;
 605    struct pipe_screen *pscreen;
 606    struct nouveau_object *chan;
 607    uint64_t value;
 608    uint32_t tesla_class;
 609    unsigned stack_size;
 610    int ret;
 611
 612    screen = CALLOC_STRUCT(nv50_screen);
 613    if (!screen)
 614       return NULL;
 615    pscreen = &screen->base.base;
 616
 617    ret = nouveau_screen_init(&screen->base, dev);
 618    if (ret) {
 619       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 620       goto fail;
 621    }
 622
 623    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 624     *  admit them to VRAM.
 625     */
 626    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 627       PIPE_BIND_VERTEX_BUFFER;
 628    screen->base.sysmem_bindings |=
 629       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 630
 631    screen->base.pushbuf->user_priv = screen;
 632    screen->base.pushbuf->rsvd_kick = 5;
 633
 634    chan = screen->base.channel;
 635
 636    pscreen->destroy = nv50_screen_destroy;
 637    pscreen->context_create = nv50_create;
 638    pscreen->is_format_supported = nv50_screen_is_format_supported;
 639    pscreen->get_param = nv50_screen_get_param;
 640    pscreen->get_shader_param = nv50_screen_get_shader_param;
 641    pscreen->get_paramf = nv50_screen_get_paramf;
 642
 643    nv50_screen_init_resource_functions(pscreen);
 644
 645    nouveau_screen_init_vdec(&screen->base);
 646
 647    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 648                         NULL, &screen->fence.bo);
 649    if (ret) {
 650       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 651       goto fail;
 652    }
 653
 654    nouveau_bo_map(screen->fence.bo, 0, NULL);
 655    screen->fence.map = screen->fence.bo->map;
 656    screen->base.fence.emit = nv50_screen_fence_emit;
 657    screen->base.fence.update = nv50_screen_fence_update;
 658
 659    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 660                             &(struct nv04_notify){ .length = 32 },
 661                             sizeof(struct nv04_notify), &screen->sync);
 662    if (ret) {
 663       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 664       goto fail;
 665    }
 666
 667    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 668                             NULL, 0, &screen->m2mf);
 669    if (ret) {
 670       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 671       goto fail;
 672    }
 673
 674    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 675                             NULL, 0, &screen->eng2d);
 676    if (ret) {
 677       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 678       goto fail;
 679    }
 680
 681    switch (dev->chipset & 0xf0) {
 682    case 0x50:
 683       tesla_class = NV50_3D_CLASS;
 684       break;
 685    case 0x80:
 686    case 0x90:
 687       tesla_class = NV84_3D_CLASS;
 688       break;
 689    case 0xa0:
 690       switch (dev->chipset) {
 691       case 0xa0:
 692       case 0xaa:
 693       case 0xac:
 694          tesla_class = NVA0_3D_CLASS;
 695          break;
 696       case 0xaf:
 697          tesla_class = NVAF_3D_CLASS;
 698          break;
 699       default:
 700          tesla_class = NVA3_3D_CLASS;
 701          break;
 702       }
 703       break;
 704    default:
 705       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 706       goto fail;
 707    }
 708    screen->base.class_3d = tesla_class;
 709
 710    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 711                             NULL, 0, &screen->tesla);
 712    if (ret) {
 713       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 714       goto fail;
 715    }
 716
 717    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 718                         3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 719    if (ret) {
 720       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 721       goto fail;
 722    }
 723
 724    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 725    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 726    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 727
 728    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 729
 730    screen->TPs = util_bitcount(value & 0xffff);
 731    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 732
 733    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 734          STACK_WARPS_ALLOC * 64 * 8;
 735
 736    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 737                         &screen->stack_bo);
 738    if (ret) {
 739       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 740       goto fail;
 741    }
 742
 743    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 744          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 745          ONE_TEMP_SIZE;
 746    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 747    screen->max_tls_space /= 2; /* half of vram */
 748
 749    /* hw can address max 64 KiB */
 750    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 751
 752    uint64_t tls_size;
 753    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 754    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 755    if (ret)
 756       goto fail;
 757
 758    if (nouveau_mesa_debug)
 759       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 760             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 761
 762    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 763                         &screen->uniforms);
 764    if (ret) {
 765       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 766       goto fail;
 767    }
 768
 769    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 770                         &screen->txc);
 771    if (ret) {
 772       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 773       goto fail;
 774    }
 775
 776    screen->tic.entries = CALLOC(4096, sizeof(void *));
 777    screen->tsc.entries = screen->tic.entries + 2048;
 778
 779    if (!nv50_blitter_create(screen))
 780       goto fail;
 781
 782    nv50_screen_init_hwctx(screen);
 783
 784    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 785
 786    return pscreen;
 787
 788 fail:
 789    nv50_screen_destroy(pscreen);
 790    return NULL;
 791 }
 792
 793 int
 794 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 795 {
 796    int i = screen->tic.next;
 797
 798    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 799       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 800
 801    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 802
 803    if (screen->tic.entries[i])
 804       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 805
 806    screen->tic.entries[i] = entry;
 807    return i;
 808 }
 809
 810 int
 811 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 812 {
 813    int i = screen->tsc.next;
 814
 815    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 816       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 817
 818    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 819
 820    if (screen->tsc.entries[i])
 821       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 822
 823    screen->tsc.entries[i] = entry;
 824    return i;
 825 }