src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nv50_context.h"
  27 #include "nv50_screen.h"
  28 #include "nv50_resource.h"
  29
  30 #include "nouveau/nouveau_stateobj.h"
  31
  32 static boolean
  33 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  34                                 enum pipe_format format,
  35                                 enum pipe_texture_target target,
  36                                 unsigned sample_count,
  37                                 unsigned usage, unsigned geom_flags)
  38 {
  39         if (sample_count > 1)
  40                 return FALSE;
  41
  42         if (!util_format_s3tc_enabled) {
  43                 switch (format) {
  44                 case PIPE_FORMAT_DXT1_RGB:
  45                 case PIPE_FORMAT_DXT1_RGBA:
  46                 case PIPE_FORMAT_DXT3_RGBA:
  47                 case PIPE_FORMAT_DXT5_RGBA:
  48                         return FALSE;
  49                 default:
  50                         break;
  51                 }
  52         }
  53
  54         switch (format) {
  55         case PIPE_FORMAT_Z16_UNORM:
  56                 if ((nouveau_screen(pscreen)->device->chipset & 0xf0) != 0xa0)
  57                         return FALSE;
  58                 break;
  59         default:
  60                 break;
  61         }
  62
  63         /* transfers & shared are always supported */
  64         usage &= ~(PIPE_BIND_TRANSFER_READ |
  65                    PIPE_BIND_TRANSFER_WRITE |
  66                    PIPE_BIND_SHARED);
  67
  68         return (nv50_format_table[format].usage & usage) == usage;
  69 }
  70
  71 static int
  72 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  73 {
  74         switch (param) {
  75         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  76                 return 32;
  77         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  78                 return 32;
  79         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  80                 return 64;
  81         case PIPE_CAP_NPOT_TEXTURES:
  82                 return 1;
  83         case PIPE_CAP_TWO_SIDED_STENCIL:
  84                 return 1;
  85         case PIPE_CAP_GLSL:
  86                 return 1;
  87         case PIPE_CAP_ANISOTROPIC_FILTER:
  88                 return 1;
  89         case PIPE_CAP_POINT_SPRITE:
  90                 return 1;
  91         case PIPE_CAP_MAX_RENDER_TARGETS:
  92                 return 8;
  93         case PIPE_CAP_OCCLUSION_QUERY:
  94                 return 1;
  95         case PIPE_CAP_TIMER_QUERY:
  96                 return 0;
  97         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  98                 return 1;
  99         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 100                 return 13;
 101         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 102                 return 10;
 103         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 104                 return 13;
 105         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 106         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
 107                 return 1;
 108         case PIPE_CAP_TGSI_CONT_SUPPORTED:
 109                 return 1;
 110         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 111                 return 1;
 112         case PIPE_CAP_INDEP_BLEND_ENABLE:
 113                 return 1;
 114         case PIPE_CAP_INDEP_BLEND_FUNC:
 115                 return 0;
 116         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 117                 return 1;
 118         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 119         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 120                 return 1;
 121         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 122         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 123                 return 0;
 124         case PIPE_CAP_MAX_VS_INSTRUCTIONS:
 125         case PIPE_CAP_MAX_FS_INSTRUCTIONS:
 126         case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS:
 127         case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS:
 128         case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS:
 129         case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS:
 130         case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS:
 131         case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS: /* arbitrary limit */
 132                 return 16384;
 133         case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH:
 134         case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH: /* need stack bo */
 135                 return 4;
 136         case PIPE_CAP_MAX_VS_INPUTS:
 137                 return 16;
 138         case PIPE_CAP_MAX_FS_INPUTS: /* 128 / 4 with GP */
 139                 return 64 / 4;
 140         case PIPE_CAP_MAX_VS_CONSTS:
 141         case PIPE_CAP_MAX_FS_CONSTS:
 142                 return 65536 / 16;
 143         case PIPE_CAP_MAX_VS_ADDRS:
 144         case PIPE_CAP_MAX_FS_ADDRS: /* no spilling atm */
 145                 return 1;
 146         case PIPE_CAP_MAX_VS_PREDS:
 147         case PIPE_CAP_MAX_FS_PREDS: /* not yet handled */
 148                 return 0;
 149         case PIPE_CAP_MAX_VS_TEMPS:
 150         case PIPE_CAP_MAX_FS_TEMPS: /* no spilling atm */
 151                 return 128 / 4;
 152         case PIPE_CAP_DEPTH_CLAMP:
 153                 return 1;
 154         default:
 155                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 156                 return 0;
 157         }
 158 }
 159
 160 static float
 161 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 162 {
 163         switch (param) {
 164         case PIPE_CAP_MAX_LINE_WIDTH:
 165         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 166                 return 10.0;
 167         case PIPE_CAP_MAX_POINT_WIDTH:
 168         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 169                 return 64.0;
 170         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 171                 return 16.0;
 172         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 173                 return 4.0;
 174         default:
 175                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 176                 return 0.0;
 177         }
 178 }
 179
 180 static void
 181 nv50_screen_destroy(struct pipe_screen *pscreen)
 182 {
 183         struct nv50_screen *screen = nv50_screen(pscreen);
 184         unsigned i;
 185
 186         for (i = 0; i < 3; i++) {
 187                 if (screen->constbuf_parm[i])
 188                         nouveau_bo_ref(NULL, &screen->constbuf_parm[i]);
 189         }
 190
 191         if (screen->constbuf_misc[0])
 192                 nouveau_bo_ref(NULL, &screen->constbuf_misc[0]);
 193         if (screen->tic)
 194                 nouveau_bo_ref(NULL, &screen->tic);
 195         if (screen->tsc)
 196                 nouveau_bo_ref(NULL, &screen->tsc);
 197
 198         nouveau_notifier_free(&screen->sync);
 199         nouveau_grobj_free(&screen->tesla);
 200         nouveau_grobj_free(&screen->eng2d);
 201         nouveau_grobj_free(&screen->m2mf);
 202         nouveau_resource_destroy(&screen->immd_heap);
 203         nouveau_screen_fini(&screen->base);
 204         FREE(screen);
 205 }
 206
 207 #define BGN_RELOC(ch, bo, gr, m, n, fl) \
 208    OUT_RELOC(ch, bo, (n << 18) | (gr->subc << 13) | m, fl, 0, 0)
 209
 210 void
 211 nv50_screen_relocs(struct nv50_screen *screen)
 212 {
 213         struct nouveau_channel *chan = screen->base.channel;
 214         struct nouveau_grobj *tesla = screen->tesla;
 215         unsigned i;
 216         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
 217
 218         MARK_RING (chan, 28, 26);
 219
 220         /* cause grobj autobind */
 221         BEGIN_RING(chan, tesla, 0x0100, 1);
 222         OUT_RING  (chan, 0);
 223
 224         BGN_RELOC (chan, screen->tic, tesla, NV50TCL_TIC_ADDRESS_HIGH, 2, rl);
 225         OUT_RELOCh(chan, screen->tic, 0, rl);
 226         OUT_RELOCl(chan, screen->tic, 0, rl);
 227
 228         BGN_RELOC (chan, screen->tsc, tesla, NV50TCL_TSC_ADDRESS_HIGH, 2, rl);
 229         OUT_RELOCh(chan, screen->tsc, 0, rl);
 230         OUT_RELOCl(chan, screen->tsc, 0, rl);
 231
 232         BGN_RELOC (chan, screen->constbuf_misc[0],
 233                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 234         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 235         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 236         OUT_RELOC (chan, screen->constbuf_misc[0],
 237                    (NV50_CB_PMISC << 16) | 0x0200, rl, 0, 0);
 238
 239         BGN_RELOC (chan, screen->constbuf_misc[0],
 240                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 241         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 242         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 243         OUT_RELOC (chan, screen->constbuf_misc[0],
 244                    (NV50_CB_AUX << 16) | 0x0200, rl, 0, 0);
 245
 246         for (i = 0; i < 3; ++i) {
 247                 BGN_RELOC (chan, screen->constbuf_parm[i],
 248                            tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 249                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 250                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 251                 OUT_RELOC (chan, screen->constbuf_parm[i],
 252                            ((NV50_CB_PVP + i) << 16) | 0x0000, rl, 0, 0);
 253         }
 254 }
 255
 256 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
 257 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
 258 #endif
 259
 260 extern int nouveau_device_get_param(struct nouveau_device *dev,
 261                                     uint64_t param, uint64_t *value);
 262
 263 struct pipe_screen *
 264 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 265 {
 266         struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen);
 267         struct nouveau_channel *chan;
 268         struct pipe_screen *pscreen;
 269         uint64_t value;
 270         unsigned chipset = dev->chipset;
 271         unsigned tesla_class = 0;
 272         unsigned stack_size;
 273         int ret, i;
 274         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 275
 276         if (!screen)
 277                 return NULL;
 278         pscreen = &screen->base.base;
 279
 280         ret = nouveau_screen_init(&screen->base, dev);
 281         if (ret) {
 282                 nv50_screen_destroy(pscreen);
 283                 return NULL;
 284         }
 285         chan = screen->base.channel;
 286
 287         pscreen->winsys = ws;
 288         pscreen->destroy = nv50_screen_destroy;
 289         pscreen->get_param = nv50_screen_get_param;
 290         pscreen->get_paramf = nv50_screen_get_paramf;
 291         pscreen->is_format_supported = nv50_screen_is_format_supported;
 292         pscreen->context_create = nv50_create;
 293
 294         nv50_screen_init_resource_functions(pscreen);
 295
 296         /* DMA engine object */
 297         ret = nouveau_grobj_alloc(chan, 0xbeef5039,
 298                 NV50_MEMORY_TO_MEMORY_FORMAT, &screen->m2mf);
 299         if (ret) {
 300                 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret);
 301                 nv50_screen_destroy(pscreen);
 302                 return NULL;
 303         }
 304
 305         /* 2D object */
 306         ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 307         if (ret) {
 308                 NOUVEAU_ERR("Error creating 2D object: %d\n", ret);
 309                 nv50_screen_destroy(pscreen);
 310                 return NULL;
 311         }
 312
 313         /* 3D object */
 314         switch (chipset & 0xf0) {
 315         case 0x50:
 316                 tesla_class = NV50TCL;
 317                 break;
 318         case 0x80:
 319         case 0x90:
 320                 tesla_class = NV84TCL;
 321                 break;
 322         case 0xa0:
 323                 switch (chipset) {
 324                 case 0xa0:
 325                 case 0xaa:
 326                 case 0xac:
 327                         tesla_class = NVA0TCL;
 328                         break;
 329                 default:
 330                         tesla_class = NVA8TCL;
 331                         break;
 332                 }
 333                 break;
 334         default:
 335                 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset);
 336                 nv50_screen_destroy(pscreen);
 337                 return NULL;
 338         }
 339
 340         ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class,
 341                 &screen->tesla);
 342         if (ret) {
 343                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 344                 nv50_screen_destroy(pscreen);
 345                 return NULL;
 346         }
 347
 348         /* this is necessary for the new RING_3D / statebuffer code */
 349         BIND_RING(chan, screen->tesla, 7);
 350
 351         /* Sync notifier */
 352         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 353         if (ret) {
 354                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 355                 nv50_screen_destroy(pscreen);
 356                 return NULL;
 357         }
 358
 359         /* Static M2MF init */
 360         BEGIN_RING(chan, screen->m2mf,
 361                    NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 362         OUT_RING  (chan, screen->sync->handle);
 363         OUT_RING  (chan, chan->vram->handle);
 364         OUT_RING  (chan, chan->vram->handle);
 365
 366         /* Static 2D init */
 367         BEGIN_RING(chan, screen->eng2d, NV50_2D_DMA_NOTIFY, 4);
 368         OUT_RING  (chan, screen->sync->handle);
 369         OUT_RING  (chan, chan->vram->handle);
 370         OUT_RING  (chan, chan->vram->handle);
 371         OUT_RING  (chan, chan->vram->handle);
 372         BEGIN_RING(chan, screen->eng2d, NV50_2D_OPERATION, 1);
 373         OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 374         BEGIN_RING(chan, screen->eng2d, NV50_2D_CLIP_ENABLE, 1);
 375         OUT_RING  (chan, 0);
 376         BEGIN_RING(chan, screen->eng2d, 0x0888, 1);
 377         OUT_RING  (chan, 1);
 378
 379         /* Static tesla init */
 380         BEGIN_RING(chan, screen->tesla, NV50TCL_COND_MODE, 1);
 381         OUT_RING  (chan, NV50TCL_COND_MODE_ALWAYS);
 382         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
 383         OUT_RING  (chan, screen->sync->handle);
 384         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_ZETA, 11);
 385         for (i = 0; i < 11; i++)
 386                 OUT_RING  (chan, chan->vram->handle);
 387         BEGIN_RING(chan, screen->tesla,
 388                    NV50TCL_DMA_COLOR(0), NV50TCL_DMA_COLOR__SIZE);
 389         for (i = 0; i < NV50TCL_DMA_COLOR__SIZE; i++)
 390                 OUT_RING  (chan, chan->vram->handle);
 391
 392         BEGIN_RING(chan, screen->tesla, NV50TCL_RT_CONTROL, 1);
 393         OUT_RING  (chan, 1);
 394
 395         /* activate all 32 lanes (threads) in a warp */
 396         BEGIN_RING(chan, screen->tesla, NV50TCL_REG_MODE, 1);
 397         OUT_RING  (chan, NV50TCL_REG_MODE_STRIPED);
 398         BEGIN_RING(chan, screen->tesla, 0x1400, 1);
 399         OUT_RING  (chan, 0xf);
 400
 401         /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
 402         for (i = 0; i < 3; ++i) {
 403                 BEGIN_RING(chan, screen->tesla, NV50TCL_TEX_LIMITS(i), 1);
 404                 OUT_RING  (chan, 0x54);
 405         }
 406
 407         /* origin is top left (set to 1 for bottom left) */
 408         BEGIN_RING(chan, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1);
 409         OUT_RING  (chan, 0);
 410         BEGIN_RING(chan, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
 411         OUT_RING  (chan, 8);
 412
 413         /* constant buffers for immediates and VP/FP parameters */
 414         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (32 * 4) * 4,
 415                              &screen->constbuf_misc[0]);
 416         if (ret) {
 417                 nv50_screen_destroy(pscreen);
 418                 return NULL;
 419         }
 420         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 421         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 422         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 423         OUT_RING  (chan, (NV50_CB_PMISC << 16) | 0x0200);
 424         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 425         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 426         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 427         OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 428
 429         for (i = 0; i < 3; i++) {
 430                 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (4096 * 4) * 4,
 431                                      &screen->constbuf_parm[i]);
 432                 if (ret) {
 433                         nv50_screen_destroy(pscreen);
 434                         return NULL;
 435                 }
 436                 BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 437                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 438                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 439                 /* CB_DEF_SET_SIZE value of 0x0000 means 65536 */
 440                 OUT_RING  (chan, ((NV50_CB_PVP + i) << 16) | 0x0000);
 441         }
 442
 443         if (nouveau_resource_init(&screen->immd_heap, 0, 128)) {
 444                 NOUVEAU_ERR("Error initialising shader immediates heap.\n");
 445                 nv50_screen_destroy(pscreen);
 446                 return NULL;
 447         }
 448
 449         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 450                              &screen->tic);
 451         if (ret) {
 452                 nv50_screen_destroy(pscreen);
 453                 return NULL;
 454         }
 455         BEGIN_RING(chan, screen->tesla, NV50TCL_TIC_ADDRESS_HIGH, 3);
 456         OUT_RELOCh(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 457         OUT_RELOCl(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 458         OUT_RING  (chan, 3 * 32 - 1);
 459
 460         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 461                              &screen->tsc);
 462         if (ret) {
 463                 nv50_screen_destroy(pscreen);
 464                 return NULL;
 465         }
 466         BEGIN_RING(chan, screen->tesla, NV50TCL_TSC_ADDRESS_HIGH, 3);
 467         OUT_RELOCh(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 468         OUT_RELOCl(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 469         OUT_RING  (chan, 0); /* ignored if TSC_LINKED (0x1234) == 1 */
 470
 471         /* map constant buffers:
 472          *  B = buffer ID (maybe more than 1 byte)
 473          *  N = CB index used in shader instruction
 474          *  P = program type (0 = VP, 2 = GP, 3 = FP)
 475          * SET_PROGRAM_CB = 0x000BBNP1
 476          */
 477         BEGIN_RING_NI(chan, screen->tesla, NV50TCL_SET_PROGRAM_CB, 8);
 478         /* bind immediate buffer */
 479         OUT_RING  (chan, 0x001 | (NV50_CB_PMISC << 12));
 480         OUT_RING  (chan, 0x021 | (NV50_CB_PMISC << 12));
 481         OUT_RING  (chan, 0x031 | (NV50_CB_PMISC << 12));
 482         /* bind auxiliary constbuf to immediate data bo */
 483         OUT_RING  (chan, 0x201 | (NV50_CB_AUX << 12));
 484         OUT_RING  (chan, 0x221 | (NV50_CB_AUX << 12));
 485         /* bind parameter buffers */
 486         OUT_RING  (chan, 0x101 | (NV50_CB_PVP << 12));
 487         OUT_RING  (chan, 0x121 | (NV50_CB_PGP << 12));
 488         OUT_RING  (chan, 0x131 | (NV50_CB_PFP << 12));
 489
 490         /* shader stack */
 491         nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 492
 493         stack_size  = util_bitcount(value & 0xffff);
 494         stack_size *= util_bitcount((value >> 24) & 0xf);
 495         stack_size *= 32 * 64 * 8;
 496
 497         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 498                              stack_size, &screen->stack_bo);
 499         if (ret) {
 500                 nv50_screen_destroy(pscreen);
 501                 return NULL;
 502         }
 503         BEGIN_RING(chan, screen->tesla, NV50TCL_STACK_ADDRESS_HIGH, 3);
 504         OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 505         OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
 506         OUT_RING  (chan, 4);
 507
 508         /* Vertex array limits - max them out */
 509         for (i = 0; i < 16; i++) {
 510                 BEGIN_RING(chan, screen->tesla,
 511                            NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
 512                 OUT_RING  (chan, 0x000000ff);
 513                 OUT_RING  (chan, 0xffffffff);
 514         }
 515
 516         BEGIN_RING(chan, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
 517         OUT_RINGf (chan, 0.0f);
 518         OUT_RINGf (chan, 1.0f);
 519
 520         BEGIN_RING(chan, screen->tesla, NV50TCL_VIEWPORT_TRANSFORM_EN, 1);
 521         OUT_RING  (chan, 1);
 522
 523         /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
 524         BEGIN_RING(chan, screen->tesla, NV50TCL_LINKED_TSC, 1);
 525         OUT_RING  (chan, 1);
 526
 527         BEGIN_RING(chan, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
 528         OUT_RING  (chan, 1); /* default edgeflag to TRUE */
 529
 530         FIRE_RING (chan);
 531
 532         screen->force_push = debug_get_bool_option("NV50_ALWAYS_PUSH", FALSE);
 533         if(!screen->force_push)
 534                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = NOUVEAU_BO_GART;
 535         return pscreen;
 536 }
 537