src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "pipe/p_screen.h"
  24
  25 #include "nv50_context.h"
  26 #include "nv50_screen.h"
  27 #include "nv50_resource.h"
  28
  29 #include "nouveau/nouveau_stateobj.h"
  30
  31 static boolean
  32 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  33                                 enum pipe_format format,
  34                                 enum pipe_texture_target target,
  35                                 unsigned tex_usage, unsigned geom_flags)
  36 {
  37         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
  38                 switch (format) {
  39                 case PIPE_FORMAT_B8G8R8X8_UNORM:
  40                 case PIPE_FORMAT_B8G8R8A8_UNORM:
  41                 case PIPE_FORMAT_B5G6R5_UNORM:
  42                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  43                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  44                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  45                 case PIPE_FORMAT_R16G16_SNORM:
  46                 case PIPE_FORMAT_R16G16_UNORM:
  47                         return TRUE;
  48                 default:
  49                         break;
  50                 }
  51         } else
  52         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
  53                 switch (format) {
  54                 case PIPE_FORMAT_Z32_FLOAT:
  55                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
  56                 case PIPE_FORMAT_Z24X8_UNORM:
  57                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
  58                         return TRUE;
  59                 default:
  60                         break;
  61                 }
  62         } else {
  63                 switch (format) {
  64                 case PIPE_FORMAT_B8G8R8A8_UNORM:
  65                 case PIPE_FORMAT_B8G8R8X8_UNORM:
  66                 case PIPE_FORMAT_B8G8R8A8_SRGB:
  67                 case PIPE_FORMAT_B8G8R8X8_SRGB:
  68                 case PIPE_FORMAT_B5G5R5A1_UNORM:
  69                 case PIPE_FORMAT_B4G4R4A4_UNORM:
  70                 case PIPE_FORMAT_B5G6R5_UNORM:
  71                 case PIPE_FORMAT_L8_UNORM:
  72                 case PIPE_FORMAT_A8_UNORM:
  73                 case PIPE_FORMAT_I8_UNORM:
  74                 case PIPE_FORMAT_L8A8_UNORM:
  75                 case PIPE_FORMAT_DXT1_RGB:
  76                 case PIPE_FORMAT_DXT1_RGBA:
  77                 case PIPE_FORMAT_DXT3_RGBA:
  78                 case PIPE_FORMAT_DXT5_RGBA:
  79                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
  80                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
  81                 case PIPE_FORMAT_Z32_FLOAT:
  82                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  83                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  84                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  85                 case PIPE_FORMAT_R16G16_SNORM:
  86                 case PIPE_FORMAT_R16G16_UNORM:
  87                         return TRUE;
  88                 default:
  89                         break;
  90                 }
  91         }
  92
  93         return FALSE;
  94 }
  95
  96 static int
  97 nv50_screen_get_param(struct pipe_screen *pscreen, int param)
  98 {
  99         struct nv50_screen *screen = nv50_screen(pscreen);
 100
 101         switch (param) {
 102         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 103                 return 32;
 104         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 105                 return 32;
 106         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 107                 return 64;
 108         case PIPE_CAP_NPOT_TEXTURES:
 109                 return 1;
 110         case PIPE_CAP_TWO_SIDED_STENCIL:
 111                 return 1;
 112         case PIPE_CAP_GLSL:
 113                 return 1;
 114         case PIPE_CAP_ANISOTROPIC_FILTER:
 115                 return 1;
 116         case PIPE_CAP_POINT_SPRITE:
 117                 return 1;
 118         case PIPE_CAP_MAX_RENDER_TARGETS:
 119                 return 8;
 120         case PIPE_CAP_OCCLUSION_QUERY:
 121                 return 1;
 122         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 123                 return 1;
 124         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 125                 return 13;
 126         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 127                 return 10;
 128         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 129                 return 13;
 130         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 131         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
 132                 return 1;
 133         case PIPE_CAP_TGSI_CONT_SUPPORTED:
 134                 return 1;
 135         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 136                 return 1;
 137         case PIPE_CAP_INDEP_BLEND_ENABLE:
 138                 return 1;
 139         case PIPE_CAP_INDEP_BLEND_FUNC:
 140                 return 0;
 141         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 142         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 143                 return 1;
 144         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 145         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 146                 return 0;
 147         default:
 148                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 149                 return 0;
 150         }
 151 }
 152
 153 static float
 154 nv50_screen_get_paramf(struct pipe_screen *pscreen, int param)
 155 {
 156         switch (param) {
 157         case PIPE_CAP_MAX_LINE_WIDTH:
 158         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 159                 return 10.0;
 160         case PIPE_CAP_MAX_POINT_WIDTH:
 161         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 162                 return 64.0;
 163         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 164                 return 16.0;
 165         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 166                 return 4.0;
 167         default:
 168                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 169                 return 0.0;
 170         }
 171 }
 172
 173 static void
 174 nv50_screen_destroy(struct pipe_screen *pscreen)
 175 {
 176         struct nv50_screen *screen = nv50_screen(pscreen);
 177         unsigned i;
 178
 179         for (i = 0; i < 3; i++) {
 180                 if (screen->constbuf_parm[i])
 181                         nouveau_bo_ref(NULL, &screen->constbuf_parm[i]);
 182         }
 183
 184         if (screen->constbuf_misc[0])
 185                 nouveau_bo_ref(NULL, &screen->constbuf_misc[0]);
 186         if (screen->tic)
 187                 nouveau_bo_ref(NULL, &screen->tic);
 188         if (screen->tsc)
 189                 nouveau_bo_ref(NULL, &screen->tsc);
 190
 191         nouveau_notifier_free(&screen->sync);
 192         nouveau_grobj_free(&screen->tesla);
 193         nouveau_grobj_free(&screen->eng2d);
 194         nouveau_grobj_free(&screen->m2mf);
 195         nouveau_resource_destroy(&screen->immd_heap[0]);
 196         nouveau_resource_destroy(&screen->parm_heap[0]);
 197         nouveau_resource_destroy(&screen->parm_heap[1]);
 198         nouveau_screen_fini(&screen->base);
 199         FREE(screen);
 200 }
 201
 202 #define BGN_RELOC(ch, bo, gr, m, n, fl) \
 203    OUT_RELOC(ch, bo, (n << 18) | (gr->subc << 13) | m, fl, 0, 0)
 204
 205 void
 206 nv50_screen_relocs(struct nv50_screen *screen)
 207 {
 208         struct nouveau_channel *chan = screen->base.channel;
 209         struct nouveau_grobj *tesla = screen->tesla;
 210         unsigned i;
 211         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
 212
 213         MARK_RING (chan, 28, 26);
 214
 215         /* cause grobj autobind */
 216         BEGIN_RING(chan, tesla, 0x0100, 1);
 217         OUT_RING  (chan, 0);
 218
 219         BGN_RELOC (chan, screen->tic, tesla, NV50TCL_TIC_ADDRESS_HIGH, 2, rl);
 220         OUT_RELOCh(chan, screen->tic, 0, rl);
 221         OUT_RELOCl(chan, screen->tic, 0, rl);
 222
 223         BGN_RELOC (chan, screen->tsc, tesla, NV50TCL_TSC_ADDRESS_HIGH, 2, rl);
 224         OUT_RELOCh(chan, screen->tsc, 0, rl);
 225         OUT_RELOCl(chan, screen->tsc, 0, rl);
 226
 227         BGN_RELOC (chan, screen->constbuf_misc[0],
 228                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 229         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 230         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 231         OUT_RELOC (chan, screen->constbuf_misc[0],
 232                    (NV50_CB_PMISC << 16) | 0x0200, rl, 0, 0);
 233
 234         BGN_RELOC (chan, screen->constbuf_misc[0],
 235                    tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 236         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 237         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 238         OUT_RELOC (chan, screen->constbuf_misc[0],
 239                    (NV50_CB_AUX << 16) | 0x0200, rl, 0, 0);
 240
 241         for (i = 0; i < 3; ++i) {
 242                 BGN_RELOC (chan, screen->constbuf_parm[i],
 243                            tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3, rl);
 244                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 245                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 246                 OUT_RELOC (chan, screen->constbuf_parm[i],
 247                            ((NV50_CB_PVP + i) << 16) | 0x0800, rl, 0, 0);
 248         }
 249 }
 250
 251 struct pipe_screen *
 252 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 253 {
 254         struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen);
 255         struct nouveau_channel *chan;
 256         struct pipe_screen *pscreen;
 257         unsigned chipset = dev->chipset;
 258         unsigned tesla_class = 0;
 259         int ret, i;
 260         const unsigned rl = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 261
 262         if (!screen)
 263                 return NULL;
 264         pscreen = &screen->base.base;
 265
 266         ret = nouveau_screen_init(&screen->base, dev);
 267         if (ret) {
 268                 nv50_screen_destroy(pscreen);
 269                 return NULL;
 270         }
 271         chan = screen->base.channel;
 272
 273         pscreen->winsys = ws;
 274         pscreen->destroy = nv50_screen_destroy;
 275         pscreen->get_param = nv50_screen_get_param;
 276         pscreen->get_paramf = nv50_screen_get_paramf;
 277         pscreen->is_format_supported = nv50_screen_is_format_supported;
 278         pscreen->context_create = nv50_create;
 279
 280         nv50_screen_init_resource_functions(pscreen);
 281
 282         /* DMA engine object */
 283         ret = nouveau_grobj_alloc(chan, 0xbeef5039,
 284                 NV50_MEMORY_TO_MEMORY_FORMAT, &screen->m2mf);
 285         if (ret) {
 286                 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret);
 287                 nv50_screen_destroy(pscreen);
 288                 return NULL;
 289         }
 290
 291         /* 2D object */
 292         ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 293         if (ret) {
 294                 NOUVEAU_ERR("Error creating 2D object: %d\n", ret);
 295                 nv50_screen_destroy(pscreen);
 296                 return NULL;
 297         }
 298
 299         /* 3D object */
 300         switch (chipset & 0xf0) {
 301         case 0x50:
 302                 tesla_class = NV50TCL;
 303                 break;
 304         case 0x80:
 305         case 0x90:
 306                 tesla_class = NV84TCL;
 307                 break;
 308         case 0xa0:
 309                 switch (chipset) {
 310                 case 0xa0:
 311                 case 0xaa:
 312                 case 0xac:
 313                         tesla_class = NVA0TCL;
 314                         break;
 315                 default:
 316                         tesla_class = NVA8TCL;
 317                         break;
 318                 }
 319                 break;
 320         default:
 321                 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset);
 322                 nv50_screen_destroy(pscreen);
 323                 return NULL;
 324         }
 325
 326         ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class,
 327                 &screen->tesla);
 328         if (ret) {
 329                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 330                 nv50_screen_destroy(pscreen);
 331                 return NULL;
 332         }
 333
 334         /* this is necessary for the new RING_3D / statebuffer code */
 335         BIND_RING(chan, screen->tesla, 7);
 336
 337         /* Sync notifier */
 338         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 339         if (ret) {
 340                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 341                 nv50_screen_destroy(pscreen);
 342                 return NULL;
 343         }
 344
 345         /* Static M2MF init */
 346         BEGIN_RING(chan, screen->m2mf,
 347                    NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 348         OUT_RING  (chan, screen->sync->handle);
 349         OUT_RING  (chan, chan->vram->handle);
 350         OUT_RING  (chan, chan->vram->handle);
 351
 352         /* Static 2D init */
 353         BEGIN_RING(chan, screen->eng2d, NV50_2D_DMA_NOTIFY, 4);
 354         OUT_RING  (chan, screen->sync->handle);
 355         OUT_RING  (chan, chan->vram->handle);
 356         OUT_RING  (chan, chan->vram->handle);
 357         OUT_RING  (chan, chan->vram->handle);
 358         BEGIN_RING(chan, screen->eng2d, NV50_2D_OPERATION, 1);
 359         OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 360         BEGIN_RING(chan, screen->eng2d, NV50_2D_CLIP_ENABLE, 1);
 361         OUT_RING  (chan, 0);
 362         BEGIN_RING(chan, screen->eng2d, 0x0888, 1);
 363         OUT_RING  (chan, 1);
 364
 365         /* Static tesla init */
 366         BEGIN_RING(chan, screen->tesla, NV50TCL_COND_MODE, 1);
 367         OUT_RING  (chan, NV50TCL_COND_MODE_ALWAYS);
 368         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
 369         OUT_RING  (chan, screen->sync->handle);
 370         BEGIN_RING(chan, screen->tesla, NV50TCL_DMA_ZETA, 11);
 371         for (i = 0; i < 11; i++)
 372                 OUT_RING  (chan, chan->vram->handle);
 373         BEGIN_RING(chan, screen->tesla,
 374                    NV50TCL_DMA_COLOR(0), NV50TCL_DMA_COLOR__SIZE);
 375         for (i = 0; i < NV50TCL_DMA_COLOR__SIZE; i++)
 376                 OUT_RING  (chan, chan->vram->handle);
 377
 378         BEGIN_RING(chan, screen->tesla, NV50TCL_RT_CONTROL, 1);
 379         OUT_RING  (chan, 1);
 380
 381         /* activate all 32 lanes (threads) in a warp */
 382         BEGIN_RING(chan, screen->tesla, NV50TCL_REG_MODE, 1);
 383         OUT_RING  (chan, NV50TCL_REG_MODE_STRIPED);
 384         BEGIN_RING(chan, screen->tesla, 0x1400, 1);
 385         OUT_RING  (chan, 0xf);
 386
 387         /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
 388         for (i = 0; i < 3; ++i) {
 389                 BEGIN_RING(chan, screen->tesla, NV50TCL_TEX_LIMITS(i), 1);
 390                 OUT_RING  (chan, 0x54);
 391         }
 392
 393         /* origin is top left (set to 1 for bottom left) */
 394         BEGIN_RING(chan, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1);
 395         OUT_RING  (chan, 0);
 396         BEGIN_RING(chan, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
 397         OUT_RING  (chan, 8);
 398
 399         /* constant buffers for immediates and VP/FP parameters */
 400         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (32 * 4) * 4,
 401                              &screen->constbuf_misc[0]);
 402         if (ret) {
 403                 nv50_screen_destroy(pscreen);
 404                 return NULL;
 405         }
 406         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 407         OUT_RELOCh(chan, screen->constbuf_misc[0], 0, rl);
 408         OUT_RELOCl(chan, screen->constbuf_misc[0], 0, rl);
 409         OUT_RING  (chan, (NV50_CB_PMISC << 16) | 0x0200);
 410         BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 411         OUT_RELOCh(chan, screen->constbuf_misc[0], 0x200, rl);
 412         OUT_RELOCl(chan, screen->constbuf_misc[0], 0x200, rl);
 413         OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 414
 415         for (i = 0; i < 3; i++) {
 416                 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (256 * 4) * 4,
 417                                      &screen->constbuf_parm[i]);
 418                 if (ret) {
 419                         nv50_screen_destroy(pscreen);
 420                         return NULL;
 421                 }
 422                 BEGIN_RING(chan, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 423                 OUT_RELOCh(chan, screen->constbuf_parm[i], 0, rl);
 424                 OUT_RELOCl(chan, screen->constbuf_parm[i], 0, rl);
 425                 OUT_RING  (chan, ((NV50_CB_PVP + i) << 16) | 0x0800);
 426         }
 427
 428         if (nouveau_resource_init(&screen->immd_heap[0], 0, 128) ||
 429             nouveau_resource_init(&screen->parm_heap[0], 0, 512) ||
 430             nouveau_resource_init(&screen->parm_heap[1], 0, 512))
 431         {
 432                 NOUVEAU_ERR("Error initialising constant buffers.\n");
 433                 nv50_screen_destroy(pscreen);
 434                 return NULL;
 435         }
 436
 437         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 438                              &screen->tic);
 439         if (ret) {
 440                 nv50_screen_destroy(pscreen);
 441                 return NULL;
 442         }
 443         BEGIN_RING(chan, screen->tesla, NV50TCL_TIC_ADDRESS_HIGH, 3);
 444         OUT_RELOCh(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 445         OUT_RELOCl(chan, screen->tic, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 446         OUT_RING  (chan, 3 * 32 - 1);
 447
 448         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 3 * 32 * (8 * 4),
 449                              &screen->tsc);
 450         if (ret) {
 451                 nv50_screen_destroy(pscreen);
 452                 return NULL;
 453         }
 454         BEGIN_RING(chan, screen->tesla, NV50TCL_TSC_ADDRESS_HIGH, 3);
 455         OUT_RELOCh(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 456         OUT_RELOCl(chan, screen->tsc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 457         OUT_RING  (chan, 0); /* ignored if TSC_LINKED (0x1234) == 1 */
 458
 459         /* map constant buffers:
 460          *  B = buffer ID (maybe more than 1 byte)
 461          *  N = CB index used in shader instruction
 462          *  P = program type (0 = VP, 2 = GP, 3 = FP)
 463          * SET_PROGRAM_CB = 0x000BBNP1
 464          */
 465         BEGIN_RING_NI(chan, screen->tesla, NV50TCL_SET_PROGRAM_CB, 8);
 466         /* bind immediate buffer */
 467         OUT_RING  (chan, 0x001 | (NV50_CB_PMISC << 12));
 468         OUT_RING  (chan, 0x021 | (NV50_CB_PMISC << 12));
 469         OUT_RING  (chan, 0x031 | (NV50_CB_PMISC << 12));
 470         /* bind auxiliary constbuf to immediate data bo */
 471         OUT_RING  (chan, 0x201 | (NV50_CB_AUX << 12));
 472         OUT_RING  (chan, 0x221 | (NV50_CB_AUX << 12));
 473         /* bind parameter buffers */
 474         OUT_RING  (chan, 0x101 | (NV50_CB_PVP << 12));
 475         OUT_RING  (chan, 0x121 | (NV50_CB_PGP << 12));
 476         OUT_RING  (chan, 0x131 | (NV50_CB_PFP << 12));
 477
 478         /* Vertex array limits - max them out */
 479         for (i = 0; i < 16; i++) {
 480                 BEGIN_RING(chan, screen->tesla,
 481                            NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
 482                 OUT_RING  (chan, 0x000000ff);
 483                 OUT_RING  (chan, 0xffffffff);
 484         }
 485
 486         BEGIN_RING(chan, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
 487         OUT_RINGf (chan, 0.0f);
 488         OUT_RINGf (chan, 1.0f);
 489
 490         /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
 491         BEGIN_RING(chan, screen->tesla, NV50TCL_LINKED_TSC, 1);
 492         OUT_RING  (chan, 1);
 493
 494         BEGIN_RING(chan, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
 495         OUT_RING  (chan, 1); /* default edgeflag to TRUE */
 496
 497         FIRE_RING (chan);
 498
 499         screen->force_push = debug_get_bool_option("NV50_ALWAYS_PUSH", FALSE);
 500         if(!screen->force_push)
 501                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = NOUVEAU_BO_GART;
 502         return pscreen;
 503 }
 504