src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31 #include <errno.h>
  32
  33 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  34 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  35 #endif
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  45
  46 static boolean
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return FALSE;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return FALSE;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return FALSE;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return FALSE;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return FALSE;
  67       break;
  68    default:
  69       break;
  70    }
  71
  72    /* transfers & shared are always supported */
  73    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  74                  PIPE_BIND_TRANSFER_WRITE |
  75                  PIPE_BIND_SHARED);
  76
  77    return (nv50_format_table[format].usage & bindings) == bindings;
  78 }
  79
  80 static int
  81 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  82 {
  83    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  84
  85    switch (param) {
  86    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  87       return 64;
  88    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  89       return 14;
  90    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  91       return 12;
  92    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  93       return 14;
  94    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  95       return 512;
  96    case PIPE_CAP_MIN_TEXEL_OFFSET:
  97       return -8;
  98    case PIPE_CAP_MAX_TEXEL_OFFSET:
  99       return 7;
 100    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 101    case PIPE_CAP_TEXTURE_SWIZZLE:
 102    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 103    case PIPE_CAP_NPOT_TEXTURES:
 104    case PIPE_CAP_ANISOTROPIC_FILTER:
 105    case PIPE_CAP_SCALED_RESOLVE:
 106    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 107       return 1;
 108    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 109       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 110    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 111       return 0;
 112    case PIPE_CAP_CUBE_MAP_ARRAY:
 113       return 0;
 114       /*
 115       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 116       */
 117    case PIPE_CAP_TWO_SIDED_STENCIL:
 118    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 119    case PIPE_CAP_POINT_SPRITE:
 120       return 1;
 121    case PIPE_CAP_SM3:
 122       return 1;
 123    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 124       return 140;
 125    case PIPE_CAP_MAX_RENDER_TARGETS:
 126       return 8;
 127    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 128       return 1;
 129    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 130    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 131    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 132       return 1;
 133    case PIPE_CAP_QUERY_TIMESTAMP:
 134    case PIPE_CAP_QUERY_TIME_ELAPSED:
 135    case PIPE_CAP_OCCLUSION_QUERY:
 136       return 1;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 138       return 4;
 139    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 140    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 141       return 64;
 142    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 143       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 144    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 145    case PIPE_CAP_INDEP_BLEND_ENABLE:
 146       return 1;
 147    case PIPE_CAP_INDEP_BLEND_FUNC:
 148       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 149    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 150    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 151       return 1;
 152    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 153    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 154       return 0;
 155    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 156       return 0;
 157    case PIPE_CAP_PRIMITIVE_RESTART:
 158    case PIPE_CAP_TGSI_INSTANCEID:
 159    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 160    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 161    case PIPE_CAP_CONDITIONAL_RENDER:
 162    case PIPE_CAP_TEXTURE_BARRIER:
 163    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 164    case PIPE_CAP_START_INSTANCE:
 165       return 1;
 166    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 167    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 168       return 0; /* state trackers will know better */
 169    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 170    case PIPE_CAP_USER_INDEX_BUFFERS:
 171    case PIPE_CAP_USER_VERTEX_BUFFERS:
 172       return 1;
 173    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 174       return 256;
 175    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 176       return 1; /* 256 for binding as RT, but that's not possible in GL */
 177    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 178       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 179    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 180    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 181    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 182    case PIPE_CAP_TGSI_TEXCOORD:
 183    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 184       return 0;
 185    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 186       return 1;
 187    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 188       return 0;
 189    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 190       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
 191    default:
 192       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 193       return 0;
 194    }
 195 }
 196
 197 static int
 198 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 199                              enum pipe_shader_cap param)
 200 {
 201    switch (shader) {
 202    case PIPE_SHADER_VERTEX:
 203    case PIPE_SHADER_GEOMETRY:
 204    case PIPE_SHADER_FRAGMENT:
 205       break;
 206    default:
 207       return 0;
 208    }
 209
 210    switch (param) {
 211    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 212    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 213    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 214    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 215       return 16384;
 216    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 217       return 4;
 218    case PIPE_SHADER_CAP_MAX_INPUTS:
 219       if (shader == PIPE_SHADER_VERTEX)
 220          return 32;
 221       return 0x300 / 16;
 222    case PIPE_SHADER_CAP_MAX_CONSTS:
 223       return 65536 / 16;
 224    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 225       return NV50_MAX_PIPE_CONSTBUFS;
 226    case PIPE_SHADER_CAP_MAX_ADDRS:
 227       return 1;
 228    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 229    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 230       return shader != PIPE_SHADER_FRAGMENT;
 231    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 232    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 233       return 1;
 234    case PIPE_SHADER_CAP_MAX_PREDS:
 235       return 0;
 236    case PIPE_SHADER_CAP_MAX_TEMPS:
 237       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 238    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 239       return 1;
 240    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 241       return 0;
 242    case PIPE_SHADER_CAP_SUBROUTINES:
 243       return 0; /* please inline, or provide function declarations */
 244    case PIPE_SHADER_CAP_INTEGERS:
 245       return 1;
 246    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 247       return 32;
 248    default:
 249       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 250       return 0;
 251    }
 252 }
 253
 254 static float
 255 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 256 {
 257    switch (param) {
 258    case PIPE_CAPF_MAX_LINE_WIDTH:
 259    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 260       return 10.0f;
 261    case PIPE_CAPF_MAX_POINT_WIDTH:
 262    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 263       return 64.0f;
 264    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 265       return 16.0f;
 266    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 267       return 4.0f;
 268    default:
 269       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 270       return 0.0f;
 271    }
 272 }
 273
 274 static void
 275 nv50_screen_destroy(struct pipe_screen *pscreen)
 276 {
 277    struct nv50_screen *screen = nv50_screen(pscreen);
 278
 279    if (screen->base.fence.current) {
 280       nouveau_fence_wait(screen->base.fence.current);
 281       nouveau_fence_ref (NULL, &screen->base.fence.current);
 282    }
 283    if (screen->base.pushbuf)
 284       screen->base.pushbuf->user_priv = NULL;
 285
 286    if (screen->blitter)
 287       nv50_blitter_destroy(screen);
 288
 289    nouveau_bo_ref(NULL, &screen->code);
 290    nouveau_bo_ref(NULL, &screen->tls_bo);
 291    nouveau_bo_ref(NULL, &screen->stack_bo);
 292    nouveau_bo_ref(NULL, &screen->txc);
 293    nouveau_bo_ref(NULL, &screen->uniforms);
 294    nouveau_bo_ref(NULL, &screen->fence.bo);
 295
 296    nouveau_heap_destroy(&screen->vp_code_heap);
 297    nouveau_heap_destroy(&screen->gp_code_heap);
 298    nouveau_heap_destroy(&screen->fp_code_heap);
 299
 300    FREE(screen->tic.entries);
 301
 302    nouveau_object_del(&screen->tesla);
 303    nouveau_object_del(&screen->eng2d);
 304    nouveau_object_del(&screen->m2mf);
 305    nouveau_object_del(&screen->sync);
 306
 307    nouveau_screen_fini(&screen->base);
 308
 309    FREE(screen);
 310 }
 311
 312 static void
 313 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 314 {
 315    struct nv50_screen *screen = nv50_screen(pscreen);
 316    struct nouveau_pushbuf *push = screen->base.pushbuf;
 317
 318    /* we need to do it after possible flush in MARK_RING */
 319    *sequence = ++screen->base.fence.sequence;
 320
 321    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 322    PUSH_DATAh(push, screen->fence.bo->offset);
 323    PUSH_DATA (push, screen->fence.bo->offset);
 324    PUSH_DATA (push, *sequence);
 325    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 326                     NV50_3D_QUERY_GET_UNK4 |
 327                     NV50_3D_QUERY_GET_UNIT_CROP |
 328                     NV50_3D_QUERY_GET_TYPE_QUERY |
 329                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 330                     NV50_3D_QUERY_GET_SHORT);
 331 }
 332
 333 static u32
 334 nv50_screen_fence_update(struct pipe_screen *pscreen)
 335 {
 336    return nv50_screen(pscreen)->fence.map[0];
 337 }
 338
 339 static void
 340 nv50_screen_init_hwctx(struct nv50_screen *screen)
 341 {
 342    struct nouveau_pushbuf *push = screen->base.pushbuf;
 343    struct nv04_fifo *fifo;
 344    unsigned i;
 345
 346    fifo = (struct nv04_fifo *)screen->base.channel->data;
 347
 348    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 349    PUSH_DATA (push, screen->m2mf->handle);
 350    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 351    PUSH_DATA (push, screen->sync->handle);
 352    PUSH_DATA (push, fifo->vram);
 353    PUSH_DATA (push, fifo->vram);
 354
 355    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 356    PUSH_DATA (push, screen->eng2d->handle);
 357    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 358    PUSH_DATA (push, screen->sync->handle);
 359    PUSH_DATA (push, fifo->vram);
 360    PUSH_DATA (push, fifo->vram);
 361    PUSH_DATA (push, fifo->vram);
 362    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 363    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 364    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 365    PUSH_DATA (push, 0);
 366    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 367    PUSH_DATA (push, 0);
 368    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 369    PUSH_DATA (push, 1);
 370
 371    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 372    PUSH_DATA (push, screen->tesla->handle);
 373
 374    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 375    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 376
 377    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 378    PUSH_DATA (push, screen->sync->handle);
 379    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 380    for (i = 0; i < 11; ++i)
 381       PUSH_DATA(push, fifo->vram);
 382    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 383    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 384       PUSH_DATA(push, fifo->vram);
 385
 386    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 387    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 388    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 389    PUSH_DATA (push, 0xf);
 390
 391    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 392       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 393       PUSH_DATA (push, 0x18);
 394    }
 395
 396    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 397    PUSH_DATA (push, 1);
 398
 399    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 400    PUSH_DATA (push, 0);
 401    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 402    PUSH_DATA (push, 0);
 403    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 404    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 405    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 406    PUSH_DATA (push, 0);
 407    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 408    PUSH_DATA (push, 0);
 409    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 410    PUSH_DATA (push, 1);
 411
 412    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 413       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 414       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 415    }
 416
 417    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 418    PUSH_DATA (push, 0);
 419    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 420    PUSH_DATA (push, 0);
 421    PUSH_DATA (push, 0);
 422    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 423    PUSH_DATA (push, 0x3f);
 424
 425    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 426    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 427    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 428
 429    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 430    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 431    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 432
 433    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 434    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 435    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 436
 437    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 438    PUSH_DATAh(push, screen->tls_bo->offset);
 439    PUSH_DATA (push, screen->tls_bo->offset);
 440    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 441
 442    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 443    PUSH_DATAh(push, screen->stack_bo->offset);
 444    PUSH_DATA (push, screen->stack_bo->offset);
 445    PUSH_DATA (push, 4);
 446
 447    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 448    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 449    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 450    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 451
 452    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 453    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 454    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 455    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 456
 457    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 458    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 459    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 460    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 461
 462    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 463    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 464    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 465    PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
 466
 467    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 468    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 469    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 470    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 471
 472    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 473    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 474    PUSH_DATA (push, ((1 << 9) << 6) | NV50_CB_AUX);
 475    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 476    PUSH_DATAf(push, 0.0f);
 477    PUSH_DATAf(push, 0.0f);
 478    PUSH_DATAf(push, 0.0f);
 479    PUSH_DATAf(push, 0.0f);
 480    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 481    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 482    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 483
 484    /* max TIC (bits 4:8) & TSC bindings, per program type */
 485    for (i = 0; i < 3; ++i) {
 486       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 487       PUSH_DATA (push, 0x54);
 488    }
 489
 490    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 491    PUSH_DATAh(push, screen->txc->offset);
 492    PUSH_DATA (push, screen->txc->offset);
 493    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 494
 495    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 496    PUSH_DATAh(push, screen->txc->offset + 65536);
 497    PUSH_DATA (push, screen->txc->offset + 65536);
 498    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 499
 500    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 501    PUSH_DATA (push, 0);
 502
 503    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 504    PUSH_DATA (push, 0);
 505    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 506    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 507    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 508    for (i = 0; i < 8 * 2; ++i)
 509       PUSH_DATA(push, 0);
 510    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 511    PUSH_DATA (push, 0);
 512
 513    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 514    PUSH_DATA (push, 1);
 515    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 516    PUSH_DATAf(push, 0.0f);
 517    PUSH_DATAf(push, 1.0f);
 518
 519    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 520 #ifdef NV50_SCISSORS_CLIPPING
 521    PUSH_DATA (push, 0x0000);
 522 #else
 523    PUSH_DATA (push, 0x1080);
 524 #endif
 525
 526    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 527    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 528
 529    /* We use scissors instead of exact view volume clipping,
 530     * so they're always enabled.
 531     */
 532    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 533    PUSH_DATA (push, 1);
 534    PUSH_DATA (push, 8192 << 16);
 535    PUSH_DATA (push, 8192 << 16);
 536
 537    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 538    PUSH_DATA (push, 1);
 539    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 540    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 541    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 542    PUSH_DATA (push, 0x11111111);
 543    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 544    PUSH_DATA (push, 1);
 545
 546    PUSH_KICK (push);
 547 }
 548
 549 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 550       uint64_t *tls_size)
 551 {
 552    struct nouveau_device *dev = screen->base.device;
 553    int ret;
 554
 555    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 556          ONE_TEMP_SIZE;
 557    if (nouveau_mesa_debug)
 558       debug_printf("allocating space for %u temps\n",
 559             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 560    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 561          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 562
 563    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 564                         *tls_size, NULL, &screen->tls_bo);
 565    if (ret) {
 566       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 567       return ret;
 568    }
 569
 570    return 0;
 571 }
 572
 573 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 574 {
 575    struct nouveau_pushbuf *push = screen->base.pushbuf;
 576    int ret;
 577    uint64_t tls_size;
 578
 579    if (tls_space < screen->cur_tls_space)
 580       return 0;
 581    if (tls_space > screen->max_tls_space) {
 582       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 583        * LOCAL_WARPS_NO_CLAMP) */
 584       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 585             (unsigned)(tls_space / ONE_TEMP_SIZE),
 586             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 587       return -ENOMEM;
 588    }
 589
 590    nouveau_bo_ref(NULL, &screen->tls_bo);
 591    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 592    if (ret)
 593       return ret;
 594
 595    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 596    PUSH_DATAh(push, screen->tls_bo->offset);
 597    PUSH_DATA (push, screen->tls_bo->offset);
 598    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 599
 600    return 1;
 601 }
 602
 603 struct pipe_screen *
 604 nv50_screen_create(struct nouveau_device *dev)
 605 {
 606    struct nv50_screen *screen;
 607    struct pipe_screen *pscreen;
 608    struct nouveau_object *chan;
 609    uint64_t value;
 610    uint32_t tesla_class;
 611    unsigned stack_size;
 612    int ret;
 613
 614    screen = CALLOC_STRUCT(nv50_screen);
 615    if (!screen)
 616       return NULL;
 617    pscreen = &screen->base.base;
 618
 619    ret = nouveau_screen_init(&screen->base, dev);
 620    if (ret) {
 621       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 622       goto fail;
 623    }
 624
 625    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 626     *  admit them to VRAM.
 627     */
 628    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 629       PIPE_BIND_VERTEX_BUFFER;
 630    screen->base.sysmem_bindings |=
 631       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 632
 633    screen->base.pushbuf->user_priv = screen;
 634    screen->base.pushbuf->rsvd_kick = 5;
 635
 636    chan = screen->base.channel;
 637
 638    pscreen->destroy = nv50_screen_destroy;
 639    pscreen->context_create = nv50_create;
 640    pscreen->is_format_supported = nv50_screen_is_format_supported;
 641    pscreen->get_param = nv50_screen_get_param;
 642    pscreen->get_shader_param = nv50_screen_get_shader_param;
 643    pscreen->get_paramf = nv50_screen_get_paramf;
 644
 645    nv50_screen_init_resource_functions(pscreen);
 646
 647    nouveau_screen_init_vdec(&screen->base);
 648
 649    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 650                         NULL, &screen->fence.bo);
 651    if (ret) {
 652       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 653       goto fail;
 654    }
 655
 656    nouveau_bo_map(screen->fence.bo, 0, NULL);
 657    screen->fence.map = screen->fence.bo->map;
 658    screen->base.fence.emit = nv50_screen_fence_emit;
 659    screen->base.fence.update = nv50_screen_fence_update;
 660
 661    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 662                             &(struct nv04_notify){ .length = 32 },
 663                             sizeof(struct nv04_notify), &screen->sync);
 664    if (ret) {
 665       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 666       goto fail;
 667    }
 668
 669    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 670                             NULL, 0, &screen->m2mf);
 671    if (ret) {
 672       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 673       goto fail;
 674    }
 675
 676    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 677                             NULL, 0, &screen->eng2d);
 678    if (ret) {
 679       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 680       goto fail;
 681    }
 682
 683    switch (dev->chipset & 0xf0) {
 684    case 0x50:
 685       tesla_class = NV50_3D_CLASS;
 686       break;
 687    case 0x80:
 688    case 0x90:
 689       tesla_class = NV84_3D_CLASS;
 690       break;
 691    case 0xa0:
 692       switch (dev->chipset) {
 693       case 0xa0:
 694       case 0xaa:
 695       case 0xac:
 696          tesla_class = NVA0_3D_CLASS;
 697          break;
 698       case 0xaf:
 699          tesla_class = NVAF_3D_CLASS;
 700          break;
 701       default:
 702          tesla_class = NVA3_3D_CLASS;
 703          break;
 704       }
 705       break;
 706    default:
 707       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 708       goto fail;
 709    }
 710    screen->base.class_3d = tesla_class;
 711
 712    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 713                             NULL, 0, &screen->tesla);
 714    if (ret) {
 715       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 716       goto fail;
 717    }
 718
 719    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 720                         3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 721    if (ret) {
 722       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 723       goto fail;
 724    }
 725
 726    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 727    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 728    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 729
 730    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 731
 732    screen->TPs = util_bitcount(value & 0xffff);
 733    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 734
 735    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 736          STACK_WARPS_ALLOC * 64 * 8;
 737
 738    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 739                         &screen->stack_bo);
 740    if (ret) {
 741       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 742       goto fail;
 743    }
 744
 745    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 746          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 747          ONE_TEMP_SIZE;
 748    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 749    screen->max_tls_space /= 2; /* half of vram */
 750
 751    /* hw can address max 64 KiB */
 752    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 753
 754    uint64_t tls_size;
 755    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 756    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 757    if (ret)
 758       goto fail;
 759
 760    if (nouveau_mesa_debug)
 761       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 762             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 763
 764    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 765                         &screen->uniforms);
 766    if (ret) {
 767       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 768       goto fail;
 769    }
 770
 771    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 772                         &screen->txc);
 773    if (ret) {
 774       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 775       goto fail;
 776    }
 777
 778    screen->tic.entries = CALLOC(4096, sizeof(void *));
 779    screen->tsc.entries = screen->tic.entries + 2048;
 780
 781    if (!nv50_blitter_create(screen))
 782       goto fail;
 783
 784    nv50_screen_init_hwctx(screen);
 785
 786    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 787
 788    return pscreen;
 789
 790 fail:
 791    nv50_screen_destroy(pscreen);
 792    return NULL;
 793 }
 794
 795 int
 796 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 797 {
 798    int i = screen->tic.next;
 799
 800    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 801       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 802
 803    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 804
 805    if (screen->tic.entries[i])
 806       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 807
 808    screen->tic.entries[i] = entry;
 809    return i;
 810 }
 811
 812 int
 813 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 814 {
 815    int i = screen->tsc.next;
 816
 817    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 818       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 819
 820    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 821
 822    if (screen->tsc.entries[i])
 823       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 824
 825    screen->tsc.entries[i] = entry;
 826    return i;
 827 }