src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 static boolean
  37 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  38                                 enum pipe_format format,
  39                                 enum pipe_texture_target target,
  40                                 unsigned sample_count,
  41                                 unsigned bindings)
  42 {
  43    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  44       return FALSE;
  45    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  46       return FALSE;
  47
  48    if (!util_format_is_supported(format, bindings))
  49       return FALSE;
  50
  51    switch (format) {
  52    case PIPE_FORMAT_Z16_UNORM:
  53       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  54          return FALSE;
  55       break;
  56    case PIPE_FORMAT_R8G8B8A8_UNORM:
  57    case PIPE_FORMAT_R8G8B8X8_UNORM:
  58       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  59       if (bindings & PIPE_BIND_RENDER_TARGET)
  60          return FALSE;
  61    default:
  62       break;
  63    }
  64
  65    /* transfers & shared are always supported */
  66    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  67                  PIPE_BIND_TRANSFER_WRITE |
  68                  PIPE_BIND_SHARED);
  69
  70    return (nv50_format_table[format].usage & bindings) == bindings;
  71 }
  72
  73 static int
  74 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  75 {
  76    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  77
  78    switch (param) {
  79    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  80       return 64;
  81    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  82       return 14;
  83    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  84       return 12;
  85    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  86       return 14;
  87    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  88       return 512;
  89    case PIPE_CAP_MIN_TEXEL_OFFSET:
  90       return -8;
  91    case PIPE_CAP_MAX_TEXEL_OFFSET:
  92       return 7;
  93    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  94    case PIPE_CAP_TEXTURE_SWIZZLE:
  95    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  96    case PIPE_CAP_NPOT_TEXTURES:
  97    case PIPE_CAP_ANISOTROPIC_FILTER:
  98    case PIPE_CAP_SCALED_RESOLVE:
  99       return 1;
 100    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 101       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 102    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 103       return 0;
 104    case PIPE_CAP_TWO_SIDED_STENCIL:
 105    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 106    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 107    case PIPE_CAP_POINT_SPRITE:
 108       return 1;
 109    case PIPE_CAP_SM3:
 110       return 1;
 111    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 112       return 130;
 113    case PIPE_CAP_MAX_RENDER_TARGETS:
 114       return 8;
 115    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 116       return 1;
 117    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 118    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 119    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 120       return 1;
 121    case PIPE_CAP_TIMER_QUERY:
 122    case PIPE_CAP_OCCLUSION_QUERY:
 123       return 1;
 124    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 125       return 4;
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 128       return 64;
 129    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 130       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 131    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 132    case PIPE_CAP_INDEP_BLEND_ENABLE:
 133       return 1;
 134    case PIPE_CAP_INDEP_BLEND_FUNC:
 135       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 136    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 137    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 138       return 1;
 139    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 140    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 141       return 0;
 142    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 143       return 0;
 144    case PIPE_CAP_PRIMITIVE_RESTART:
 145    case PIPE_CAP_TGSI_INSTANCEID:
 146    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 147    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 148    case PIPE_CAP_CONDITIONAL_RENDER:
 149    case PIPE_CAP_TEXTURE_BARRIER:
 150    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 151       return 1;
 152    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 153    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 154    case PIPE_CAP_USER_VERTEX_BUFFERS:
 155    case PIPE_CAP_USER_INDEX_BUFFERS:
 156       return 0; /* state trackers will know better */
 157    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 158       return 1;
 159    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 160       return 256;
 161    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 162    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 163    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 164       return 0;
 165    default:
 166       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 167       return 0;
 168    }
 169 }
 170
 171 static int
 172 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 173                              enum pipe_shader_cap param)
 174 {
 175    switch (shader) {
 176    case PIPE_SHADER_VERTEX:
 177    case PIPE_SHADER_GEOMETRY:
 178    case PIPE_SHADER_FRAGMENT:
 179       break;
 180    default:
 181       return 0;
 182    }
 183
 184    switch (param) {
 185    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 186    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 187    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 188    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 189       return 16384;
 190    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 191       return 4;
 192    case PIPE_SHADER_CAP_MAX_INPUTS:
 193       if (shader == PIPE_SHADER_VERTEX)
 194          return 32;
 195       return 0x300 / 16;
 196    case PIPE_SHADER_CAP_MAX_CONSTS:
 197       return 65536 / 16;
 198    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 199       return 14;
 200    case PIPE_SHADER_CAP_MAX_ADDRS:
 201       return 1;
 202    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 203    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 204       return shader != PIPE_SHADER_FRAGMENT;
 205    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 206    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 207       return 1;
 208    case PIPE_SHADER_CAP_MAX_PREDS:
 209       return 0;
 210    case PIPE_SHADER_CAP_MAX_TEMPS:
 211       return NV50_CAP_MAX_PROGRAM_TEMPS;
 212    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 213       return 1;
 214    case PIPE_SHADER_CAP_SUBROUTINES:
 215       return 0; /* please inline, or provide function declarations */
 216    case PIPE_SHADER_CAP_INTEGERS:
 217       return 1;
 218    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 219       return 32;
 220    default:
 221       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 222       return 0;
 223    }
 224 }
 225
 226 static float
 227 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 228 {
 229    switch (param) {
 230    case PIPE_CAPF_MAX_LINE_WIDTH:
 231    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 232       return 10.0f;
 233    case PIPE_CAPF_MAX_POINT_WIDTH:
 234    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 235       return 64.0f;
 236    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 237       return 16.0f;
 238    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 239       return 4.0f;
 240    default:
 241       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 242       return 0.0f;
 243    }
 244 }
 245
 246 static void
 247 nv50_screen_destroy(struct pipe_screen *pscreen)
 248 {
 249    struct nv50_screen *screen = nv50_screen(pscreen);
 250
 251    if (screen->base.fence.current) {
 252       nouveau_fence_wait(screen->base.fence.current);
 253       nouveau_fence_ref (NULL, &screen->base.fence.current);
 254    }
 255    if (screen->base.pushbuf)
 256       screen->base.pushbuf->user_priv = NULL;
 257
 258    if (screen->blitctx)
 259       FREE(screen->blitctx);
 260
 261    nouveau_bo_ref(NULL, &screen->code);
 262    nouveau_bo_ref(NULL, &screen->tls_bo);
 263    nouveau_bo_ref(NULL, &screen->stack_bo);
 264    nouveau_bo_ref(NULL, &screen->txc);
 265    nouveau_bo_ref(NULL, &screen->uniforms);
 266    nouveau_bo_ref(NULL, &screen->fence.bo);
 267
 268    nouveau_heap_destroy(&screen->vp_code_heap);
 269    nouveau_heap_destroy(&screen->gp_code_heap);
 270    nouveau_heap_destroy(&screen->fp_code_heap);
 271
 272    if (screen->tic.entries)
 273       FREE(screen->tic.entries);
 274
 275    nouveau_object_del(&screen->tesla);
 276    nouveau_object_del(&screen->eng2d);
 277    nouveau_object_del(&screen->m2mf);
 278    nouveau_object_del(&screen->sync);
 279
 280    nouveau_screen_fini(&screen->base);
 281
 282    FREE(screen);
 283 }
 284
 285 static void
 286 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 287 {
 288    struct nv50_screen *screen = nv50_screen(pscreen);
 289    struct nouveau_pushbuf *push = screen->base.pushbuf;
 290
 291    /* we need to do it after possible flush in MARK_RING */
 292    *sequence = ++screen->base.fence.sequence;
 293
 294    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 295    PUSH_DATAh(push, screen->fence.bo->offset);
 296    PUSH_DATA (push, screen->fence.bo->offset);
 297    PUSH_DATA (push, *sequence);
 298    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 299                     NV50_3D_QUERY_GET_UNK4 |
 300                     NV50_3D_QUERY_GET_UNIT_CROP |
 301                     NV50_3D_QUERY_GET_TYPE_QUERY |
 302                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 303                     NV50_3D_QUERY_GET_SHORT);
 304 }
 305
 306 static u32
 307 nv50_screen_fence_update(struct pipe_screen *pscreen)
 308 {
 309    return nv50_screen(pscreen)->fence.map[0];
 310 }
 311
 312 static int
 313 nv50_screen_init_hwctx(struct nv50_screen *screen, unsigned tls_space)
 314 {
 315    struct nouveau_pushbuf *push = screen->base.pushbuf;
 316    struct nv04_fifo *fifo;
 317    unsigned i;
 318
 319    fifo = (struct nv04_fifo *)screen->base.channel->data;
 320
 321    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 322    PUSH_DATA (push, screen->m2mf->handle);
 323    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 324    PUSH_DATA (push, screen->sync->handle);
 325    PUSH_DATA (push, fifo->vram);
 326    PUSH_DATA (push, fifo->vram);
 327
 328    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 329    PUSH_DATA (push, screen->eng2d->handle);
 330    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 331    PUSH_DATA (push, screen->sync->handle);
 332    PUSH_DATA (push, fifo->vram);
 333    PUSH_DATA (push, fifo->vram);
 334    PUSH_DATA (push, fifo->vram);
 335    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 336    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 337    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 338    PUSH_DATA (push, 0);
 339    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 340    PUSH_DATA (push, 0);
 341    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 342    PUSH_DATA (push, 1);
 343
 344    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 345    PUSH_DATA (push, screen->tesla->handle);
 346
 347    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 348    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 349
 350    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 351    PUSH_DATA (push, screen->sync->handle);
 352    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 353    for (i = 0; i < 11; ++i)
 354       PUSH_DATA(push, fifo->vram);
 355    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 356    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 357       PUSH_DATA(push, fifo->vram);
 358
 359    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 360    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 361    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 362    PUSH_DATA (push, 0xf);
 363
 364    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 365       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 366       PUSH_DATA (push, 0x18);
 367    }
 368
 369    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 370    PUSH_DATA (push, 1);
 371
 372    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 373    PUSH_DATA (push, 0);
 374    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 375    PUSH_DATA (push, 0);
 376    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 377    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 378    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 379    PUSH_DATA (push, 0);
 380    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 381    PUSH_DATA (push, 0);
 382    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 383    PUSH_DATA (push, 1);
 384
 385    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 386       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 387       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 388    }
 389
 390    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 391    PUSH_DATA (push, 0);
 392    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 393    PUSH_DATA (push, 0);
 394    PUSH_DATA (push, 0);
 395    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 396    PUSH_DATA (push, 0x3f);
 397
 398    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 399    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 400    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 401
 402    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 403    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 404    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 405
 406    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 407    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 408    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 409
 410    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 411    PUSH_DATAh(push, screen->tls_bo->offset);
 412    PUSH_DATA (push, screen->tls_bo->offset);
 413    PUSH_DATA (push, util_logbase2(tls_space / 8));
 414
 415    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 416    PUSH_DATAh(push, screen->stack_bo->offset);
 417    PUSH_DATA (push, screen->stack_bo->offset);
 418    PUSH_DATA (push, 4);
 419
 420    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 421    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 422    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 423    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 424
 425    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 426    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 427    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 428    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 429
 430    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 431    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 432    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 433    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 434
 435    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 436    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 437    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 438    PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
 439
 440    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 6);
 441    PUSH_DATA (push, (NV50_CB_PVP << 12) | 0x001);
 442    PUSH_DATA (push, (NV50_CB_PGP << 12) | 0x021);
 443    PUSH_DATA (push, (NV50_CB_PFP << 12) | 0x031);
 444    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 445    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 446    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 447
 448    /* max TIC (bits 4:8) & TSC bindings, per program type */
 449    for (i = 0; i < 3; ++i) {
 450       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 451       PUSH_DATA (push, 0x54);
 452    }
 453
 454    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 455    PUSH_DATAh(push, screen->txc->offset);
 456    PUSH_DATA (push, screen->txc->offset);
 457    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 458
 459    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 460    PUSH_DATAh(push, screen->txc->offset + 65536);
 461    PUSH_DATA (push, screen->txc->offset + 65536);
 462    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 463
 464    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 465    PUSH_DATA (push, 0);
 466
 467    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 468    PUSH_DATA (push, 0);
 469    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 470    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 471    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 472    for (i = 0; i < 8 * 2; ++i)
 473       PUSH_DATA(push, 0);
 474    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 475    PUSH_DATA (push, 0);
 476
 477    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 478    PUSH_DATA (push, 1);
 479    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 480    PUSH_DATAf(push, 0.0f);
 481    PUSH_DATAf(push, 1.0f);
 482
 483    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 484 #ifdef NV50_SCISSORS_CLIPPING
 485    PUSH_DATA (push, 0x0000);
 486 #else
 487    PUSH_DATA (push, 0x1080);
 488 #endif
 489
 490    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 491    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 492
 493    /* We use scissors instead of exact view volume clipping,
 494     * so they're always enabled.
 495     */
 496    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 497    PUSH_DATA (push, 1);
 498    PUSH_DATA (push, 8192 << 16);
 499    PUSH_DATA (push, 8192 << 16);
 500
 501    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 502    PUSH_DATA (push, 1);
 503    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 504    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 505    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 506    PUSH_DATA (push, 0x11111111);
 507    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 508    PUSH_DATA (push, 1);
 509
 510    PUSH_KICK (push);
 511
 512    return 0;
 513 }
 514
 515 #define FAIL_SCREEN_INIT(str, err)                    \
 516    do {                                               \
 517       NOUVEAU_ERR(str, err);                          \
 518       nv50_screen_destroy(pscreen);                   \
 519       return NULL;                                    \
 520    } while(0)
 521
 522 struct pipe_screen *
 523 nv50_screen_create(struct nouveau_device *dev)
 524 {
 525    struct nv50_screen *screen;
 526    struct pipe_screen *pscreen;
 527    struct nouveau_object *chan;
 528    uint64_t value;
 529    uint32_t tesla_class;
 530    unsigned stack_size, max_warps, tls_space;
 531    int ret;
 532
 533    screen = CALLOC_STRUCT(nv50_screen);
 534    if (!screen)
 535       return NULL;
 536    pscreen = &screen->base.base;
 537
 538    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 539
 540    ret = nouveau_screen_init(&screen->base, dev);
 541    if (ret)
 542       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 543
 544    screen->base.pushbuf->user_priv = screen;
 545    screen->base.pushbuf->rsvd_kick = 5;
 546
 547    chan = screen->base.channel;
 548
 549    pscreen->destroy = nv50_screen_destroy;
 550    pscreen->context_create = nv50_create;
 551    pscreen->is_format_supported = nv50_screen_is_format_supported;
 552    pscreen->get_param = nv50_screen_get_param;
 553    pscreen->get_shader_param = nv50_screen_get_shader_param;
 554    pscreen->get_paramf = nv50_screen_get_paramf;
 555
 556    nv50_screen_init_resource_functions(pscreen);
 557
 558    nouveau_screen_init_vdec(&screen->base);
 559
 560    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 561                         NULL, &screen->fence.bo);
 562    if (ret)
 563       goto fail;
 564    nouveau_bo_map(screen->fence.bo, 0, NULL);
 565    screen->fence.map = screen->fence.bo->map;
 566    screen->base.fence.emit = nv50_screen_fence_emit;
 567    screen->base.fence.update = nv50_screen_fence_update;
 568
 569    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 570                             &(struct nv04_notify){ .length = 32 },
 571                             sizeof(struct nv04_notify), &screen->sync);
 572    if (ret)
 573       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 574
 575
 576    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 577                             NULL, 0, &screen->m2mf);
 578    if (ret)
 579       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 580
 581
 582    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 583                             NULL, 0, &screen->eng2d);
 584    if (ret)
 585       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 586
 587    switch (dev->chipset & 0xf0) {
 588    case 0x50:
 589       tesla_class = NV50_3D_CLASS;
 590       break;
 591    case 0x80:
 592    case 0x90:
 593       tesla_class = NV84_3D_CLASS;
 594       break;
 595    case 0xa0:
 596       switch (dev->chipset) {
 597       case 0xa0:
 598       case 0xaa:
 599       case 0xac:
 600          tesla_class = NVA0_3D_CLASS;
 601          break;
 602       case 0xaf:
 603          tesla_class = NVAF_3D_CLASS;
 604          break;
 605       default:
 606          tesla_class = NVA3_3D_CLASS;
 607          break;
 608       }
 609       break;
 610    default:
 611       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 612       break;
 613    }
 614    screen->base.class_3d = tesla_class;
 615
 616    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 617                             NULL, 0, &screen->tesla);
 618    if (ret)
 619       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 620
 621
 622    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 623                         3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 624    if (ret)
 625       goto fail;
 626
 627    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 628    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 629    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 630
 631    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 632
 633    max_warps  = util_bitcount(value & 0xffff);
 634    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 635
 636    stack_size = max_warps * 64 * 8;
 637
 638    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 639                         &screen->stack_bo);
 640    if (ret)
 641       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 642
 643    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 644
 645    screen->tls_size = tls_space * max_warps * 32;
 646
 647    if (nouveau_mesa_debug)
 648       debug_printf("max_warps = %i, tls_size = %"PRIu64" KiB\n",
 649                      max_warps, screen->tls_size >> 10);
 650
 651    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size, NULL,
 652                         &screen->tls_bo);
 653    if (ret)
 654       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 655
 656
 657    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 658                         &screen->uniforms);
 659    if (ret)
 660       goto fail;
 661
 662    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 663                         &screen->txc);
 664    if (ret)
 665       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 666
 667    screen->tic.entries = CALLOC(4096, sizeof(void *));
 668    screen->tsc.entries = screen->tic.entries + 2048;
 669
 670
 671    if (!nv50_blitctx_create(screen))
 672       goto fail;
 673
 674    if (nv50_screen_init_hwctx(screen, tls_space))
 675       goto fail;
 676
 677    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 678
 679    return pscreen;
 680
 681 fail:
 682    nv50_screen_destroy(pscreen);
 683    return NULL;
 684 }
 685
 686 int
 687 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 688 {
 689    int i = screen->tic.next;
 690
 691    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 692       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 693
 694    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 695
 696    if (screen->tic.entries[i])
 697       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 698
 699    screen->tic.entries[i] = entry;
 700    return i;
 701 }
 702
 703 int
 704 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 705 {
 706    int i = screen->tsc.next;
 707
 708    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 709       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 710
 711    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 712
 713    if (screen->tsc.entries[i])
 714       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 715
 716    screen->tsc.entries[i] = entry;
 717    return i;
 718 }