src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 extern int nouveau_device_get_param(struct nouveau_device *dev,
  37                                     uint64_t param, uint64_t *value);
  38
  39 static boolean
  40 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (sample_count > 1)
  47       return FALSE;
  48
  49    if (!util_format_is_supported(format, bindings))
  50       return FALSE;
  51
  52    switch (format) {
  53    case PIPE_FORMAT_Z16_UNORM:
  54       if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D)
  55          return FALSE;
  56       break;
  57    default:
  58       break;
  59    }
  60
  61    /* transfers & shared are always supported */
  62    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  63                  PIPE_BIND_TRANSFER_WRITE |
  64                  PIPE_BIND_SHARED);
  65
  66    return (nv50_format_table[format].usage & bindings) == bindings;
  67 }
  68
  69 static int
  70 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  71 {
  72    switch (param) {
  73    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  74    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  75       return 32;
  76    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  77       return 64;
  78    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  79       return 13;
  80    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  81       return 10;
  82    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  83       return 13;
  84    case PIPE_CAP_ARRAY_TEXTURES: /* shader support missing */
  85       return 0;
  86    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  87    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  88    case PIPE_CAP_TEXTURE_SWIZZLE:
  89    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  90    case PIPE_CAP_NPOT_TEXTURES:
  91    case PIPE_CAP_ANISOTROPIC_FILTER:
  92       return 1;
  93    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  94       return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
  95    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  96       return 0;
  97    case PIPE_CAP_TWO_SIDED_STENCIL:
  98    case PIPE_CAP_DEPTH_CLAMP:
  99    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 100    case PIPE_CAP_POINT_SPRITE:
 101       return 1;
 102    case PIPE_CAP_GLSL:
 103    case PIPE_CAP_SM3:
 104       return 1;
 105    case PIPE_CAP_MAX_RENDER_TARGETS:
 106       return 8;
 107    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 108       return 1;
 109    case PIPE_CAP_TIMER_QUERY:
 110    case PIPE_CAP_OCCLUSION_QUERY:
 111       return 1;
 112    case PIPE_CAP_STREAM_OUTPUT:
 113       return 0;
 114    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 115    case PIPE_CAP_INDEP_BLEND_ENABLE:
 116       return 1;
 117    case PIPE_CAP_INDEP_BLEND_FUNC:
 118       return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D;
 119    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 120    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 121       return 1;
 122    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 123    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 124       return 0;
 125    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 126       return 0;
 127    case PIPE_CAP_PRIMITIVE_RESTART:
 128    case PIPE_CAP_TGSI_INSTANCEID:
 129    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 130    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 131       return 1;
 132    default:
 133       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 134       return 0;
 135    }
 136 }
 137
 138 static int
 139 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 140                              enum pipe_shader_cap param)
 141 {
 142    switch (shader) {
 143    case PIPE_SHADER_VERTEX:
 144    case PIPE_SHADER_GEOMETRY:
 145    case PIPE_SHADER_FRAGMENT:
 146       break;
 147    default:
 148       return 0;
 149    }
 150
 151    switch (param) {
 152    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 153    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 154    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 155    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 156       return 16384;
 157    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 158       return 4;
 159    case PIPE_SHADER_CAP_MAX_INPUTS:
 160       if (shader == PIPE_SHADER_VERTEX)
 161          return 32;
 162       return 0x300 / 16;
 163    case PIPE_SHADER_CAP_MAX_CONSTS:
 164       return 65536 / 16;
 165    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 166       return 14;
 167    case PIPE_SHADER_CAP_MAX_ADDRS:
 168       return 1;
 169    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 170    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 171       return shader != PIPE_SHADER_FRAGMENT;
 172    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 173    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 174       return 1;
 175    case PIPE_SHADER_CAP_MAX_PREDS:
 176       return 0;
 177    case PIPE_SHADER_CAP_MAX_TEMPS:
 178       return NV50_CAP_MAX_PROGRAM_TEMPS;
 179    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 180       return 1;
 181    case PIPE_SHADER_CAP_SUBROUTINES:
 182       return 0; /* please inline, or provide function declarations */
 183    default:
 184       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 185       return 0;
 186    }
 187 }
 188
 189 static float
 190 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 191 {
 192    switch (param) {
 193    case PIPE_CAP_MAX_LINE_WIDTH:
 194    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 195       return 10.0f;
 196    case PIPE_CAP_MAX_POINT_WIDTH:
 197    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 198       return 64.0f;
 199    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 200       return 16.0f;
 201    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 202       return 4.0f;
 203    default:
 204       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 205       return 0.0f;
 206    }
 207 }
 208
 209 static void
 210 nv50_screen_destroy(struct pipe_screen *pscreen)
 211 {
 212    struct nv50_screen *screen = nv50_screen(pscreen);
 213
 214    if (screen->base.fence.current) {
 215       nouveau_fence_wait(screen->base.fence.current);
 216       nouveau_fence_ref (NULL, &screen->base.fence.current);
 217    }
 218
 219    nouveau_bo_ref(NULL, &screen->code);
 220    nouveau_bo_ref(NULL, &screen->tls_bo);
 221    nouveau_bo_ref(NULL, &screen->stack_bo);
 222    nouveau_bo_ref(NULL, &screen->txc);
 223    nouveau_bo_ref(NULL, &screen->uniforms);
 224    nouveau_bo_ref(NULL, &screen->fence.bo);
 225
 226    nouveau_resource_destroy(&screen->vp_code_heap);
 227    nouveau_resource_destroy(&screen->gp_code_heap);
 228    nouveau_resource_destroy(&screen->fp_code_heap);
 229
 230    if (screen->tic.entries)
 231       FREE(screen->tic.entries);
 232
 233    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 234
 235    nouveau_grobj_free(&screen->tesla);
 236    nouveau_grobj_free(&screen->eng2d);
 237    nouveau_grobj_free(&screen->m2mf);
 238
 239    nouveau_notifier_free(&screen->sync);
 240
 241    nouveau_screen_fini(&screen->base);
 242
 243    FREE(screen);
 244 }
 245
 246 static void
 247 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 248 {
 249    struct nv50_screen *screen = nv50_screen(pscreen);
 250    struct nouveau_channel *chan = screen->base.channel;
 251
 252    MARK_RING (chan, 5, 2);
 253    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 254    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 255    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 256    OUT_RING  (chan, sequence);
 257    OUT_RING  (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 258                     NV50_3D_QUERY_GET_UNK4 |
 259                     NV50_3D_QUERY_GET_UNIT_CROP |
 260                     NV50_3D_QUERY_GET_TYPE_QUERY |
 261                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 262                     NV50_3D_QUERY_GET_SHORT);
 263 }
 264
 265 static u32
 266 nv50_screen_fence_update(struct pipe_screen *pscreen)
 267 {
 268    struct nv50_screen *screen = nv50_screen(pscreen);
 269    return screen->fence.map[0];
 270 }
 271
 272 #define FAIL_SCREEN_INIT(str, err)                    \
 273    do {                                               \
 274       NOUVEAU_ERR(str, err);                          \
 275       nv50_screen_destroy(pscreen);                   \
 276       return NULL;                                    \
 277    } while(0)
 278
 279 struct pipe_screen *
 280 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 281 {
 282    struct nv50_screen *screen;
 283    struct nouveau_channel *chan;
 284    struct pipe_screen *pscreen;
 285    uint64_t value;
 286    uint32_t tesla_class;
 287    unsigned stack_size, max_warps, tls_space;
 288    int ret;
 289    unsigned i, base;
 290
 291    screen = CALLOC_STRUCT(nv50_screen);
 292    if (!screen)
 293       return NULL;
 294    pscreen = &screen->base.base;
 295
 296    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 297
 298    ret = nouveau_screen_init(&screen->base, dev);
 299    if (ret)
 300       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 301
 302    chan = screen->base.channel;
 303
 304    pscreen->winsys = ws;
 305    pscreen->destroy = nv50_screen_destroy;
 306    pscreen->context_create = nv50_create;
 307    pscreen->is_format_supported = nv50_screen_is_format_supported;
 308    pscreen->get_param = nv50_screen_get_param;
 309    pscreen->get_shader_param = nv50_screen_get_shader_param;
 310    pscreen->get_paramf = nv50_screen_get_paramf;
 311
 312    nv50_screen_init_resource_functions(pscreen);
 313
 314    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 315                         &screen->fence.bo);
 316    if (ret)
 317       goto fail;
 318    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 319    screen->fence.map = screen->fence.bo->map;
 320    nouveau_bo_unmap(screen->fence.bo);
 321    screen->base.fence.emit = nv50_screen_fence_emit;
 322    screen->base.fence.update = nv50_screen_fence_update;
 323
 324    ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 325    if (ret)
 326       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 327
 328    ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
 329    if (ret)
 330       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 331
 332    BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
 333    BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
 334    OUT_RING  (chan, screen->sync->handle);
 335    OUT_RING  (chan, chan->vram->handle);
 336    OUT_RING  (chan, chan->vram->handle);
 337
 338    ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 339    if (ret)
 340       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 341
 342    BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
 343    BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
 344    OUT_RING  (chan, screen->sync->handle);
 345    OUT_RING  (chan, chan->vram->handle);
 346    OUT_RING  (chan, chan->vram->handle);
 347    OUT_RING  (chan, chan->vram->handle);
 348    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 349    OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 350    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 351    OUT_RING  (chan, 0);
 352    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 353    OUT_RING  (chan, 0);
 354    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 355    OUT_RING  (chan, 1);
 356
 357    switch (dev->chipset & 0xf0) {
 358    case 0x50:
 359       tesla_class = NV50_3D;
 360       break;
 361    case 0x80:
 362    case 0x90:
 363       tesla_class = NV84_3D;
 364       break;
 365    case 0xa0:
 366       switch (dev->chipset) {
 367       case 0xa0:
 368       case 0xaa:
 369       case 0xac:
 370          tesla_class = NVA0_3D;
 371          break;
 372       case 0xaf:
 373          tesla_class = NVAF_3D;
 374          break;
 375       default:
 376          tesla_class = NVA3_3D;
 377          break;
 378       }
 379       break;
 380    default:
 381       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 382       break;
 383    }
 384
 385    ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
 386    if (ret)
 387       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 388
 389    BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
 390
 391    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 392    OUT_RING  (chan, NV50_3D_COND_MODE_ALWAYS);
 393
 394    BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
 395    OUT_RING  (chan, screen->sync->handle);
 396    BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
 397    for (i = 0; i < 11; ++i)
 398       OUT_RING(chan, chan->vram->handle);
 399    BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 400    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 401       OUT_RING(chan, chan->vram->handle);
 402
 403    BEGIN_RING(chan, RING_3D(REG_MODE), 1);
 404    OUT_RING  (chan, NV50_3D_REG_MODE_STRIPED);
 405    BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
 406    OUT_RING  (chan, 0xf);
 407
 408    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 409    OUT_RING  (chan, 1);
 410
 411    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 412    OUT_RING  (chan, 0);
 413    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 414    OUT_RING  (chan, 0);
 415    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 416    OUT_RING  (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
 417    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 418    OUT_RING  (chan, 0);
 419    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 420    OUT_RING  (chan, 0);
 421    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 422    OUT_RING  (chan, 1);
 423
 424    if (tesla_class >= NVA0_3D) {
 425       BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1);
 426       OUT_RING  (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 427    }
 428
 429    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 430    OUT_RING  (chan, 0);
 431    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 432    OUT_RING  (chan, 0);
 433    OUT_RING  (chan, 0);
 434    BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 435    OUT_RING  (chan, 0x3f);
 436
 437    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 438                         3 << NV50_CODE_BO_SIZE_LOG2, &screen->code);
 439    if (ret)
 440       goto fail;
 441
 442    nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 443    nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 444    nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 445
 446    base = 1 << NV50_CODE_BO_SIZE_LOG2;
 447
 448    BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
 449    OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 450    OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 451
 452    BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
 453    OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 454    OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 455
 456    BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
 457    OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 458    OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 459
 460    nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 461
 462    max_warps  = util_bitcount(value & 0xffff);
 463    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 464
 465    stack_size = max_warps * 64 * 8;
 466
 467    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
 468                         &screen->stack_bo);
 469    if (ret)
 470       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 471
 472    BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
 473    OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 474    OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 475    OUT_RING  (chan, 4);
 476
 477    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 478
 479    screen->tls_size = tls_space * max_warps * 32;
 480
 481    debug_printf("max_warps = %i, tls_size = %llu KiB\n",
 482                 max_warps, screen->tls_size >> 10);
 483
 484    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
 485                         &screen->tls_bo);
 486    if (ret)
 487       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 488
 489    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
 490    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 491    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 492    OUT_RING  (chan, util_logbase2(tls_space / 8));
 493
 494    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
 495                         &screen->uniforms);
 496    if (ret)
 497       goto fail;
 498
 499    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 500    OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 501    OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 502    OUT_RING  (chan, (NV50_CB_PVP << 16) | 0x0000);
 503
 504    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 505    OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 506    OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 507    OUT_RING  (chan, (NV50_CB_PGP << 16) | 0x0000);
 508
 509    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 510    OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 511    OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 512    OUT_RING  (chan, (NV50_CB_PFP << 16) | 0x0000);
 513
 514    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 515    OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 516    OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 517    OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 518
 519    BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
 520    OUT_RING  (chan, (NV50_CB_PVP << 12) | 0x001);
 521    OUT_RING  (chan, (NV50_CB_PGP << 12) | 0x021);
 522    OUT_RING  (chan, (NV50_CB_PFP << 12) | 0x031);
 523    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf01);
 524    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf21);
 525    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf31);
 526
 527    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
 528                         &screen->txc);
 529    if (ret)
 530       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 531
 532    /* max TIC (bits 4:8) & TSC bindings, per program type */
 533    for (i = 0; i < 3; ++i) {
 534       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 535       OUT_RING  (chan, 0x54);
 536    }
 537
 538    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 539    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 540    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 541    OUT_RING  (chan, NV50_TIC_MAX_ENTRIES - 1);
 542
 543    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 544    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 545    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 546    OUT_RING  (chan, NV50_TSC_MAX_ENTRIES - 1);
 547
 548    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 549    OUT_RING  (chan, 0);
 550
 551    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 552    OUT_RING  (chan, 0);
 553    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 554    OUT_RING  (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 555    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 556    for (i = 0; i < 8 * 2; ++i)
 557       OUT_RING(chan, 0);
 558    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 559    OUT_RING  (chan, 0);
 560
 561    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 562    OUT_RING  (chan, 1);
 563    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 564    OUT_RINGf (chan, 0.0f);
 565    OUT_RINGf (chan, 1.0f);
 566
 567    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 568 #ifdef NV50_SCISSORS_CLIPPING
 569    OUT_RING  (chan, 0x0000);
 570 #else
 571    OUT_RING  (chan, 0x1080);
 572 #endif
 573
 574    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 575    OUT_RING  (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 576
 577    /* We use scissors instead of exact view volume clipping,
 578     * so they're always enabled.
 579     */
 580    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 581    OUT_RING  (chan, 1);
 582    OUT_RING  (chan, 8192 << 16);
 583    OUT_RING  (chan, 8192 << 16);
 584
 585    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 586    OUT_RING  (chan, 1);
 587    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 588    OUT_RING  (chan, NV50_3D_POINT_RASTER_RULES_OGL);
 589    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 590    OUT_RING  (chan, 0x11111111);
 591    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 592    OUT_RING  (chan, 1);
 593
 594    FIRE_RING (chan);
 595
 596    screen->tic.entries = CALLOC(4096, sizeof(void *));
 597    screen->tsc.entries = screen->tic.entries + 2048;
 598
 599    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 600
 601    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 602
 603    return pscreen;
 604
 605 fail:
 606    nv50_screen_destroy(pscreen);
 607    return NULL;
 608 }
 609
 610 void
 611 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
 612 {
 613    struct nouveau_channel *chan = screen->base.channel;
 614
 615    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 616
 617    MARK_RING(chan, 5, 5);
 618    nouveau_bo_validate(chan, screen->code, flags);
 619    nouveau_bo_validate(chan, screen->uniforms, flags);
 620    nouveau_bo_validate(chan, screen->txc, flags);
 621    nouveau_bo_validate(chan, screen->tls_bo, flags);
 622    nouveau_bo_validate(chan, screen->stack_bo, flags);
 623 }
 624
 625 int
 626 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 627 {
 628    int i = screen->tic.next;
 629
 630    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 631       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 632
 633    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 634
 635    if (screen->tic.entries[i])
 636       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 637
 638    screen->tic.entries[i] = entry;
 639    return i;
 640 }
 641
 642 int
 643 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 644 {
 645    int i = screen->tsc.next;
 646
 647    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 648       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 649
 650    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 651
 652    if (screen->tsc.entries[i])
 653       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 654
 655    screen->tsc.entries[i] = entry;
 656    return i;
 657 }