2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
27 #include "nv50_context.h"
28 #include "nv50_screen.h"
30 #include "nouveau/nv_object.xml.h"
32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
36 extern int nouveau_device_get_param(struct nouveau_device
*dev
,
37 uint64_t param
, uint64_t *value
);
40 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
41 enum pipe_format format
,
42 enum pipe_texture_target target
,
43 unsigned sample_count
,
46 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
48 if (sample_count
== 8 && util_format_get_blocksizebits(format
) >= 128)
51 if (!util_format_is_supported(format
, bindings
))
55 case PIPE_FORMAT_Z16_UNORM
:
56 if (nv50_screen(pscreen
)->tesla
->grclass
< NVA0_3D
)
59 case PIPE_FORMAT_R8G8B8A8_UNORM
:
60 case PIPE_FORMAT_R8G8B8X8_UNORM
:
61 /* HACK: GL requires equal formats for MS resolve and window is BGRA */
62 if (bindings
& PIPE_BIND_RENDER_TARGET
)
68 /* transfers & shared are always supported */
69 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
70 PIPE_BIND_TRANSFER_WRITE
|
73 return (nv50_format_table
[format
].usage
& bindings
) == bindings
;
77 nv50_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
80 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
82 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
84 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
86 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
88 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
: /* shader support missing */
90 case PIPE_CAP_MIN_TEXEL_OFFSET
:
91 return 0 /* -8, TODO */;
92 case PIPE_CAP_MAX_TEXEL_OFFSET
:
93 return 0 /* +7, TODO */;
94 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
95 case PIPE_CAP_TEXTURE_SWIZZLE
:
96 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
97 case PIPE_CAP_NPOT_TEXTURES
:
98 case PIPE_CAP_ANISOTROPIC_FILTER
:
99 case PIPE_CAP_SCALED_RESOLVE
:
101 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
102 return nv50_screen(pscreen
)->tesla
->grclass
>= NVA0_3D
;
103 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
105 case PIPE_CAP_TWO_SIDED_STENCIL
:
106 case PIPE_CAP_DEPTH_CLAMP
:
107 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
108 case PIPE_CAP_POINT_SPRITE
:
113 case PIPE_CAP_MAX_RENDER_TARGETS
:
115 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL
:
117 case PIPE_CAP_TIMER_QUERY
:
118 case PIPE_CAP_OCCLUSION_QUERY
:
120 case PIPE_CAP_STREAM_OUTPUT
:
122 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
123 case PIPE_CAP_INDEP_BLEND_ENABLE
:
125 case PIPE_CAP_INDEP_BLEND_FUNC
:
126 return nv50_screen(pscreen
)->tesla
->grclass
>= NVA3_3D
;
127 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
128 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
130 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
131 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
133 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
135 case PIPE_CAP_PRIMITIVE_RESTART
:
136 case PIPE_CAP_TGSI_INSTANCEID
:
137 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
138 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
139 case PIPE_CAP_CONDITIONAL_RENDER
:
142 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
148 nv50_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
149 enum pipe_shader_cap param
)
152 case PIPE_SHADER_VERTEX
:
153 case PIPE_SHADER_GEOMETRY
:
154 case PIPE_SHADER_FRAGMENT
:
161 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
162 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
163 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
164 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
166 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
168 case PIPE_SHADER_CAP_MAX_INPUTS
:
169 if (shader
== PIPE_SHADER_VERTEX
)
172 case PIPE_SHADER_CAP_MAX_CONSTS
:
174 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
176 case PIPE_SHADER_CAP_MAX_ADDRS
:
178 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
179 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
180 return shader
!= PIPE_SHADER_FRAGMENT
;
181 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
182 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
184 case PIPE_SHADER_CAP_MAX_PREDS
:
186 case PIPE_SHADER_CAP_MAX_TEMPS
:
187 return NV50_CAP_MAX_PROGRAM_TEMPS
;
188 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
190 case PIPE_SHADER_CAP_SUBROUTINES
:
191 return 0; /* please inline, or provide function declarations */
192 case PIPE_SHADER_CAP_INTEGERS
:
194 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
197 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
203 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_cap param
)
206 case PIPE_CAP_MAX_LINE_WIDTH
:
207 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
209 case PIPE_CAP_MAX_POINT_WIDTH
:
210 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
212 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
214 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
217 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
223 nv50_screen_destroy(struct pipe_screen
*pscreen
)
225 struct nv50_screen
*screen
= nv50_screen(pscreen
);
227 if (screen
->base
.fence
.current
) {
228 nouveau_fence_wait(screen
->base
.fence
.current
);
229 nouveau_fence_ref (NULL
, &screen
->base
.fence
.current
);
231 screen
->base
.channel
->user_private
= NULL
;
233 FREE(screen
->blitctx
);
235 nouveau_bo_ref(NULL
, &screen
->code
);
236 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
237 nouveau_bo_ref(NULL
, &screen
->stack_bo
);
238 nouveau_bo_ref(NULL
, &screen
->txc
);
239 nouveau_bo_ref(NULL
, &screen
->uniforms
);
240 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
242 nouveau_resource_destroy(&screen
->vp_code_heap
);
243 nouveau_resource_destroy(&screen
->gp_code_heap
);
244 nouveau_resource_destroy(&screen
->fp_code_heap
);
246 if (screen
->tic
.entries
)
247 FREE(screen
->tic
.entries
);
249 nouveau_mm_destroy(screen
->mm_VRAM_fe0
);
251 nouveau_grobj_free(&screen
->tesla
);
252 nouveau_grobj_free(&screen
->eng2d
);
253 nouveau_grobj_free(&screen
->m2mf
);
255 nouveau_notifier_free(&screen
->sync
);
257 nouveau_screen_fini(&screen
->base
);
263 nv50_screen_fence_emit(struct pipe_screen
*pscreen
, u32 sequence
)
265 struct nv50_screen
*screen
= nv50_screen(pscreen
);
266 struct nouveau_channel
*chan
= screen
->base
.channel
;
268 MARK_RING (chan
, 5, 2);
269 BEGIN_RING(chan
, RING_3D(QUERY_ADDRESS_HIGH
), 4);
270 OUT_RELOCh(chan
, screen
->fence
.bo
, 0, NOUVEAU_BO_WR
);
271 OUT_RELOCl(chan
, screen
->fence
.bo
, 0, NOUVEAU_BO_WR
);
272 OUT_RING (chan
, sequence
);
273 OUT_RING (chan
, NV50_3D_QUERY_GET_MODE_WRITE_UNK0
|
274 NV50_3D_QUERY_GET_UNK4
|
275 NV50_3D_QUERY_GET_UNIT_CROP
|
276 NV50_3D_QUERY_GET_TYPE_QUERY
|
277 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO
|
278 NV50_3D_QUERY_GET_SHORT
);
282 nv50_screen_fence_update(struct pipe_screen
*pscreen
)
284 struct nv50_screen
*screen
= nv50_screen(pscreen
);
285 return screen
->fence
.map
[0];
288 #define FAIL_SCREEN_INIT(str, err) \
290 NOUVEAU_ERR(str, err); \
291 nv50_screen_destroy(pscreen); \
296 nv50_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
298 struct nv50_screen
*screen
;
299 struct nouveau_channel
*chan
;
300 struct pipe_screen
*pscreen
;
302 uint32_t tesla_class
;
303 unsigned stack_size
, max_warps
, tls_space
;
307 screen
= CALLOC_STRUCT(nv50_screen
);
310 pscreen
= &screen
->base
.base
;
312 screen
->base
.sysmem_bindings
= PIPE_BIND_CONSTANT_BUFFER
;
314 ret
= nouveau_screen_init(&screen
->base
, dev
);
316 FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret
);
318 chan
= screen
->base
.channel
;
319 chan
->user_private
= screen
;
321 pscreen
->winsys
= ws
;
322 pscreen
->destroy
= nv50_screen_destroy
;
323 pscreen
->context_create
= nv50_create
;
324 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
325 pscreen
->get_param
= nv50_screen_get_param
;
326 pscreen
->get_shader_param
= nv50_screen_get_shader_param
;
327 pscreen
->get_paramf
= nv50_screen_get_paramf
;
329 nv50_screen_init_resource_functions(pscreen
);
331 nouveau_screen_init_vdec(&screen
->base
);
333 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096,
337 nouveau_bo_map(screen
->fence
.bo
, NOUVEAU_BO_RDWR
);
338 screen
->fence
.map
= screen
->fence
.bo
->map
;
339 nouveau_bo_unmap(screen
->fence
.bo
);
340 screen
->base
.fence
.emit
= nv50_screen_fence_emit
;
341 screen
->base
.fence
.update
= nv50_screen_fence_update
;
343 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
345 FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret
);
347 ret
= nouveau_grobj_alloc(chan
, 0xbeef5039, NV50_M2MF
, &screen
->m2mf
);
349 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
351 BIND_RING (chan
, screen
->m2mf
, NV50_SUBCH_MF
);
352 BEGIN_RING(chan
, RING_MF_(NV04_M2MF_DMA_NOTIFY
), 3);
353 OUT_RING (chan
, screen
->sync
->handle
);
354 OUT_RING (chan
, chan
->vram
->handle
);
355 OUT_RING (chan
, chan
->vram
->handle
);
357 ret
= nouveau_grobj_alloc(chan
, 0xbeef502d, NV50_2D
, &screen
->eng2d
);
359 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
361 BIND_RING (chan
, screen
->eng2d
, NV50_SUBCH_2D
);
362 BEGIN_RING(chan
, RING_2D(DMA_NOTIFY
), 4);
363 OUT_RING (chan
, screen
->sync
->handle
);
364 OUT_RING (chan
, chan
->vram
->handle
);
365 OUT_RING (chan
, chan
->vram
->handle
);
366 OUT_RING (chan
, chan
->vram
->handle
);
367 BEGIN_RING(chan
, RING_2D(OPERATION
), 1);
368 OUT_RING (chan
, NV50_2D_OPERATION_SRCCOPY
);
369 BEGIN_RING(chan
, RING_2D(CLIP_ENABLE
), 1);
371 BEGIN_RING(chan
, RING_2D(COLOR_KEY_ENABLE
), 1);
373 BEGIN_RING(chan
, RING_2D_(0x0888), 1);
376 switch (dev
->chipset
& 0xf0) {
378 tesla_class
= NV50_3D
;
382 tesla_class
= NV84_3D
;
385 switch (dev
->chipset
) {
389 tesla_class
= NVA0_3D
;
392 tesla_class
= NVAF_3D
;
395 tesla_class
= NVA3_3D
;
400 FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev
->chipset
);
404 ret
= nouveau_grobj_alloc(chan
, 0xbeef5097, tesla_class
, &screen
->tesla
);
406 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
408 BIND_RING (chan
, screen
->tesla
, NV50_SUBCH_3D
);
410 BEGIN_RING(chan
, RING_3D(COND_MODE
), 1);
411 OUT_RING (chan
, NV50_3D_COND_MODE_ALWAYS
);
413 BEGIN_RING(chan
, RING_3D(DMA_NOTIFY
), 1);
414 OUT_RING (chan
, screen
->sync
->handle
);
415 BEGIN_RING(chan
, RING_3D(DMA_ZETA
), 11);
416 for (i
= 0; i
< 11; ++i
)
417 OUT_RING(chan
, chan
->vram
->handle
);
418 BEGIN_RING(chan
, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN
);
419 for (i
= 0; i
< NV50_3D_DMA_COLOR__LEN
; ++i
)
420 OUT_RING(chan
, chan
->vram
->handle
);
422 BEGIN_RING(chan
, RING_3D(REG_MODE
), 1);
423 OUT_RING (chan
, NV50_3D_REG_MODE_STRIPED
);
424 BEGIN_RING(chan
, RING_3D(UNK1400_LANES
), 1);
425 OUT_RING (chan
, 0xf);
427 BEGIN_RING(chan
, RING_3D(RT_CONTROL
), 1);
430 BEGIN_RING(chan
, RING_3D(CSAA_ENABLE
), 1);
432 BEGIN_RING(chan
, RING_3D(MULTISAMPLE_ENABLE
), 1);
434 BEGIN_RING(chan
, RING_3D(MULTISAMPLE_MODE
), 1);
435 OUT_RING (chan
, NV50_3D_MULTISAMPLE_MODE_MS1
);
436 BEGIN_RING(chan
, RING_3D(MULTISAMPLE_CTRL
), 1);
438 BEGIN_RING(chan
, RING_3D(LINE_LAST_PIXEL
), 1);
440 BEGIN_RING(chan
, RING_3D(BLEND_SEPARATE_ALPHA
), 1);
443 if (tesla_class
>= NVA0_3D
) {
444 BEGIN_RING(chan
, RING_3D_(NVA0_3D_TEX_MISC
), 1);
445 OUT_RING (chan
, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
448 BEGIN_RING(chan
, RING_3D(SCREEN_Y_CONTROL
), 1);
450 BEGIN_RING(chan
, RING_3D(WINDOW_OFFSET_X
), 2);
453 BEGIN_RING(chan
, RING_3D(ZCULL_REGION
), 1); /* deactivate ZCULL */
454 OUT_RING (chan
, 0x3f);
456 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
457 3 << NV50_CODE_BO_SIZE_LOG2
, &screen
->code
);
461 nouveau_resource_init(&screen
->vp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
462 nouveau_resource_init(&screen
->gp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
463 nouveau_resource_init(&screen
->fp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
465 base
= 1 << NV50_CODE_BO_SIZE_LOG2
;
467 BEGIN_RING(chan
, RING_3D(VP_ADDRESS_HIGH
), 2);
468 OUT_RELOCh(chan
, screen
->code
, base
* 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
469 OUT_RELOCl(chan
, screen
->code
, base
* 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
471 BEGIN_RING(chan
, RING_3D(FP_ADDRESS_HIGH
), 2);
472 OUT_RELOCh(chan
, screen
->code
, base
* 1, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
473 OUT_RELOCl(chan
, screen
->code
, base
* 1, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
475 BEGIN_RING(chan
, RING_3D(GP_ADDRESS_HIGH
), 2);
476 OUT_RELOCh(chan
, screen
->code
, base
* 2, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
477 OUT_RELOCl(chan
, screen
->code
, base
* 2, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
479 nouveau_device_get_param(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
481 max_warps
= util_bitcount(value
& 0xffff);
482 max_warps
*= util_bitcount((value
>> 24) & 0xf) * 32;
484 stack_size
= max_warps
* 64 * 8;
486 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, stack_size
,
489 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret
);
491 BEGIN_RING(chan
, RING_3D(STACK_ADDRESS_HIGH
), 3);
492 OUT_RELOCh(chan
, screen
->stack_bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
493 OUT_RELOCl(chan
, screen
->stack_bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
496 tls_space
= NV50_CAP_MAX_PROGRAM_TEMPS
* 16;
498 screen
->tls_size
= tls_space
* max_warps
* 32;
500 debug_printf("max_warps = %i, tls_size = %"PRIu64
" KiB\n",
501 max_warps
, screen
->tls_size
>> 10);
503 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, screen
->tls_size
,
506 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret
);
508 BEGIN_RING(chan
, RING_3D(LOCAL_ADDRESS_HIGH
), 3);
509 OUT_RELOCh(chan
, screen
->tls_bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
510 OUT_RELOCl(chan
, screen
->tls_bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
511 OUT_RING (chan
, util_logbase2(tls_space
/ 8));
513 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 4 << 16,
518 BEGIN_RING(chan
, RING_3D(CB_DEF_ADDRESS_HIGH
), 3);
519 OUT_RELOCh(chan
, screen
->uniforms
, 0 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
520 OUT_RELOCl(chan
, screen
->uniforms
, 0 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
521 OUT_RING (chan
, (NV50_CB_PVP
<< 16) | 0x0000);
523 BEGIN_RING(chan
, RING_3D(CB_DEF_ADDRESS_HIGH
), 3);
524 OUT_RELOCh(chan
, screen
->uniforms
, 1 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
525 OUT_RELOCl(chan
, screen
->uniforms
, 1 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
526 OUT_RING (chan
, (NV50_CB_PGP
<< 16) | 0x0000);
528 BEGIN_RING(chan
, RING_3D(CB_DEF_ADDRESS_HIGH
), 3);
529 OUT_RELOCh(chan
, screen
->uniforms
, 2 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
530 OUT_RELOCl(chan
, screen
->uniforms
, 2 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
531 OUT_RING (chan
, (NV50_CB_PFP
<< 16) | 0x0000);
533 BEGIN_RING(chan
, RING_3D(CB_DEF_ADDRESS_HIGH
), 3);
534 OUT_RELOCh(chan
, screen
->uniforms
, 3 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
535 OUT_RELOCl(chan
, screen
->uniforms
, 3 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
536 OUT_RING (chan
, (NV50_CB_AUX
<< 16) | 0x0200);
538 BEGIN_RING_NI(chan
, RING_3D(SET_PROGRAM_CB
), 6);
539 OUT_RING (chan
, (NV50_CB_PVP
<< 12) | 0x001);
540 OUT_RING (chan
, (NV50_CB_PGP
<< 12) | 0x021);
541 OUT_RING (chan
, (NV50_CB_PFP
<< 12) | 0x031);
542 OUT_RING (chan
, (NV50_CB_AUX
<< 12) | 0xf01);
543 OUT_RING (chan
, (NV50_CB_AUX
<< 12) | 0xf21);
544 OUT_RING (chan
, (NV50_CB_AUX
<< 12) | 0xf31);
546 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 3 << 16,
549 FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret
);
551 /* max TIC (bits 4:8) & TSC bindings, per program type */
552 for (i
= 0; i
< 3; ++i
) {
553 BEGIN_RING(chan
, RING_3D(TEX_LIMITS(i
)), 1);
554 OUT_RING (chan
, 0x54);
557 BEGIN_RING(chan
, RING_3D(TIC_ADDRESS_HIGH
), 3);
558 OUT_RELOCh(chan
, screen
->txc
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
559 OUT_RELOCl(chan
, screen
->txc
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
560 OUT_RING (chan
, NV50_TIC_MAX_ENTRIES
- 1);
562 BEGIN_RING(chan
, RING_3D(TSC_ADDRESS_HIGH
), 3);
563 OUT_RELOCh(chan
, screen
->txc
, 65536, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
564 OUT_RELOCl(chan
, screen
->txc
, 65536, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
565 OUT_RING (chan
, NV50_TSC_MAX_ENTRIES
- 1);
567 BEGIN_RING(chan
, RING_3D(LINKED_TSC
), 1);
570 BEGIN_RING(chan
, RING_3D(CLIP_RECTS_EN
), 1);
572 BEGIN_RING(chan
, RING_3D(CLIP_RECTS_MODE
), 1);
573 OUT_RING (chan
, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
574 BEGIN_RING(chan
, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
575 for (i
= 0; i
< 8 * 2; ++i
)
577 BEGIN_RING(chan
, RING_3D(CLIPID_ENABLE
), 1);
580 BEGIN_RING(chan
, RING_3D(VIEWPORT_TRANSFORM_EN
), 1);
582 BEGIN_RING(chan
, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
583 OUT_RINGf (chan
, 0.0f
);
584 OUT_RINGf (chan
, 1.0f
);
586 BEGIN_RING(chan
, RING_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
587 #ifdef NV50_SCISSORS_CLIPPING
588 OUT_RING (chan
, 0x0000);
590 OUT_RING (chan
, 0x1080);
593 BEGIN_RING(chan
, RING_3D(CLEAR_FLAGS
), 1);
594 OUT_RING (chan
, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT
);
596 /* We use scissors instead of exact view volume clipping,
597 * so they're always enabled.
599 BEGIN_RING(chan
, RING_3D(SCISSOR_ENABLE(0)), 3);
601 OUT_RING (chan
, 8192 << 16);
602 OUT_RING (chan
, 8192 << 16);
604 BEGIN_RING(chan
, RING_3D(RASTERIZE_ENABLE
), 1);
606 BEGIN_RING(chan
, RING_3D(POINT_RASTER_RULES
), 1);
607 OUT_RING (chan
, NV50_3D_POINT_RASTER_RULES_OGL
);
608 BEGIN_RING(chan
, RING_3D(FRAG_COLOR_CLAMP_EN
), 1);
609 OUT_RING (chan
, 0x11111111);
610 BEGIN_RING(chan
, RING_3D(EDGEFLAG_ENABLE
), 1);
615 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
616 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
618 screen
->mm_VRAM_fe0
= nouveau_mm_create(dev
, NOUVEAU_BO_VRAM
, 0xfe0);
620 if (!nv50_blitctx_create(screen
))
623 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);
628 nv50_screen_destroy(pscreen
);
633 nv50_screen_make_buffers_resident(struct nv50_screen
*screen
)
635 struct nouveau_channel
*chan
= screen
->base
.channel
;
637 const unsigned flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
;
639 MARK_RING(chan
, 5, 5);
640 nouveau_bo_validate(chan
, screen
->code
, flags
);
641 nouveau_bo_validate(chan
, screen
->uniforms
, flags
);
642 nouveau_bo_validate(chan
, screen
->txc
, flags
);
643 nouveau_bo_validate(chan
, screen
->tls_bo
, flags
);
644 nouveau_bo_validate(chan
, screen
->stack_bo
, flags
);
648 nv50_screen_tic_alloc(struct nv50_screen
*screen
, void *entry
)
650 int i
= screen
->tic
.next
;
652 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
653 i
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
655 screen
->tic
.next
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
657 if (screen
->tic
.entries
[i
])
658 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
660 screen
->tic
.entries
[i
] = entry
;
665 nv50_screen_tsc_alloc(struct nv50_screen
*screen
, void *entry
)
667 int i
= screen
->tsc
.next
;
669 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
670 i
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
672 screen
->tsc
.next
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
674 if (screen
->tsc
.entries
[i
])
675 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
677 screen
->tsc
.entries
[i
] = entry
;