1 #include "pipe/p_screen.h"
2 #include "pipe/p_util.h"
4 #include "nv50_context.h"
5 #include "nv50_screen.h"
7 #include "nouveau/nouveau_stateobj.h"
9 #define NV5X_GRCLASS5097_CHIPSETS 0x00000001
10 #define NV8X_GRCLASS8297_CHIPSETS 0x00000010
11 #define NV9X_GRCLASS8297_CHIPSETS 0x00000004
14 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
15 enum pipe_format format
, uint type
)
20 case PIPE_FORMAT_A8R8G8B8_UNORM
:
21 case PIPE_FORMAT_R5G6B5_UNORM
:
22 case PIPE_FORMAT_Z24S8_UNORM
:
23 case PIPE_FORMAT_Z16_UNORM
:
31 case PIPE_FORMAT_I8_UNORM
:
45 nv50_screen_get_name(struct pipe_screen
*pscreen
)
47 struct nv50_screen
*screen
= nv50_screen(pscreen
);
48 struct nouveau_device
*dev
= screen
->nvws
->channel
->device
;
49 static char buffer
[128];
51 snprintf(buffer
, sizeof(buffer
), "NV%02X", dev
->chipset
);
56 nv50_screen_get_vendor(struct pipe_screen
*pscreen
)
62 nv50_screen_get_param(struct pipe_screen
*pscreen
, int param
)
65 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
67 case PIPE_CAP_NPOT_TEXTURES
:
69 case PIPE_CAP_TWO_SIDED_STENCIL
:
75 case PIPE_CAP_ANISOTROPIC_FILTER
:
77 case PIPE_CAP_POINT_SPRITE
:
79 case PIPE_CAP_MAX_RENDER_TARGETS
:
81 case PIPE_CAP_OCCLUSION_QUERY
:
83 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
85 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
87 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
89 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
91 case NOUVEAU_CAP_HW_VTXBUF
:
92 case NOUVEAU_CAP_HW_IDXBUF
:
95 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
101 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
104 case PIPE_CAP_MAX_LINE_WIDTH
:
105 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
107 case PIPE_CAP_MAX_POINT_WIDTH
:
108 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
110 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
112 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
115 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
121 nv50_surface_map(struct pipe_screen
*screen
, struct pipe_surface
*surface
,
124 struct pipe_winsys
*ws
= screen
->winsys
;
127 map
= ws
->buffer_map(ws
, surface
->buffer
, flags
);
131 return map
+ surface
->offset
;
135 nv50_surface_unmap(struct pipe_screen
*screen
, struct pipe_surface
*surface
)
137 struct pipe_winsys
*ws
= screen
->winsys
;
139 ws
->buffer_unmap(ws
, surface
->buffer
);
143 nv50_screen_destroy(struct pipe_screen
*pscreen
)
149 nv50_screen_create(struct pipe_winsys
*ws
, struct nouveau_winsys
*nvws
)
151 struct nv50_screen
*screen
= CALLOC_STRUCT(nv50_screen
);
152 struct nouveau_stateobj
*so
;
153 unsigned tesla_class
= 0, ret
;
154 unsigned chipset
= nvws
->channel
->device
->chipset
;
162 if ((chipset
& 0xf0) != 0x50 && (chipset
& 0xf0) != 0x80) {
163 NOUVEAU_ERR("Not a G8x chipset\n");
164 nv50_screen_destroy(&screen
->pipe
);
168 switch (chipset
& 0xf0) {
170 if (NV5X_GRCLASS5097_CHIPSETS
& (1 << (chipset
& 0x0f)))
171 tesla_class
= 0x5097;
174 if (NV8X_GRCLASS8297_CHIPSETS
& (1 << (chipset
& 0x0f)))
175 tesla_class
= 0x8297;
178 if (NV9X_GRCLASS8297_CHIPSETS
& (1 << (chipset
& 0x0f)))
179 tesla_class
= 0x8297;
185 if (tesla_class
== 0) {
186 NOUVEAU_ERR("Unknown G8x chipset: NV%02x\n", chipset
);
187 nv50_screen_destroy(&screen
->pipe
);
191 ret
= nvws
->grobj_alloc(nvws
, tesla_class
, &screen
->tesla
);
193 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
194 nv50_screen_destroy(&screen
->pipe
);
199 ret
= nvws
->notifier_alloc(nvws
, 1, &screen
->sync
);
201 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
202 nv50_screen_destroy(&screen
->pipe
);
206 /* Static tesla init */
207 so
= so_new(256, 20);
209 so_method(so
, screen
->tesla
, 0x1558, 1);
211 so_method(so
, screen
->tesla
, NV50TCL_DMA_NOTIFY
, 1);
212 so_data (so
, screen
->sync
->handle
);
213 so_method(so
, screen
->tesla
, NV50TCL_DMA_IN_MEMORY0(0),
214 NV50TCL_DMA_IN_MEMORY0__SIZE
);
215 for (i
= 0; i
< NV50TCL_DMA_IN_MEMORY0__SIZE
; i
++)
216 so_data(so
, nvws
->channel
->vram
->handle
);
217 so_method(so
, screen
->tesla
, NV50TCL_DMA_IN_MEMORY1(0),
218 NV50TCL_DMA_IN_MEMORY1__SIZE
);
219 for (i
= 0; i
< NV50TCL_DMA_IN_MEMORY1__SIZE
; i
++)
220 so_data(so
, nvws
->channel
->vram
->handle
);
221 so_method(so
, screen
->tesla
, 0x121c, 1);
224 so_method(so
, screen
->tesla
, 0x13bc, 1);
226 so_method(so
, screen
->tesla
, 0x13ac, 1);
228 so_method(so
, screen
->tesla
, 0x16b8, 1);
231 /* Shared constant buffer */
232 screen
->constbuf
= ws
->buffer_create(ws
, 0, 0, 128 * 4 * 4);
233 if (nvws
->res_init(&screen
->vp_data_heap
, 0, 128)) {
234 NOUVEAU_ERR("Error initialising constant buffer\n");
235 nv50_screen_destroy(&screen
->pipe
);
239 so_method(so
, screen
->tesla
, 0x1280, 3);
240 so_reloc (so
, screen
->constbuf
, 0, NOUVEAU_BO_VRAM
|
241 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
242 so_reloc (so
, screen
->constbuf
, 0, NOUVEAU_BO_VRAM
|
243 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
244 so_data (so
, (NV50_CB_PMISC
<< 16) | 0x00001000);
246 /* Texture sampler/image unit setup - we abuse the constant buffer
247 * upload mechanism for the moment to upload data to the tex config
248 * blocks. At some point we *may* want to go the NVIDIA way of doing
251 screen
->tic
= ws
->buffer_create(ws
, 0, 0, 32 * 8 * 4);
252 so_method(so
, screen
->tesla
, 0x1280, 3);
253 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
254 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
255 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
256 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
257 so_data (so
, (NV50_CB_TIC
<< 16) | 0x0800);
258 so_method(so
, screen
->tesla
, 0x1574, 3);
259 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
260 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
261 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
262 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
263 so_data (so
, 0x00000800);
265 screen
->tsc
= ws
->buffer_create(ws
, 0, 0, 32 * 8 * 4);
266 so_method(so
, screen
->tesla
, 0x1280, 3);
267 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
268 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
269 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
270 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
271 so_data (so
, (NV50_CB_TSC
<< 16) | 0x0800);
272 so_method(so
, screen
->tesla
, 0x155c, 3);
273 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
274 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
275 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
276 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
277 so_data (so
, 0x00000800);
280 /* Vertex array limits - max them out */
281 for (i
= 0; i
< 16; i
++) {
282 so_method(so
, screen
->tesla
, 0x1080 + (i
* 8), 2);
283 so_data (so
, 0x000000ff);
284 so_data (so
, 0xffffffff);
287 so_method(so
, screen
->tesla
, NV50TCL_DEPTH_RANGE_NEAR
, 2);
288 so_data (so
, fui(0.0));
289 so_data (so
, fui(1.0));
293 nvws
->push_flush(nvws
, 0, NULL
);
295 screen
->pipe
.winsys
= ws
;
297 screen
->pipe
.destroy
= nv50_screen_destroy
;
299 screen
->pipe
.get_name
= nv50_screen_get_name
;
300 screen
->pipe
.get_vendor
= nv50_screen_get_vendor
;
301 screen
->pipe
.get_param
= nv50_screen_get_param
;
302 screen
->pipe
.get_paramf
= nv50_screen_get_paramf
;
304 screen
->pipe
.is_format_supported
= nv50_screen_is_format_supported
;
306 screen
->pipe
.surface_map
= nv50_surface_map
;
307 screen
->pipe
.surface_unmap
= nv50_surface_unmap
;
309 nv50_screen_init_miptree_functions(&screen
->pipe
);
311 return &screen
->pipe
;