src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31 #include <errno.h>
  32
  33 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  34 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  35 #endif
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  45
  46 static boolean
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  54       return FALSE;
  55    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  56       return FALSE;
  57
  58    if (!util_format_is_supported(format, bindings))
  59       return FALSE;
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  64          return FALSE;
  65       break;
  66    case PIPE_FORMAT_R8G8B8A8_UNORM:
  67    case PIPE_FORMAT_R8G8B8X8_UNORM:
  68       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  69       if (bindings & PIPE_BIND_RENDER_TARGET)
  70          return FALSE;
  71    default:
  72       break;
  73    }
  74
  75    /* transfers & shared are always supported */
  76    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  77                  PIPE_BIND_TRANSFER_WRITE |
  78                  PIPE_BIND_SHARED);
  79
  80    return (nv50_format_table[format].usage & bindings) == bindings;
  81 }
  82
  83 static int
  84 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  85 {
  86    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  87
  88    switch (param) {
  89    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  90       return 64;
  91    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  92       return 14;
  93    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  94       return 12;
  95    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  96       return 14;
  97    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  98       return 512;
  99    case PIPE_CAP_MIN_TEXEL_OFFSET:
 100       return -8;
 101    case PIPE_CAP_MAX_TEXEL_OFFSET:
 102       return 7;
 103    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 104    case PIPE_CAP_TEXTURE_SWIZZLE:
 105    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 106    case PIPE_CAP_NPOT_TEXTURES:
 107    case PIPE_CAP_ANISOTROPIC_FILTER:
 108    case PIPE_CAP_SCALED_RESOLVE:
 109       return 1;
 110    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 111       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 112    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 113       return 0;
 114    case PIPE_CAP_TWO_SIDED_STENCIL:
 115    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 116    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 117    case PIPE_CAP_POINT_SPRITE:
 118       return 1;
 119    case PIPE_CAP_SM3:
 120       return 1;
 121    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 122       return 130;
 123    case PIPE_CAP_MAX_RENDER_TARGETS:
 124       return 8;
 125    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 126       return 1;
 127    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 128    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 129    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 130       return 1;
 131    case PIPE_CAP_QUERY_TIMESTAMP:
 132    case PIPE_CAP_TIMER_QUERY:
 133    case PIPE_CAP_OCCLUSION_QUERY:
 134       return 1;
 135    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 136       return 4;
 137    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 138    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 139       return 64;
 140    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 141       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 142    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 143    case PIPE_CAP_INDEP_BLEND_ENABLE:
 144       return 1;
 145    case PIPE_CAP_INDEP_BLEND_FUNC:
 146       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 147    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 148    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 149       return 1;
 150    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 151    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 152       return 0;
 153    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 154       return 0;
 155    case PIPE_CAP_PRIMITIVE_RESTART:
 156    case PIPE_CAP_TGSI_INSTANCEID:
 157    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 158    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 159    case PIPE_CAP_CONDITIONAL_RENDER:
 160    case PIPE_CAP_TEXTURE_BARRIER:
 161    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 162    case PIPE_CAP_START_INSTANCE:
 163       return 1;
 164    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 165    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 166       return 0; /* state trackers will know better */
 167    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 168    case PIPE_CAP_USER_INDEX_BUFFERS:
 169    case PIPE_CAP_USER_VERTEX_BUFFERS:
 170       return 1;
 171    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 172       return 256;
 173    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 174    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 175    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 176    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 177       return 0;
 178    default:
 179       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 180       return 0;
 181    }
 182 }
 183
 184 static int
 185 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 186                              enum pipe_shader_cap param)
 187 {
 188    switch (shader) {
 189    case PIPE_SHADER_VERTEX:
 190    case PIPE_SHADER_GEOMETRY:
 191    case PIPE_SHADER_FRAGMENT:
 192       break;
 193    default:
 194       return 0;
 195    }
 196
 197    switch (param) {
 198    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 199    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 200    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 201    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 202       return 16384;
 203    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 204       return 4;
 205    case PIPE_SHADER_CAP_MAX_INPUTS:
 206       if (shader == PIPE_SHADER_VERTEX)
 207          return 32;
 208       return 0x300 / 16;
 209    case PIPE_SHADER_CAP_MAX_CONSTS:
 210       return 65536 / 16;
 211    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 212       return NV50_MAX_PIPE_CONSTBUFS;
 213    case PIPE_SHADER_CAP_MAX_ADDRS:
 214       return 1;
 215    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 216    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 217       return shader != PIPE_SHADER_FRAGMENT;
 218    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 219    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 220       return 1;
 221    case PIPE_SHADER_CAP_MAX_PREDS:
 222       return 0;
 223    case PIPE_SHADER_CAP_MAX_TEMPS:
 224       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 225    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 226       return 1;
 227    case PIPE_SHADER_CAP_SUBROUTINES:
 228       return 0; /* please inline, or provide function declarations */
 229    case PIPE_SHADER_CAP_INTEGERS:
 230       return 1;
 231    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 232       return 32;
 233    default:
 234       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 235       return 0;
 236    }
 237 }
 238
 239 static float
 240 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 241 {
 242    switch (param) {
 243    case PIPE_CAPF_MAX_LINE_WIDTH:
 244    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 245       return 10.0f;
 246    case PIPE_CAPF_MAX_POINT_WIDTH:
 247    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 248       return 64.0f;
 249    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 250       return 16.0f;
 251    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 252       return 4.0f;
 253    default:
 254       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 255       return 0.0f;
 256    }
 257 }
 258
 259 static void
 260 nv50_screen_destroy(struct pipe_screen *pscreen)
 261 {
 262    struct nv50_screen *screen = nv50_screen(pscreen);
 263
 264    if (screen->base.fence.current) {
 265       nouveau_fence_wait(screen->base.fence.current);
 266       nouveau_fence_ref (NULL, &screen->base.fence.current);
 267    }
 268    if (screen->base.pushbuf)
 269       screen->base.pushbuf->user_priv = NULL;
 270
 271    FREE(screen->blitctx);
 272
 273    nouveau_bo_ref(NULL, &screen->code);
 274    nouveau_bo_ref(NULL, &screen->tls_bo);
 275    nouveau_bo_ref(NULL, &screen->stack_bo);
 276    nouveau_bo_ref(NULL, &screen->txc);
 277    nouveau_bo_ref(NULL, &screen->uniforms);
 278    nouveau_bo_ref(NULL, &screen->fence.bo);
 279
 280    nouveau_heap_destroy(&screen->vp_code_heap);
 281    nouveau_heap_destroy(&screen->gp_code_heap);
 282    nouveau_heap_destroy(&screen->fp_code_heap);
 283
 284    FREE(screen->tic.entries);
 285
 286    nouveau_object_del(&screen->tesla);
 287    nouveau_object_del(&screen->eng2d);
 288    nouveau_object_del(&screen->m2mf);
 289    nouveau_object_del(&screen->sync);
 290
 291    nouveau_screen_fini(&screen->base);
 292
 293    FREE(screen);
 294 }
 295
 296 static void
 297 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 298 {
 299    struct nv50_screen *screen = nv50_screen(pscreen);
 300    struct nouveau_pushbuf *push = screen->base.pushbuf;
 301
 302    /* we need to do it after possible flush in MARK_RING */
 303    *sequence = ++screen->base.fence.sequence;
 304
 305    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 306    PUSH_DATAh(push, screen->fence.bo->offset);
 307    PUSH_DATA (push, screen->fence.bo->offset);
 308    PUSH_DATA (push, *sequence);
 309    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 310                     NV50_3D_QUERY_GET_UNK4 |
 311                     NV50_3D_QUERY_GET_UNIT_CROP |
 312                     NV50_3D_QUERY_GET_TYPE_QUERY |
 313                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 314                     NV50_3D_QUERY_GET_SHORT);
 315 }
 316
 317 static u32
 318 nv50_screen_fence_update(struct pipe_screen *pscreen)
 319 {
 320    return nv50_screen(pscreen)->fence.map[0];
 321 }
 322
 323 static void
 324 nv50_screen_init_hwctx(struct nv50_screen *screen)
 325 {
 326    struct nouveau_pushbuf *push = screen->base.pushbuf;
 327    struct nv04_fifo *fifo;
 328    unsigned i;
 329
 330    fifo = (struct nv04_fifo *)screen->base.channel->data;
 331
 332    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 333    PUSH_DATA (push, screen->m2mf->handle);
 334    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 335    PUSH_DATA (push, screen->sync->handle);
 336    PUSH_DATA (push, fifo->vram);
 337    PUSH_DATA (push, fifo->vram);
 338
 339    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 340    PUSH_DATA (push, screen->eng2d->handle);
 341    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 342    PUSH_DATA (push, screen->sync->handle);
 343    PUSH_DATA (push, fifo->vram);
 344    PUSH_DATA (push, fifo->vram);
 345    PUSH_DATA (push, fifo->vram);
 346    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 347    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 348    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 349    PUSH_DATA (push, 0);
 350    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 351    PUSH_DATA (push, 0);
 352    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 353    PUSH_DATA (push, 1);
 354
 355    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 356    PUSH_DATA (push, screen->tesla->handle);
 357
 358    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 359    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 360
 361    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 362    PUSH_DATA (push, screen->sync->handle);
 363    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 364    for (i = 0; i < 11; ++i)
 365       PUSH_DATA(push, fifo->vram);
 366    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 367    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 368       PUSH_DATA(push, fifo->vram);
 369
 370    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 371    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 372    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 373    PUSH_DATA (push, 0xf);
 374
 375    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 376       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 377       PUSH_DATA (push, 0x18);
 378    }
 379
 380    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 381    PUSH_DATA (push, 1);
 382
 383    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 384    PUSH_DATA (push, 0);
 385    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 386    PUSH_DATA (push, 0);
 387    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 388    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 389    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 390    PUSH_DATA (push, 0);
 391    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 392    PUSH_DATA (push, 0);
 393    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 394    PUSH_DATA (push, 1);
 395
 396    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 397       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 398       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 399    }
 400
 401    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 402    PUSH_DATA (push, 0);
 403    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 404    PUSH_DATA (push, 0);
 405    PUSH_DATA (push, 0);
 406    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 407    PUSH_DATA (push, 0x3f);
 408
 409    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 410    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 411    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 412
 413    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 414    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 415    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 416
 417    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 418    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 419    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 420
 421    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 422    PUSH_DATAh(push, screen->tls_bo->offset);
 423    PUSH_DATA (push, screen->tls_bo->offset);
 424    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 425
 426    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 427    PUSH_DATAh(push, screen->stack_bo->offset);
 428    PUSH_DATA (push, screen->stack_bo->offset);
 429    PUSH_DATA (push, 4);
 430
 431    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 432    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 433    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 434    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 435
 436    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 437    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 438    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 439    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 440
 441    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 442    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 443    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 444    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 445
 446    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 447    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 448    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 449    PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
 450
 451    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 452    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 453    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 454    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 455
 456    /* max TIC (bits 4:8) & TSC bindings, per program type */
 457    for (i = 0; i < 3; ++i) {
 458       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 459       PUSH_DATA (push, 0x54);
 460    }
 461
 462    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 463    PUSH_DATAh(push, screen->txc->offset);
 464    PUSH_DATA (push, screen->txc->offset);
 465    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 466
 467    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 468    PUSH_DATAh(push, screen->txc->offset + 65536);
 469    PUSH_DATA (push, screen->txc->offset + 65536);
 470    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 471
 472    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 473    PUSH_DATA (push, 0);
 474
 475    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 476    PUSH_DATA (push, 0);
 477    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 478    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 479    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 480    for (i = 0; i < 8 * 2; ++i)
 481       PUSH_DATA(push, 0);
 482    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 483    PUSH_DATA (push, 0);
 484
 485    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 486    PUSH_DATA (push, 1);
 487    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 488    PUSH_DATAf(push, 0.0f);
 489    PUSH_DATAf(push, 1.0f);
 490
 491    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 492 #ifdef NV50_SCISSORS_CLIPPING
 493    PUSH_DATA (push, 0x0000);
 494 #else
 495    PUSH_DATA (push, 0x1080);
 496 #endif
 497
 498    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 499    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 500
 501    /* We use scissors instead of exact view volume clipping,
 502     * so they're always enabled.
 503     */
 504    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 505    PUSH_DATA (push, 1);
 506    PUSH_DATA (push, 8192 << 16);
 507    PUSH_DATA (push, 8192 << 16);
 508
 509    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 510    PUSH_DATA (push, 1);
 511    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 512    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 513    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 514    PUSH_DATA (push, 0x11111111);
 515    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 516    PUSH_DATA (push, 1);
 517
 518    PUSH_KICK (push);
 519 }
 520
 521 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 522       uint64_t *tls_size)
 523 {
 524    struct nouveau_device *dev = screen->base.device;
 525    int ret;
 526
 527    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 528          ONE_TEMP_SIZE;
 529    if (nouveau_mesa_debug)
 530       debug_printf("allocating space for %u temps\n",
 531             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 532    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 533          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 534
 535    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 536                         *tls_size, NULL, &screen->tls_bo);
 537    if (ret) {
 538       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 539       return ret;
 540    }
 541
 542    return 0;
 543 }
 544
 545 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 546 {
 547    struct nouveau_pushbuf *push = screen->base.pushbuf;
 548    int ret;
 549    uint64_t tls_size;
 550
 551    if (tls_space < screen->cur_tls_space)
 552       return 0;
 553    if (tls_space > screen->max_tls_space) {
 554       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 555        * LOCAL_WARPS_NO_CLAMP) */
 556       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 557             (unsigned)(tls_space / ONE_TEMP_SIZE),
 558             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 559       return -ENOMEM;
 560    }
 561
 562    nouveau_bo_ref(NULL, &screen->tls_bo);
 563    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 564    if (ret)
 565       return ret;
 566
 567    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 568    PUSH_DATAh(push, screen->tls_bo->offset);
 569    PUSH_DATA (push, screen->tls_bo->offset);
 570    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 571
 572    return 1;
 573 }
 574
 575 struct pipe_screen *
 576 nv50_screen_create(struct nouveau_device *dev)
 577 {
 578    struct nv50_screen *screen;
 579    struct pipe_screen *pscreen;
 580    struct nouveau_object *chan;
 581    uint64_t value;
 582    uint32_t tesla_class;
 583    unsigned stack_size;
 584    int ret;
 585
 586    screen = CALLOC_STRUCT(nv50_screen);
 587    if (!screen)
 588       return NULL;
 589    pscreen = &screen->base.base;
 590
 591    ret = nouveau_screen_init(&screen->base, dev);
 592    if (ret) {
 593       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 594       goto fail;
 595    }
 596
 597    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 598     *  admit them to VRAM.
 599     */
 600    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 601       PIPE_BIND_VERTEX_BUFFER;
 602    screen->base.sysmem_bindings |=
 603       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 604
 605    screen->base.pushbuf->user_priv = screen;
 606    screen->base.pushbuf->rsvd_kick = 5;
 607
 608    chan = screen->base.channel;
 609
 610    pscreen->destroy = nv50_screen_destroy;
 611    pscreen->context_create = nv50_create;
 612    pscreen->is_format_supported = nv50_screen_is_format_supported;
 613    pscreen->get_param = nv50_screen_get_param;
 614    pscreen->get_shader_param = nv50_screen_get_shader_param;
 615    pscreen->get_paramf = nv50_screen_get_paramf;
 616
 617    nv50_screen_init_resource_functions(pscreen);
 618
 619    nouveau_screen_init_vdec(&screen->base);
 620
 621    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 622                         NULL, &screen->fence.bo);
 623    if (ret) {
 624       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 625       goto fail;
 626    }
 627
 628    nouveau_bo_map(screen->fence.bo, 0, NULL);
 629    screen->fence.map = screen->fence.bo->map;
 630    screen->base.fence.emit = nv50_screen_fence_emit;
 631    screen->base.fence.update = nv50_screen_fence_update;
 632
 633    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 634                             &(struct nv04_notify){ .length = 32 },
 635                             sizeof(struct nv04_notify), &screen->sync);
 636    if (ret) {
 637       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 638       goto fail;
 639    }
 640
 641    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 642                             NULL, 0, &screen->m2mf);
 643    if (ret) {
 644       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 645       goto fail;
 646    }
 647
 648    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 649                             NULL, 0, &screen->eng2d);
 650    if (ret) {
 651       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 652       goto fail;
 653    }
 654
 655    switch (dev->chipset & 0xf0) {
 656    case 0x50:
 657       tesla_class = NV50_3D_CLASS;
 658       break;
 659    case 0x80:
 660    case 0x90:
 661       tesla_class = NV84_3D_CLASS;
 662       break;
 663    case 0xa0:
 664       switch (dev->chipset) {
 665       case 0xa0:
 666       case 0xaa:
 667       case 0xac:
 668          tesla_class = NVA0_3D_CLASS;
 669          break;
 670       case 0xaf:
 671          tesla_class = NVAF_3D_CLASS;
 672          break;
 673       default:
 674          tesla_class = NVA3_3D_CLASS;
 675          break;
 676       }
 677       break;
 678    default:
 679       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 680       goto fail;
 681    }
 682    screen->base.class_3d = tesla_class;
 683
 684    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 685                             NULL, 0, &screen->tesla);
 686    if (ret) {
 687       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 688       goto fail;
 689    }
 690
 691    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 692                         3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 693    if (ret) {
 694       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 695       goto fail;
 696    }
 697
 698    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 699    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 700    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 701
 702    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 703
 704    screen->TPs = util_bitcount(value & 0xffff);
 705    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 706
 707    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 708          STACK_WARPS_ALLOC * 64 * 8;
 709
 710    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 711                         &screen->stack_bo);
 712    if (ret) {
 713       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 714       goto fail;
 715    }
 716
 717    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 718          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 719          ONE_TEMP_SIZE;
 720    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 721    screen->max_tls_space /= 2; /* half of vram */
 722
 723    /* hw can address max 64 KiB */
 724    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 725
 726    uint64_t tls_size;
 727    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 728    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 729    if (ret)
 730       goto fail;
 731
 732    if (nouveau_mesa_debug)
 733       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 734             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 735
 736    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 737                         &screen->uniforms);
 738    if (ret) {
 739       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 740       goto fail;
 741    }
 742
 743    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 744                         &screen->txc);
 745    if (ret) {
 746       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 747       goto fail;
 748    }
 749
 750    screen->tic.entries = CALLOC(4096, sizeof(void *));
 751    screen->tsc.entries = screen->tic.entries + 2048;
 752
 753    if (!nv50_blitctx_create(screen))
 754       goto fail;
 755
 756    nv50_screen_init_hwctx(screen);
 757
 758    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 759
 760    return pscreen;
 761
 762 fail:
 763    nv50_screen_destroy(pscreen);
 764    return NULL;
 765 }
 766
 767 int
 768 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 769 {
 770    int i = screen->tic.next;
 771
 772    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 773       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 774
 775    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 776
 777    if (screen->tic.entries[i])
 778       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 779
 780    screen->tic.entries[i] = entry;
 781    return i;
 782 }
 783
 784 int
 785 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 786 {
 787    int i = screen->tsc.next;
 788
 789    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 790       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 791
 792    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 793
 794    if (screen->tsc.entries[i])
 795       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 796
 797    screen->tsc.entries[i] = entry;
 798    return i;
 799 }