gallium: it's a reference value, not a reference number
[mesa.git] / src / gallium / drivers / nv50 / nv50_screen.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_screen.h"
24
25 #include "nv50_context.h"
26 #include "nv50_screen.h"
27
28 #include "nouveau/nouveau_stateobj.h"
29
30 #define NV5X_GRCLASS5097_CHIPSETS 0x00000001
31 #define NV8X_GRCLASS8297_CHIPSETS 0x00000050
32 #define NV9X_GRCLASS8297_CHIPSETS 0x00000014
33
34 static boolean
35 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
36 enum pipe_format format,
37 enum pipe_texture_target target,
38 unsigned tex_usage, unsigned geom_flags)
39 {
40 if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
41 switch (format) {
42 case PIPE_FORMAT_A8R8G8B8_UNORM:
43 case PIPE_FORMAT_R5G6B5_UNORM:
44 case PIPE_FORMAT_Z24S8_UNORM:
45 case PIPE_FORMAT_Z16_UNORM:
46 return TRUE;
47 default:
48 break;
49 }
50 } else {
51 switch (format) {
52 case PIPE_FORMAT_A8R8G8B8_UNORM:
53 case PIPE_FORMAT_A1R5G5B5_UNORM:
54 case PIPE_FORMAT_A4R4G4B4_UNORM:
55 case PIPE_FORMAT_R5G6B5_UNORM:
56 case PIPE_FORMAT_L8_UNORM:
57 case PIPE_FORMAT_A8_UNORM:
58 case PIPE_FORMAT_I8_UNORM:
59 case PIPE_FORMAT_A8L8_UNORM:
60 case PIPE_FORMAT_DXT1_RGB:
61 case PIPE_FORMAT_DXT1_RGBA:
62 case PIPE_FORMAT_DXT3_RGBA:
63 case PIPE_FORMAT_DXT5_RGBA:
64 return TRUE;
65 default:
66 break;
67 }
68 }
69
70 return FALSE;
71 }
72
73 static const char *
74 nv50_screen_get_name(struct pipe_screen *pscreen)
75 {
76 struct nv50_screen *screen = nv50_screen(pscreen);
77 struct nouveau_device *dev = screen->nvws->channel->device;
78 static char buffer[128];
79
80 snprintf(buffer, sizeof(buffer), "NV%02X", dev->chipset);
81 return buffer;
82 }
83
84 static const char *
85 nv50_screen_get_vendor(struct pipe_screen *pscreen)
86 {
87 return "nouveau";
88 }
89
90 static int
91 nv50_screen_get_param(struct pipe_screen *pscreen, int param)
92 {
93 switch (param) {
94 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
95 return 32;
96 case PIPE_CAP_NPOT_TEXTURES:
97 return 1;
98 case PIPE_CAP_TWO_SIDED_STENCIL:
99 return 1;
100 case PIPE_CAP_GLSL:
101 return 0;
102 case PIPE_CAP_S3TC:
103 return 1;
104 case PIPE_CAP_ANISOTROPIC_FILTER:
105 return 1;
106 case PIPE_CAP_POINT_SPRITE:
107 return 0;
108 case PIPE_CAP_MAX_RENDER_TARGETS:
109 return 8;
110 case PIPE_CAP_OCCLUSION_QUERY:
111 return 1;
112 case PIPE_CAP_TEXTURE_SHADOW_MAP:
113 return 1;
114 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
115 return 13;
116 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
117 return 10;
118 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
119 return 13;
120 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
121 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
122 return 1;
123 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
124 return 0;
125 case NOUVEAU_CAP_HW_VTXBUF:
126 return 1;
127 case NOUVEAU_CAP_HW_IDXBUF:
128 return 0;
129 default:
130 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
131 return 0;
132 }
133 }
134
135 static float
136 nv50_screen_get_paramf(struct pipe_screen *pscreen, int param)
137 {
138 switch (param) {
139 case PIPE_CAP_MAX_LINE_WIDTH:
140 case PIPE_CAP_MAX_LINE_WIDTH_AA:
141 return 10.0;
142 case PIPE_CAP_MAX_POINT_WIDTH:
143 case PIPE_CAP_MAX_POINT_WIDTH_AA:
144 return 64.0;
145 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
146 return 16.0;
147 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
148 return 4.0;
149 default:
150 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
151 return 0.0;
152 }
153 }
154
155 static void
156 nv50_screen_destroy(struct pipe_screen *pscreen)
157 {
158 FREE(pscreen);
159 }
160
161 struct pipe_screen *
162 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws)
163 {
164 struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen);
165 struct nouveau_stateobj *so;
166 unsigned tesla_class = 0, ret;
167 unsigned chipset = nvws->channel->device->chipset;
168 int i;
169
170 if (!screen)
171 return NULL;
172 screen->nvws = nvws;
173
174 /* 3D object */
175 if ((chipset & 0xf0) != 0x50 && (chipset & 0xf0) != 0x80) {
176 NOUVEAU_ERR("Not a G8x chipset\n");
177 nv50_screen_destroy(&screen->pipe);
178 return NULL;
179 }
180
181 switch (chipset & 0xf0) {
182 case 0x50:
183 if (NV5X_GRCLASS5097_CHIPSETS & (1 << (chipset & 0x0f)))
184 tesla_class = 0x5097;
185 break;
186 case 0x80:
187 if (NV8X_GRCLASS8297_CHIPSETS & (1 << (chipset & 0x0f)))
188 tesla_class = 0x8297;
189 break;
190 case 0x90:
191 if (NV9X_GRCLASS8297_CHIPSETS & (1 << (chipset & 0x0f)))
192 tesla_class = 0x8297;
193 break;
194 default:
195 break;
196 }
197
198 if (tesla_class == 0) {
199 NOUVEAU_ERR("Unknown G8x chipset: NV%02x\n", chipset);
200 nv50_screen_destroy(&screen->pipe);
201 return NULL;
202 }
203
204 ret = nvws->grobj_alloc(nvws, tesla_class, &screen->tesla);
205 if (ret) {
206 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
207 nv50_screen_destroy(&screen->pipe);
208 return NULL;
209 }
210
211 /* Sync notifier */
212 ret = nvws->notifier_alloc(nvws, 1, &screen->sync);
213 if (ret) {
214 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
215 nv50_screen_destroy(&screen->pipe);
216 return NULL;
217 }
218
219 /* Static tesla init */
220 so = so_new(256, 20);
221
222 so_method(so, screen->tesla, 0x1558, 1);
223 so_data (so, 1);
224 so_method(so, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
225 so_data (so, screen->sync->handle);
226 so_method(so, screen->tesla, NV50TCL_DMA_UNK0(0),
227 NV50TCL_DMA_UNK0__SIZE);
228 for (i = 0; i < NV50TCL_DMA_UNK0__SIZE; i++)
229 so_data(so, nvws->channel->vram->handle);
230 so_method(so, screen->tesla, NV50TCL_DMA_UNK1(0),
231 NV50TCL_DMA_UNK1__SIZE);
232 for (i = 0; i < NV50TCL_DMA_UNK1__SIZE; i++)
233 so_data(so, nvws->channel->vram->handle);
234 so_method(so, screen->tesla, 0x121c, 1);
235 so_data (so, 1);
236
237 so_method(so, screen->tesla, 0x13bc, 1);
238 so_data (so, 0x54);
239 so_method(so, screen->tesla, 0x13ac, 1);
240 so_data (so, 1);
241 so_method(so, screen->tesla, 0x16b8, 1);
242 so_data (so, 8);
243
244 /* Shared constant buffer */
245 screen->constbuf = ws->buffer_create(ws, 0, 0, 128 * 4 * 4);
246 if (nvws->res_init(&screen->vp_data_heap, 0, 128)) {
247 NOUVEAU_ERR("Error initialising constant buffer\n");
248 nv50_screen_destroy(&screen->pipe);
249 return NULL;
250 }
251
252 so_method(so, screen->tesla, 0x1280, 3);
253 so_reloc (so, screen->constbuf, 0, NOUVEAU_BO_VRAM |
254 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
255 so_reloc (so, screen->constbuf, 0, NOUVEAU_BO_VRAM |
256 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
257 so_data (so, (NV50_CB_PMISC << 16) | 0x00001000);
258
259 /* Texture sampler/image unit setup - we abuse the constant buffer
260 * upload mechanism for the moment to upload data to the tex config
261 * blocks. At some point we *may* want to go the NVIDIA way of doing
262 * things?
263 */
264 screen->tic = ws->buffer_create(ws, 0, 0, 32 * 8 * 4);
265 so_method(so, screen->tesla, 0x1280, 3);
266 so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
267 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
268 so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
269 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
270 so_data (so, (NV50_CB_TIC << 16) | 0x0800);
271 so_method(so, screen->tesla, 0x1574, 3);
272 so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
273 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
274 so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
275 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
276 so_data (so, 0x00000800);
277
278 screen->tsc = ws->buffer_create(ws, 0, 0, 32 * 8 * 4);
279 so_method(so, screen->tesla, 0x1280, 3);
280 so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
281 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
282 so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
283 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
284 so_data (so, (NV50_CB_TSC << 16) | 0x0800);
285 so_method(so, screen->tesla, 0x155c, 3);
286 so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
287 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
288 so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
289 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
290 so_data (so, 0x00000800);
291
292
293 /* Vertex array limits - max them out */
294 for (i = 0; i < 16; i++) {
295 so_method(so, screen->tesla, 0x1080 + (i * 8), 2);
296 so_data (so, 0x000000ff);
297 so_data (so, 0xffffffff);
298 }
299
300 so_method(so, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR, 2);
301 so_data (so, fui(0.0));
302 so_data (so, fui(1.0));
303
304 so_method(so, screen->tesla, 0x1234, 1);
305 so_data (so, 1);
306 so_method(so, screen->tesla, 0x1458, 1);
307 so_data (so, 1);
308
309 so_emit(nvws, so);
310 so_ref(so, &screen->static_init);
311 nvws->push_flush(nvws, 0, NULL);
312
313 screen->pipe.winsys = ws;
314
315 screen->pipe.destroy = nv50_screen_destroy;
316
317 screen->pipe.get_name = nv50_screen_get_name;
318 screen->pipe.get_vendor = nv50_screen_get_vendor;
319 screen->pipe.get_param = nv50_screen_get_param;
320 screen->pipe.get_paramf = nv50_screen_get_paramf;
321
322 screen->pipe.is_format_supported = nv50_screen_is_format_supported;
323
324 nv50_screen_init_miptree_functions(&screen->pipe);
325 nv50_surface_init_screen_functions(&screen->pipe);
326
327 return &screen->pipe;
328 }
329