src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31 #include <errno.h>
  32
  33 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  34 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  35 #endif
  36
  37 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
  38 #define LOCAL_WARPS_ALLOC 32
  39 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
  40 #define STACK_WARPS_ALLOC 32
  41
  42 #define THREADS_IN_WARP 32
  43
  44 #define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float))
  45
  46 static boolean
  47 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  48                                 enum pipe_format format,
  49                                 enum pipe_texture_target target,
  50                                 unsigned sample_count,
  51                                 unsigned bindings)
  52 {
  53    if (sample_count > 8)
  54       return FALSE;
  55    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  56       return FALSE;
  57    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  58       return FALSE;
  59
  60    if (!util_format_is_supported(format, bindings))
  61       return FALSE;
  62
  63    switch (format) {
  64    case PIPE_FORMAT_Z16_UNORM:
  65       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  66          return FALSE;
  67       break;
  68    case PIPE_FORMAT_R8G8B8A8_UNORM:
  69    case PIPE_FORMAT_R8G8B8X8_UNORM:
  70       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  71       if (bindings & PIPE_BIND_RENDER_TARGET)
  72          return FALSE;
  73    default:
  74       break;
  75    }
  76
  77    /* transfers & shared are always supported */
  78    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  79                  PIPE_BIND_TRANSFER_WRITE |
  80                  PIPE_BIND_SHARED);
  81
  82    return (nv50_format_table[format].usage & bindings) == bindings;
  83 }
  84
  85 static int
  86 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  87 {
  88    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  89
  90    switch (param) {
  91    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  92       return 64;
  93    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  94       return 14;
  95    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  96       return 12;
  97    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  98       return 14;
  99    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 100       return 512;
 101    case PIPE_CAP_MIN_TEXEL_OFFSET:
 102       return -8;
 103    case PIPE_CAP_MAX_TEXEL_OFFSET:
 104       return 7;
 105    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 106    case PIPE_CAP_TEXTURE_SWIZZLE:
 107    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 108    case PIPE_CAP_NPOT_TEXTURES:
 109    case PIPE_CAP_ANISOTROPIC_FILTER:
 110    case PIPE_CAP_SCALED_RESOLVE:
 111    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 112       return 1;
 113    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 114       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 115    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 116       return 0;
 117    case PIPE_CAP_CUBE_MAP_ARRAY:
 118       return 0;
 119       /*
 120       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 121       */
 122    case PIPE_CAP_TWO_SIDED_STENCIL:
 123    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 124    case PIPE_CAP_POINT_SPRITE:
 125       return 1;
 126    case PIPE_CAP_SM3:
 127       return 1;
 128    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 129       return 140;
 130    case PIPE_CAP_MAX_RENDER_TARGETS:
 131       return 8;
 132    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 133       return 1;
 134    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 135    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 136    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 137       return 1;
 138    case PIPE_CAP_QUERY_TIMESTAMP:
 139    case PIPE_CAP_QUERY_TIME_ELAPSED:
 140    case PIPE_CAP_OCCLUSION_QUERY:
 141       return 1;
 142    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 143       return 4;
 144    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 145    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 146       return 64;
 147    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 148       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 149    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 150    case PIPE_CAP_INDEP_BLEND_ENABLE:
 151       return 1;
 152    case PIPE_CAP_INDEP_BLEND_FUNC:
 153       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 154    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 155    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 156       return 1;
 157    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 158    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 159       return 0;
 160    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 161       return 0;
 162    case PIPE_CAP_PRIMITIVE_RESTART:
 163    case PIPE_CAP_TGSI_INSTANCEID:
 164    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 165    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 166    case PIPE_CAP_CONDITIONAL_RENDER:
 167    case PIPE_CAP_TEXTURE_BARRIER:
 168    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 169    case PIPE_CAP_START_INSTANCE:
 170       return 1;
 171    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 172    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 173       return 0; /* state trackers will know better */
 174    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 175    case PIPE_CAP_USER_INDEX_BUFFERS:
 176    case PIPE_CAP_USER_VERTEX_BUFFERS:
 177       return 1;
 178    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 179       return 256;
 180    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 181       return 1; /* 256 for binding as RT, but that's not possible in GL */
 182    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 183       return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
 184    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 185    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 186    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 187    case PIPE_CAP_TGSI_TEXCOORD:
 188    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 189       return 0;
 190    default:
 191       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 192       return 0;
 193    }
 194 }
 195
 196 static int
 197 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 198                              enum pipe_shader_cap param)
 199 {
 200    switch (shader) {
 201    case PIPE_SHADER_VERTEX:
 202    case PIPE_SHADER_GEOMETRY:
 203    case PIPE_SHADER_FRAGMENT:
 204       break;
 205    default:
 206       return 0;
 207    }
 208
 209    switch (param) {
 210    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 211    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 212    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 213    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 214       return 16384;
 215    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 216       return 4;
 217    case PIPE_SHADER_CAP_MAX_INPUTS:
 218       if (shader == PIPE_SHADER_VERTEX)
 219          return 32;
 220       return 0x300 / 16;
 221    case PIPE_SHADER_CAP_MAX_CONSTS:
 222       return 65536 / 16;
 223    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 224       return NV50_MAX_PIPE_CONSTBUFS;
 225    case PIPE_SHADER_CAP_MAX_ADDRS:
 226       return 1;
 227    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 228    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 229       return shader != PIPE_SHADER_FRAGMENT;
 230    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 231    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 232       return 1;
 233    case PIPE_SHADER_CAP_MAX_PREDS:
 234       return 0;
 235    case PIPE_SHADER_CAP_MAX_TEMPS:
 236       return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
 237    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 238       return 1;
 239    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 240       return 0;
 241    case PIPE_SHADER_CAP_SUBROUTINES:
 242       return 0; /* please inline, or provide function declarations */
 243    case PIPE_SHADER_CAP_INTEGERS:
 244       return 1;
 245    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 246       return 32;
 247    default:
 248       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 249       return 0;
 250    }
 251 }
 252
 253 static float
 254 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 255 {
 256    switch (param) {
 257    case PIPE_CAPF_MAX_LINE_WIDTH:
 258    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 259       return 10.0f;
 260    case PIPE_CAPF_MAX_POINT_WIDTH:
 261    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 262       return 64.0f;
 263    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 264       return 16.0f;
 265    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 266       return 4.0f;
 267    default:
 268       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 269       return 0.0f;
 270    }
 271 }
 272
 273 static void
 274 nv50_screen_destroy(struct pipe_screen *pscreen)
 275 {
 276    struct nv50_screen *screen = nv50_screen(pscreen);
 277
 278    if (screen->base.fence.current) {
 279       nouveau_fence_wait(screen->base.fence.current);
 280       nouveau_fence_ref (NULL, &screen->base.fence.current);
 281    }
 282    if (screen->base.pushbuf)
 283       screen->base.pushbuf->user_priv = NULL;
 284
 285    if (screen->blitter)
 286       nv50_blitter_destroy(screen);
 287
 288    nouveau_bo_ref(NULL, &screen->code);
 289    nouveau_bo_ref(NULL, &screen->tls_bo);
 290    nouveau_bo_ref(NULL, &screen->stack_bo);
 291    nouveau_bo_ref(NULL, &screen->txc);
 292    nouveau_bo_ref(NULL, &screen->uniforms);
 293    nouveau_bo_ref(NULL, &screen->fence.bo);
 294
 295    nouveau_heap_destroy(&screen->vp_code_heap);
 296    nouveau_heap_destroy(&screen->gp_code_heap);
 297    nouveau_heap_destroy(&screen->fp_code_heap);
 298
 299    FREE(screen->tic.entries);
 300
 301    nouveau_object_del(&screen->tesla);
 302    nouveau_object_del(&screen->eng2d);
 303    nouveau_object_del(&screen->m2mf);
 304    nouveau_object_del(&screen->sync);
 305
 306    nouveau_screen_fini(&screen->base);
 307
 308    FREE(screen);
 309 }
 310
 311 static void
 312 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 313 {
 314    struct nv50_screen *screen = nv50_screen(pscreen);
 315    struct nouveau_pushbuf *push = screen->base.pushbuf;
 316
 317    /* we need to do it after possible flush in MARK_RING */
 318    *sequence = ++screen->base.fence.sequence;
 319
 320    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 321    PUSH_DATAh(push, screen->fence.bo->offset);
 322    PUSH_DATA (push, screen->fence.bo->offset);
 323    PUSH_DATA (push, *sequence);
 324    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 325                     NV50_3D_QUERY_GET_UNK4 |
 326                     NV50_3D_QUERY_GET_UNIT_CROP |
 327                     NV50_3D_QUERY_GET_TYPE_QUERY |
 328                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 329                     NV50_3D_QUERY_GET_SHORT);
 330 }
 331
 332 static u32
 333 nv50_screen_fence_update(struct pipe_screen *pscreen)
 334 {
 335    return nv50_screen(pscreen)->fence.map[0];
 336 }
 337
 338 static void
 339 nv50_screen_init_hwctx(struct nv50_screen *screen)
 340 {
 341    struct nouveau_pushbuf *push = screen->base.pushbuf;
 342    struct nv04_fifo *fifo;
 343    unsigned i;
 344
 345    fifo = (struct nv04_fifo *)screen->base.channel->data;
 346
 347    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 348    PUSH_DATA (push, screen->m2mf->handle);
 349    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 350    PUSH_DATA (push, screen->sync->handle);
 351    PUSH_DATA (push, fifo->vram);
 352    PUSH_DATA (push, fifo->vram);
 353
 354    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 355    PUSH_DATA (push, screen->eng2d->handle);
 356    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 357    PUSH_DATA (push, screen->sync->handle);
 358    PUSH_DATA (push, fifo->vram);
 359    PUSH_DATA (push, fifo->vram);
 360    PUSH_DATA (push, fifo->vram);
 361    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 362    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 363    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 364    PUSH_DATA (push, 0);
 365    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 366    PUSH_DATA (push, 0);
 367    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 368    PUSH_DATA (push, 1);
 369
 370    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 371    PUSH_DATA (push, screen->tesla->handle);
 372
 373    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 374    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 375
 376    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 377    PUSH_DATA (push, screen->sync->handle);
 378    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 379    for (i = 0; i < 11; ++i)
 380       PUSH_DATA(push, fifo->vram);
 381    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 382    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 383       PUSH_DATA(push, fifo->vram);
 384
 385    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 386    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 387    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 388    PUSH_DATA (push, 0xf);
 389
 390    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 391       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 392       PUSH_DATA (push, 0x18);
 393    }
 394
 395    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 396    PUSH_DATA (push, 1);
 397
 398    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 399    PUSH_DATA (push, 0);
 400    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 401    PUSH_DATA (push, 0);
 402    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 403    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 404    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 405    PUSH_DATA (push, 0);
 406    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 407    PUSH_DATA (push, 0);
 408    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 409    PUSH_DATA (push, 1);
 410
 411    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 412       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 413       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 414    }
 415
 416    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 417    PUSH_DATA (push, 0);
 418    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 419    PUSH_DATA (push, 0);
 420    PUSH_DATA (push, 0);
 421    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 422    PUSH_DATA (push, 0x3f);
 423
 424    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 425    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 426    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 427
 428    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 429    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 430    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 431
 432    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 433    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 434    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 435
 436    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 437    PUSH_DATAh(push, screen->tls_bo->offset);
 438    PUSH_DATA (push, screen->tls_bo->offset);
 439    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 440
 441    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 442    PUSH_DATAh(push, screen->stack_bo->offset);
 443    PUSH_DATA (push, screen->stack_bo->offset);
 444    PUSH_DATA (push, 4);
 445
 446    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 447    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 448    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 449    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 450
 451    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 452    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 453    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 454    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 455
 456    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 457    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 458    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 459    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 460
 461    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 462    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 463    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 464    PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
 465
 466    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
 467    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 468    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 469    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 470
 471    /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
 472    BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
 473    PUSH_DATA (push, ((1 << 9) << 6) | NV50_CB_AUX);
 474    BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
 475    PUSH_DATAf(push, 0.0f);
 476    PUSH_DATAf(push, 0.0f);
 477    PUSH_DATAf(push, 0.0f);
 478    PUSH_DATAf(push, 0.0f);
 479    BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
 480    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 481    PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + (1 << 9));
 482
 483    /* max TIC (bits 4:8) & TSC bindings, per program type */
 484    for (i = 0; i < 3; ++i) {
 485       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 486       PUSH_DATA (push, 0x54);
 487    }
 488
 489    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 490    PUSH_DATAh(push, screen->txc->offset);
 491    PUSH_DATA (push, screen->txc->offset);
 492    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 493
 494    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 495    PUSH_DATAh(push, screen->txc->offset + 65536);
 496    PUSH_DATA (push, screen->txc->offset + 65536);
 497    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 498
 499    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 500    PUSH_DATA (push, 0);
 501
 502    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 503    PUSH_DATA (push, 0);
 504    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 505    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 506    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 507    for (i = 0; i < 8 * 2; ++i)
 508       PUSH_DATA(push, 0);
 509    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 510    PUSH_DATA (push, 0);
 511
 512    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 513    PUSH_DATA (push, 1);
 514    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 515    PUSH_DATAf(push, 0.0f);
 516    PUSH_DATAf(push, 1.0f);
 517
 518    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 519 #ifdef NV50_SCISSORS_CLIPPING
 520    PUSH_DATA (push, 0x0000);
 521 #else
 522    PUSH_DATA (push, 0x1080);
 523 #endif
 524
 525    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 526    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 527
 528    /* We use scissors instead of exact view volume clipping,
 529     * so they're always enabled.
 530     */
 531    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 532    PUSH_DATA (push, 1);
 533    PUSH_DATA (push, 8192 << 16);
 534    PUSH_DATA (push, 8192 << 16);
 535
 536    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 537    PUSH_DATA (push, 1);
 538    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 539    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 540    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 541    PUSH_DATA (push, 0x11111111);
 542    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 543    PUSH_DATA (push, 1);
 544
 545    PUSH_KICK (push);
 546 }
 547
 548 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
 549       uint64_t *tls_size)
 550 {
 551    struct nouveau_device *dev = screen->base.device;
 552    int ret;
 553
 554    screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
 555          ONE_TEMP_SIZE;
 556    if (nouveau_mesa_debug)
 557       debug_printf("allocating space for %u temps\n",
 558             util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
 559    *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
 560          screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
 561
 562    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 563                         *tls_size, NULL, &screen->tls_bo);
 564    if (ret) {
 565       NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
 566       return ret;
 567    }
 568
 569    return 0;
 570 }
 571
 572 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
 573 {
 574    struct nouveau_pushbuf *push = screen->base.pushbuf;
 575    int ret;
 576    uint64_t tls_size;
 577
 578    if (tls_space < screen->cur_tls_space)
 579       return 0;
 580    if (tls_space > screen->max_tls_space) {
 581       /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
 582        * LOCAL_WARPS_NO_CLAMP) */
 583       NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
 584             (unsigned)(tls_space / ONE_TEMP_SIZE),
 585             (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
 586       return -ENOMEM;
 587    }
 588
 589    nouveau_bo_ref(NULL, &screen->tls_bo);
 590    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 591    if (ret)
 592       return ret;
 593
 594    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 595    PUSH_DATAh(push, screen->tls_bo->offset);
 596    PUSH_DATA (push, screen->tls_bo->offset);
 597    PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
 598
 599    return 1;
 600 }
 601
 602 struct pipe_screen *
 603 nv50_screen_create(struct nouveau_device *dev)
 604 {
 605    struct nv50_screen *screen;
 606    struct pipe_screen *pscreen;
 607    struct nouveau_object *chan;
 608    uint64_t value;
 609    uint32_t tesla_class;
 610    unsigned stack_size;
 611    int ret;
 612
 613    screen = CALLOC_STRUCT(nv50_screen);
 614    if (!screen)
 615       return NULL;
 616    pscreen = &screen->base.base;
 617
 618    ret = nouveau_screen_init(&screen->base, dev);
 619    if (ret) {
 620       NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
 621       goto fail;
 622    }
 623
 624    /* TODO: Prevent FIFO prefetch before transfer of index buffers and
 625     *  admit them to VRAM.
 626     */
 627    screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
 628       PIPE_BIND_VERTEX_BUFFER;
 629    screen->base.sysmem_bindings |=
 630       PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
 631
 632    screen->base.pushbuf->user_priv = screen;
 633    screen->base.pushbuf->rsvd_kick = 5;
 634
 635    chan = screen->base.channel;
 636
 637    pscreen->destroy = nv50_screen_destroy;
 638    pscreen->context_create = nv50_create;
 639    pscreen->is_format_supported = nv50_screen_is_format_supported;
 640    pscreen->get_param = nv50_screen_get_param;
 641    pscreen->get_shader_param = nv50_screen_get_shader_param;
 642    pscreen->get_paramf = nv50_screen_get_paramf;
 643
 644    nv50_screen_init_resource_functions(pscreen);
 645
 646    nouveau_screen_init_vdec(&screen->base);
 647
 648    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 649                         NULL, &screen->fence.bo);
 650    if (ret) {
 651       NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
 652       goto fail;
 653    }
 654
 655    nouveau_bo_map(screen->fence.bo, 0, NULL);
 656    screen->fence.map = screen->fence.bo->map;
 657    screen->base.fence.emit = nv50_screen_fence_emit;
 658    screen->base.fence.update = nv50_screen_fence_update;
 659
 660    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 661                             &(struct nv04_notify){ .length = 32 },
 662                             sizeof(struct nv04_notify), &screen->sync);
 663    if (ret) {
 664       NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
 665       goto fail;
 666    }
 667
 668    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 669                             NULL, 0, &screen->m2mf);
 670    if (ret) {
 671       NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
 672       goto fail;
 673    }
 674
 675    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 676                             NULL, 0, &screen->eng2d);
 677    if (ret) {
 678       NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
 679       goto fail;
 680    }
 681
 682    switch (dev->chipset & 0xf0) {
 683    case 0x50:
 684       tesla_class = NV50_3D_CLASS;
 685       break;
 686    case 0x80:
 687    case 0x90:
 688       tesla_class = NV84_3D_CLASS;
 689       break;
 690    case 0xa0:
 691       switch (dev->chipset) {
 692       case 0xa0:
 693       case 0xaa:
 694       case 0xac:
 695          tesla_class = NVA0_3D_CLASS;
 696          break;
 697       case 0xaf:
 698          tesla_class = NVAF_3D_CLASS;
 699          break;
 700       default:
 701          tesla_class = NVA3_3D_CLASS;
 702          break;
 703       }
 704       break;
 705    default:
 706       NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 707       goto fail;
 708    }
 709    screen->base.class_3d = tesla_class;
 710
 711    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 712                             NULL, 0, &screen->tesla);
 713    if (ret) {
 714       NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
 715       goto fail;
 716    }
 717
 718    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 719                         3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 720    if (ret) {
 721       NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
 722       goto fail;
 723    }
 724
 725    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 726    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 727    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 728
 729    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 730
 731    screen->TPs = util_bitcount(value & 0xffff);
 732    screen->MPsInTP = util_bitcount((value >> 24) & 0xf);
 733
 734    stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
 735          STACK_WARPS_ALLOC * 64 * 8;
 736
 737    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 738                         &screen->stack_bo);
 739    if (ret) {
 740       NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
 741       goto fail;
 742    }
 743
 744    uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
 745          screen->MPsInTP * LOCAL_WARPS_ALLOC *  THREADS_IN_WARP *
 746          ONE_TEMP_SIZE;
 747    screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
 748    screen->max_tls_space /= 2; /* half of vram */
 749
 750    /* hw can address max 64 KiB */
 751    screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
 752
 753    uint64_t tls_size;
 754    unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
 755    ret = nv50_tls_alloc(screen, tls_space, &tls_size);
 756    if (ret)
 757       goto fail;
 758
 759    if (nouveau_mesa_debug)
 760       debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
 761             screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
 762
 763    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 764                         &screen->uniforms);
 765    if (ret) {
 766       NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
 767       goto fail;
 768    }
 769
 770    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 771                         &screen->txc);
 772    if (ret) {
 773       NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
 774       goto fail;
 775    }
 776
 777    screen->tic.entries = CALLOC(4096, sizeof(void *));
 778    screen->tsc.entries = screen->tic.entries + 2048;
 779
 780    if (!nv50_blitter_create(screen))
 781       goto fail;
 782
 783    nv50_screen_init_hwctx(screen);
 784
 785    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 786
 787    return pscreen;
 788
 789 fail:
 790    nv50_screen_destroy(pscreen);
 791    return NULL;
 792 }
 793
 794 int
 795 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 796 {
 797    int i = screen->tic.next;
 798
 799    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 800       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 801
 802    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 803
 804    if (screen->tic.entries[i])
 805       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 806
 807    screen->tic.entries[i] = entry;
 808    return i;
 809 }
 810
 811 int
 812 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 813 {
 814    int i = screen->tsc.next;
 815
 816    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 817       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 818
 819    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 820
 821    if (screen->tsc.entries[i])
 822       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 823
 824    screen->tsc.entries[i] = entry;
 825    return i;
 826 }