src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 static boolean
  37 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  38                                 enum pipe_format format,
  39                                 enum pipe_texture_target target,
  40                                 unsigned sample_count,
  41                                 unsigned bindings)
  42 {
  43    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  44       return FALSE;
  45    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  46       return FALSE;
  47
  48    if (!util_format_is_supported(format, bindings))
  49       return FALSE;
  50
  51    switch (format) {
  52    case PIPE_FORMAT_Z16_UNORM:
  53       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  54          return FALSE;
  55       break;
  56    case PIPE_FORMAT_R8G8B8A8_UNORM:
  57    case PIPE_FORMAT_R8G8B8X8_UNORM:
  58       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  59       if (bindings & PIPE_BIND_RENDER_TARGET)
  60          return FALSE;
  61    default:
  62       break;
  63    }
  64
  65    /* transfers & shared are always supported */
  66    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  67                  PIPE_BIND_TRANSFER_WRITE |
  68                  PIPE_BIND_SHARED);
  69
  70    return (nv50_format_table[format].usage & bindings) == bindings;
  71 }
  72
  73 static int
  74 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  75 {
  76    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
  77
  78    switch (param) {
  79    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  80       return 64;
  81    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  82       return 14;
  83    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  84       return 12;
  85    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  86       return 14;
  87    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  88       return 512;
  89    case PIPE_CAP_MIN_TEXEL_OFFSET:
  90       return -8;
  91    case PIPE_CAP_MAX_TEXEL_OFFSET:
  92       return 7;
  93    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  94    case PIPE_CAP_TEXTURE_SWIZZLE:
  95    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  96    case PIPE_CAP_NPOT_TEXTURES:
  97    case PIPE_CAP_ANISOTROPIC_FILTER:
  98    case PIPE_CAP_SCALED_RESOLVE:
  99       return 1;
 100    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 101       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 102    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 103       return 0;
 104    case PIPE_CAP_TWO_SIDED_STENCIL:
 105    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 106    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 107    case PIPE_CAP_POINT_SPRITE:
 108       return 1;
 109    case PIPE_CAP_SM3:
 110       return 1;
 111    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 112       return 130;
 113    case PIPE_CAP_MAX_RENDER_TARGETS:
 114       return 8;
 115    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 116       return 1;
 117    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 118    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 119    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 120       return 1;
 121    case PIPE_CAP_TIMER_QUERY:
 122    case PIPE_CAP_OCCLUSION_QUERY:
 123       return 1;
 124    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 125       return 4;
 126    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 128       return 64;
 129    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 130       return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
 131    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 132    case PIPE_CAP_INDEP_BLEND_ENABLE:
 133       return 1;
 134    case PIPE_CAP_INDEP_BLEND_FUNC:
 135       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 136    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 137    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 138       return 1;
 139    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 140    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 141       return 0;
 142    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 143       return 0;
 144    case PIPE_CAP_PRIMITIVE_RESTART:
 145    case PIPE_CAP_TGSI_INSTANCEID:
 146    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 147    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 148    case PIPE_CAP_CONDITIONAL_RENDER:
 149    case PIPE_CAP_TEXTURE_BARRIER:
 150    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 151       return 1;
 152    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 153    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 154       return 0; /* state trackers will know better */
 155    case PIPE_CAP_USER_VERTEX_BUFFERS:
 156       return 1;
 157    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 158    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 159    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 160       return 0;
 161    default:
 162       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 163       return 0;
 164    }
 165 }
 166
 167 static int
 168 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 169                              enum pipe_shader_cap param)
 170 {
 171    switch (shader) {
 172    case PIPE_SHADER_VERTEX:
 173    case PIPE_SHADER_GEOMETRY:
 174    case PIPE_SHADER_FRAGMENT:
 175       break;
 176    default:
 177       return 0;
 178    }
 179
 180    switch (param) {
 181    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 182    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 183    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 184    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 185       return 16384;
 186    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 187       return 4;
 188    case PIPE_SHADER_CAP_MAX_INPUTS:
 189       if (shader == PIPE_SHADER_VERTEX)
 190          return 32;
 191       return 0x300 / 16;
 192    case PIPE_SHADER_CAP_MAX_CONSTS:
 193       return 65536 / 16;
 194    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 195       return 14;
 196    case PIPE_SHADER_CAP_MAX_ADDRS:
 197       return 1;
 198    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 199    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 200       return shader != PIPE_SHADER_FRAGMENT;
 201    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 202    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 203       return 1;
 204    case PIPE_SHADER_CAP_MAX_PREDS:
 205       return 0;
 206    case PIPE_SHADER_CAP_MAX_TEMPS:
 207       return NV50_CAP_MAX_PROGRAM_TEMPS;
 208    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 209       return 1;
 210    case PIPE_SHADER_CAP_SUBROUTINES:
 211       return 0; /* please inline, or provide function declarations */
 212    case PIPE_SHADER_CAP_INTEGERS:
 213       return 1;
 214    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 215       return 32;
 216    default:
 217       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 218       return 0;
 219    }
 220 }
 221
 222 static float
 223 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 224 {
 225    switch (param) {
 226    case PIPE_CAPF_MAX_LINE_WIDTH:
 227    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 228       return 10.0f;
 229    case PIPE_CAPF_MAX_POINT_WIDTH:
 230    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 231       return 64.0f;
 232    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 233       return 16.0f;
 234    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 235       return 4.0f;
 236    default:
 237       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 238       return 0.0f;
 239    }
 240 }
 241
 242 static void
 243 nv50_screen_destroy(struct pipe_screen *pscreen)
 244 {
 245    struct nv50_screen *screen = nv50_screen(pscreen);
 246
 247    if (screen->base.fence.current) {
 248       nouveau_fence_wait(screen->base.fence.current);
 249       nouveau_fence_ref (NULL, &screen->base.fence.current);
 250    }
 251    if (screen->base.pushbuf)
 252       screen->base.pushbuf->user_priv = NULL;
 253
 254    if (screen->blitctx)
 255       FREE(screen->blitctx);
 256
 257    nouveau_bo_ref(NULL, &screen->code);
 258    nouveau_bo_ref(NULL, &screen->tls_bo);
 259    nouveau_bo_ref(NULL, &screen->stack_bo);
 260    nouveau_bo_ref(NULL, &screen->txc);
 261    nouveau_bo_ref(NULL, &screen->uniforms);
 262    nouveau_bo_ref(NULL, &screen->fence.bo);
 263
 264    nouveau_heap_destroy(&screen->vp_code_heap);
 265    nouveau_heap_destroy(&screen->gp_code_heap);
 266    nouveau_heap_destroy(&screen->fp_code_heap);
 267
 268    if (screen->tic.entries)
 269       FREE(screen->tic.entries);
 270
 271    nouveau_object_del(&screen->tesla);
 272    nouveau_object_del(&screen->eng2d);
 273    nouveau_object_del(&screen->m2mf);
 274    nouveau_object_del(&screen->sync);
 275
 276    nouveau_screen_fini(&screen->base);
 277
 278    FREE(screen);
 279 }
 280
 281 static void
 282 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 283 {
 284    struct nv50_screen *screen = nv50_screen(pscreen);
 285    struct nouveau_pushbuf *push = screen->base.pushbuf;
 286
 287    /* we need to do it after possible flush in MARK_RING */
 288    *sequence = ++screen->base.fence.sequence;
 289
 290    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 291    PUSH_DATAh(push, screen->fence.bo->offset);
 292    PUSH_DATA (push, screen->fence.bo->offset);
 293    PUSH_DATA (push, *sequence);
 294    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 295                     NV50_3D_QUERY_GET_UNK4 |
 296                     NV50_3D_QUERY_GET_UNIT_CROP |
 297                     NV50_3D_QUERY_GET_TYPE_QUERY |
 298                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 299                     NV50_3D_QUERY_GET_SHORT);
 300 }
 301
 302 static u32
 303 nv50_screen_fence_update(struct pipe_screen *pscreen)
 304 {
 305    return nv50_screen(pscreen)->fence.map[0];
 306 }
 307
 308 static int
 309 nv50_screen_init_hwctx(struct nv50_screen *screen, unsigned tls_space)
 310 {
 311    struct nouveau_pushbuf *push = screen->base.pushbuf;
 312    struct nv04_fifo *fifo;
 313    unsigned i;
 314
 315    fifo = (struct nv04_fifo *)screen->base.channel->data;
 316
 317    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 318    PUSH_DATA (push, screen->m2mf->handle);
 319    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 320    PUSH_DATA (push, screen->sync->handle);
 321    PUSH_DATA (push, fifo->vram);
 322    PUSH_DATA (push, fifo->vram);
 323
 324    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 325    PUSH_DATA (push, screen->eng2d->handle);
 326    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 327    PUSH_DATA (push, screen->sync->handle);
 328    PUSH_DATA (push, fifo->vram);
 329    PUSH_DATA (push, fifo->vram);
 330    PUSH_DATA (push, fifo->vram);
 331    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 332    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 333    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 334    PUSH_DATA (push, 0);
 335    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 336    PUSH_DATA (push, 0);
 337    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 338    PUSH_DATA (push, 1);
 339
 340    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 341    PUSH_DATA (push, screen->tesla->handle);
 342
 343    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 344    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 345
 346    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 347    PUSH_DATA (push, screen->sync->handle);
 348    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 349    for (i = 0; i < 11; ++i)
 350       PUSH_DATA(push, fifo->vram);
 351    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 352    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 353       PUSH_DATA(push, fifo->vram);
 354
 355    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 356    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 357    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 358    PUSH_DATA (push, 0xf);
 359
 360    if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) {
 361       BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
 362       PUSH_DATA (push, 0x18);
 363    }
 364
 365    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 366    PUSH_DATA (push, 1);
 367
 368    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 369    PUSH_DATA (push, 0);
 370    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 371    PUSH_DATA (push, 0);
 372    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 373    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 374    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 375    PUSH_DATA (push, 0);
 376    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 377    PUSH_DATA (push, 0);
 378    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 379    PUSH_DATA (push, 1);
 380
 381    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 382       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 383       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 384    }
 385
 386    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 387    PUSH_DATA (push, 0);
 388    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 389    PUSH_DATA (push, 0);
 390    PUSH_DATA (push, 0);
 391    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 392    PUSH_DATA (push, 0x3f);
 393
 394    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 395    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 396    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 397
 398    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 399    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 400    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 401
 402    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 403    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 404    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 405
 406    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 407    PUSH_DATAh(push, screen->tls_bo->offset);
 408    PUSH_DATA (push, screen->tls_bo->offset);
 409    PUSH_DATA (push, util_logbase2(tls_space / 8));
 410
 411    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 412    PUSH_DATAh(push, screen->stack_bo->offset);
 413    PUSH_DATA (push, screen->stack_bo->offset);
 414    PUSH_DATA (push, 4);
 415
 416    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 417    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 418    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 419    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 420
 421    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 422    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 423    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 424    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 425
 426    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 427    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 428    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 429    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 430
 431    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 432    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 433    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 434    PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
 435
 436    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 6);
 437    PUSH_DATA (push, (NV50_CB_PVP << 12) | 0x001);
 438    PUSH_DATA (push, (NV50_CB_PGP << 12) | 0x021);
 439    PUSH_DATA (push, (NV50_CB_PFP << 12) | 0x031);
 440    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 441    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 442    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 443
 444    /* max TIC (bits 4:8) & TSC bindings, per program type */
 445    for (i = 0; i < 3; ++i) {
 446       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 447       PUSH_DATA (push, 0x54);
 448    }
 449
 450    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 451    PUSH_DATAh(push, screen->txc->offset);
 452    PUSH_DATA (push, screen->txc->offset);
 453    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 454
 455    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 456    PUSH_DATAh(push, screen->txc->offset + 65536);
 457    PUSH_DATA (push, screen->txc->offset + 65536);
 458    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 459
 460    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 461    PUSH_DATA (push, 0);
 462
 463    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 464    PUSH_DATA (push, 0);
 465    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 466    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 467    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 468    for (i = 0; i < 8 * 2; ++i)
 469       PUSH_DATA(push, 0);
 470    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 471    PUSH_DATA (push, 0);
 472
 473    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 474    PUSH_DATA (push, 1);
 475    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 476    PUSH_DATAf(push, 0.0f);
 477    PUSH_DATAf(push, 1.0f);
 478
 479    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 480 #ifdef NV50_SCISSORS_CLIPPING
 481    PUSH_DATA (push, 0x0000);
 482 #else
 483    PUSH_DATA (push, 0x1080);
 484 #endif
 485
 486    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 487    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 488
 489    /* We use scissors instead of exact view volume clipping,
 490     * so they're always enabled.
 491     */
 492    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 493    PUSH_DATA (push, 1);
 494    PUSH_DATA (push, 8192 << 16);
 495    PUSH_DATA (push, 8192 << 16);
 496
 497    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 498    PUSH_DATA (push, 1);
 499    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 500    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 501    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 502    PUSH_DATA (push, 0x11111111);
 503    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 504    PUSH_DATA (push, 1);
 505
 506    PUSH_KICK (push);
 507
 508    return 0;
 509 }
 510
 511 #define FAIL_SCREEN_INIT(str, err)                    \
 512    do {                                               \
 513       NOUVEAU_ERR(str, err);                          \
 514       nv50_screen_destroy(pscreen);                   \
 515       return NULL;                                    \
 516    } while(0)
 517
 518 struct pipe_screen *
 519 nv50_screen_create(struct nouveau_device *dev)
 520 {
 521    struct nv50_screen *screen;
 522    struct pipe_screen *pscreen;
 523    struct nouveau_object *chan;
 524    uint64_t value;
 525    uint32_t tesla_class;
 526    unsigned stack_size, max_warps, tls_space;
 527    int ret;
 528
 529    screen = CALLOC_STRUCT(nv50_screen);
 530    if (!screen)
 531       return NULL;
 532    pscreen = &screen->base.base;
 533
 534    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 535
 536    ret = nouveau_screen_init(&screen->base, dev);
 537    if (ret)
 538       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 539
 540    screen->base.pushbuf->user_priv = screen;
 541    screen->base.pushbuf->rsvd_kick = 5;
 542
 543    chan = screen->base.channel;
 544
 545    pscreen->destroy = nv50_screen_destroy;
 546    pscreen->context_create = nv50_create;
 547    pscreen->is_format_supported = nv50_screen_is_format_supported;
 548    pscreen->get_param = nv50_screen_get_param;
 549    pscreen->get_shader_param = nv50_screen_get_shader_param;
 550    pscreen->get_paramf = nv50_screen_get_paramf;
 551
 552    nv50_screen_init_resource_functions(pscreen);
 553
 554    nouveau_screen_init_vdec(&screen->base);
 555
 556    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 557                         NULL, &screen->fence.bo);
 558    if (ret)
 559       goto fail;
 560    nouveau_bo_map(screen->fence.bo, 0, NULL);
 561    screen->fence.map = screen->fence.bo->map;
 562    screen->base.fence.emit = nv50_screen_fence_emit;
 563    screen->base.fence.update = nv50_screen_fence_update;
 564
 565    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 566                             &(struct nv04_notify){ .length = 32 },
 567                             sizeof(struct nv04_notify), &screen->sync);
 568    if (ret)
 569       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 570
 571
 572    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 573                             NULL, 0, &screen->m2mf);
 574    if (ret)
 575       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 576
 577
 578    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 579                             NULL, 0, &screen->eng2d);
 580    if (ret)
 581       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 582
 583    switch (dev->chipset & 0xf0) {
 584    case 0x50:
 585       tesla_class = NV50_3D_CLASS;
 586       break;
 587    case 0x80:
 588    case 0x90:
 589       tesla_class = NV84_3D_CLASS;
 590       break;
 591    case 0xa0:
 592       switch (dev->chipset) {
 593       case 0xa0:
 594       case 0xaa:
 595       case 0xac:
 596          tesla_class = NVA0_3D_CLASS;
 597          break;
 598       case 0xaf:
 599          tesla_class = NVAF_3D_CLASS;
 600          break;
 601       default:
 602          tesla_class = NVA3_3D_CLASS;
 603          break;
 604       }
 605       break;
 606    default:
 607       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 608       break;
 609    }
 610    screen->base.class_3d = tesla_class;
 611
 612    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 613                             NULL, 0, &screen->tesla);
 614    if (ret)
 615       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 616
 617
 618    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 619                         3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 620    if (ret)
 621       goto fail;
 622
 623    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 624    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 625    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 626
 627    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 628
 629    max_warps  = util_bitcount(value & 0xffff);
 630    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 631
 632    stack_size = max_warps * 64 * 8;
 633
 634    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 635                         &screen->stack_bo);
 636    if (ret)
 637       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 638
 639    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 640
 641    screen->tls_size = tls_space * max_warps * 32;
 642
 643    if (nouveau_mesa_debug)
 644       debug_printf("max_warps = %i, tls_size = %"PRIu64" KiB\n",
 645                      max_warps, screen->tls_size >> 10);
 646
 647    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size, NULL,
 648                         &screen->tls_bo);
 649    if (ret)
 650       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 651
 652
 653    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 654                         &screen->uniforms);
 655    if (ret)
 656       goto fail;
 657
 658    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 659                         &screen->txc);
 660    if (ret)
 661       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 662
 663    screen->tic.entries = CALLOC(4096, sizeof(void *));
 664    screen->tsc.entries = screen->tic.entries + 2048;
 665
 666
 667    if (!nv50_blitctx_create(screen))
 668       goto fail;
 669
 670    if (nv50_screen_init_hwctx(screen, tls_space))
 671       goto fail;
 672
 673    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 674
 675    return pscreen;
 676
 677 fail:
 678    nv50_screen_destroy(pscreen);
 679    return NULL;
 680 }
 681
 682 int
 683 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 684 {
 685    int i = screen->tic.next;
 686
 687    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 688       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 689
 690    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 691
 692    if (screen->tic.entries[i])
 693       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 694
 695    screen->tic.entries[i] = entry;
 696    return i;
 697 }
 698
 699 int
 700 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 701 {
 702    int i = screen->tsc.next;
 703
 704    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 705       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 706
 707    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 708
 709    if (screen->tsc.entries[i])
 710       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 711
 712    screen->tsc.entries[i] = entry;
 713    return i;
 714 }