src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 extern int nouveau_device_get_param(struct nouveau_device *dev,
  37                                     uint64_t param, uint64_t *value);
  38
  39 static boolean
  40 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (sample_count > 1)
  47       return FALSE;
  48
  49    if (!util_format_is_supported(format, bindings))
  50       return FALSE;
  51
  52    switch (format) {
  53    case PIPE_FORMAT_Z16_UNORM:
  54       if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D)
  55          return FALSE;
  56       break;
  57    default:
  58       break;
  59    }
  60
  61    /* transfers & shared are always supported */
  62    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  63                  PIPE_BIND_TRANSFER_WRITE |
  64                  PIPE_BIND_SHARED);
  65
  66    return (nv50_format_table[format].usage & bindings) == bindings;
  67 }
  68
  69 static int
  70 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  71 {
  72    switch (param) {
  73    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  74    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  75       return 32;
  76    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  77       return 64;
  78    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  79       return 13;
  80    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  81       return 10;
  82    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  83       return 13;
  84    case PIPE_CAP_ARRAY_TEXTURES: /* shader support missing */
  85       return 0;
  86    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  87    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  88    case PIPE_CAP_TEXTURE_SWIZZLE:
  89    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  90    case PIPE_CAP_NPOT_TEXTURES:
  91    case PIPE_CAP_ANISOTROPIC_FILTER:
  92       return 1;
  93    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  94       return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
  95    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  96       return 0;
  97    case PIPE_CAP_TWO_SIDED_STENCIL:
  98    case PIPE_CAP_DEPTH_CLAMP:
  99    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 100    case PIPE_CAP_POINT_SPRITE:
 101       return 1;
 102    case PIPE_CAP_GLSL:
 103    case PIPE_CAP_SM3:
 104       return 1;
 105    case PIPE_CAP_MAX_RENDER_TARGETS:
 106       return 8;
 107    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 108       return 1;
 109    case PIPE_CAP_TIMER_QUERY:
 110    case PIPE_CAP_OCCLUSION_QUERY:
 111       return 1;
 112    case PIPE_CAP_STREAM_OUTPUT:
 113       return 0;
 114    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 115    case PIPE_CAP_INDEP_BLEND_ENABLE:
 116       return 1;
 117    case PIPE_CAP_INDEP_BLEND_FUNC:
 118       return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D;
 119    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 120    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 121       return 1;
 122    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 123    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 124       return 0;
 125    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 126       return 0;
 127    case PIPE_CAP_PRIMITIVE_RESTART:
 128    case PIPE_CAP_TGSI_INSTANCEID:
 129    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 130    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 131       return 1;
 132    default:
 133       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 134       return 0;
 135    }
 136 }
 137
 138 static int
 139 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 140                              enum pipe_shader_cap param)
 141 {
 142    switch (shader) {
 143    case PIPE_SHADER_VERTEX:
 144    case PIPE_SHADER_GEOMETRY:
 145    case PIPE_SHADER_FRAGMENT:
 146       break;
 147    default:
 148       return 0;
 149    }
 150
 151    switch (param) {
 152    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 153    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 154    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 155    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 156       return 16384;
 157    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 158       return 4;
 159    case PIPE_SHADER_CAP_MAX_INPUTS:
 160       if (shader == PIPE_SHADER_VERTEX)
 161          return 32;
 162       return 0x300 / 16;
 163    case PIPE_SHADER_CAP_MAX_CONSTS:
 164       return 65536 / 16;
 165    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 166       return 14;
 167    case PIPE_SHADER_CAP_MAX_ADDRS:
 168       return 1;
 169    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 170    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 171       return shader != PIPE_SHADER_FRAGMENT;
 172    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 173    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 174       return 1;
 175    case PIPE_SHADER_CAP_MAX_PREDS:
 176       return 0;
 177    case PIPE_SHADER_CAP_MAX_TEMPS:
 178       return NV50_CAP_MAX_PROGRAM_TEMPS;
 179    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 180       return 1;
 181    case PIPE_SHADER_CAP_SUBROUTINES:
 182       return 0; /* please inline, or provide function declarations */
 183    default:
 184       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 185       return 0;
 186    }
 187 }
 188
 189 static float
 190 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 191 {
 192    switch (param) {
 193    case PIPE_CAP_MAX_LINE_WIDTH:
 194    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 195       return 10.0f;
 196    case PIPE_CAP_MAX_POINT_WIDTH:
 197    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 198       return 64.0f;
 199    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 200       return 16.0f;
 201    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 202       return 4.0f;
 203    default:
 204       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 205       return 0.0f;
 206    }
 207 }
 208
 209 static void
 210 nv50_screen_destroy(struct pipe_screen *pscreen)
 211 {
 212    struct nv50_screen *screen = nv50_screen(pscreen);
 213
 214    if (screen->base.fence.current) {
 215       nouveau_fence_wait(screen->base.fence.current);
 216       nouveau_fence_ref (NULL, &screen->base.fence.current);
 217    }
 218    screen->base.channel->user_private = NULL;
 219
 220    nouveau_bo_ref(NULL, &screen->code);
 221    nouveau_bo_ref(NULL, &screen->tls_bo);
 222    nouveau_bo_ref(NULL, &screen->stack_bo);
 223    nouveau_bo_ref(NULL, &screen->txc);
 224    nouveau_bo_ref(NULL, &screen->uniforms);
 225    nouveau_bo_ref(NULL, &screen->fence.bo);
 226
 227    nouveau_resource_destroy(&screen->vp_code_heap);
 228    nouveau_resource_destroy(&screen->gp_code_heap);
 229    nouveau_resource_destroy(&screen->fp_code_heap);
 230
 231    if (screen->tic.entries)
 232       FREE(screen->tic.entries);
 233
 234    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 235
 236    nouveau_grobj_free(&screen->tesla);
 237    nouveau_grobj_free(&screen->eng2d);
 238    nouveau_grobj_free(&screen->m2mf);
 239
 240    nouveau_notifier_free(&screen->sync);
 241
 242    nouveau_screen_fini(&screen->base);
 243
 244    FREE(screen);
 245 }
 246
 247 static void
 248 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 249 {
 250    struct nv50_screen *screen = nv50_screen(pscreen);
 251    struct nouveau_channel *chan = screen->base.channel;
 252
 253    MARK_RING (chan, 5, 2);
 254    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 255    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 256    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 257    OUT_RING  (chan, sequence);
 258    OUT_RING  (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 259                     NV50_3D_QUERY_GET_UNK4 |
 260                     NV50_3D_QUERY_GET_UNIT_CROP |
 261                     NV50_3D_QUERY_GET_TYPE_QUERY |
 262                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 263                     NV50_3D_QUERY_GET_SHORT);
 264 }
 265
 266 static u32
 267 nv50_screen_fence_update(struct pipe_screen *pscreen)
 268 {
 269    struct nv50_screen *screen = nv50_screen(pscreen);
 270    return screen->fence.map[0];
 271 }
 272
 273 #define FAIL_SCREEN_INIT(str, err)                    \
 274    do {                                               \
 275       NOUVEAU_ERR(str, err);                          \
 276       nv50_screen_destroy(pscreen);                   \
 277       return NULL;                                    \
 278    } while(0)
 279
 280 struct pipe_screen *
 281 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 282 {
 283    struct nv50_screen *screen;
 284    struct nouveau_channel *chan;
 285    struct pipe_screen *pscreen;
 286    uint64_t value;
 287    uint32_t tesla_class;
 288    unsigned stack_size, max_warps, tls_space;
 289    int ret;
 290    unsigned i, base;
 291
 292    screen = CALLOC_STRUCT(nv50_screen);
 293    if (!screen)
 294       return NULL;
 295    pscreen = &screen->base.base;
 296
 297    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 298
 299    ret = nouveau_screen_init(&screen->base, dev);
 300    if (ret)
 301       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 302
 303    chan = screen->base.channel;
 304    chan->user_private = screen;
 305
 306    pscreen->winsys = ws;
 307    pscreen->destroy = nv50_screen_destroy;
 308    pscreen->context_create = nv50_create;
 309    pscreen->is_format_supported = nv50_screen_is_format_supported;
 310    pscreen->get_param = nv50_screen_get_param;
 311    pscreen->get_shader_param = nv50_screen_get_shader_param;
 312    pscreen->get_paramf = nv50_screen_get_paramf;
 313
 314    nv50_screen_init_resource_functions(pscreen);
 315
 316    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 317                         &screen->fence.bo);
 318    if (ret)
 319       goto fail;
 320    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 321    screen->fence.map = screen->fence.bo->map;
 322    nouveau_bo_unmap(screen->fence.bo);
 323    screen->base.fence.emit = nv50_screen_fence_emit;
 324    screen->base.fence.update = nv50_screen_fence_update;
 325
 326    ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 327    if (ret)
 328       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 329
 330    ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
 331    if (ret)
 332       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 333
 334    BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
 335    BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
 336    OUT_RING  (chan, screen->sync->handle);
 337    OUT_RING  (chan, chan->vram->handle);
 338    OUT_RING  (chan, chan->vram->handle);
 339
 340    ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 341    if (ret)
 342       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 343
 344    BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
 345    BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
 346    OUT_RING  (chan, screen->sync->handle);
 347    OUT_RING  (chan, chan->vram->handle);
 348    OUT_RING  (chan, chan->vram->handle);
 349    OUT_RING  (chan, chan->vram->handle);
 350    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 351    OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 352    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 353    OUT_RING  (chan, 0);
 354    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 355    OUT_RING  (chan, 0);
 356    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 357    OUT_RING  (chan, 1);
 358
 359    switch (dev->chipset & 0xf0) {
 360    case 0x50:
 361       tesla_class = NV50_3D;
 362       break;
 363    case 0x80:
 364    case 0x90:
 365       tesla_class = NV84_3D;
 366       break;
 367    case 0xa0:
 368       switch (dev->chipset) {
 369       case 0xa0:
 370       case 0xaa:
 371       case 0xac:
 372          tesla_class = NVA0_3D;
 373          break;
 374       case 0xaf:
 375          tesla_class = NVAF_3D;
 376          break;
 377       default:
 378          tesla_class = NVA3_3D;
 379          break;
 380       }
 381       break;
 382    default:
 383       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 384       break;
 385    }
 386
 387    ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
 388    if (ret)
 389       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 390
 391    BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
 392
 393    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 394    OUT_RING  (chan, NV50_3D_COND_MODE_ALWAYS);
 395
 396    BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
 397    OUT_RING  (chan, screen->sync->handle);
 398    BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
 399    for (i = 0; i < 11; ++i)
 400       OUT_RING(chan, chan->vram->handle);
 401    BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 402    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 403       OUT_RING(chan, chan->vram->handle);
 404
 405    BEGIN_RING(chan, RING_3D(REG_MODE), 1);
 406    OUT_RING  (chan, NV50_3D_REG_MODE_STRIPED);
 407    BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
 408    OUT_RING  (chan, 0xf);
 409
 410    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 411    OUT_RING  (chan, 1);
 412
 413    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 414    OUT_RING  (chan, 0);
 415    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 416    OUT_RING  (chan, 0);
 417    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 418    OUT_RING  (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
 419    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 420    OUT_RING  (chan, 0);
 421    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 422    OUT_RING  (chan, 0);
 423    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 424    OUT_RING  (chan, 1);
 425
 426    if (tesla_class >= NVA0_3D) {
 427       BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1);
 428       OUT_RING  (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 429    }
 430
 431    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 432    OUT_RING  (chan, 0);
 433    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 434    OUT_RING  (chan, 0);
 435    OUT_RING  (chan, 0);
 436    BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 437    OUT_RING  (chan, 0x3f);
 438
 439    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 440                         3 << NV50_CODE_BO_SIZE_LOG2, &screen->code);
 441    if (ret)
 442       goto fail;
 443
 444    nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 445    nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 446    nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 447
 448    base = 1 << NV50_CODE_BO_SIZE_LOG2;
 449
 450    BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
 451    OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 452    OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 453
 454    BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
 455    OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 456    OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 457
 458    BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
 459    OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 460    OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 461
 462    nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 463
 464    max_warps  = util_bitcount(value & 0xffff);
 465    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 466
 467    stack_size = max_warps * 64 * 8;
 468
 469    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
 470                         &screen->stack_bo);
 471    if (ret)
 472       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 473
 474    BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
 475    OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 476    OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 477    OUT_RING  (chan, 4);
 478
 479    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 480
 481    screen->tls_size = tls_space * max_warps * 32;
 482
 483    debug_printf("max_warps = %i, tls_size = %llu KiB\n",
 484                 max_warps, screen->tls_size >> 10);
 485
 486    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
 487                         &screen->tls_bo);
 488    if (ret)
 489       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 490
 491    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
 492    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 493    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 494    OUT_RING  (chan, util_logbase2(tls_space / 8));
 495
 496    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
 497                         &screen->uniforms);
 498    if (ret)
 499       goto fail;
 500
 501    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 502    OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 503    OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 504    OUT_RING  (chan, (NV50_CB_PVP << 16) | 0x0000);
 505
 506    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 507    OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 508    OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 509    OUT_RING  (chan, (NV50_CB_PGP << 16) | 0x0000);
 510
 511    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 512    OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 513    OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 514    OUT_RING  (chan, (NV50_CB_PFP << 16) | 0x0000);
 515
 516    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 517    OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 518    OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 519    OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 520
 521    BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
 522    OUT_RING  (chan, (NV50_CB_PVP << 12) | 0x001);
 523    OUT_RING  (chan, (NV50_CB_PGP << 12) | 0x021);
 524    OUT_RING  (chan, (NV50_CB_PFP << 12) | 0x031);
 525    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf01);
 526    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf21);
 527    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf31);
 528
 529    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
 530                         &screen->txc);
 531    if (ret)
 532       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 533
 534    /* max TIC (bits 4:8) & TSC bindings, per program type */
 535    for (i = 0; i < 3; ++i) {
 536       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 537       OUT_RING  (chan, 0x54);
 538    }
 539
 540    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 541    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 542    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 543    OUT_RING  (chan, NV50_TIC_MAX_ENTRIES - 1);
 544
 545    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 546    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 547    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 548    OUT_RING  (chan, NV50_TSC_MAX_ENTRIES - 1);
 549
 550    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 551    OUT_RING  (chan, 0);
 552
 553    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 554    OUT_RING  (chan, 0);
 555    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 556    OUT_RING  (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 557    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 558    for (i = 0; i < 8 * 2; ++i)
 559       OUT_RING(chan, 0);
 560    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 561    OUT_RING  (chan, 0);
 562
 563    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 564    OUT_RING  (chan, 1);
 565    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 566    OUT_RINGf (chan, 0.0f);
 567    OUT_RINGf (chan, 1.0f);
 568
 569    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 570 #ifdef NV50_SCISSORS_CLIPPING
 571    OUT_RING  (chan, 0x0000);
 572 #else
 573    OUT_RING  (chan, 0x1080);
 574 #endif
 575
 576    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 577    OUT_RING  (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 578
 579    /* We use scissors instead of exact view volume clipping,
 580     * so they're always enabled.
 581     */
 582    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 583    OUT_RING  (chan, 1);
 584    OUT_RING  (chan, 8192 << 16);
 585    OUT_RING  (chan, 8192 << 16);
 586
 587    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 588    OUT_RING  (chan, 1);
 589    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 590    OUT_RING  (chan, NV50_3D_POINT_RASTER_RULES_OGL);
 591    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 592    OUT_RING  (chan, 0x11111111);
 593    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 594    OUT_RING  (chan, 1);
 595
 596    FIRE_RING (chan);
 597
 598    screen->tic.entries = CALLOC(4096, sizeof(void *));
 599    screen->tsc.entries = screen->tic.entries + 2048;
 600
 601    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 602
 603    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 604
 605    return pscreen;
 606
 607 fail:
 608    nv50_screen_destroy(pscreen);
 609    return NULL;
 610 }
 611
 612 void
 613 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
 614 {
 615    struct nouveau_channel *chan = screen->base.channel;
 616
 617    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 618
 619    MARK_RING(chan, 5, 5);
 620    nouveau_bo_validate(chan, screen->code, flags);
 621    nouveau_bo_validate(chan, screen->uniforms, flags);
 622    nouveau_bo_validate(chan, screen->txc, flags);
 623    nouveau_bo_validate(chan, screen->tls_bo, flags);
 624    nouveau_bo_validate(chan, screen->stack_bo, flags);
 625 }
 626
 627 int
 628 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 629 {
 630    int i = screen->tic.next;
 631
 632    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 633       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 634
 635    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 636
 637    if (screen->tic.entries[i])
 638       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 639
 640    screen->tic.entries[i] = entry;
 641    return i;
 642 }
 643
 644 int
 645 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 646 {
 647    int i = screen->tsc.next;
 648
 649    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 650       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 651
 652    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 653
 654    if (screen->tsc.entries[i])
 655       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 656
 657    screen->tsc.entries[i] = entry;
 658    return i;
 659 }