src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 extern int nouveau_device_get_param(struct nouveau_device *dev,
  37                                     uint64_t param, uint64_t *value);
  38
  39 static boolean
  40 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (sample_count > 2 && sample_count != 4 && sample_count != 8)
  47       return FALSE;
  48    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  49       return FALSE;
  50
  51    if (!util_format_is_supported(format, bindings))
  52       return FALSE;
  53
  54    switch (format) {
  55    case PIPE_FORMAT_Z16_UNORM:
  56       if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D)
  57          return FALSE;
  58       break;
  59    default:
  60       break;
  61    }
  62
  63    /* transfers & shared are always supported */
  64    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  65                  PIPE_BIND_TRANSFER_WRITE |
  66                  PIPE_BIND_SHARED);
  67
  68    return (nv50_format_table[format].usage & bindings) == bindings;
  69 }
  70
  71 static int
  72 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  73 {
  74    switch (param) {
  75    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  76    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  77       return 32;
  78    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  79       return 64;
  80    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  81       return 13;
  82    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  83       return 10;
  84    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  85       return 13;
  86    case PIPE_CAP_ARRAY_TEXTURES: /* shader support missing */
  87       return 0;
  88    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  89    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  90    case PIPE_CAP_TEXTURE_SWIZZLE:
  91    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  92    case PIPE_CAP_NPOT_TEXTURES:
  93    case PIPE_CAP_ANISOTROPIC_FILTER:
  94    case PIPE_CAP_SCALED_RESOLVE:
  95       return 1;
  96    case PIPE_CAP_SEAMLESS_CUBE_MAP:
  97       return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
  98    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  99       return 0;
 100    case PIPE_CAP_TWO_SIDED_STENCIL:
 101    case PIPE_CAP_DEPTH_CLAMP:
 102    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 103    case PIPE_CAP_POINT_SPRITE:
 104       return 1;
 105    case PIPE_CAP_GLSL:
 106    case PIPE_CAP_SM3:
 107       return 1;
 108    case PIPE_CAP_MAX_RENDER_TARGETS:
 109       return 8;
 110    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 111       return 1;
 112    case PIPE_CAP_TIMER_QUERY:
 113    case PIPE_CAP_OCCLUSION_QUERY:
 114       return 1;
 115    case PIPE_CAP_STREAM_OUTPUT:
 116       return 0;
 117    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 118    case PIPE_CAP_INDEP_BLEND_ENABLE:
 119       return 1;
 120    case PIPE_CAP_INDEP_BLEND_FUNC:
 121       return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D;
 122    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 123    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 124       return 1;
 125    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 126    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 127       return 0;
 128    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 129       return 0;
 130    case PIPE_CAP_PRIMITIVE_RESTART:
 131    case PIPE_CAP_TGSI_INSTANCEID:
 132    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 133    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 134       return 1;
 135    default:
 136       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 137       return 0;
 138    }
 139 }
 140
 141 static int
 142 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 143                              enum pipe_shader_cap param)
 144 {
 145    switch (shader) {
 146    case PIPE_SHADER_VERTEX:
 147    case PIPE_SHADER_GEOMETRY:
 148    case PIPE_SHADER_FRAGMENT:
 149       break;
 150    default:
 151       return 0;
 152    }
 153
 154    switch (param) {
 155    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 156    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 157    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 158    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 159       return 16384;
 160    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 161       return 4;
 162    case PIPE_SHADER_CAP_MAX_INPUTS:
 163       if (shader == PIPE_SHADER_VERTEX)
 164          return 32;
 165       return 0x300 / 16;
 166    case PIPE_SHADER_CAP_MAX_CONSTS:
 167       return 65536 / 16;
 168    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 169       return 14;
 170    case PIPE_SHADER_CAP_MAX_ADDRS:
 171       return 1;
 172    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 173    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 174       return shader != PIPE_SHADER_FRAGMENT;
 175    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 176    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 177       return 1;
 178    case PIPE_SHADER_CAP_MAX_PREDS:
 179       return 0;
 180    case PIPE_SHADER_CAP_MAX_TEMPS:
 181       return NV50_CAP_MAX_PROGRAM_TEMPS;
 182    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 183       return 1;
 184    case PIPE_SHADER_CAP_SUBROUTINES:
 185       return 0; /* please inline, or provide function declarations */
 186    case PIPE_SHADER_CAP_INTEGERS:
 187       return 0;
 188    default:
 189       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 190       return 0;
 191    }
 192 }
 193
 194 static float
 195 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 196 {
 197    switch (param) {
 198    case PIPE_CAP_MAX_LINE_WIDTH:
 199    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 200       return 10.0f;
 201    case PIPE_CAP_MAX_POINT_WIDTH:
 202    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 203       return 64.0f;
 204    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 205       return 16.0f;
 206    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 207       return 4.0f;
 208    default:
 209       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 210       return 0.0f;
 211    }
 212 }
 213
 214 static void
 215 nv50_screen_destroy(struct pipe_screen *pscreen)
 216 {
 217    struct nv50_screen *screen = nv50_screen(pscreen);
 218
 219    if (screen->base.fence.current) {
 220       nouveau_fence_wait(screen->base.fence.current);
 221       nouveau_fence_ref (NULL, &screen->base.fence.current);
 222    }
 223    screen->base.channel->user_private = NULL;
 224
 225    nouveau_bo_ref(NULL, &screen->code);
 226    nouveau_bo_ref(NULL, &screen->tls_bo);
 227    nouveau_bo_ref(NULL, &screen->stack_bo);
 228    nouveau_bo_ref(NULL, &screen->txc);
 229    nouveau_bo_ref(NULL, &screen->uniforms);
 230    nouveau_bo_ref(NULL, &screen->fence.bo);
 231
 232    nouveau_resource_destroy(&screen->vp_code_heap);
 233    nouveau_resource_destroy(&screen->gp_code_heap);
 234    nouveau_resource_destroy(&screen->fp_code_heap);
 235
 236    if (screen->tic.entries)
 237       FREE(screen->tic.entries);
 238
 239    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 240
 241    nouveau_grobj_free(&screen->tesla);
 242    nouveau_grobj_free(&screen->eng2d);
 243    nouveau_grobj_free(&screen->m2mf);
 244
 245    nouveau_notifier_free(&screen->sync);
 246
 247    nouveau_screen_fini(&screen->base);
 248
 249    FREE(screen);
 250 }
 251
 252 static void
 253 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 254 {
 255    struct nv50_screen *screen = nv50_screen(pscreen);
 256    struct nouveau_channel *chan = screen->base.channel;
 257
 258    MARK_RING (chan, 5, 2);
 259    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 260    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 261    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 262    OUT_RING  (chan, sequence);
 263    OUT_RING  (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 264                     NV50_3D_QUERY_GET_UNK4 |
 265                     NV50_3D_QUERY_GET_UNIT_CROP |
 266                     NV50_3D_QUERY_GET_TYPE_QUERY |
 267                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 268                     NV50_3D_QUERY_GET_SHORT);
 269 }
 270
 271 static u32
 272 nv50_screen_fence_update(struct pipe_screen *pscreen)
 273 {
 274    struct nv50_screen *screen = nv50_screen(pscreen);
 275    return screen->fence.map[0];
 276 }
 277
 278 #define FAIL_SCREEN_INIT(str, err)                    \
 279    do {                                               \
 280       NOUVEAU_ERR(str, err);                          \
 281       nv50_screen_destroy(pscreen);                   \
 282       return NULL;                                    \
 283    } while(0)
 284
 285 struct pipe_screen *
 286 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 287 {
 288    struct nv50_screen *screen;
 289    struct nouveau_channel *chan;
 290    struct pipe_screen *pscreen;
 291    uint64_t value;
 292    uint32_t tesla_class;
 293    unsigned stack_size, max_warps, tls_space;
 294    int ret;
 295    unsigned i, base;
 296
 297    screen = CALLOC_STRUCT(nv50_screen);
 298    if (!screen)
 299       return NULL;
 300    pscreen = &screen->base.base;
 301
 302    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 303
 304    ret = nouveau_screen_init(&screen->base, dev);
 305    if (ret)
 306       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 307
 308    chan = screen->base.channel;
 309    chan->user_private = screen;
 310
 311    pscreen->winsys = ws;
 312    pscreen->destroy = nv50_screen_destroy;
 313    pscreen->context_create = nv50_create;
 314    pscreen->is_format_supported = nv50_screen_is_format_supported;
 315    pscreen->get_param = nv50_screen_get_param;
 316    pscreen->get_shader_param = nv50_screen_get_shader_param;
 317    pscreen->get_paramf = nv50_screen_get_paramf;
 318
 319    nv50_screen_init_resource_functions(pscreen);
 320
 321    nouveau_screen_init_vdec(&screen->base);
 322
 323    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 324                         &screen->fence.bo);
 325    if (ret)
 326       goto fail;
 327    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 328    screen->fence.map = screen->fence.bo->map;
 329    nouveau_bo_unmap(screen->fence.bo);
 330    screen->base.fence.emit = nv50_screen_fence_emit;
 331    screen->base.fence.update = nv50_screen_fence_update;
 332
 333    ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 334    if (ret)
 335       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 336
 337    ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
 338    if (ret)
 339       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 340
 341    BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
 342    BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
 343    OUT_RING  (chan, screen->sync->handle);
 344    OUT_RING  (chan, chan->vram->handle);
 345    OUT_RING  (chan, chan->vram->handle);
 346
 347    ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 348    if (ret)
 349       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 350
 351    BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
 352    BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
 353    OUT_RING  (chan, screen->sync->handle);
 354    OUT_RING  (chan, chan->vram->handle);
 355    OUT_RING  (chan, chan->vram->handle);
 356    OUT_RING  (chan, chan->vram->handle);
 357    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 358    OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 359    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 360    OUT_RING  (chan, 0);
 361    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 362    OUT_RING  (chan, 0);
 363    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 364    OUT_RING  (chan, 1);
 365
 366    switch (dev->chipset & 0xf0) {
 367    case 0x50:
 368       tesla_class = NV50_3D;
 369       break;
 370    case 0x80:
 371    case 0x90:
 372       tesla_class = NV84_3D;
 373       break;
 374    case 0xa0:
 375       switch (dev->chipset) {
 376       case 0xa0:
 377       case 0xaa:
 378       case 0xac:
 379          tesla_class = NVA0_3D;
 380          break;
 381       case 0xaf:
 382          tesla_class = NVAF_3D;
 383          break;
 384       default:
 385          tesla_class = NVA3_3D;
 386          break;
 387       }
 388       break;
 389    default:
 390       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 391       break;
 392    }
 393
 394    ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
 395    if (ret)
 396       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 397
 398    BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
 399
 400    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 401    OUT_RING  (chan, NV50_3D_COND_MODE_ALWAYS);
 402
 403    BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
 404    OUT_RING  (chan, screen->sync->handle);
 405    BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
 406    for (i = 0; i < 11; ++i)
 407       OUT_RING(chan, chan->vram->handle);
 408    BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 409    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 410       OUT_RING(chan, chan->vram->handle);
 411
 412    BEGIN_RING(chan, RING_3D(REG_MODE), 1);
 413    OUT_RING  (chan, NV50_3D_REG_MODE_STRIPED);
 414    BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
 415    OUT_RING  (chan, 0xf);
 416
 417    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 418    OUT_RING  (chan, 1);
 419
 420    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 421    OUT_RING  (chan, 0);
 422    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 423    OUT_RING  (chan, 0);
 424    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 425    OUT_RING  (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
 426    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 427    OUT_RING  (chan, 0);
 428    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 429    OUT_RING  (chan, 0);
 430    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 431    OUT_RING  (chan, 1);
 432
 433    if (tesla_class >= NVA0_3D) {
 434       BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1);
 435       OUT_RING  (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 436    }
 437
 438    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 439    OUT_RING  (chan, 0);
 440    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 441    OUT_RING  (chan, 0);
 442    OUT_RING  (chan, 0);
 443    BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 444    OUT_RING  (chan, 0x3f);
 445
 446    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 447                         3 << NV50_CODE_BO_SIZE_LOG2, &screen->code);
 448    if (ret)
 449       goto fail;
 450
 451    nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 452    nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 453    nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 454
 455    base = 1 << NV50_CODE_BO_SIZE_LOG2;
 456
 457    BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
 458    OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 459    OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 460
 461    BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
 462    OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 463    OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 464
 465    BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
 466    OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 467    OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 468
 469    nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 470
 471    max_warps  = util_bitcount(value & 0xffff);
 472    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 473
 474    stack_size = max_warps * 64 * 8;
 475
 476    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
 477                         &screen->stack_bo);
 478    if (ret)
 479       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 480
 481    BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
 482    OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 483    OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 484    OUT_RING  (chan, 4);
 485
 486    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 487
 488    screen->tls_size = tls_space * max_warps * 32;
 489
 490    debug_printf("max_warps = %i, tls_size = %llu KiB\n",
 491                 max_warps, screen->tls_size >> 10);
 492
 493    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
 494                         &screen->tls_bo);
 495    if (ret)
 496       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 497
 498    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
 499    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 500    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 501    OUT_RING  (chan, util_logbase2(tls_space / 8));
 502
 503    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
 504                         &screen->uniforms);
 505    if (ret)
 506       goto fail;
 507
 508    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 509    OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 510    OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 511    OUT_RING  (chan, (NV50_CB_PVP << 16) | 0x0000);
 512
 513    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 514    OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 515    OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 516    OUT_RING  (chan, (NV50_CB_PGP << 16) | 0x0000);
 517
 518    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 519    OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 520    OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 521    OUT_RING  (chan, (NV50_CB_PFP << 16) | 0x0000);
 522
 523    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 524    OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 525    OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 526    OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 527
 528    BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
 529    OUT_RING  (chan, (NV50_CB_PVP << 12) | 0x001);
 530    OUT_RING  (chan, (NV50_CB_PGP << 12) | 0x021);
 531    OUT_RING  (chan, (NV50_CB_PFP << 12) | 0x031);
 532    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf01);
 533    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf21);
 534    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf31);
 535
 536    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
 537                         &screen->txc);
 538    if (ret)
 539       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 540
 541    /* max TIC (bits 4:8) & TSC bindings, per program type */
 542    for (i = 0; i < 3; ++i) {
 543       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 544       OUT_RING  (chan, 0x54);
 545    }
 546
 547    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 548    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 549    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 550    OUT_RING  (chan, NV50_TIC_MAX_ENTRIES - 1);
 551
 552    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 553    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 554    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 555    OUT_RING  (chan, NV50_TSC_MAX_ENTRIES - 1);
 556
 557    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 558    OUT_RING  (chan, 0);
 559
 560    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 561    OUT_RING  (chan, 0);
 562    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 563    OUT_RING  (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 564    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 565    for (i = 0; i < 8 * 2; ++i)
 566       OUT_RING(chan, 0);
 567    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 568    OUT_RING  (chan, 0);
 569
 570    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 571    OUT_RING  (chan, 1);
 572    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 573    OUT_RINGf (chan, 0.0f);
 574    OUT_RINGf (chan, 1.0f);
 575
 576    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 577 #ifdef NV50_SCISSORS_CLIPPING
 578    OUT_RING  (chan, 0x0000);
 579 #else
 580    OUT_RING  (chan, 0x1080);
 581 #endif
 582
 583    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 584    OUT_RING  (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 585
 586    /* We use scissors instead of exact view volume clipping,
 587     * so they're always enabled.
 588     */
 589    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 590    OUT_RING  (chan, 1);
 591    OUT_RING  (chan, 8192 << 16);
 592    OUT_RING  (chan, 8192 << 16);
 593
 594    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 595    OUT_RING  (chan, 1);
 596    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 597    OUT_RING  (chan, NV50_3D_POINT_RASTER_RULES_OGL);
 598    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 599    OUT_RING  (chan, 0x11111111);
 600    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 601    OUT_RING  (chan, 1);
 602
 603    FIRE_RING (chan);
 604
 605    screen->tic.entries = CALLOC(4096, sizeof(void *));
 606    screen->tsc.entries = screen->tic.entries + 2048;
 607
 608    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 609
 610    if (!nv50_blitctx_create(screen))
 611       goto fail;
 612
 613    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 614
 615    return pscreen;
 616
 617 fail:
 618    nv50_screen_destroy(pscreen);
 619    return NULL;
 620 }
 621
 622 void
 623 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
 624 {
 625    struct nouveau_channel *chan = screen->base.channel;
 626
 627    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 628
 629    MARK_RING(chan, 5, 5);
 630    nouveau_bo_validate(chan, screen->code, flags);
 631    nouveau_bo_validate(chan, screen->uniforms, flags);
 632    nouveau_bo_validate(chan, screen->txc, flags);
 633    nouveau_bo_validate(chan, screen->tls_bo, flags);
 634    nouveau_bo_validate(chan, screen->stack_bo, flags);
 635 }
 636
 637 int
 638 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 639 {
 640    int i = screen->tic.next;
 641
 642    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 643       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 644
 645    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 646
 647    if (screen->tic.entries[i])
 648       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 649
 650    screen->tic.entries[i] = entry;
 651    return i;
 652 }
 653
 654 int
 655 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 656 {
 657    int i = screen->tsc.next;
 658
 659    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 660       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 661
 662    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 663
 664    if (screen->tsc.entries[i])
 665       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 666
 667    screen->tsc.entries[i] = entry;
 668    return i;
 669 }