2 * Copyright 2008 Ben Skeggs
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "pipe/p_screen.h"
25 #include "nv50_context.h"
26 #include "nv50_screen.h"
28 #include "nouveau/nouveau_stateobj.h"
30 #define NV5X_GRCLASS5097_CHIPSETS 0x00000001
31 #define NV8X_GRCLASS8297_CHIPSETS 0x00000050
32 #define NV9X_GRCLASS8297_CHIPSETS 0x00000014
35 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
36 enum pipe_format format
,
37 enum pipe_texture_target target
,
38 unsigned tex_usage
, unsigned geom_flags
)
40 if (tex_usage
& PIPE_TEXTURE_USAGE_RENDER_TARGET
) {
42 case PIPE_FORMAT_A8R8G8B8_UNORM
:
43 case PIPE_FORMAT_R5G6B5_UNORM
:
44 case PIPE_FORMAT_Z24S8_UNORM
:
45 case PIPE_FORMAT_Z16_UNORM
:
52 case PIPE_FORMAT_A8R8G8B8_UNORM
:
53 case PIPE_FORMAT_A1R5G5B5_UNORM
:
54 case PIPE_FORMAT_A4R4G4B4_UNORM
:
55 case PIPE_FORMAT_R5G6B5_UNORM
:
56 case PIPE_FORMAT_L8_UNORM
:
57 case PIPE_FORMAT_A8_UNORM
:
58 case PIPE_FORMAT_I8_UNORM
:
59 case PIPE_FORMAT_A8L8_UNORM
:
70 nv50_screen_get_name(struct pipe_screen
*pscreen
)
72 struct nv50_screen
*screen
= nv50_screen(pscreen
);
73 struct nouveau_device
*dev
= screen
->nvws
->channel
->device
;
74 static char buffer
[128];
76 snprintf(buffer
, sizeof(buffer
), "NV%02X", dev
->chipset
);
81 nv50_screen_get_vendor(struct pipe_screen
*pscreen
)
87 nv50_screen_get_param(struct pipe_screen
*pscreen
, int param
)
90 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
92 case PIPE_CAP_NPOT_TEXTURES
:
94 case PIPE_CAP_TWO_SIDED_STENCIL
:
100 case PIPE_CAP_ANISOTROPIC_FILTER
:
102 case PIPE_CAP_POINT_SPRITE
:
104 case PIPE_CAP_MAX_RENDER_TARGETS
:
106 case PIPE_CAP_OCCLUSION_QUERY
:
108 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
110 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
112 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
114 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
116 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
117 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
119 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
121 case NOUVEAU_CAP_HW_VTXBUF
:
123 case NOUVEAU_CAP_HW_IDXBUF
:
126 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
132 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
135 case PIPE_CAP_MAX_LINE_WIDTH
:
136 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
138 case PIPE_CAP_MAX_POINT_WIDTH
:
139 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
141 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
143 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
146 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
152 nv50_screen_destroy(struct pipe_screen
*pscreen
)
158 nv50_screen_create(struct pipe_winsys
*ws
, struct nouveau_winsys
*nvws
)
160 struct nv50_screen
*screen
= CALLOC_STRUCT(nv50_screen
);
161 struct nouveau_stateobj
*so
;
162 unsigned tesla_class
= 0, ret
;
163 unsigned chipset
= nvws
->channel
->device
->chipset
;
171 if ((chipset
& 0xf0) != 0x50 && (chipset
& 0xf0) != 0x80) {
172 NOUVEAU_ERR("Not a G8x chipset\n");
173 nv50_screen_destroy(&screen
->pipe
);
177 switch (chipset
& 0xf0) {
179 if (NV5X_GRCLASS5097_CHIPSETS
& (1 << (chipset
& 0x0f)))
180 tesla_class
= 0x5097;
183 if (NV8X_GRCLASS8297_CHIPSETS
& (1 << (chipset
& 0x0f)))
184 tesla_class
= 0x8297;
187 if (NV9X_GRCLASS8297_CHIPSETS
& (1 << (chipset
& 0x0f)))
188 tesla_class
= 0x8297;
194 if (tesla_class
== 0) {
195 NOUVEAU_ERR("Unknown G8x chipset: NV%02x\n", chipset
);
196 nv50_screen_destroy(&screen
->pipe
);
200 ret
= nvws
->grobj_alloc(nvws
, tesla_class
, &screen
->tesla
);
202 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
203 nv50_screen_destroy(&screen
->pipe
);
208 ret
= nvws
->notifier_alloc(nvws
, 1, &screen
->sync
);
210 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
211 nv50_screen_destroy(&screen
->pipe
);
215 /* Static tesla init */
216 so
= so_new(256, 20);
218 so_method(so
, screen
->tesla
, 0x1558, 1);
220 so_method(so
, screen
->tesla
, NV50TCL_DMA_NOTIFY
, 1);
221 so_data (so
, screen
->sync
->handle
);
222 so_method(so
, screen
->tesla
, NV50TCL_DMA_UNK0(0),
223 NV50TCL_DMA_UNK0__SIZE
);
224 for (i
= 0; i
< NV50TCL_DMA_UNK0__SIZE
; i
++)
225 so_data(so
, nvws
->channel
->vram
->handle
);
226 so_method(so
, screen
->tesla
, NV50TCL_DMA_UNK1(0),
227 NV50TCL_DMA_UNK1__SIZE
);
228 for (i
= 0; i
< NV50TCL_DMA_UNK1__SIZE
; i
++)
229 so_data(so
, nvws
->channel
->vram
->handle
);
230 so_method(so
, screen
->tesla
, 0x121c, 1);
233 so_method(so
, screen
->tesla
, 0x13bc, 1);
235 so_method(so
, screen
->tesla
, 0x13ac, 1);
237 so_method(so
, screen
->tesla
, 0x16b8, 1);
240 /* Shared constant buffer */
241 screen
->constbuf
= ws
->buffer_create(ws
, 0, 0, 128 * 4 * 4);
242 if (nvws
->res_init(&screen
->vp_data_heap
, 0, 128)) {
243 NOUVEAU_ERR("Error initialising constant buffer\n");
244 nv50_screen_destroy(&screen
->pipe
);
248 so_method(so
, screen
->tesla
, 0x1280, 3);
249 so_reloc (so
, screen
->constbuf
, 0, NOUVEAU_BO_VRAM
|
250 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
251 so_reloc (so
, screen
->constbuf
, 0, NOUVEAU_BO_VRAM
|
252 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
253 so_data (so
, (NV50_CB_PMISC
<< 16) | 0x00001000);
255 /* Texture sampler/image unit setup - we abuse the constant buffer
256 * upload mechanism for the moment to upload data to the tex config
257 * blocks. At some point we *may* want to go the NVIDIA way of doing
260 screen
->tic
= ws
->buffer_create(ws
, 0, 0, 32 * 8 * 4);
261 so_method(so
, screen
->tesla
, 0x1280, 3);
262 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
263 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
264 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
265 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
266 so_data (so
, (NV50_CB_TIC
<< 16) | 0x0800);
267 so_method(so
, screen
->tesla
, 0x1574, 3);
268 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
269 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
270 so_reloc (so
, screen
->tic
, 0, NOUVEAU_BO_VRAM
|
271 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
272 so_data (so
, 0x00000800);
274 screen
->tsc
= ws
->buffer_create(ws
, 0, 0, 32 * 8 * 4);
275 so_method(so
, screen
->tesla
, 0x1280, 3);
276 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
277 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
278 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
279 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
280 so_data (so
, (NV50_CB_TSC
<< 16) | 0x0800);
281 so_method(so
, screen
->tesla
, 0x155c, 3);
282 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
283 NOUVEAU_BO_RD
| NOUVEAU_BO_HIGH
, 0, 0);
284 so_reloc (so
, screen
->tsc
, 0, NOUVEAU_BO_VRAM
|
285 NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
, 0, 0);
286 so_data (so
, 0x00000800);
289 /* Vertex array limits - max them out */
290 for (i
= 0; i
< 16; i
++) {
291 so_method(so
, screen
->tesla
, 0x1080 + (i
* 8), 2);
292 so_data (so
, 0x000000ff);
293 so_data (so
, 0xffffffff);
296 so_method(so
, screen
->tesla
, NV50TCL_DEPTH_RANGE_NEAR
, 2);
297 so_data (so
, fui(0.0));
298 so_data (so
, fui(1.0));
300 so_method(so
, screen
->tesla
, 0x1234, 1);
302 so_method(so
, screen
->tesla
, 0x1458, 1);
306 so_ref(so
, &screen
->static_init
);
307 nvws
->push_flush(nvws
, 0, NULL
);
309 screen
->pipe
.winsys
= ws
;
311 screen
->pipe
.destroy
= nv50_screen_destroy
;
313 screen
->pipe
.get_name
= nv50_screen_get_name
;
314 screen
->pipe
.get_vendor
= nv50_screen_get_vendor
;
315 screen
->pipe
.get_param
= nv50_screen_get_param
;
316 screen
->pipe
.get_paramf
= nv50_screen_get_paramf
;
318 screen
->pipe
.is_format_supported
= nv50_screen_is_format_supported
;
320 nv50_screen_init_miptree_functions(&screen
->pipe
);
321 nv50_surface_init_screen_functions(&screen
->pipe
);
323 return &screen
->pipe
;