src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nv50_context.h"
  27 #include "nv50_screen.h"
  28
  29 #include "nouveau/nv_object.xml.h"
  30
  31 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  32 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  33 #endif
  34
  35 extern int nouveau_device_get_param(struct nouveau_device *dev,
  36                                     uint64_t param, uint64_t *value);
  37
  38 static boolean
  39 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  40                                 enum pipe_format format,
  41                                 enum pipe_texture_target target,
  42                                 unsigned sample_count,
  43                                 unsigned bindings)
  44 {
  45    if (sample_count > 1)
  46       return FALSE;
  47
  48    if (!util_format_s3tc_enabled) {
  49       switch (format) {
  50       case PIPE_FORMAT_DXT1_RGB:
  51       case PIPE_FORMAT_DXT1_RGBA:
  52       case PIPE_FORMAT_DXT3_RGBA:
  53       case PIPE_FORMAT_DXT5_RGBA:
  54          return FALSE;
  55       default:
  56          break;
  57       }
  58    }
  59
  60    switch (format) {
  61    case PIPE_FORMAT_Z16_UNORM:
  62       if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D)
  63          return FALSE;
  64       break;
  65    default:
  66       break;
  67    }
  68
  69    /* transfers & shared are always supported */
  70    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  71                  PIPE_BIND_TRANSFER_WRITE |
  72                  PIPE_BIND_SHARED);
  73
  74    return (nv50_format_table[format].usage & bindings) == bindings;
  75 }
  76
  77 static int
  78 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  79 {
  80    switch (param) {
  81    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  82    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  83       return 32;
  84    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  85       return 64;
  86    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  87       return 13;
  88    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  89       return 10;
  90    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  91       return 13;
  92    case PIPE_CAP_ARRAY_TEXTURES: /* shader support missing */
  93       return 0;
  94    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  95    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  96    case PIPE_CAP_TEXTURE_SWIZZLE:
  97    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  98    case PIPE_CAP_NPOT_TEXTURES:
  99    case PIPE_CAP_ANISOTROPIC_FILTER:
 100       return 1;
 101    case PIPE_CAP_TWO_SIDED_STENCIL:
 102    case PIPE_CAP_DEPTH_CLAMP:
 103    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 104    case PIPE_CAP_POINT_SPRITE:
 105       return 1;
 106    case PIPE_CAP_GLSL:
 107    case PIPE_CAP_SM3:
 108       return 1;
 109    case PIPE_CAP_MAX_RENDER_TARGETS:
 110       return 8;
 111    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 112       return 1;
 113    case PIPE_CAP_TIMER_QUERY:
 114    case PIPE_CAP_OCCLUSION_QUERY:
 115       return 1;
 116    case PIPE_CAP_STREAM_OUTPUT:
 117       return 0;
 118    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 119    case PIPE_CAP_INDEP_BLEND_ENABLE:
 120       return 1;
 121    case PIPE_CAP_INDEP_BLEND_FUNC:
 122       return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D;
 123    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 124    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 125       return 1;
 126    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 127    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 128       return 0;
 129    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 130       return 0;
 131    case PIPE_CAP_PRIMITIVE_RESTART:
 132    case PIPE_CAP_TGSI_INSTANCEID:
 133    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 134    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 135       return 1;
 136    default:
 137       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 138       return 0;
 139    }
 140 }
 141
 142 static int
 143 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 144                              enum pipe_shader_cap param)
 145 {
 146    switch (shader) {
 147    case PIPE_SHADER_VERTEX:
 148    case PIPE_SHADER_GEOMETRY:
 149    case PIPE_SHADER_FRAGMENT:
 150       break;
 151    default:
 152       return 0;
 153    }
 154
 155    switch (param) {
 156    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 157    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 158    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 159    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 160       return 16384;
 161    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 162       return 4;
 163    case PIPE_SHADER_CAP_MAX_INPUTS:
 164       if (shader == PIPE_SHADER_VERTEX)
 165          return 32;
 166       return 0x300 / 16;
 167    case PIPE_SHADER_CAP_MAX_CONSTS:
 168       return 65536 / 16;
 169    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 170       return 14;
 171    case PIPE_SHADER_CAP_MAX_ADDRS:
 172       return 1;
 173    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 174    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 175       return shader != PIPE_SHADER_FRAGMENT;
 176    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 177    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 178       return 1;
 179    case PIPE_SHADER_CAP_MAX_PREDS:
 180       return 0;
 181    case PIPE_SHADER_CAP_MAX_TEMPS:
 182       return NV50_CAP_MAX_PROGRAM_TEMPS;
 183    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 184       return 1;
 185    case PIPE_SHADER_CAP_SUBROUTINES:
 186       return 0; /* please inline, or provide function declarations */
 187    default:
 188       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 189       return 0;
 190    }
 191 }
 192
 193 static float
 194 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 195 {
 196    switch (param) {
 197    case PIPE_CAP_MAX_LINE_WIDTH:
 198    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 199       return 10.0f;
 200    case PIPE_CAP_MAX_POINT_WIDTH:
 201    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 202       return 64.0f;
 203    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 204       return 16.0f;
 205    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 206       return 4.0f;
 207    default:
 208       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 209       return 0.0f;
 210    }
 211 }
 212
 213 static void
 214 nv50_screen_destroy(struct pipe_screen *pscreen)
 215 {
 216    struct nv50_screen *screen = nv50_screen(pscreen);
 217
 218    if (screen->base.fence.current) {
 219       nouveau_fence_wait(screen->base.fence.current);
 220       nouveau_fence_ref (NULL, &screen->base.fence.current);
 221    }
 222
 223    nouveau_bo_ref(NULL, &screen->code);
 224    nouveau_bo_ref(NULL, &screen->tls_bo);
 225    nouveau_bo_ref(NULL, &screen->stack_bo);
 226    nouveau_bo_ref(NULL, &screen->txc);
 227    nouveau_bo_ref(NULL, &screen->uniforms);
 228    nouveau_bo_ref(NULL, &screen->fence.bo);
 229
 230    nouveau_resource_destroy(&screen->vp_code_heap);
 231    nouveau_resource_destroy(&screen->gp_code_heap);
 232    nouveau_resource_destroy(&screen->fp_code_heap);
 233
 234    if (screen->tic.entries)
 235       FREE(screen->tic.entries);
 236
 237    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 238
 239    nouveau_grobj_free(&screen->tesla);
 240    nouveau_grobj_free(&screen->eng2d);
 241    nouveau_grobj_free(&screen->m2mf);
 242
 243    nouveau_notifier_free(&screen->sync);
 244
 245    nouveau_screen_fini(&screen->base);
 246
 247    FREE(screen);
 248 }
 249
 250 static void
 251 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 252 {
 253    struct nv50_screen *screen = nv50_screen(pscreen);
 254    struct nouveau_channel *chan = screen->base.channel;
 255
 256    MARK_RING (chan, 5, 2);
 257    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 258    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 259    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 260    OUT_RING  (chan, sequence);
 261    OUT_RING  (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 262                     NV50_3D_QUERY_GET_UNK4 |
 263                     NV50_3D_QUERY_GET_UNIT_CROP |
 264                     NV50_3D_QUERY_GET_TYPE_QUERY |
 265                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 266                     NV50_3D_QUERY_GET_SHORT);
 267 }
 268
 269 static u32
 270 nv50_screen_fence_update(struct pipe_screen *pscreen)
 271 {
 272    struct nv50_screen *screen = nv50_screen(pscreen);
 273    return screen->fence.map[0];
 274 }
 275
 276 #define FAIL_SCREEN_INIT(str, err)                    \
 277    do {                                               \
 278       NOUVEAU_ERR(str, err);                          \
 279       nv50_screen_destroy(pscreen);                   \
 280       return NULL;                                    \
 281    } while(0)
 282
 283 struct pipe_screen *
 284 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 285 {
 286    struct nv50_screen *screen;
 287    struct nouveau_channel *chan;
 288    struct pipe_screen *pscreen;
 289    uint64_t value;
 290    uint32_t tesla_class;
 291    unsigned stack_size, max_warps, tls_space;
 292    int ret;
 293    unsigned i, base;
 294
 295    screen = CALLOC_STRUCT(nv50_screen);
 296    if (!screen)
 297       return NULL;
 298    pscreen = &screen->base.base;
 299
 300    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 301
 302    ret = nouveau_screen_init(&screen->base, dev);
 303    if (ret)
 304       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 305
 306    chan = screen->base.channel;
 307
 308    pscreen->winsys = ws;
 309    pscreen->destroy = nv50_screen_destroy;
 310    pscreen->context_create = nv50_create;
 311    pscreen->is_format_supported = nv50_screen_is_format_supported;
 312    pscreen->get_param = nv50_screen_get_param;
 313    pscreen->get_shader_param = nv50_screen_get_shader_param;
 314    pscreen->get_paramf = nv50_screen_get_paramf;
 315
 316    nv50_screen_init_resource_functions(pscreen);
 317
 318    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 319                         &screen->fence.bo);
 320    if (ret)
 321       goto fail;
 322    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 323    screen->fence.map = screen->fence.bo->map;
 324    nouveau_bo_unmap(screen->fence.bo);
 325    screen->base.fence.emit = nv50_screen_fence_emit;
 326    screen->base.fence.update = nv50_screen_fence_update;
 327
 328    ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 329    if (ret)
 330       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 331
 332    ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
 333    if (ret)
 334       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 335
 336    BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
 337    BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
 338    OUT_RING  (chan, screen->sync->handle);
 339    OUT_RING  (chan, chan->vram->handle);
 340    OUT_RING  (chan, chan->vram->handle);
 341
 342    ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 343    if (ret)
 344       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 345
 346    BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
 347    BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
 348    OUT_RING  (chan, screen->sync->handle);
 349    OUT_RING  (chan, chan->vram->handle);
 350    OUT_RING  (chan, chan->vram->handle);
 351    OUT_RING  (chan, chan->vram->handle);
 352    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 353    OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 354    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 355    OUT_RING  (chan, 0);
 356    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 357    OUT_RING  (chan, 0);
 358    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 359    OUT_RING  (chan, 1);
 360
 361    switch (dev->chipset & 0xf0) {
 362    case 0x50:
 363       tesla_class = NV50_3D;
 364       break;
 365    case 0x80:
 366    case 0x90:
 367       tesla_class = NV84_3D;
 368       break;
 369    case 0xa0:
 370       switch (dev->chipset) {
 371       case 0xa0:
 372       case 0xaa:
 373       case 0xac:
 374          tesla_class = NVA0_3D;
 375          break;
 376       case 0xaf:
 377          tesla_class = NVAF_3D;
 378          break;
 379       default:
 380          tesla_class = NVA3_3D;
 381          break;
 382       }
 383       break;
 384    default:
 385       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 386       break;
 387    }
 388
 389    ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
 390    if (ret)
 391       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 392
 393    BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
 394
 395    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 396    OUT_RING  (chan, NV50_3D_COND_MODE_ALWAYS);
 397
 398    BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
 399    OUT_RING  (chan, screen->sync->handle);
 400    BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
 401    for (i = 0; i < 11; ++i)
 402       OUT_RING(chan, chan->vram->handle);
 403    BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 404    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 405       OUT_RING(chan, chan->vram->handle);
 406
 407    BEGIN_RING(chan, RING_3D(REG_MODE), 1);
 408    OUT_RING  (chan, NV50_3D_REG_MODE_STRIPED);
 409    BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
 410    OUT_RING  (chan, 0xf);
 411
 412    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 413    OUT_RING  (chan, 1);
 414
 415    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 416    OUT_RING  (chan, 0);
 417    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 418    OUT_RING  (chan, 0);
 419    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 420    OUT_RING  (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
 421    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 422    OUT_RING  (chan, 0);
 423    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 424    OUT_RING  (chan, 0);
 425
 426    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 427    OUT_RING  (chan, 0);
 428    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 429    OUT_RING  (chan, 0);
 430    OUT_RING  (chan, 0);
 431    BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 432    OUT_RING  (chan, 0x3f);
 433
 434    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 435                         3 << NV50_CODE_BO_SIZE_LOG2, &screen->code);
 436    if (ret)
 437       goto fail;
 438
 439    nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 440    nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 441    nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 442
 443    base = 1 << NV50_CODE_BO_SIZE_LOG2;
 444
 445    BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
 446    OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 447    OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 448
 449    BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
 450    OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 451    OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 452
 453    BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
 454    OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 455    OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 456
 457    nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 458
 459    max_warps  = util_bitcount(value & 0xffff);
 460    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 461
 462    stack_size = max_warps * 64 * 8;
 463
 464    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
 465                         &screen->stack_bo);
 466    if (ret)
 467       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 468
 469    BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
 470    OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 471    OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 472    OUT_RING  (chan, 4);
 473
 474    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 475
 476    screen->tls_size = tls_space * max_warps * 32;
 477
 478    debug_printf("max_warps = %i, tls_size = %lu KiB\n",
 479                 max_warps, screen->tls_size >> 10);
 480
 481    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
 482                         &screen->tls_bo);
 483    if (ret)
 484       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 485
 486    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
 487    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 488    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 489    OUT_RING  (chan, util_unsigned_logbase2(tls_space / 8));
 490
 491    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
 492                         &screen->uniforms);
 493    if (ret)
 494       goto fail;
 495
 496    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 497    OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 498    OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 499    OUT_RING  (chan, (NV50_CB_PVP << 16) | 0x0000);
 500
 501    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 502    OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 503    OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 504    OUT_RING  (chan, (NV50_CB_PGP << 16) | 0x0000);
 505
 506    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 507    OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 508    OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 509    OUT_RING  (chan, (NV50_CB_PFP << 16) | 0x0000);
 510
 511    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 512    OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 513    OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 514    OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 515
 516    BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
 517    OUT_RING  (chan, (NV50_CB_PVP << 12) | 0x001);
 518    OUT_RING  (chan, (NV50_CB_PGP << 12) | 0x021);
 519    OUT_RING  (chan, (NV50_CB_PFP << 12) | 0x031);
 520    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf01);
 521    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf21);
 522    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf31);
 523
 524    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
 525                         &screen->txc);
 526    if (ret)
 527       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 528
 529    /* max TIC (bits 4:8) & TSC bindings, per program type */
 530    for (i = 0; i < 3; ++i) {
 531       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 532       OUT_RING  (chan, 0x54);
 533    }
 534
 535    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 536    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 537    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 538    OUT_RING  (chan, NV50_TIC_MAX_ENTRIES - 1);
 539
 540    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 541    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 542    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 543    OUT_RING  (chan, NV50_TSC_MAX_ENTRIES - 1);
 544
 545    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 546    OUT_RING  (chan, 0);
 547
 548    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 549    OUT_RING  (chan, 0);
 550    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 551    OUT_RING  (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 552    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 553    for (i = 0; i < 8 * 2; ++i)
 554       OUT_RING(chan, 0);
 555    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 556    OUT_RING  (chan, 0);
 557
 558    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 559    OUT_RING  (chan, 1);
 560    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 561    OUT_RINGf (chan, 0.0f);
 562    OUT_RINGf (chan, 1.0f);
 563
 564    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 565 #ifdef NV50_SCISSORS_CLIPPING
 566    OUT_RING  (chan, 0x0000);
 567 #else
 568    OUT_RING  (chan, 0x1080);
 569 #endif
 570
 571    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 572    OUT_RING  (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 573
 574    /* We use scissors instead of exact view volume clipping,
 575     * so they're always enabled.
 576     */
 577    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 578    OUT_RING  (chan, 1);
 579    OUT_RING  (chan, 8192 << 16);
 580    OUT_RING  (chan, 8192 << 16);
 581
 582    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 583    OUT_RING  (chan, 1);
 584    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 585    OUT_RING  (chan, NV50_3D_POINT_RASTER_RULES_OGL);
 586    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 587    OUT_RING  (chan, 0x11111111);
 588    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 589    OUT_RING  (chan, 1);
 590
 591    FIRE_RING (chan);
 592
 593    screen->tic.entries = CALLOC(4096, sizeof(void *));
 594    screen->tsc.entries = screen->tic.entries + 2048;
 595
 596    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 597
 598    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 599
 600    return pscreen;
 601
 602 fail:
 603    nv50_screen_destroy(pscreen);
 604    return NULL;
 605 }
 606
 607 void
 608 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
 609 {
 610    struct nouveau_channel *chan = screen->base.channel;
 611
 612    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 613
 614    MARK_RING(chan, 5, 5);
 615    nouveau_bo_validate(chan, screen->code, flags);
 616    nouveau_bo_validate(chan, screen->uniforms, flags);
 617    nouveau_bo_validate(chan, screen->txc, flags);
 618    nouveau_bo_validate(chan, screen->tls_bo, flags);
 619    nouveau_bo_validate(chan, screen->stack_bo, flags);
 620 }
 621
 622 int
 623 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 624 {
 625    int i = screen->tic.next;
 626
 627    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 628       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 629
 630    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 631
 632    if (screen->tic.entries[i])
 633       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 634
 635    screen->tic.entries[i] = entry;
 636    return i;
 637 }
 638
 639 int
 640 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 641 {
 642    int i = screen->tsc.next;
 643
 644    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 645       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 646
 647    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 648
 649    if (screen->tsc.entries[i])
 650       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 651
 652    screen->tsc.entries[i] = entry;
 653    return i;
 654 }