src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 static boolean
  37 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  38                                 enum pipe_format format,
  39                                 enum pipe_texture_target target,
  40                                 unsigned sample_count,
  41                                 unsigned bindings)
  42 {
  43    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  44       return FALSE;
  45    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  46       return FALSE;
  47
  48    if (!util_format_is_supported(format, bindings))
  49       return FALSE;
  50
  51    switch (format) {
  52    case PIPE_FORMAT_Z16_UNORM:
  53       if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
  54          return FALSE;
  55       break;
  56    case PIPE_FORMAT_R8G8B8A8_UNORM:
  57    case PIPE_FORMAT_R8G8B8X8_UNORM:
  58       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  59       if (bindings & PIPE_BIND_RENDER_TARGET)
  60          return FALSE;
  61    default:
  62       break;
  63    }
  64
  65    /* transfers & shared are always supported */
  66    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  67                  PIPE_BIND_TRANSFER_WRITE |
  68                  PIPE_BIND_SHARED);
  69
  70    return (nv50_format_table[format].usage & bindings) == bindings;
  71 }
  72
  73 static int
  74 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  75 {
  76    switch (param) {
  77    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  78       return 64;
  79    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  80       return 14;
  81    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  82       return 12;
  83    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  84       return 14;
  85    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* shader support missing */
  86       return 0;
  87    case PIPE_CAP_MIN_TEXEL_OFFSET:
  88       return -8;
  89    case PIPE_CAP_MAX_TEXEL_OFFSET:
  90       return 7;
  91    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  92    case PIPE_CAP_TEXTURE_SWIZZLE:
  93    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  94    case PIPE_CAP_NPOT_TEXTURES:
  95    case PIPE_CAP_ANISOTROPIC_FILTER:
  96    case PIPE_CAP_SCALED_RESOLVE:
  97       return 1;
  98    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
  99    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 100       return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
 101    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 102       return 0;
 103    case PIPE_CAP_TWO_SIDED_STENCIL:
 104    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 105    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 106    case PIPE_CAP_POINT_SPRITE:
 107       return 1;
 108    case PIPE_CAP_SM3:
 109       return 1;
 110    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 111       return 130;
 112    case PIPE_CAP_MAX_RENDER_TARGETS:
 113       return 8;
 114    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 115       return 1;
 116    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 117    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 118    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 119       return 1;
 120    case PIPE_CAP_TIMER_QUERY:
 121    case PIPE_CAP_OCCLUSION_QUERY:
 122       return 1;
 123    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 124       return 0;
 125    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 126       return 128;
 127    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 128       return 32;
 129    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 130    case PIPE_CAP_INDEP_BLEND_ENABLE:
 131       return 1;
 132    case PIPE_CAP_INDEP_BLEND_FUNC:
 133       return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
 134    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 135    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 136       return 1;
 137    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 138    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 139       return 0;
 140    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 141       return 0;
 142    case PIPE_CAP_PRIMITIVE_RESTART:
 143    case PIPE_CAP_TGSI_INSTANCEID:
 144    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 145    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 146    case PIPE_CAP_CONDITIONAL_RENDER:
 147    case PIPE_CAP_TEXTURE_BARRIER:
 148    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 149       return 1;
 150    case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 151    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 152       return 0; /* state trackers will know better */
 153    case PIPE_CAP_USER_VERTEX_BUFFERS:
 154       return 1;
 155    default:
 156       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 157       return 0;
 158    }
 159 }
 160
 161 static int
 162 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 163                              enum pipe_shader_cap param)
 164 {
 165    switch (shader) {
 166    case PIPE_SHADER_VERTEX:
 167    case PIPE_SHADER_GEOMETRY:
 168    case PIPE_SHADER_FRAGMENT:
 169       break;
 170    default:
 171       return 0;
 172    }
 173
 174    switch (param) {
 175    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 176    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 177    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 178    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 179       return 16384;
 180    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 181       return 4;
 182    case PIPE_SHADER_CAP_MAX_INPUTS:
 183       if (shader == PIPE_SHADER_VERTEX)
 184          return 32;
 185       return 0x300 / 16;
 186    case PIPE_SHADER_CAP_MAX_CONSTS:
 187       return 65536 / 16;
 188    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 189       return 14;
 190    case PIPE_SHADER_CAP_MAX_ADDRS:
 191       return 1;
 192    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 193    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 194       return shader != PIPE_SHADER_FRAGMENT;
 195    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 196    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 197       return 1;
 198    case PIPE_SHADER_CAP_MAX_PREDS:
 199       return 0;
 200    case PIPE_SHADER_CAP_MAX_TEMPS:
 201       return NV50_CAP_MAX_PROGRAM_TEMPS;
 202    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 203       return 1;
 204    case PIPE_SHADER_CAP_SUBROUTINES:
 205       return 0; /* please inline, or provide function declarations */
 206    case PIPE_SHADER_CAP_INTEGERS:
 207       return 1;
 208    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 209       return 32;
 210    default:
 211       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 212       return 0;
 213    }
 214 }
 215
 216 static float
 217 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 218 {
 219    switch (param) {
 220    case PIPE_CAPF_MAX_LINE_WIDTH:
 221    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 222       return 10.0f;
 223    case PIPE_CAPF_MAX_POINT_WIDTH:
 224    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 225       return 64.0f;
 226    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 227       return 16.0f;
 228    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 229       return 4.0f;
 230    default:
 231       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 232       return 0.0f;
 233    }
 234 }
 235
 236 static void
 237 nv50_screen_destroy(struct pipe_screen *pscreen)
 238 {
 239    struct nv50_screen *screen = nv50_screen(pscreen);
 240
 241    if (screen->base.fence.current) {
 242       nouveau_fence_wait(screen->base.fence.current);
 243       nouveau_fence_ref (NULL, &screen->base.fence.current);
 244    }
 245    if (screen->base.pushbuf)
 246       screen->base.pushbuf->user_priv = NULL;
 247
 248    if (screen->blitctx)
 249       FREE(screen->blitctx);
 250
 251    nouveau_bo_ref(NULL, &screen->code);
 252    nouveau_bo_ref(NULL, &screen->tls_bo);
 253    nouveau_bo_ref(NULL, &screen->stack_bo);
 254    nouveau_bo_ref(NULL, &screen->txc);
 255    nouveau_bo_ref(NULL, &screen->uniforms);
 256    nouveau_bo_ref(NULL, &screen->fence.bo);
 257
 258    nouveau_heap_destroy(&screen->vp_code_heap);
 259    nouveau_heap_destroy(&screen->gp_code_heap);
 260    nouveau_heap_destroy(&screen->fp_code_heap);
 261
 262    if (screen->tic.entries)
 263       FREE(screen->tic.entries);
 264
 265    nouveau_object_del(&screen->tesla);
 266    nouveau_object_del(&screen->eng2d);
 267    nouveau_object_del(&screen->m2mf);
 268    nouveau_object_del(&screen->sync);
 269
 270    nouveau_screen_fini(&screen->base);
 271
 272    FREE(screen);
 273 }
 274
 275 static void
 276 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
 277 {
 278    struct nv50_screen *screen = nv50_screen(pscreen);
 279    struct nouveau_pushbuf *push = screen->base.pushbuf;
 280
 281    /* we need to do it after possible flush in MARK_RING */
 282    *sequence = ++screen->base.fence.sequence;
 283
 284    PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
 285    PUSH_DATAh(push, screen->fence.bo->offset);
 286    PUSH_DATA (push, screen->fence.bo->offset);
 287    PUSH_DATA (push, *sequence);
 288    PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 289                     NV50_3D_QUERY_GET_UNK4 |
 290                     NV50_3D_QUERY_GET_UNIT_CROP |
 291                     NV50_3D_QUERY_GET_TYPE_QUERY |
 292                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 293                     NV50_3D_QUERY_GET_SHORT);
 294 }
 295
 296 static u32
 297 nv50_screen_fence_update(struct pipe_screen *pscreen)
 298 {
 299    return nv50_screen(pscreen)->fence.map[0];
 300 }
 301
 302 static int
 303 nv50_screen_init_hwctx(struct nv50_screen *screen, unsigned tls_space)
 304 {
 305    struct nouveau_pushbuf *push = screen->base.pushbuf;
 306    struct nv04_fifo *fifo;
 307    unsigned i;
 308
 309    fifo = (struct nv04_fifo *)screen->base.channel->data;
 310
 311    BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
 312    PUSH_DATA (push, screen->m2mf->handle);
 313    BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
 314    PUSH_DATA (push, screen->sync->handle);
 315    PUSH_DATA (push, fifo->vram);
 316    PUSH_DATA (push, fifo->vram);
 317
 318    BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
 319    PUSH_DATA (push, screen->eng2d->handle);
 320    BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
 321    PUSH_DATA (push, screen->sync->handle);
 322    PUSH_DATA (push, fifo->vram);
 323    PUSH_DATA (push, fifo->vram);
 324    PUSH_DATA (push, fifo->vram);
 325    BEGIN_NV04(push, NV50_2D(OPERATION), 1);
 326    PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
 327    BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
 328    PUSH_DATA (push, 0);
 329    BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
 330    PUSH_DATA (push, 0);
 331    BEGIN_NV04(push, SUBC_2D(0x0888), 1);
 332    PUSH_DATA (push, 1);
 333
 334    BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
 335    PUSH_DATA (push, screen->tesla->handle);
 336
 337    BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
 338    PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
 339
 340    BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
 341    PUSH_DATA (push, screen->sync->handle);
 342    BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
 343    for (i = 0; i < 11; ++i)
 344       PUSH_DATA(push, fifo->vram);
 345    BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 346    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 347       PUSH_DATA(push, fifo->vram);
 348
 349    BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
 350    PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
 351    BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
 352    PUSH_DATA (push, 0xf);
 353
 354    BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
 355    PUSH_DATA (push, 1);
 356
 357    BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
 358    PUSH_DATA (push, 0);
 359    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
 360    PUSH_DATA (push, 0);
 361    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
 362    PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
 363    BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
 364    PUSH_DATA (push, 0);
 365    BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1);
 366    PUSH_DATA (push, 0);
 367    BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
 368    PUSH_DATA (push, 1);
 369
 370    if (screen->tesla->oclass >= NVA0_3D_CLASS) {
 371       BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
 372       PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 373    }
 374
 375    BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
 376    PUSH_DATA (push, 0);
 377    BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
 378    PUSH_DATA (push, 0);
 379    PUSH_DATA (push, 0);
 380    BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
 381    PUSH_DATA (push, 0x3f);
 382
 383    BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
 384    PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 385    PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
 386
 387    BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
 388    PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 389    PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
 390
 391    BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
 392    PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 393    PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
 394
 395    BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
 396    PUSH_DATAh(push, screen->tls_bo->offset);
 397    PUSH_DATA (push, screen->tls_bo->offset);
 398    PUSH_DATA (push, util_logbase2(tls_space / 8));
 399
 400    BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
 401    PUSH_DATAh(push, screen->stack_bo->offset);
 402    PUSH_DATA (push, screen->stack_bo->offset);
 403    PUSH_DATA (push, 4);
 404
 405    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 406    PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
 407    PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
 408    PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
 409
 410    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 411    PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
 412    PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
 413    PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
 414
 415    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 416    PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
 417    PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
 418    PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
 419
 420    BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
 421    PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
 422    PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
 423    PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
 424
 425    BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 6);
 426    PUSH_DATA (push, (NV50_CB_PVP << 12) | 0x001);
 427    PUSH_DATA (push, (NV50_CB_PGP << 12) | 0x021);
 428    PUSH_DATA (push, (NV50_CB_PFP << 12) | 0x031);
 429    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
 430    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
 431    PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
 432
 433    /* max TIC (bits 4:8) & TSC bindings, per program type */
 434    for (i = 0; i < 3; ++i) {
 435       BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
 436       PUSH_DATA (push, 0x54);
 437    }
 438
 439    BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
 440    PUSH_DATAh(push, screen->txc->offset);
 441    PUSH_DATA (push, screen->txc->offset);
 442    PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
 443
 444    BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
 445    PUSH_DATAh(push, screen->txc->offset + 65536);
 446    PUSH_DATA (push, screen->txc->offset + 65536);
 447    PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
 448
 449    BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
 450    PUSH_DATA (push, 0);
 451
 452    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
 453    PUSH_DATA (push, 0);
 454    BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
 455    PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 456    BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 457    for (i = 0; i < 8 * 2; ++i)
 458       PUSH_DATA(push, 0);
 459    BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
 460    PUSH_DATA (push, 0);
 461
 462    BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
 463    PUSH_DATA (push, 1);
 464    BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
 465    PUSH_DATAf(push, 0.0f);
 466    PUSH_DATAf(push, 1.0f);
 467
 468    BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 469 #ifdef NV50_SCISSORS_CLIPPING
 470    PUSH_DATA (push, 0x0000);
 471 #else
 472    PUSH_DATA (push, 0x1080);
 473 #endif
 474
 475    BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
 476    PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 477
 478    /* We use scissors instead of exact view volume clipping,
 479     * so they're always enabled.
 480     */
 481    BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
 482    PUSH_DATA (push, 1);
 483    PUSH_DATA (push, 8192 << 16);
 484    PUSH_DATA (push, 8192 << 16);
 485
 486    BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
 487    PUSH_DATA (push, 1);
 488    BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
 489    PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
 490    BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
 491    PUSH_DATA (push, 0x11111111);
 492    BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
 493    PUSH_DATA (push, 1);
 494
 495    PUSH_KICK (push);
 496
 497    return 0;
 498 }
 499
 500 #define FAIL_SCREEN_INIT(str, err)                    \
 501    do {                                               \
 502       NOUVEAU_ERR(str, err);                          \
 503       nv50_screen_destroy(pscreen);                   \
 504       return NULL;                                    \
 505    } while(0)
 506
 507 struct pipe_screen *
 508 nv50_screen_create(struct nouveau_device *dev)
 509 {
 510    struct nv50_screen *screen;
 511    struct pipe_screen *pscreen;
 512    struct nouveau_object *chan;
 513    uint64_t value;
 514    uint32_t tesla_class;
 515    unsigned stack_size, max_warps, tls_space;
 516    int ret;
 517
 518    screen = CALLOC_STRUCT(nv50_screen);
 519    if (!screen)
 520       return NULL;
 521    pscreen = &screen->base.base;
 522
 523    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 524
 525    ret = nouveau_screen_init(&screen->base, dev);
 526    if (ret)
 527       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 528
 529    screen->base.pushbuf->user_priv = screen;
 530    screen->base.pushbuf->rsvd_kick = 5;
 531
 532    chan = screen->base.channel;
 533
 534    pscreen->destroy = nv50_screen_destroy;
 535    pscreen->context_create = nv50_create;
 536    pscreen->is_format_supported = nv50_screen_is_format_supported;
 537    pscreen->get_param = nv50_screen_get_param;
 538    pscreen->get_shader_param = nv50_screen_get_shader_param;
 539    pscreen->get_paramf = nv50_screen_get_paramf;
 540
 541    nv50_screen_init_resource_functions(pscreen);
 542
 543    nouveau_screen_init_vdec(&screen->base);
 544
 545    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 546                         NULL, &screen->fence.bo);
 547    if (ret)
 548       goto fail;
 549    nouveau_bo_map(screen->fence.bo, 0, NULL);
 550    screen->fence.map = screen->fence.bo->map;
 551    screen->base.fence.emit = nv50_screen_fence_emit;
 552    screen->base.fence.update = nv50_screen_fence_update;
 553
 554    ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
 555                             &(struct nv04_notify){ .length = 32 },
 556                             sizeof(struct nv04_notify), &screen->sync);
 557    if (ret)
 558       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 559
 560
 561    ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
 562                             NULL, 0, &screen->m2mf);
 563    if (ret)
 564       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 565
 566
 567    ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
 568                             NULL, 0, &screen->eng2d);
 569    if (ret)
 570       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 571
 572    switch (dev->chipset & 0xf0) {
 573    case 0x50:
 574       tesla_class = NV50_3D_CLASS;
 575       break;
 576    case 0x80:
 577    case 0x90:
 578       tesla_class = NV84_3D_CLASS;
 579       break;
 580    case 0xa0:
 581       switch (dev->chipset) {
 582       case 0xa0:
 583       case 0xaa:
 584       case 0xac:
 585          tesla_class = NVA0_3D_CLASS;
 586          break;
 587       case 0xaf:
 588          tesla_class = NVAF_3D_CLASS;
 589          break;
 590       default:
 591          tesla_class = NVA3_3D_CLASS;
 592          break;
 593       }
 594       break;
 595    default:
 596       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 597       break;
 598    }
 599    screen->base.class_3d = tesla_class;
 600
 601    ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
 602                             NULL, 0, &screen->tesla);
 603    if (ret)
 604       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 605
 606
 607    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 608                         3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
 609    if (ret)
 610       goto fail;
 611
 612    nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 613    nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 614    nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 615
 616    nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 617
 618    max_warps  = util_bitcount(value & 0xffff);
 619    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 620
 621    stack_size = max_warps * 64 * 8;
 622
 623    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
 624                         &screen->stack_bo);
 625    if (ret)
 626       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 627
 628    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 629
 630    screen->tls_size = tls_space * max_warps * 32;
 631
 632    if (nouveau_mesa_debug)
 633       debug_printf("max_warps = %i, tls_size = %"PRIu64" KiB\n",
 634                      max_warps, screen->tls_size >> 10);
 635
 636    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size, NULL,
 637                         &screen->tls_bo);
 638    if (ret)
 639       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 640
 641
 642    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL,
 643                         &screen->uniforms);
 644    if (ret)
 645       goto fail;
 646
 647    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
 648                         &screen->txc);
 649    if (ret)
 650       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 651
 652    screen->tic.entries = CALLOC(4096, sizeof(void *));
 653    screen->tsc.entries = screen->tic.entries + 2048;
 654
 655
 656    if (!nv50_blitctx_create(screen))
 657       goto fail;
 658
 659    if (nv50_screen_init_hwctx(screen, tls_space))
 660       goto fail;
 661
 662    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 663
 664    return pscreen;
 665
 666 fail:
 667    nv50_screen_destroy(pscreen);
 668    return NULL;
 669 }
 670
 671 int
 672 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 673 {
 674    int i = screen->tic.next;
 675
 676    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 677       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 678
 679    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 680
 681    if (screen->tic.entries[i])
 682       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 683
 684    screen->tic.entries[i] = entry;
 685    return i;
 686 }
 687
 688 int
 689 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 690 {
 691    int i = screen->tsc.next;
 692
 693    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 694       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 695
 696    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 697
 698    if (screen->tsc.entries[i])
 699       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 700
 701    screen->tsc.entries[i] = entry;
 702    return i;
 703 }