src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format.h"
  24 #include "util/u_format_s3tc.h"
  25 #include "pipe/p_screen.h"
  26
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 extern int nouveau_device_get_param(struct nouveau_device *dev,
  37                                     uint64_t param, uint64_t *value);
  38
  39 static boolean
  40 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings)
  45 {
  46    if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
  47       return FALSE;
  48    if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
  49       return FALSE;
  50
  51    if (!util_format_is_supported(format, bindings))
  52       return FALSE;
  53
  54    switch (format) {
  55    case PIPE_FORMAT_Z16_UNORM:
  56       if (nv50_screen(pscreen)->tesla->grclass < NVA0_3D)
  57          return FALSE;
  58       break;
  59    case PIPE_FORMAT_R8G8B8A8_UNORM:
  60    case PIPE_FORMAT_R8G8B8X8_UNORM:
  61       /* HACK: GL requires equal formats for MS resolve and window is BGRA */
  62       if (sample_count > 1)
  63          return FALSE;
  64    default:
  65       break;
  66    }
  67
  68    /* transfers & shared are always supported */
  69    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  70                  PIPE_BIND_TRANSFER_WRITE |
  71                  PIPE_BIND_SHARED);
  72
  73    return (nv50_format_table[format].usage & bindings) == bindings;
  74 }
  75
  76 static int
  77 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  78 {
  79    switch (param) {
  80    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  81    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  82       return 32;
  83    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  84       return 64;
  85    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  86       return 13;
  87    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  88       return 10;
  89    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  90       return 13;
  91    case PIPE_CAP_ARRAY_TEXTURES: /* shader support missing */
  92       return 0;
  93    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  94    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  95    case PIPE_CAP_TEXTURE_SWIZZLE:
  96    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  97    case PIPE_CAP_NPOT_TEXTURES:
  98    case PIPE_CAP_ANISOTROPIC_FILTER:
  99    case PIPE_CAP_SCALED_RESOLVE:
 100       return 1;
 101    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 102       return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
 103    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 104       return 0;
 105    case PIPE_CAP_TWO_SIDED_STENCIL:
 106    case PIPE_CAP_DEPTH_CLAMP:
 107    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 108    case PIPE_CAP_POINT_SPRITE:
 109       return 1;
 110    case PIPE_CAP_GLSL:
 111    case PIPE_CAP_SM3:
 112       return 1;
 113    case PIPE_CAP_MAX_RENDER_TARGETS:
 114       return 8;
 115    case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
 116       return 1;
 117    case PIPE_CAP_TIMER_QUERY:
 118    case PIPE_CAP_OCCLUSION_QUERY:
 119       return 1;
 120    case PIPE_CAP_STREAM_OUTPUT:
 121       return 0;
 122    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 123    case PIPE_CAP_INDEP_BLEND_ENABLE:
 124       return 1;
 125    case PIPE_CAP_INDEP_BLEND_FUNC:
 126       return nv50_screen(pscreen)->tesla->grclass >= NVA3_3D;
 127    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 128    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 129       return 1;
 130    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 131    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 132       return 0;
 133    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 134       return 0;
 135    case PIPE_CAP_PRIMITIVE_RESTART:
 136    case PIPE_CAP_TGSI_INSTANCEID:
 137    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 138    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 139       return 1;
 140    default:
 141       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 142       return 0;
 143    }
 144 }
 145
 146 static int
 147 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 148                              enum pipe_shader_cap param)
 149 {
 150    switch (shader) {
 151    case PIPE_SHADER_VERTEX:
 152    case PIPE_SHADER_GEOMETRY:
 153    case PIPE_SHADER_FRAGMENT:
 154       break;
 155    default:
 156       return 0;
 157    }
 158
 159    switch (param) {
 160    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 161    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 162    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 163    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 164       return 16384;
 165    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 166       return 4;
 167    case PIPE_SHADER_CAP_MAX_INPUTS:
 168       if (shader == PIPE_SHADER_VERTEX)
 169          return 32;
 170       return 0x300 / 16;
 171    case PIPE_SHADER_CAP_MAX_CONSTS:
 172       return 65536 / 16;
 173    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 174       return 14;
 175    case PIPE_SHADER_CAP_MAX_ADDRS:
 176       return 1;
 177    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 178    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 179       return shader != PIPE_SHADER_FRAGMENT;
 180    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 181    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 182       return 1;
 183    case PIPE_SHADER_CAP_MAX_PREDS:
 184       return 0;
 185    case PIPE_SHADER_CAP_MAX_TEMPS:
 186       return NV50_CAP_MAX_PROGRAM_TEMPS;
 187    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 188       return 1;
 189    case PIPE_SHADER_CAP_SUBROUTINES:
 190       return 0; /* please inline, or provide function declarations */
 191    case PIPE_SHADER_CAP_INTEGERS:
 192       return 0;
 193    default:
 194       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 195       return 0;
 196    }
 197 }
 198
 199 static float
 200 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 201 {
 202    switch (param) {
 203    case PIPE_CAP_MAX_LINE_WIDTH:
 204    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 205       return 10.0f;
 206    case PIPE_CAP_MAX_POINT_WIDTH:
 207    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 208       return 64.0f;
 209    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 210       return 16.0f;
 211    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 212       return 4.0f;
 213    default:
 214       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 215       return 0.0f;
 216    }
 217 }
 218
 219 static void
 220 nv50_screen_destroy(struct pipe_screen *pscreen)
 221 {
 222    struct nv50_screen *screen = nv50_screen(pscreen);
 223
 224    if (screen->base.fence.current) {
 225       nouveau_fence_wait(screen->base.fence.current);
 226       nouveau_fence_ref (NULL, &screen->base.fence.current);
 227    }
 228    screen->base.channel->user_private = NULL;
 229
 230    nouveau_bo_ref(NULL, &screen->code);
 231    nouveau_bo_ref(NULL, &screen->tls_bo);
 232    nouveau_bo_ref(NULL, &screen->stack_bo);
 233    nouveau_bo_ref(NULL, &screen->txc);
 234    nouveau_bo_ref(NULL, &screen->uniforms);
 235    nouveau_bo_ref(NULL, &screen->fence.bo);
 236
 237    nouveau_resource_destroy(&screen->vp_code_heap);
 238    nouveau_resource_destroy(&screen->gp_code_heap);
 239    nouveau_resource_destroy(&screen->fp_code_heap);
 240
 241    if (screen->tic.entries)
 242       FREE(screen->tic.entries);
 243
 244    nouveau_mm_destroy(screen->mm_VRAM_fe0);
 245
 246    nouveau_grobj_free(&screen->tesla);
 247    nouveau_grobj_free(&screen->eng2d);
 248    nouveau_grobj_free(&screen->m2mf);
 249
 250    nouveau_notifier_free(&screen->sync);
 251
 252    nouveau_screen_fini(&screen->base);
 253
 254    FREE(screen);
 255 }
 256
 257 static void
 258 nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 sequence)
 259 {
 260    struct nv50_screen *screen = nv50_screen(pscreen);
 261    struct nouveau_channel *chan = screen->base.channel;
 262
 263    MARK_RING (chan, 5, 2);
 264    BEGIN_RING(chan, RING_3D(QUERY_ADDRESS_HIGH), 4);
 265    OUT_RELOCh(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 266    OUT_RELOCl(chan, screen->fence.bo, 0, NOUVEAU_BO_WR);
 267    OUT_RING  (chan, sequence);
 268    OUT_RING  (chan, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
 269                     NV50_3D_QUERY_GET_UNK4 |
 270                     NV50_3D_QUERY_GET_UNIT_CROP |
 271                     NV50_3D_QUERY_GET_TYPE_QUERY |
 272                     NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
 273                     NV50_3D_QUERY_GET_SHORT);
 274 }
 275
 276 static u32
 277 nv50_screen_fence_update(struct pipe_screen *pscreen)
 278 {
 279    struct nv50_screen *screen = nv50_screen(pscreen);
 280    return screen->fence.map[0];
 281 }
 282
 283 #define FAIL_SCREEN_INIT(str, err)                    \
 284    do {                                               \
 285       NOUVEAU_ERR(str, err);                          \
 286       nv50_screen_destroy(pscreen);                   \
 287       return NULL;                                    \
 288    } while(0)
 289
 290 struct pipe_screen *
 291 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 292 {
 293    struct nv50_screen *screen;
 294    struct nouveau_channel *chan;
 295    struct pipe_screen *pscreen;
 296    uint64_t value;
 297    uint32_t tesla_class;
 298    unsigned stack_size, max_warps, tls_space;
 299    int ret;
 300    unsigned i, base;
 301
 302    screen = CALLOC_STRUCT(nv50_screen);
 303    if (!screen)
 304       return NULL;
 305    pscreen = &screen->base.base;
 306
 307    screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
 308
 309    ret = nouveau_screen_init(&screen->base, dev);
 310    if (ret)
 311       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 312
 313    chan = screen->base.channel;
 314    chan->user_private = screen;
 315
 316    pscreen->winsys = ws;
 317    pscreen->destroy = nv50_screen_destroy;
 318    pscreen->context_create = nv50_create;
 319    pscreen->is_format_supported = nv50_screen_is_format_supported;
 320    pscreen->get_param = nv50_screen_get_param;
 321    pscreen->get_shader_param = nv50_screen_get_shader_param;
 322    pscreen->get_paramf = nv50_screen_get_paramf;
 323
 324    nv50_screen_init_resource_functions(pscreen);
 325
 326    nouveau_screen_init_vdec(&screen->base);
 327
 328    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 329                         &screen->fence.bo);
 330    if (ret)
 331       goto fail;
 332    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 333    screen->fence.map = screen->fence.bo->map;
 334    nouveau_bo_unmap(screen->fence.bo);
 335    screen->base.fence.emit = nv50_screen_fence_emit;
 336    screen->base.fence.update = nv50_screen_fence_update;
 337
 338    ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 339    if (ret)
 340       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 341
 342    ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
 343    if (ret)
 344       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 345
 346    BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
 347    BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
 348    OUT_RING  (chan, screen->sync->handle);
 349    OUT_RING  (chan, chan->vram->handle);
 350    OUT_RING  (chan, chan->vram->handle);
 351
 352    ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 353    if (ret)
 354       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 355
 356    BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
 357    BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
 358    OUT_RING  (chan, screen->sync->handle);
 359    OUT_RING  (chan, chan->vram->handle);
 360    OUT_RING  (chan, chan->vram->handle);
 361    OUT_RING  (chan, chan->vram->handle);
 362    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 363    OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 364    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 365    OUT_RING  (chan, 0);
 366    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 367    OUT_RING  (chan, 0);
 368    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 369    OUT_RING  (chan, 1);
 370
 371    switch (dev->chipset & 0xf0) {
 372    case 0x50:
 373       tesla_class = NV50_3D;
 374       break;
 375    case 0x80:
 376    case 0x90:
 377       tesla_class = NV84_3D;
 378       break;
 379    case 0xa0:
 380       switch (dev->chipset) {
 381       case 0xa0:
 382       case 0xaa:
 383       case 0xac:
 384          tesla_class = NVA0_3D;
 385          break;
 386       case 0xaf:
 387          tesla_class = NVAF_3D;
 388          break;
 389       default:
 390          tesla_class = NVA3_3D;
 391          break;
 392       }
 393       break;
 394    default:
 395       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 396       break;
 397    }
 398
 399    ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
 400    if (ret)
 401       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 402
 403    BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
 404
 405    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 406    OUT_RING  (chan, NV50_3D_COND_MODE_ALWAYS);
 407
 408    BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
 409    OUT_RING  (chan, screen->sync->handle);
 410    BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
 411    for (i = 0; i < 11; ++i)
 412       OUT_RING(chan, chan->vram->handle);
 413    BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 414    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 415       OUT_RING(chan, chan->vram->handle);
 416
 417    BEGIN_RING(chan, RING_3D(REG_MODE), 1);
 418    OUT_RING  (chan, NV50_3D_REG_MODE_STRIPED);
 419    BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
 420    OUT_RING  (chan, 0xf);
 421
 422    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 423    OUT_RING  (chan, 1);
 424
 425    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 426    OUT_RING  (chan, 0);
 427    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 428    OUT_RING  (chan, 0);
 429    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 430    OUT_RING  (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
 431    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 432    OUT_RING  (chan, 0);
 433    BEGIN_RING(chan, RING_3D(LINE_LAST_PIXEL), 1);
 434    OUT_RING  (chan, 0);
 435    BEGIN_RING(chan, RING_3D(BLEND_SEPARATE_ALPHA), 1);
 436    OUT_RING  (chan, 1);
 437
 438    if (tesla_class >= NVA0_3D) {
 439       BEGIN_RING(chan, RING_3D_(NVA0_3D_TEX_MISC), 1);
 440       OUT_RING  (chan, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP);
 441    }
 442
 443    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 444    OUT_RING  (chan, 0);
 445    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 446    OUT_RING  (chan, 0);
 447    OUT_RING  (chan, 0);
 448    BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 449    OUT_RING  (chan, 0x3f);
 450
 451    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
 452                         3 << NV50_CODE_BO_SIZE_LOG2, &screen->code);
 453    if (ret)
 454       goto fail;
 455
 456    nouveau_resource_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 457    nouveau_resource_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 458    nouveau_resource_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
 459
 460    base = 1 << NV50_CODE_BO_SIZE_LOG2;
 461
 462    BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
 463    OUT_RELOCh(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 464    OUT_RELOCl(chan, screen->code, base * 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 465
 466    BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
 467    OUT_RELOCh(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 468    OUT_RELOCl(chan, screen->code, base * 1, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 469
 470    BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
 471    OUT_RELOCh(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 472    OUT_RELOCl(chan, screen->code, base * 2, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 473
 474    nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 475
 476    max_warps  = util_bitcount(value & 0xffff);
 477    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 478
 479    stack_size = max_warps * 64 * 8;
 480
 481    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
 482                         &screen->stack_bo);
 483    if (ret)
 484       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 485
 486    BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
 487    OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 488    OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 489    OUT_RING  (chan, 4);
 490
 491    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 492
 493    screen->tls_size = tls_space * max_warps * 32;
 494
 495    debug_printf("max_warps = %i, tls_size = %llu KiB\n",
 496                 max_warps, screen->tls_size >> 10);
 497
 498    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
 499                         &screen->tls_bo);
 500    if (ret)
 501       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 502
 503    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
 504    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 505    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 506    OUT_RING  (chan, util_logbase2(tls_space / 8));
 507
 508    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
 509                         &screen->uniforms);
 510    if (ret)
 511       goto fail;
 512
 513    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 514    OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 515    OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 516    OUT_RING  (chan, (NV50_CB_PVP << 16) | 0x0000);
 517
 518    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 519    OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 520    OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 521    OUT_RING  (chan, (NV50_CB_PGP << 16) | 0x0000);
 522
 523    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 524    OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 525    OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 526    OUT_RING  (chan, (NV50_CB_PFP << 16) | 0x0000);
 527
 528    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 529    OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 530    OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 531    OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 532
 533    BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
 534    OUT_RING  (chan, (NV50_CB_PVP << 12) | 0x001);
 535    OUT_RING  (chan, (NV50_CB_PGP << 12) | 0x021);
 536    OUT_RING  (chan, (NV50_CB_PFP << 12) | 0x031);
 537    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf01);
 538    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf21);
 539    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf31);
 540
 541    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
 542                         &screen->txc);
 543    if (ret)
 544       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 545
 546    /* max TIC (bits 4:8) & TSC bindings, per program type */
 547    for (i = 0; i < 3; ++i) {
 548       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 549       OUT_RING  (chan, 0x54);
 550    }
 551
 552    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 553    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 554    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 555    OUT_RING  (chan, NV50_TIC_MAX_ENTRIES - 1);
 556
 557    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 558    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 559    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 560    OUT_RING  (chan, NV50_TSC_MAX_ENTRIES - 1);
 561
 562    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 563    OUT_RING  (chan, 0);
 564
 565    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 566    OUT_RING  (chan, 0);
 567    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 568    OUT_RING  (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 569    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 570    for (i = 0; i < 8 * 2; ++i)
 571       OUT_RING(chan, 0);
 572    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 573    OUT_RING  (chan, 0);
 574
 575    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 576    OUT_RING  (chan, 1);
 577    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 578    OUT_RINGf (chan, 0.0f);
 579    OUT_RINGf (chan, 1.0f);
 580
 581    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 582 #ifdef NV50_SCISSORS_CLIPPING
 583    OUT_RING  (chan, 0x0000);
 584 #else
 585    OUT_RING  (chan, 0x1080);
 586 #endif
 587
 588    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 589    OUT_RING  (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 590
 591    /* We use scissors instead of exact view volume clipping,
 592     * so they're always enabled.
 593     */
 594    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 595    OUT_RING  (chan, 1);
 596    OUT_RING  (chan, 8192 << 16);
 597    OUT_RING  (chan, 8192 << 16);
 598
 599    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 600    OUT_RING  (chan, 1);
 601    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 602    OUT_RING  (chan, NV50_3D_POINT_RASTER_RULES_OGL);
 603    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 604    OUT_RING  (chan, 0x11111111);
 605    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 606    OUT_RING  (chan, 1);
 607
 608    FIRE_RING (chan);
 609
 610    screen->tic.entries = CALLOC(4096, sizeof(void *));
 611    screen->tsc.entries = screen->tic.entries + 2048;
 612
 613    screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 614
 615    if (!nv50_blitctx_create(screen))
 616       goto fail;
 617
 618    nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE);
 619
 620    return pscreen;
 621
 622 fail:
 623    nv50_screen_destroy(pscreen);
 624    return NULL;
 625 }
 626
 627 void
 628 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
 629 {
 630    struct nouveau_channel *chan = screen->base.channel;
 631
 632    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 633
 634    MARK_RING(chan, 5, 5);
 635    nouveau_bo_validate(chan, screen->code, flags);
 636    nouveau_bo_validate(chan, screen->uniforms, flags);
 637    nouveau_bo_validate(chan, screen->txc, flags);
 638    nouveau_bo_validate(chan, screen->tls_bo, flags);
 639    nouveau_bo_validate(chan, screen->stack_bo, flags);
 640 }
 641
 642 int
 643 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 644 {
 645    int i = screen->tic.next;
 646
 647    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 648       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 649
 650    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 651
 652    if (screen->tic.entries[i])
 653       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 654
 655    screen->tic.entries[i] = entry;
 656    return i;
 657 }
 658
 659 int
 660 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 661 {
 662    int i = screen->tsc.next;
 663
 664    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 665       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 666
 667    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 668
 669    if (screen->tsc.entries[i])
 670       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 671
 672    screen->tsc.entries[i] = entry;
 673    return i;
 674 }