2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
27 #include "nv50_context.h"
28 #include "nv50_screen.h"
30 #include "nouveau/nv_object.xml.h"
32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
37 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
38 enum pipe_format format
,
39 enum pipe_texture_target target
,
40 unsigned sample_count
,
43 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
45 if (sample_count
== 8 && util_format_get_blocksizebits(format
) >= 128)
48 if (!util_format_is_supported(format
, bindings
))
52 case PIPE_FORMAT_Z16_UNORM
:
53 if (nv50_screen(pscreen
)->tesla
->oclass
< NVA0_3D_CLASS
)
56 case PIPE_FORMAT_R8G8B8A8_UNORM
:
57 case PIPE_FORMAT_R8G8B8X8_UNORM
:
58 /* HACK: GL requires equal formats for MS resolve and window is BGRA */
59 if (bindings
& PIPE_BIND_RENDER_TARGET
)
65 /* transfers & shared are always supported */
66 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
67 PIPE_BIND_TRANSFER_WRITE
|
70 return (nv50_format_table
[format
].usage
& bindings
) == bindings
;
74 nv50_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
76 const uint16_t class_3d
= nouveau_screen(pscreen
)->class_3d
;
79 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
81 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
83 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
85 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
87 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
89 case PIPE_CAP_MIN_TEXEL_OFFSET
:
91 case PIPE_CAP_MAX_TEXEL_OFFSET
:
93 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
94 case PIPE_CAP_TEXTURE_SWIZZLE
:
95 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
96 case PIPE_CAP_NPOT_TEXTURES
:
97 case PIPE_CAP_ANISOTROPIC_FILTER
:
98 case PIPE_CAP_SCALED_RESOLVE
:
100 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
101 return nv50_screen(pscreen
)->tesla
->oclass
>= NVA0_3D_CLASS
;
102 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
104 case PIPE_CAP_TWO_SIDED_STENCIL
:
105 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
106 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
107 case PIPE_CAP_POINT_SPRITE
:
111 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
113 case PIPE_CAP_MAX_RENDER_TARGETS
:
115 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
117 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
118 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
119 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
121 case PIPE_CAP_TIMER_QUERY
:
122 case PIPE_CAP_OCCLUSION_QUERY
:
124 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
126 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
127 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
129 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
130 return (class_3d
>= NVA0_3D_CLASS
) ? 1 : 0;
131 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
132 case PIPE_CAP_INDEP_BLEND_ENABLE
:
134 case PIPE_CAP_INDEP_BLEND_FUNC
:
135 return nv50_screen(pscreen
)->tesla
->oclass
>= NVA3_3D_CLASS
;
136 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
137 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
139 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
140 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
142 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
144 case PIPE_CAP_PRIMITIVE_RESTART
:
145 case PIPE_CAP_TGSI_INSTANCEID
:
146 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
147 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
148 case PIPE_CAP_CONDITIONAL_RENDER
:
149 case PIPE_CAP_TEXTURE_BARRIER
:
150 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
151 case PIPE_CAP_START_INSTANCE
:
153 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS
:
154 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
155 return 0; /* state trackers will know better */
156 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
157 case PIPE_CAP_USER_INDEX_BUFFERS
:
158 case PIPE_CAP_USER_VERTEX_BUFFERS
:
160 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
162 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
163 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
164 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
167 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
173 nv50_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
174 enum pipe_shader_cap param
)
177 case PIPE_SHADER_VERTEX
:
178 case PIPE_SHADER_GEOMETRY
:
179 case PIPE_SHADER_FRAGMENT
:
186 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
187 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
188 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
189 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
191 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
193 case PIPE_SHADER_CAP_MAX_INPUTS
:
194 if (shader
== PIPE_SHADER_VERTEX
)
197 case PIPE_SHADER_CAP_MAX_CONSTS
:
199 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
200 return NV50_MAX_PIPE_CONSTBUFS
;
201 case PIPE_SHADER_CAP_MAX_ADDRS
:
203 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
204 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
205 return shader
!= PIPE_SHADER_FRAGMENT
;
206 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
207 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
209 case PIPE_SHADER_CAP_MAX_PREDS
:
211 case PIPE_SHADER_CAP_MAX_TEMPS
:
212 return NV50_CAP_MAX_PROGRAM_TEMPS
;
213 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
215 case PIPE_SHADER_CAP_SUBROUTINES
:
216 return 0; /* please inline, or provide function declarations */
217 case PIPE_SHADER_CAP_INTEGERS
:
219 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
222 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
228 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
231 case PIPE_CAPF_MAX_LINE_WIDTH
:
232 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
234 case PIPE_CAPF_MAX_POINT_WIDTH
:
235 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
237 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
239 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
242 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
248 nv50_screen_destroy(struct pipe_screen
*pscreen
)
250 struct nv50_screen
*screen
= nv50_screen(pscreen
);
252 if (screen
->base
.fence
.current
) {
253 nouveau_fence_wait(screen
->base
.fence
.current
);
254 nouveau_fence_ref (NULL
, &screen
->base
.fence
.current
);
256 if (screen
->base
.pushbuf
)
257 screen
->base
.pushbuf
->user_priv
= NULL
;
260 FREE(screen
->blitctx
);
262 nouveau_bo_ref(NULL
, &screen
->code
);
263 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
264 nouveau_bo_ref(NULL
, &screen
->stack_bo
);
265 nouveau_bo_ref(NULL
, &screen
->txc
);
266 nouveau_bo_ref(NULL
, &screen
->uniforms
);
267 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
269 nouveau_heap_destroy(&screen
->vp_code_heap
);
270 nouveau_heap_destroy(&screen
->gp_code_heap
);
271 nouveau_heap_destroy(&screen
->fp_code_heap
);
273 if (screen
->tic
.entries
)
274 FREE(screen
->tic
.entries
);
276 nouveau_object_del(&screen
->tesla
);
277 nouveau_object_del(&screen
->eng2d
);
278 nouveau_object_del(&screen
->m2mf
);
279 nouveau_object_del(&screen
->sync
);
281 nouveau_screen_fini(&screen
->base
);
287 nv50_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
289 struct nv50_screen
*screen
= nv50_screen(pscreen
);
290 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
292 /* we need to do it after possible flush in MARK_RING */
293 *sequence
= ++screen
->base
.fence
.sequence
;
295 PUSH_DATA (push
, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH
), 4));
296 PUSH_DATAh(push
, screen
->fence
.bo
->offset
);
297 PUSH_DATA (push
, screen
->fence
.bo
->offset
);
298 PUSH_DATA (push
, *sequence
);
299 PUSH_DATA (push
, NV50_3D_QUERY_GET_MODE_WRITE_UNK0
|
300 NV50_3D_QUERY_GET_UNK4
|
301 NV50_3D_QUERY_GET_UNIT_CROP
|
302 NV50_3D_QUERY_GET_TYPE_QUERY
|
303 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO
|
304 NV50_3D_QUERY_GET_SHORT
);
308 nv50_screen_fence_update(struct pipe_screen
*pscreen
)
310 return nv50_screen(pscreen
)->fence
.map
[0];
314 nv50_screen_init_hwctx(struct nv50_screen
*screen
, unsigned tls_space
)
316 struct nouveau_pushbuf
*push
= screen
->base
.pushbuf
;
317 struct nv04_fifo
*fifo
;
320 fifo
= (struct nv04_fifo
*)screen
->base
.channel
->data
;
322 BEGIN_NV04(push
, SUBC_M2MF(NV01_SUBCHAN_OBJECT
), 1);
323 PUSH_DATA (push
, screen
->m2mf
->handle
);
324 BEGIN_NV04(push
, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY
), 3);
325 PUSH_DATA (push
, screen
->sync
->handle
);
326 PUSH_DATA (push
, fifo
->vram
);
327 PUSH_DATA (push
, fifo
->vram
);
329 BEGIN_NV04(push
, SUBC_2D(NV01_SUBCHAN_OBJECT
), 1);
330 PUSH_DATA (push
, screen
->eng2d
->handle
);
331 BEGIN_NV04(push
, NV50_2D(DMA_NOTIFY
), 4);
332 PUSH_DATA (push
, screen
->sync
->handle
);
333 PUSH_DATA (push
, fifo
->vram
);
334 PUSH_DATA (push
, fifo
->vram
);
335 PUSH_DATA (push
, fifo
->vram
);
336 BEGIN_NV04(push
, NV50_2D(OPERATION
), 1);
337 PUSH_DATA (push
, NV50_2D_OPERATION_SRCCOPY
);
338 BEGIN_NV04(push
, NV50_2D(CLIP_ENABLE
), 1);
340 BEGIN_NV04(push
, NV50_2D(COLOR_KEY_ENABLE
), 1);
342 BEGIN_NV04(push
, SUBC_2D(0x0888), 1);
345 BEGIN_NV04(push
, SUBC_3D(NV01_SUBCHAN_OBJECT
), 1);
346 PUSH_DATA (push
, screen
->tesla
->handle
);
348 BEGIN_NV04(push
, NV50_3D(COND_MODE
), 1);
349 PUSH_DATA (push
, NV50_3D_COND_MODE_ALWAYS
);
351 BEGIN_NV04(push
, NV50_3D(DMA_NOTIFY
), 1);
352 PUSH_DATA (push
, screen
->sync
->handle
);
353 BEGIN_NV04(push
, NV50_3D(DMA_ZETA
), 11);
354 for (i
= 0; i
< 11; ++i
)
355 PUSH_DATA(push
, fifo
->vram
);
356 BEGIN_NV04(push
, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN
);
357 for (i
= 0; i
< NV50_3D_DMA_COLOR__LEN
; ++i
)
358 PUSH_DATA(push
, fifo
->vram
);
360 BEGIN_NV04(push
, NV50_3D(REG_MODE
), 1);
361 PUSH_DATA (push
, NV50_3D_REG_MODE_STRIPED
);
362 BEGIN_NV04(push
, NV50_3D(UNK1400_LANES
), 1);
363 PUSH_DATA (push
, 0xf);
365 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE
)) {
366 BEGIN_NV04(push
, NV50_3D(WATCHDOG_TIMER
), 1);
367 PUSH_DATA (push
, 0x18);
370 BEGIN_NV04(push
, NV50_3D(RT_CONTROL
), 1);
373 BEGIN_NV04(push
, NV50_3D(CSAA_ENABLE
), 1);
375 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_ENABLE
), 1);
377 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_MODE
), 1);
378 PUSH_DATA (push
, NV50_3D_MULTISAMPLE_MODE_MS1
);
379 BEGIN_NV04(push
, NV50_3D(MULTISAMPLE_CTRL
), 1);
381 BEGIN_NV04(push
, NV50_3D(LINE_LAST_PIXEL
), 1);
383 BEGIN_NV04(push
, NV50_3D(BLEND_SEPARATE_ALPHA
), 1);
386 if (screen
->tesla
->oclass
>= NVA0_3D_CLASS
) {
387 BEGIN_NV04(push
, SUBC_3D(NVA0_3D_TEX_MISC
), 1);
388 PUSH_DATA (push
, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
391 BEGIN_NV04(push
, NV50_3D(SCREEN_Y_CONTROL
), 1);
393 BEGIN_NV04(push
, NV50_3D(WINDOW_OFFSET_X
), 2);
396 BEGIN_NV04(push
, NV50_3D(ZCULL_REGION
), 1);
397 PUSH_DATA (push
, 0x3f);
399 BEGIN_NV04(push
, NV50_3D(VP_ADDRESS_HIGH
), 2);
400 PUSH_DATAh(push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
401 PUSH_DATA (push
, screen
->code
->offset
+ (0 << NV50_CODE_BO_SIZE_LOG2
));
403 BEGIN_NV04(push
, NV50_3D(FP_ADDRESS_HIGH
), 2);
404 PUSH_DATAh(push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
405 PUSH_DATA (push
, screen
->code
->offset
+ (1 << NV50_CODE_BO_SIZE_LOG2
));
407 BEGIN_NV04(push
, NV50_3D(GP_ADDRESS_HIGH
), 2);
408 PUSH_DATAh(push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
409 PUSH_DATA (push
, screen
->code
->offset
+ (2 << NV50_CODE_BO_SIZE_LOG2
));
411 BEGIN_NV04(push
, NV50_3D(LOCAL_ADDRESS_HIGH
), 3);
412 PUSH_DATAh(push
, screen
->tls_bo
->offset
);
413 PUSH_DATA (push
, screen
->tls_bo
->offset
);
414 PUSH_DATA (push
, util_logbase2(tls_space
/ 8));
416 BEGIN_NV04(push
, NV50_3D(STACK_ADDRESS_HIGH
), 3);
417 PUSH_DATAh(push
, screen
->stack_bo
->offset
);
418 PUSH_DATA (push
, screen
->stack_bo
->offset
);
421 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
422 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (0 << 16));
423 PUSH_DATA (push
, screen
->uniforms
->offset
+ (0 << 16));
424 PUSH_DATA (push
, (NV50_CB_PVP
<< 16) | 0x0000);
426 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
427 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (1 << 16));
428 PUSH_DATA (push
, screen
->uniforms
->offset
+ (1 << 16));
429 PUSH_DATA (push
, (NV50_CB_PGP
<< 16) | 0x0000);
431 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
432 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (2 << 16));
433 PUSH_DATA (push
, screen
->uniforms
->offset
+ (2 << 16));
434 PUSH_DATA (push
, (NV50_CB_PFP
<< 16) | 0x0000);
436 BEGIN_NV04(push
, NV50_3D(CB_DEF_ADDRESS_HIGH
), 3);
437 PUSH_DATAh(push
, screen
->uniforms
->offset
+ (3 << 16));
438 PUSH_DATA (push
, screen
->uniforms
->offset
+ (3 << 16));
439 PUSH_DATA (push
, (NV50_CB_AUX
<< 16) | 0x0200);
441 BEGIN_NI04(push
, NV50_3D(SET_PROGRAM_CB
), 3);
442 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf01);
443 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf21);
444 PUSH_DATA (push
, (NV50_CB_AUX
<< 12) | 0xf31);
446 /* max TIC (bits 4:8) & TSC bindings, per program type */
447 for (i
= 0; i
< 3; ++i
) {
448 BEGIN_NV04(push
, NV50_3D(TEX_LIMITS(i
)), 1);
449 PUSH_DATA (push
, 0x54);
452 BEGIN_NV04(push
, NV50_3D(TIC_ADDRESS_HIGH
), 3);
453 PUSH_DATAh(push
, screen
->txc
->offset
);
454 PUSH_DATA (push
, screen
->txc
->offset
);
455 PUSH_DATA (push
, NV50_TIC_MAX_ENTRIES
- 1);
457 BEGIN_NV04(push
, NV50_3D(TSC_ADDRESS_HIGH
), 3);
458 PUSH_DATAh(push
, screen
->txc
->offset
+ 65536);
459 PUSH_DATA (push
, screen
->txc
->offset
+ 65536);
460 PUSH_DATA (push
, NV50_TSC_MAX_ENTRIES
- 1);
462 BEGIN_NV04(push
, NV50_3D(LINKED_TSC
), 1);
465 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_EN
), 1);
467 BEGIN_NV04(push
, NV50_3D(CLIP_RECTS_MODE
), 1);
468 PUSH_DATA (push
, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
469 BEGIN_NV04(push
, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
470 for (i
= 0; i
< 8 * 2; ++i
)
472 BEGIN_NV04(push
, NV50_3D(CLIPID_ENABLE
), 1);
475 BEGIN_NV04(push
, NV50_3D(VIEWPORT_TRANSFORM_EN
), 1);
477 BEGIN_NV04(push
, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
478 PUSH_DATAf(push
, 0.0f
);
479 PUSH_DATAf(push
, 1.0f
);
481 BEGIN_NV04(push
, NV50_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
482 #ifdef NV50_SCISSORS_CLIPPING
483 PUSH_DATA (push
, 0x0000);
485 PUSH_DATA (push
, 0x1080);
488 BEGIN_NV04(push
, NV50_3D(CLEAR_FLAGS
), 1);
489 PUSH_DATA (push
, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT
);
491 /* We use scissors instead of exact view volume clipping,
492 * so they're always enabled.
494 BEGIN_NV04(push
, NV50_3D(SCISSOR_ENABLE(0)), 3);
496 PUSH_DATA (push
, 8192 << 16);
497 PUSH_DATA (push
, 8192 << 16);
499 BEGIN_NV04(push
, NV50_3D(RASTERIZE_ENABLE
), 1);
501 BEGIN_NV04(push
, NV50_3D(POINT_RASTER_RULES
), 1);
502 PUSH_DATA (push
, NV50_3D_POINT_RASTER_RULES_OGL
);
503 BEGIN_NV04(push
, NV50_3D(FRAG_COLOR_CLAMP_EN
), 1);
504 PUSH_DATA (push
, 0x11111111);
505 BEGIN_NV04(push
, NV50_3D(EDGEFLAG
), 1);
513 #define FAIL_SCREEN_INIT(str, err) \
515 NOUVEAU_ERR(str, err); \
516 nv50_screen_destroy(pscreen); \
521 nv50_screen_create(struct nouveau_device
*dev
)
523 struct nv50_screen
*screen
;
524 struct pipe_screen
*pscreen
;
525 struct nouveau_object
*chan
;
527 uint32_t tesla_class
;
528 unsigned stack_size
, max_warps
, tls_space
;
531 screen
= CALLOC_STRUCT(nv50_screen
);
534 pscreen
= &screen
->base
.base
;
536 ret
= nouveau_screen_init(&screen
->base
, dev
);
538 FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret
);
540 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
541 * admit them to VRAM.
543 screen
->base
.vidmem_bindings
|= PIPE_BIND_CONSTANT_BUFFER
|
544 PIPE_BIND_VERTEX_BUFFER
;
545 screen
->base
.sysmem_bindings
|=
546 PIPE_BIND_VERTEX_BUFFER
| PIPE_BIND_INDEX_BUFFER
;
548 screen
->base
.pushbuf
->user_priv
= screen
;
549 screen
->base
.pushbuf
->rsvd_kick
= 5;
551 chan
= screen
->base
.channel
;
553 pscreen
->destroy
= nv50_screen_destroy
;
554 pscreen
->context_create
= nv50_create
;
555 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
556 pscreen
->get_param
= nv50_screen_get_param
;
557 pscreen
->get_shader_param
= nv50_screen_get_shader_param
;
558 pscreen
->get_paramf
= nv50_screen_get_paramf
;
560 nv50_screen_init_resource_functions(pscreen
);
562 nouveau_screen_init_vdec(&screen
->base
);
564 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096,
565 NULL
, &screen
->fence
.bo
);
568 nouveau_bo_map(screen
->fence
.bo
, 0, NULL
);
569 screen
->fence
.map
= screen
->fence
.bo
->map
;
570 screen
->base
.fence
.emit
= nv50_screen_fence_emit
;
571 screen
->base
.fence
.update
= nv50_screen_fence_update
;
573 ret
= nouveau_object_new(chan
, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS
,
574 &(struct nv04_notify
){ .length
= 32 },
575 sizeof(struct nv04_notify
), &screen
->sync
);
577 FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret
);
580 ret
= nouveau_object_new(chan
, 0xbeef5039, NV50_M2MF_CLASS
,
581 NULL
, 0, &screen
->m2mf
);
583 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
586 ret
= nouveau_object_new(chan
, 0xbeef502d, NV50_2D_CLASS
,
587 NULL
, 0, &screen
->eng2d
);
589 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
591 switch (dev
->chipset
& 0xf0) {
593 tesla_class
= NV50_3D_CLASS
;
597 tesla_class
= NV84_3D_CLASS
;
600 switch (dev
->chipset
) {
604 tesla_class
= NVA0_3D_CLASS
;
607 tesla_class
= NVAF_3D_CLASS
;
610 tesla_class
= NVA3_3D_CLASS
;
615 FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev
->chipset
);
618 screen
->base
.class_3d
= tesla_class
;
620 ret
= nouveau_object_new(chan
, 0xbeef5097, tesla_class
,
621 NULL
, 0, &screen
->tesla
);
623 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
626 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
627 3 << NV50_CODE_BO_SIZE_LOG2
, NULL
, &screen
->code
);
631 nouveau_heap_init(&screen
->vp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
632 nouveau_heap_init(&screen
->gp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
633 nouveau_heap_init(&screen
->fp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
635 nouveau_getparam(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
637 max_warps
= util_bitcount(value
& 0xffff);
638 max_warps
*= util_bitcount((value
>> 24) & 0xf) * 32;
640 stack_size
= max_warps
* 64 * 8;
642 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, stack_size
, NULL
,
645 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret
);
647 tls_space
= NV50_CAP_MAX_PROGRAM_TEMPS
* 16;
649 screen
->tls_size
= tls_space
* max_warps
* 32;
651 if (nouveau_mesa_debug
)
652 debug_printf("max_warps = %i, tls_size = %"PRIu64
" KiB\n",
653 max_warps
, screen
->tls_size
>> 10);
655 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, screen
->tls_size
, NULL
,
658 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret
);
661 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 4 << 16, NULL
,
666 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 3 << 16, NULL
,
669 FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret
);
671 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
672 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
675 if (!nv50_blitctx_create(screen
))
678 if (nv50_screen_init_hwctx(screen
, tls_space
))
681 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);
686 nv50_screen_destroy(pscreen
);
691 nv50_screen_tic_alloc(struct nv50_screen
*screen
, void *entry
)
693 int i
= screen
->tic
.next
;
695 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
696 i
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
698 screen
->tic
.next
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
700 if (screen
->tic
.entries
[i
])
701 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
703 screen
->tic
.entries
[i
] = entry
;
708 nv50_screen_tsc_alloc(struct nv50_screen
*screen
, void *entry
)
710 int i
= screen
->tsc
.next
;
712 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
713 i
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
715 screen
->tsc
.next
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
717 if (screen
->tsc
.entries
[i
])
718 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
720 screen
->tsc
.entries
[i
] = entry
;