src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2008 Ben Skeggs
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "pipe/p_screen.h"
  24
  25 #include "nv50_context.h"
  26 #include "nv50_screen.h"
  27
  28 #include "nouveau/nouveau_stateobj.h"
  29
  30 static boolean
  31 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  32                                 enum pipe_format format,
  33                                 enum pipe_texture_target target,
  34                                 unsigned tex_usage, unsigned geom_flags)
  35 {
  36         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
  37                 switch (format) {
  38                 case PIPE_FORMAT_X8R8G8B8_UNORM:
  39                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  40                 case PIPE_FORMAT_R5G6B5_UNORM:
  41                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  42                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  43                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  44                 case PIPE_FORMAT_R16G16_SNORM:
  45                 case PIPE_FORMAT_R16G16_UNORM:
  46                         return TRUE;
  47                 default:
  48                         break;
  49                 }
  50         } else
  51         if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
  52                 switch (format) {
  53                 case PIPE_FORMAT_Z32_FLOAT:
  54                 case PIPE_FORMAT_Z24S8_UNORM:
  55                 case PIPE_FORMAT_X8Z24_UNORM:
  56                 case PIPE_FORMAT_S8Z24_UNORM:
  57                         return TRUE;
  58                 default:
  59                         break;
  60                 }
  61         } else {
  62                 switch (format) {
  63                 case PIPE_FORMAT_A8R8G8B8_UNORM:
  64                 case PIPE_FORMAT_X8R8G8B8_UNORM:
  65                 case PIPE_FORMAT_A8R8G8B8_SRGB:
  66                 case PIPE_FORMAT_X8R8G8B8_SRGB:
  67                 case PIPE_FORMAT_A1R5G5B5_UNORM:
  68                 case PIPE_FORMAT_A4R4G4B4_UNORM:
  69                 case PIPE_FORMAT_R5G6B5_UNORM:
  70                 case PIPE_FORMAT_L8_UNORM:
  71                 case PIPE_FORMAT_A8_UNORM:
  72                 case PIPE_FORMAT_I8_UNORM:
  73                 case PIPE_FORMAT_A8L8_UNORM:
  74                 case PIPE_FORMAT_DXT1_RGB:
  75                 case PIPE_FORMAT_DXT1_RGBA:
  76                 case PIPE_FORMAT_DXT3_RGBA:
  77                 case PIPE_FORMAT_DXT5_RGBA:
  78                 case PIPE_FORMAT_Z24S8_UNORM:
  79                 case PIPE_FORMAT_S8Z24_UNORM:
  80                 case PIPE_FORMAT_Z32_FLOAT:
  81                 case PIPE_FORMAT_R16G16B16A16_SNORM:
  82                 case PIPE_FORMAT_R16G16B16A16_UNORM:
  83                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
  84                 case PIPE_FORMAT_R16G16_SNORM:
  85                 case PIPE_FORMAT_R16G16_UNORM:
  86                         return TRUE;
  87                 default:
  88                         break;
  89                 }
  90         }
  91
  92         return FALSE;
  93 }
  94
  95 static int
  96 nv50_screen_get_param(struct pipe_screen *pscreen, int param)
  97 {
  98         switch (param) {
  99         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 100                 return 32;
 101         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 102                 return 32;
 103         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 104                 return 64;
 105         case PIPE_CAP_NPOT_TEXTURES:
 106                 return 1;
 107         case PIPE_CAP_TWO_SIDED_STENCIL:
 108                 return 1;
 109         case PIPE_CAP_GLSL:
 110                 return 0;
 111         case PIPE_CAP_ANISOTROPIC_FILTER:
 112                 return 1;
 113         case PIPE_CAP_POINT_SPRITE:
 114                 return 1;
 115         case PIPE_CAP_MAX_RENDER_TARGETS:
 116                 return 8;
 117         case PIPE_CAP_OCCLUSION_QUERY:
 118                 return 1;
 119         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 120                 return 1;
 121         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 122                 return 13;
 123         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 124                 return 10;
 125         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 126                 return 13;
 127         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 128         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
 129                 return 1;
 130         case PIPE_CAP_TGSI_CONT_SUPPORTED:
 131                 return 1;
 132         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 133                 return 1;
 134         case NOUVEAU_CAP_HW_VTXBUF:
 135                 return 1;
 136         case NOUVEAU_CAP_HW_IDXBUF:
 137                 return 0;
 138         default:
 139                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 140                 return 0;
 141         }
 142 }
 143
 144 static float
 145 nv50_screen_get_paramf(struct pipe_screen *pscreen, int param)
 146 {
 147         switch (param) {
 148         case PIPE_CAP_MAX_LINE_WIDTH:
 149         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 150                 return 10.0;
 151         case PIPE_CAP_MAX_POINT_WIDTH:
 152         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 153                 return 64.0;
 154         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 155                 return 16.0;
 156         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 157                 return 4.0;
 158         default:
 159                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 160                 return 0.0;
 161         }
 162 }
 163
 164 static void
 165 nv50_screen_destroy(struct pipe_screen *pscreen)
 166 {
 167         struct nv50_screen *screen = nv50_screen(pscreen);
 168
 169         nouveau_notifier_free(&screen->sync);
 170         nouveau_grobj_free(&screen->tesla);
 171         nouveau_grobj_free(&screen->eng2d);
 172         nouveau_grobj_free(&screen->m2mf);
 173         nouveau_screen_fini(&screen->base);
 174         FREE(screen);
 175 }
 176
 177 struct pipe_screen *
 178 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 179 {
 180         struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen);
 181         struct nouveau_channel *chan;
 182         struct pipe_screen *pscreen;
 183         struct nouveau_stateobj *so;
 184         unsigned chipset = dev->chipset;
 185         unsigned tesla_class = 0;
 186         int ret, i;
 187
 188         if (!screen)
 189                 return NULL;
 190         pscreen = &screen->base.base;
 191
 192         ret = nouveau_screen_init(&screen->base, dev);
 193         if (ret) {
 194                 nv50_screen_destroy(pscreen);
 195                 return NULL;
 196         }
 197         chan = screen->base.channel;
 198
 199         pscreen->winsys = ws;
 200         pscreen->destroy = nv50_screen_destroy;
 201         pscreen->get_param = nv50_screen_get_param;
 202         pscreen->get_paramf = nv50_screen_get_paramf;
 203         pscreen->is_format_supported = nv50_screen_is_format_supported;
 204
 205         nv50_screen_init_miptree_functions(pscreen);
 206         nv50_transfer_init_screen_functions(pscreen);
 207
 208         /* DMA engine object */
 209         ret = nouveau_grobj_alloc(chan, 0xbeef5039,
 210                 NV50_MEMORY_TO_MEMORY_FORMAT, &screen->m2mf);
 211         if (ret) {
 212                 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret);
 213                 nv50_screen_destroy(pscreen);
 214                 return NULL;
 215         }
 216         BIND_RING(chan, screen->m2mf, 1);
 217
 218         /* 2D object */
 219         ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 220         if (ret) {
 221                 NOUVEAU_ERR("Error creating 2D object: %d\n", ret);
 222                 nv50_screen_destroy(pscreen);
 223                 return NULL;
 224         }
 225         BIND_RING(chan, screen->eng2d, 2);
 226
 227         /* 3D object */
 228         switch (chipset & 0xf0) {
 229         case 0x50:
 230                 tesla_class = NV50TCL;
 231                 break;
 232         case 0x80:
 233         case 0x90:
 234                 tesla_class = NV84TCL;
 235                 break;
 236         case 0xa0:
 237                 switch (chipset) {
 238                 case 0xa0:
 239                 case 0xaa:
 240                 case 0xac:
 241                         tesla_class = NVA0TCL;
 242                         break;
 243                 default:
 244                         tesla_class = NVA8TCL;
 245                         break;
 246                 }
 247                 break;
 248         default:
 249                 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset);
 250                 nv50_screen_destroy(pscreen);
 251                 return NULL;
 252         }
 253
 254         ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class,
 255                 &screen->tesla);
 256         if (ret) {
 257                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 258                 nv50_screen_destroy(pscreen);
 259                 return NULL;
 260         }
 261         BIND_RING(chan, screen->tesla, 3);
 262
 263         /* Sync notifier */
 264         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 265         if (ret) {
 266                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 267                 nv50_screen_destroy(pscreen);
 268                 return NULL;
 269         }
 270
 271         /* Static M2MF init */
 272         so = so_new(32, 0);
 273         so_method(so, screen->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 3);
 274         so_data  (so, screen->sync->handle);
 275         so_data  (so, chan->vram->handle);
 276         so_data  (so, chan->vram->handle);
 277         so_emit(chan, so);
 278         so_ref (NULL, &so);
 279
 280         /* Static 2D init */
 281         so = so_new(64, 0);
 282         so_method(so, screen->eng2d, NV50_2D_DMA_NOTIFY, 4);
 283         so_data  (so, screen->sync->handle);
 284         so_data  (so, chan->vram->handle);
 285         so_data  (so, chan->vram->handle);
 286         so_data  (so, chan->vram->handle);
 287         so_method(so, screen->eng2d, NV50_2D_OPERATION, 1);
 288         so_data  (so, NV50_2D_OPERATION_SRCCOPY);
 289         so_method(so, screen->eng2d, NV50_2D_CLIP_ENABLE, 1);
 290         so_data  (so, 0);
 291         so_method(so, screen->eng2d, 0x0888, 1);
 292         so_data  (so, 1);
 293         so_emit(chan, so);
 294         so_ref(NULL, &so);
 295
 296         /* Static tesla init */
 297         so = so_new(256, 20);
 298
 299         so_method(so, screen->tesla, NV50TCL_COND_MODE, 1);
 300         so_data  (so, NV50TCL_COND_MODE_ALWAYS);
 301         so_method(so, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
 302         so_data  (so, screen->sync->handle);
 303         so_method(so, screen->tesla, NV50TCL_DMA_ZETA, 11);
 304         for (i = 0; i < 11; i++)
 305                 so_data(so, chan->vram->handle);
 306         so_method(so, screen->tesla, NV50TCL_DMA_COLOR(0),
 307                                      NV50TCL_DMA_COLOR__SIZE);
 308         for (i = 0; i < NV50TCL_DMA_COLOR__SIZE; i++)
 309                 so_data(so, chan->vram->handle);
 310         so_method(so, screen->tesla, NV50TCL_RT_CONTROL, 1);
 311         so_data  (so, 1);
 312
 313         /* activate all 32 lanes (threads) in a warp */
 314         so_method(so, screen->tesla, NV50TCL_WARP_HALVES, 1);
 315         so_data  (so, 0x2);
 316         so_method(so, screen->tesla, 0x1400, 1);
 317         so_data  (so, 0xf);
 318
 319         /* max TIC (bits 4:8) & TSC (ignored) bindings, per program type */
 320         so_method(so, screen->tesla, NV50TCL_TEX_LIMITS(0), 1);
 321         so_data  (so, 0x54);
 322         so_method(so, screen->tesla, NV50TCL_TEX_LIMITS(2), 1);
 323         so_data  (so, 0x54);
 324         /* origin is top left (set to 1 for bottom left) */
 325         so_method(so, screen->tesla, NV50TCL_Y_ORIGIN_BOTTOM, 1);
 326         so_data  (so, 0);
 327         so_method(so, screen->tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1);
 328         so_data  (so, 8);
 329
 330         /* constant buffers for immediates and VP/FP parameters */
 331         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (32 * 4) * 4,
 332                              &screen->constbuf_misc[0]);
 333         if (ret) {
 334                 nv50_screen_destroy(pscreen);
 335                 return NULL;
 336         }
 337
 338         for (i = 0; i < 2; i++) {
 339                 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, (128 * 4) * 4,
 340                                      &screen->constbuf_parm[i]);
 341                 if (ret) {
 342                         nv50_screen_destroy(pscreen);
 343                         return NULL;
 344                 }
 345         }
 346
 347         if (nouveau_resource_init(&screen->immd_heap[0], 0, 128) ||
 348             nouveau_resource_init(&screen->parm_heap[0], 0, 512) ||
 349             nouveau_resource_init(&screen->parm_heap[1], 0, 512))
 350         {
 351                 NOUVEAU_ERR("Error initialising constant buffers.\n");
 352                 nv50_screen_destroy(pscreen);
 353                 return NULL;
 354         }
 355
 356         /*
 357         // map constant buffers:
 358         //  B = buffer ID (maybe more than 1 byte)
 359         //  N = CB index used in shader instruction
 360         //  P = program type (0 = VP, 2 = GP, 3 = FP)
 361         so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1);
 362         so_data  (so, 0x000BBNP1);
 363         */
 364
 365         so_method(so, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 366         so_reloc (so, screen->constbuf_misc[0], 0, NOUVEAU_BO_VRAM |
 367                   NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
 368         so_reloc (so, screen->constbuf_misc[0], 0, NOUVEAU_BO_VRAM |
 369                   NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
 370         so_data  (so, (NV50_CB_PMISC << 16) | 0x00000200);
 371         so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1);
 372         so_data  (so, 0x00000001 | (NV50_CB_PMISC << 12));
 373         so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1);
 374         so_data  (so, 0x00000031 | (NV50_CB_PMISC << 12));
 375
 376         so_method(so, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 377         so_reloc (so, screen->constbuf_parm[0], 0, NOUVEAU_BO_VRAM |
 378                   NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
 379         so_reloc (so, screen->constbuf_parm[0], 0, NOUVEAU_BO_VRAM |
 380                   NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
 381         so_data  (so, (NV50_CB_PVP << 16) | 0x00000800);
 382         so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1);
 383         so_data  (so, 0x00000101 | (NV50_CB_PVP << 12));
 384
 385         so_method(so, screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3);
 386         so_reloc (so, screen->constbuf_parm[1], 0, NOUVEAU_BO_VRAM |
 387                   NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
 388         so_reloc (so, screen->constbuf_parm[1], 0, NOUVEAU_BO_VRAM |
 389                   NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
 390         so_data  (so, (NV50_CB_PFP << 16) | 0x00000800);
 391         so_method(so, screen->tesla, NV50TCL_SET_PROGRAM_CB, 1);
 392         so_data  (so, 0x00000131 | (NV50_CB_PFP << 12));
 393
 394         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, PIPE_SHADER_TYPES*32*32,
 395                              &screen->tic);
 396         if (ret) {
 397                 nv50_screen_destroy(pscreen);
 398                 return NULL;
 399         }
 400
 401         so_method(so, screen->tesla, NV50TCL_TIC_ADDRESS_HIGH, 3);
 402         so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
 403                   NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
 404         so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
 405                   NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
 406         so_data  (so, PIPE_SHADER_TYPES * 32 - 1);
 407
 408         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, PIPE_SHADER_TYPES*32*32,
 409                              &screen->tsc);
 410         if (ret) {
 411                 nv50_screen_destroy(pscreen);
 412                 return NULL;
 413         }
 414
 415         so_method(so, screen->tesla, NV50TCL_TSC_ADDRESS_HIGH, 3);
 416         so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
 417                   NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
 418         so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
 419                   NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
 420         so_data  (so, 0x00000000); /* ignored if TSC_LINKED (0x1234) = 1 */
 421
 422
 423         /* Vertex array limits - max them out */
 424         for (i = 0; i < 16; i++) {
 425                 so_method(so, screen->tesla, NV50TCL_VERTEX_ARRAY_LIMIT_HIGH(i), 2);
 426                 so_data  (so, 0x000000ff);
 427                 so_data  (so, 0xffffffff);
 428         }
 429
 430         so_method(so, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR(0), 2);
 431         so_data  (so, fui(0.0));
 432         so_data  (so, fui(1.0));
 433
 434         /* no dynamic combination of TIC & TSC entries => only BIND_TIC used */
 435         so_method(so, screen->tesla, NV50TCL_LINKED_TSC, 1);
 436         so_data  (so, 1);
 437
 438         /* activate first scissor rectangle */
 439         so_method(so, screen->tesla, NV50TCL_SCISSOR_ENABLE(0), 1);
 440         so_data  (so, 1);
 441
 442         so_method(so, screen->tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
 443         so_data  (so, 1); /* default edgeflag to TRUE */
 444
 445         so_emit(chan, so);
 446         so_ref (so, &screen->static_init);
 447         so_ref (NULL, &so);
 448         nouveau_pushbuf_flush(chan, 0);
 449
 450         return pscreen;
 451 }
 452