Merge commit 'origin/openvg-1.0'
[mesa.git] / src / gallium / drivers / nv50 / nv50_screen.c
1 /*
2 * Copyright 2008 Ben Skeggs
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_screen.h"
24
25 #include "nv50_context.h"
26 #include "nv50_screen.h"
27
28 #include "nouveau/nouveau_stateobj.h"
29
30 static boolean
31 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
32 enum pipe_format format,
33 enum pipe_texture_target target,
34 unsigned tex_usage, unsigned geom_flags)
35 {
36 if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
37 switch (format) {
38 case PIPE_FORMAT_A8R8G8B8_UNORM:
39 case PIPE_FORMAT_R5G6B5_UNORM:
40 return TRUE;
41 default:
42 break;
43 }
44 } else
45 if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
46 switch (format) {
47 case PIPE_FORMAT_Z24S8_UNORM:
48 case PIPE_FORMAT_Z24X8_UNORM:
49 case PIPE_FORMAT_Z16_UNORM:
50 return TRUE;
51 default:
52 break;
53 }
54 } else {
55 switch (format) {
56 case PIPE_FORMAT_A8R8G8B8_UNORM:
57 case PIPE_FORMAT_A1R5G5B5_UNORM:
58 case PIPE_FORMAT_A4R4G4B4_UNORM:
59 case PIPE_FORMAT_R5G6B5_UNORM:
60 case PIPE_FORMAT_L8_UNORM:
61 case PIPE_FORMAT_A8_UNORM:
62 case PIPE_FORMAT_I8_UNORM:
63 case PIPE_FORMAT_A8L8_UNORM:
64 case PIPE_FORMAT_DXT1_RGB:
65 case PIPE_FORMAT_DXT1_RGBA:
66 case PIPE_FORMAT_DXT3_RGBA:
67 case PIPE_FORMAT_DXT5_RGBA:
68 return TRUE;
69 default:
70 break;
71 }
72 }
73
74 return FALSE;
75 }
76
77 static int
78 nv50_screen_get_param(struct pipe_screen *pscreen, int param)
79 {
80 switch (param) {
81 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
82 return 32;
83 case PIPE_CAP_NPOT_TEXTURES:
84 return 1;
85 case PIPE_CAP_TWO_SIDED_STENCIL:
86 return 1;
87 case PIPE_CAP_GLSL:
88 return 0;
89 case PIPE_CAP_S3TC:
90 return 1;
91 case PIPE_CAP_ANISOTROPIC_FILTER:
92 return 1;
93 case PIPE_CAP_POINT_SPRITE:
94 return 0;
95 case PIPE_CAP_MAX_RENDER_TARGETS:
96 return 8;
97 case PIPE_CAP_OCCLUSION_QUERY:
98 return 1;
99 case PIPE_CAP_TEXTURE_SHADOW_MAP:
100 return 1;
101 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
102 return 13;
103 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
104 return 10;
105 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
106 return 13;
107 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
108 case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
109 return 1;
110 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
111 return 0;
112 case PIPE_CAP_TGSI_CONT_SUPPORTED:
113 return 0;
114 case NOUVEAU_CAP_HW_VTXBUF:
115 return 1;
116 case NOUVEAU_CAP_HW_IDXBUF:
117 return 0;
118 default:
119 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
120 return 0;
121 }
122 }
123
124 static float
125 nv50_screen_get_paramf(struct pipe_screen *pscreen, int param)
126 {
127 switch (param) {
128 case PIPE_CAP_MAX_LINE_WIDTH:
129 case PIPE_CAP_MAX_LINE_WIDTH_AA:
130 return 10.0;
131 case PIPE_CAP_MAX_POINT_WIDTH:
132 case PIPE_CAP_MAX_POINT_WIDTH_AA:
133 return 64.0;
134 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
135 return 16.0;
136 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
137 return 4.0;
138 default:
139 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
140 return 0.0;
141 }
142 }
143
144 static void
145 nv50_screen_destroy(struct pipe_screen *pscreen)
146 {
147 struct nv50_screen *screen = nv50_screen(pscreen);
148
149 nouveau_notifier_free(&screen->sync);
150 nouveau_grobj_free(&screen->tesla);
151 nouveau_grobj_free(&screen->eng2d);
152 nouveau_grobj_free(&screen->m2mf);
153 nouveau_screen_fini(&screen->base);
154 FREE(screen);
155 }
156
157 struct pipe_screen *
158 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
159 {
160 struct nv50_screen *screen = CALLOC_STRUCT(nv50_screen);
161 struct nouveau_channel *chan;
162 struct pipe_screen *pscreen;
163 struct nouveau_stateobj *so;
164 unsigned chipset = dev->chipset;
165 unsigned tesla_class = 0;
166 int ret, i;
167
168 if (!screen)
169 return NULL;
170 pscreen = &screen->base.base;
171
172 ret = nouveau_screen_init(&screen->base, dev);
173 if (ret) {
174 nv50_screen_destroy(pscreen);
175 return NULL;
176 }
177 chan = screen->base.channel;
178
179 pscreen->winsys = ws;
180 pscreen->destroy = nv50_screen_destroy;
181 pscreen->get_param = nv50_screen_get_param;
182 pscreen->get_paramf = nv50_screen_get_paramf;
183 pscreen->is_format_supported = nv50_screen_is_format_supported;
184
185 nv50_screen_init_miptree_functions(pscreen);
186 nv50_transfer_init_screen_functions(pscreen);
187
188 /* DMA engine object */
189 ret = nouveau_grobj_alloc(chan, 0xbeef5039, 0x5039, &screen->m2mf);
190 if (ret) {
191 NOUVEAU_ERR("Error creating M2MF object: %d\n", ret);
192 nv50_screen_destroy(pscreen);
193 return NULL;
194 }
195 BIND_RING(chan, screen->m2mf, 1);
196
197 /* 2D object */
198 ret = nouveau_grobj_alloc(chan, 0xbeef502d, 0x502d, &screen->eng2d);
199 if (ret) {
200 NOUVEAU_ERR("Error creating 2D object: %d\n", ret);
201 nv50_screen_destroy(pscreen);
202 return NULL;
203 }
204 BIND_RING(chan, screen->eng2d, 2);
205
206 /* 3D object */
207 switch (chipset & 0xf0) {
208 case 0x50:
209 tesla_class = 0x5097;
210 break;
211 case 0x80:
212 case 0x90:
213 tesla_class = 0x8297;
214 break;
215 case 0xa0:
216 tesla_class = 0x8397;
217 break;
218 default:
219 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", chipset);
220 nv50_screen_destroy(pscreen);
221 return NULL;
222 }
223
224 if (tesla_class == 0) {
225 NOUVEAU_ERR("Unknown G8x chipset: NV%02x\n", chipset);
226 nv50_screen_destroy(pscreen);
227 return NULL;
228 }
229
230 ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
231 if (ret) {
232 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
233 nv50_screen_destroy(pscreen);
234 return NULL;
235 }
236 BIND_RING(chan, screen->tesla, 3);
237
238 /* Sync notifier */
239 ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
240 if (ret) {
241 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
242 nv50_screen_destroy(pscreen);
243 return NULL;
244 }
245
246 /* Static M2MF init */
247 so = so_new(32, 0);
248 so_method(so, screen->m2mf, 0x0180, 3);
249 so_data (so, screen->sync->handle);
250 so_data (so, chan->vram->handle);
251 so_data (so, chan->vram->handle);
252 so_emit(chan, so);
253 so_ref (NULL, &so);
254
255 /* Static 2D init */
256 so = so_new(64, 0);
257 so_method(so, screen->eng2d, NV50_2D_DMA_NOTIFY, 4);
258 so_data (so, screen->sync->handle);
259 so_data (so, chan->vram->handle);
260 so_data (so, chan->vram->handle);
261 so_data (so, chan->vram->handle);
262 so_method(so, screen->eng2d, NV50_2D_OPERATION, 1);
263 so_data (so, NV50_2D_OPERATION_SRCCOPY);
264 so_method(so, screen->eng2d, 0x0290, 1);
265 so_data (so, 0);
266 so_method(so, screen->eng2d, 0x0888, 1);
267 so_data (so, 1);
268 so_emit(chan, so);
269 so_ref(NULL, &so);
270
271 /* Static tesla init */
272 so = so_new(256, 20);
273
274 so_method(so, screen->tesla, 0x1558, 1);
275 so_data (so, 1);
276 so_method(so, screen->tesla, NV50TCL_DMA_NOTIFY, 1);
277 so_data (so, screen->sync->handle);
278 so_method(so, screen->tesla, NV50TCL_DMA_UNK0(0),
279 NV50TCL_DMA_UNK0__SIZE);
280 for (i = 0; i < NV50TCL_DMA_UNK0__SIZE; i++)
281 so_data(so, chan->vram->handle);
282 so_method(so, screen->tesla, NV50TCL_DMA_UNK1(0),
283 NV50TCL_DMA_UNK1__SIZE);
284 for (i = 0; i < NV50TCL_DMA_UNK1__SIZE; i++)
285 so_data(so, chan->vram->handle);
286 so_method(so, screen->tesla, 0x121c, 1);
287 so_data (so, 1);
288
289 so_method(so, screen->tesla, 0x13bc, 1);
290 so_data (so, 0x54);
291 so_method(so, screen->tesla, 0x13ac, 1);
292 so_data (so, 1);
293 so_method(so, screen->tesla, 0x16b8, 1);
294 so_data (so, 8);
295
296 /* constant buffers for immediates and VP/FP parameters */
297 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 128*4*4,
298 &screen->constbuf_misc[0]);
299 if (ret) {
300 nv50_screen_destroy(pscreen);
301 return NULL;
302 }
303
304 for (i = 0; i < 2; i++) {
305 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 128*4*4,
306 &screen->constbuf_parm[i]);
307 if (ret) {
308 nv50_screen_destroy(pscreen);
309 return NULL;
310 }
311 }
312
313 if (nouveau_resource_init(&screen->immd_heap[0], 0, 128) ||
314 nouveau_resource_init(&screen->parm_heap[0], 0, 128) ||
315 nouveau_resource_init(&screen->parm_heap[1], 0, 128))
316 {
317 NOUVEAU_ERR("Error initialising constant buffers.\n");
318 nv50_screen_destroy(pscreen);
319 return NULL;
320 }
321
322 /*
323 // map constant buffers:
324 // B = buffer ID (maybe more than 1 byte)
325 // N = CB index used in shader instruction
326 // P = program type (0 = VP, 2 = GP, 3 = FP)
327 so_method(so, screen->tesla, 0x1694, 1);
328 so_data (so, 0x000BBNP1);
329 */
330
331 so_method(so, screen->tesla, 0x1280, 3);
332 so_reloc (so, screen->constbuf_misc[0], 0, NOUVEAU_BO_VRAM |
333 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
334 so_reloc (so, screen->constbuf_misc[0], 0, NOUVEAU_BO_VRAM |
335 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
336 so_data (so, (NV50_CB_PMISC << 16) | 0x00000800);
337 so_method(so, screen->tesla, 0x1694, 1);
338 so_data (so, 0x00000001 | (NV50_CB_PMISC << 12));
339 so_method(so, screen->tesla, 0x1694, 1);
340 so_data (so, 0x00000031 | (NV50_CB_PMISC << 12));
341
342 so_method(so, screen->tesla, 0x1280, 3);
343 so_reloc (so, screen->constbuf_parm[0], 0, NOUVEAU_BO_VRAM |
344 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
345 so_reloc (so, screen->constbuf_parm[0], 0, NOUVEAU_BO_VRAM |
346 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
347 so_data (so, (NV50_CB_PVP << 16) | 0x00000800);
348 so_method(so, screen->tesla, 0x1694, 1);
349 so_data (so, 0x00000101 | (NV50_CB_PVP << 12));
350
351 so_method(so, screen->tesla, 0x1280, 3);
352 so_reloc (so, screen->constbuf_parm[1], 0, NOUVEAU_BO_VRAM |
353 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
354 so_reloc (so, screen->constbuf_parm[1], 0, NOUVEAU_BO_VRAM |
355 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
356 so_data (so, (NV50_CB_PFP << 16) | 0x00000800);
357 so_method(so, screen->tesla, 0x1694, 1);
358 so_data (so, 0x00000131 | (NV50_CB_PFP << 12));
359
360 /* Texture sampler/image unit setup - we abuse the constant buffer
361 * upload mechanism for the moment to upload data to the tex config
362 * blocks. At some point we *may* want to go the NVIDIA way of doing
363 * things?
364 */
365 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 32*8*4, &screen->tic);
366 if (ret) {
367 nv50_screen_destroy(pscreen);
368 return NULL;
369 }
370
371 so_method(so, screen->tesla, 0x1280, 3);
372 so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
373 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
374 so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
375 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
376 so_data (so, (NV50_CB_TIC << 16) | 0x0800);
377 so_method(so, screen->tesla, 0x1574, 3);
378 so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
379 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
380 so_reloc (so, screen->tic, 0, NOUVEAU_BO_VRAM |
381 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
382 so_data (so, 0x00000800);
383
384 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 32*8*4, &screen->tsc);
385 if (ret) {
386 nv50_screen_destroy(pscreen);
387 return NULL;
388 }
389
390 so_method(so, screen->tesla, 0x1280, 3);
391 so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
392 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
393 so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
394 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
395 so_data (so, (NV50_CB_TSC << 16) | 0x0800);
396 so_method(so, screen->tesla, 0x155c, 3);
397 so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
398 NOUVEAU_BO_RD | NOUVEAU_BO_HIGH, 0, 0);
399 so_reloc (so, screen->tsc, 0, NOUVEAU_BO_VRAM |
400 NOUVEAU_BO_RD | NOUVEAU_BO_LOW, 0, 0);
401 so_data (so, 0x00000800);
402
403
404 /* Vertex array limits - max them out */
405 for (i = 0; i < 16; i++) {
406 so_method(so, screen->tesla, 0x1080 + (i * 8), 2);
407 so_data (so, 0x000000ff);
408 so_data (so, 0xffffffff);
409 }
410
411 so_method(so, screen->tesla, NV50TCL_DEPTH_RANGE_NEAR, 2);
412 so_data (so, fui(0.0));
413 so_data (so, fui(1.0));
414
415 so_method(so, screen->tesla, 0x1234, 1);
416 so_data (so, 1);
417
418 so_emit(chan, so);
419 so_ref (so, &screen->static_init);
420 so_ref (NULL, &so);
421 nouveau_pushbuf_flush(chan, 0);
422
423 return pscreen;
424 }
425