2 * Copyright 2010 Christoph Bumiller
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "util/u_format.h"
24 #include "util/u_format_s3tc.h"
25 #include "pipe/p_screen.h"
27 #include "nv50_context.h"
28 #include "nv50_screen.h"
30 #include "nouveau/nv_object.xml.h"
32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
36 extern int nouveau_device_get_param(struct nouveau_device
*dev
,
37 uint64_t param
, uint64_t *value
);
40 nv50_screen_is_format_supported(struct pipe_screen
*pscreen
,
41 enum pipe_format format
,
42 enum pipe_texture_target target
,
43 unsigned sample_count
,
46 if (!(0x117 & (1 << sample_count
))) /* 0, 1, 2, 4 or 8 */
48 if (sample_count
== 8 && util_format_get_blocksizebits(format
) >= 128)
51 if (!util_format_is_supported(format
, bindings
))
55 case PIPE_FORMAT_Z16_UNORM
:
56 if (nv50_screen(pscreen
)->tesla
->grclass
< NVA0_3D
)
59 case PIPE_FORMAT_R8G8B8A8_UNORM
:
60 case PIPE_FORMAT_R8G8B8X8_UNORM
:
61 /* HACK: GL requires equal formats for MS resolve and window is BGRA */
62 if (bindings
& PIPE_BIND_RENDER_TARGET
)
68 /* transfers & shared are always supported */
69 bindings
&= ~(PIPE_BIND_TRANSFER_READ
|
70 PIPE_BIND_TRANSFER_WRITE
|
73 return (nv50_format_table
[format
].usage
& bindings
) == bindings
;
77 nv50_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
80 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
82 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
84 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
86 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
88 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
: /* shader support missing */
90 case PIPE_CAP_MIN_TEXEL_OFFSET
:
91 return 0 /* -8, TODO */;
92 case PIPE_CAP_MAX_TEXEL_OFFSET
:
93 return 0 /* +7, TODO */;
94 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
95 case PIPE_CAP_TEXTURE_SWIZZLE
:
96 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
97 case PIPE_CAP_NPOT_TEXTURES
:
98 case PIPE_CAP_ANISOTROPIC_FILTER
:
99 case PIPE_CAP_SCALED_RESOLVE
:
101 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
102 return nv50_screen(pscreen
)->tesla
->grclass
>= NVA0_3D
;
103 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
105 case PIPE_CAP_TWO_SIDED_STENCIL
:
106 case PIPE_CAP_DEPTH_CLAMP
:
107 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
108 case PIPE_CAP_POINT_SPRITE
:
113 case PIPE_CAP_MAX_RENDER_TARGETS
:
115 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL
:
117 case PIPE_CAP_TIMER_QUERY
:
118 case PIPE_CAP_OCCLUSION_QUERY
:
120 case PIPE_CAP_STREAM_OUTPUT
:
122 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
123 case PIPE_CAP_INDEP_BLEND_ENABLE
:
125 case PIPE_CAP_INDEP_BLEND_FUNC
:
126 return nv50_screen(pscreen
)->tesla
->grclass
>= NVA3_3D
;
127 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
128 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
130 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
131 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
133 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
135 case PIPE_CAP_PRIMITIVE_RESTART
:
136 case PIPE_CAP_TGSI_INSTANCEID
:
137 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
138 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
139 case PIPE_CAP_CONDITIONAL_RENDER
:
140 case PIPE_CAP_TEXTURE_BARRIER
:
143 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
149 nv50_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
150 enum pipe_shader_cap param
)
153 case PIPE_SHADER_VERTEX
:
154 case PIPE_SHADER_GEOMETRY
:
155 case PIPE_SHADER_FRAGMENT
:
162 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
163 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
164 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
165 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
167 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
169 case PIPE_SHADER_CAP_MAX_INPUTS
:
170 if (shader
== PIPE_SHADER_VERTEX
)
173 case PIPE_SHADER_CAP_MAX_CONSTS
:
175 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
177 case PIPE_SHADER_CAP_MAX_ADDRS
:
179 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
180 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
181 return shader
!= PIPE_SHADER_FRAGMENT
;
182 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
183 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
185 case PIPE_SHADER_CAP_MAX_PREDS
:
187 case PIPE_SHADER_CAP_MAX_TEMPS
:
188 return NV50_CAP_MAX_PROGRAM_TEMPS
;
189 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
191 case PIPE_SHADER_CAP_SUBROUTINES
:
192 return 0; /* please inline, or provide function declarations */
193 case PIPE_SHADER_CAP_INTEGERS
:
195 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
198 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param
);
204 nv50_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_cap param
)
207 case PIPE_CAP_MAX_LINE_WIDTH
:
208 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
210 case PIPE_CAP_MAX_POINT_WIDTH
:
211 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
213 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
215 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
218 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param
);
224 nv50_screen_destroy(struct pipe_screen
*pscreen
)
226 struct nv50_screen
*screen
= nv50_screen(pscreen
);
228 if (screen
->base
.fence
.current
) {
229 nouveau_fence_wait(screen
->base
.fence
.current
);
230 nouveau_fence_ref (NULL
, &screen
->base
.fence
.current
);
232 screen
->base
.channel
->user_private
= NULL
;
234 FREE(screen
->blitctx
);
236 nouveau_bo_ref(NULL
, &screen
->code
);
237 nouveau_bo_ref(NULL
, &screen
->tls_bo
);
238 nouveau_bo_ref(NULL
, &screen
->stack_bo
);
239 nouveau_bo_ref(NULL
, &screen
->txc
);
240 nouveau_bo_ref(NULL
, &screen
->uniforms
);
241 nouveau_bo_ref(NULL
, &screen
->fence
.bo
);
243 nouveau_resource_destroy(&screen
->vp_code_heap
);
244 nouveau_resource_destroy(&screen
->gp_code_heap
);
245 nouveau_resource_destroy(&screen
->fp_code_heap
);
247 if (screen
->tic
.entries
)
248 FREE(screen
->tic
.entries
);
250 nouveau_mm_destroy(screen
->mm_VRAM_fe0
);
252 nouveau_grobj_free(&screen
->tesla
);
253 nouveau_grobj_free(&screen
->eng2d
);
254 nouveau_grobj_free(&screen
->m2mf
);
256 nouveau_notifier_free(&screen
->sync
);
258 nouveau_screen_fini(&screen
->base
);
264 nv50_screen_fence_emit(struct pipe_screen
*pscreen
, u32
*sequence
)
266 struct nv50_screen
*screen
= nv50_screen(pscreen
);
267 struct nouveau_channel
*chan
= screen
->base
.channel
;
269 MARK_RING (chan
, 5, 2);
271 /* we need to do it after possible flush in MARK_RING */
272 *sequence
= ++screen
->base
.fence
.sequence
;
274 BEGIN_RING(chan
, RING_3D(QUERY_ADDRESS_HIGH
), 4);
275 OUT_RELOCh(chan
, screen
->fence
.bo
, 0, NOUVEAU_BO_WR
);
276 OUT_RELOCl(chan
, screen
->fence
.bo
, 0, NOUVEAU_BO_WR
);
277 OUT_RING (chan
, *sequence
);
278 OUT_RING (chan
, NV50_3D_QUERY_GET_MODE_WRITE_UNK0
|
279 NV50_3D_QUERY_GET_UNK4
|
280 NV50_3D_QUERY_GET_UNIT_CROP
|
281 NV50_3D_QUERY_GET_TYPE_QUERY
|
282 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO
|
283 NV50_3D_QUERY_GET_SHORT
);
287 nv50_screen_fence_update(struct pipe_screen
*pscreen
)
289 struct nv50_screen
*screen
= nv50_screen(pscreen
);
290 return screen
->fence
.map
[0];
293 #define FAIL_SCREEN_INIT(str, err) \
295 NOUVEAU_ERR(str, err); \
296 nv50_screen_destroy(pscreen); \
301 nv50_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
303 struct nv50_screen
*screen
;
304 struct nouveau_channel
*chan
;
305 struct pipe_screen
*pscreen
;
307 uint32_t tesla_class
;
308 unsigned stack_size
, max_warps
, tls_space
;
312 screen
= CALLOC_STRUCT(nv50_screen
);
315 pscreen
= &screen
->base
.base
;
317 screen
->base
.sysmem_bindings
= PIPE_BIND_CONSTANT_BUFFER
;
319 ret
= nouveau_screen_init(&screen
->base
, dev
);
321 FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret
);
323 chan
= screen
->base
.channel
;
324 chan
->user_private
= screen
;
326 pscreen
->winsys
= ws
;
327 pscreen
->destroy
= nv50_screen_destroy
;
328 pscreen
->context_create
= nv50_create
;
329 pscreen
->is_format_supported
= nv50_screen_is_format_supported
;
330 pscreen
->get_param
= nv50_screen_get_param
;
331 pscreen
->get_shader_param
= nv50_screen_get_shader_param
;
332 pscreen
->get_paramf
= nv50_screen_get_paramf
;
334 nv50_screen_init_resource_functions(pscreen
);
336 nouveau_screen_init_vdec(&screen
->base
);
338 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_GART
| NOUVEAU_BO_MAP
, 0, 4096,
342 nouveau_bo_map(screen
->fence
.bo
, NOUVEAU_BO_RDWR
);
343 screen
->fence
.map
= screen
->fence
.bo
->map
;
344 nouveau_bo_unmap(screen
->fence
.bo
);
345 screen
->base
.fence
.emit
= nv50_screen_fence_emit
;
346 screen
->base
.fence
.update
= nv50_screen_fence_update
;
348 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
350 FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret
);
352 ret
= nouveau_grobj_alloc(chan
, 0xbeef5039, NV50_M2MF
, &screen
->m2mf
);
354 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret
);
356 BIND_RING (chan
, screen
->m2mf
, NV50_SUBCH_MF
);
357 BEGIN_RING(chan
, RING_MF_(NV04_M2MF_DMA_NOTIFY
), 3);
358 OUT_RING (chan
, screen
->sync
->handle
);
359 OUT_RING (chan
, chan
->vram
->handle
);
360 OUT_RING (chan
, chan
->vram
->handle
);
362 ret
= nouveau_grobj_alloc(chan
, 0xbeef502d, NV50_2D
, &screen
->eng2d
);
364 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret
);
366 BIND_RING (chan
, screen
->eng2d
, NV50_SUBCH_2D
);
367 BEGIN_RING(chan
, RING_2D(DMA_NOTIFY
), 4);
368 OUT_RING (chan
, screen
->sync
->handle
);
369 OUT_RING (chan
, chan
->vram
->handle
);
370 OUT_RING (chan
, chan
->vram
->handle
);
371 OUT_RING (chan
, chan
->vram
->handle
);
372 BEGIN_RING(chan
, RING_2D(OPERATION
), 1);
373 OUT_RING (chan
, NV50_2D_OPERATION_SRCCOPY
);
374 BEGIN_RING(chan
, RING_2D(CLIP_ENABLE
), 1);
376 BEGIN_RING(chan
, RING_2D(COLOR_KEY_ENABLE
), 1);
378 BEGIN_RING(chan
, RING_2D_(0x0888), 1);
381 switch (dev
->chipset
& 0xf0) {
383 tesla_class
= NV50_3D
;
387 tesla_class
= NV84_3D
;
390 switch (dev
->chipset
) {
394 tesla_class
= NVA0_3D
;
397 tesla_class
= NVAF_3D
;
400 tesla_class
= NVA3_3D
;
405 FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev
->chipset
);
409 ret
= nouveau_grobj_alloc(chan
, 0xbeef5097, tesla_class
, &screen
->tesla
);
411 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret
);
413 BIND_RING (chan
, screen
->tesla
, NV50_SUBCH_3D
);
415 BEGIN_RING(chan
, RING_3D(COND_MODE
), 1);
416 OUT_RING (chan
, NV50_3D_COND_MODE_ALWAYS
);
418 BEGIN_RING(chan
, RING_3D(DMA_NOTIFY
), 1);
419 OUT_RING (chan
, screen
->sync
->handle
);
420 BEGIN_RING(chan
, RING_3D(DMA_ZETA
), 11);
421 for (i
= 0; i
< 11; ++i
)
422 OUT_RING(chan
, chan
->vram
->handle
);
423 BEGIN_RING(chan
, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN
);
424 for (i
= 0; i
< NV50_3D_DMA_COLOR__LEN
; ++i
)
425 OUT_RING(chan
, chan
->vram
->handle
);
427 BEGIN_RING(chan
, RING_3D(REG_MODE
), 1);
428 OUT_RING (chan
, NV50_3D_REG_MODE_STRIPED
);
429 BEGIN_RING(chan
, RING_3D(UNK1400_LANES
), 1);
430 OUT_RING (chan
, 0xf);
432 BEGIN_RING(chan
, RING_3D(RT_CONTROL
), 1);
435 BEGIN_RING(chan
, RING_3D(CSAA_ENABLE
), 1);
437 BEGIN_RING(chan
, RING_3D(MULTISAMPLE_ENABLE
), 1);
439 BEGIN_RING(chan
, RING_3D(MULTISAMPLE_MODE
), 1);
440 OUT_RING (chan
, NV50_3D_MULTISAMPLE_MODE_MS1
);
441 BEGIN_RING(chan
, RING_3D(MULTISAMPLE_CTRL
), 1);
443 BEGIN_RING(chan
, RING_3D(LINE_LAST_PIXEL
), 1);
445 BEGIN_RING(chan
, RING_3D(BLEND_SEPARATE_ALPHA
), 1);
448 if (tesla_class
>= NVA0_3D
) {
449 BEGIN_RING(chan
, RING_3D_(NVA0_3D_TEX_MISC
), 1);
450 OUT_RING (chan
, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP
);
453 BEGIN_RING(chan
, RING_3D(SCREEN_Y_CONTROL
), 1);
455 BEGIN_RING(chan
, RING_3D(WINDOW_OFFSET_X
), 2);
458 BEGIN_RING(chan
, RING_3D(ZCULL_REGION
), 1); /* deactivate ZCULL */
459 OUT_RING (chan
, 0x3f);
461 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16,
462 3 << NV50_CODE_BO_SIZE_LOG2
, &screen
->code
);
466 nouveau_resource_init(&screen
->vp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
467 nouveau_resource_init(&screen
->gp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
468 nouveau_resource_init(&screen
->fp_code_heap
, 0, 1 << NV50_CODE_BO_SIZE_LOG2
);
470 base
= 1 << NV50_CODE_BO_SIZE_LOG2
;
472 BEGIN_RING(chan
, RING_3D(VP_ADDRESS_HIGH
), 2);
473 OUT_RELOCh(chan
, screen
->code
, base
* 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
474 OUT_RELOCl(chan
, screen
->code
, base
* 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
476 BEGIN_RING(chan
, RING_3D(FP_ADDRESS_HIGH
), 2);
477 OUT_RELOCh(chan
, screen
->code
, base
* 1, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
478 OUT_RELOCl(chan
, screen
->code
, base
* 1, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
480 BEGIN_RING(chan
, RING_3D(GP_ADDRESS_HIGH
), 2);
481 OUT_RELOCh(chan
, screen
->code
, base
* 2, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
482 OUT_RELOCl(chan
, screen
->code
, base
* 2, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
484 nouveau_device_get_param(dev
, NOUVEAU_GETPARAM_GRAPH_UNITS
, &value
);
486 max_warps
= util_bitcount(value
& 0xffff);
487 max_warps
*= util_bitcount((value
>> 24) & 0xf) * 32;
489 stack_size
= max_warps
* 64 * 8;
491 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, stack_size
,
494 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret
);
496 BEGIN_RING(chan
, RING_3D(STACK_ADDRESS_HIGH
), 3);
497 OUT_RELOCh(chan
, screen
->stack_bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
498 OUT_RELOCl(chan
, screen
->stack_bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
501 tls_space
= NV50_CAP_MAX_PROGRAM_TEMPS
* 16;
503 screen
->tls_size
= tls_space
* max_warps
* 32;
505 debug_printf("max_warps = %i, tls_size = %"PRIu64
" KiB\n",
506 max_warps
, screen
->tls_size
>> 10);
508 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, screen
->tls_size
,
511 FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret
);
513 BEGIN_RING(chan
, RING_3D(LOCAL_ADDRESS_HIGH
), 3);
514 OUT_RELOCh(chan
, screen
->tls_bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
515 OUT_RELOCl(chan
, screen
->tls_bo
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RDWR
);
516 OUT_RING (chan
, util_logbase2(tls_space
/ 8));
518 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 4 << 16,
523 BEGIN_RING(chan
, RING_3D(CB_DEF_ADDRESS_HIGH
), 3);
524 OUT_RELOCh(chan
, screen
->uniforms
, 0 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
525 OUT_RELOCl(chan
, screen
->uniforms
, 0 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
526 OUT_RING (chan
, (NV50_CB_PVP
<< 16) | 0x0000);
528 BEGIN_RING(chan
, RING_3D(CB_DEF_ADDRESS_HIGH
), 3);
529 OUT_RELOCh(chan
, screen
->uniforms
, 1 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
530 OUT_RELOCl(chan
, screen
->uniforms
, 1 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
531 OUT_RING (chan
, (NV50_CB_PGP
<< 16) | 0x0000);
533 BEGIN_RING(chan
, RING_3D(CB_DEF_ADDRESS_HIGH
), 3);
534 OUT_RELOCh(chan
, screen
->uniforms
, 2 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
535 OUT_RELOCl(chan
, screen
->uniforms
, 2 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
536 OUT_RING (chan
, (NV50_CB_PFP
<< 16) | 0x0000);
538 BEGIN_RING(chan
, RING_3D(CB_DEF_ADDRESS_HIGH
), 3);
539 OUT_RELOCh(chan
, screen
->uniforms
, 3 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
540 OUT_RELOCl(chan
, screen
->uniforms
, 3 << 16, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
541 OUT_RING (chan
, (NV50_CB_AUX
<< 16) | 0x0200);
543 BEGIN_RING_NI(chan
, RING_3D(SET_PROGRAM_CB
), 6);
544 OUT_RING (chan
, (NV50_CB_PVP
<< 12) | 0x001);
545 OUT_RING (chan
, (NV50_CB_PGP
<< 12) | 0x021);
546 OUT_RING (chan
, (NV50_CB_PFP
<< 12) | 0x031);
547 OUT_RING (chan
, (NV50_CB_AUX
<< 12) | 0xf01);
548 OUT_RING (chan
, (NV50_CB_AUX
<< 12) | 0xf21);
549 OUT_RING (chan
, (NV50_CB_AUX
<< 12) | 0xf31);
551 ret
= nouveau_bo_new(dev
, NOUVEAU_BO_VRAM
, 1 << 16, 3 << 16,
554 FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret
);
556 /* max TIC (bits 4:8) & TSC bindings, per program type */
557 for (i
= 0; i
< 3; ++i
) {
558 BEGIN_RING(chan
, RING_3D(TEX_LIMITS(i
)), 1);
559 OUT_RING (chan
, 0x54);
562 BEGIN_RING(chan
, RING_3D(TIC_ADDRESS_HIGH
), 3);
563 OUT_RELOCh(chan
, screen
->txc
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
564 OUT_RELOCl(chan
, screen
->txc
, 0, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
565 OUT_RING (chan
, NV50_TIC_MAX_ENTRIES
- 1);
567 BEGIN_RING(chan
, RING_3D(TSC_ADDRESS_HIGH
), 3);
568 OUT_RELOCh(chan
, screen
->txc
, 65536, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
569 OUT_RELOCl(chan
, screen
->txc
, 65536, NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
);
570 OUT_RING (chan
, NV50_TSC_MAX_ENTRIES
- 1);
572 BEGIN_RING(chan
, RING_3D(LINKED_TSC
), 1);
575 BEGIN_RING(chan
, RING_3D(CLIP_RECTS_EN
), 1);
577 BEGIN_RING(chan
, RING_3D(CLIP_RECTS_MODE
), 1);
578 OUT_RING (chan
, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY
);
579 BEGIN_RING(chan
, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
580 for (i
= 0; i
< 8 * 2; ++i
)
582 BEGIN_RING(chan
, RING_3D(CLIPID_ENABLE
), 1);
585 BEGIN_RING(chan
, RING_3D(VIEWPORT_TRANSFORM_EN
), 1);
587 BEGIN_RING(chan
, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
588 OUT_RINGf (chan
, 0.0f
);
589 OUT_RINGf (chan
, 1.0f
);
591 BEGIN_RING(chan
, RING_3D(VIEW_VOLUME_CLIP_CTRL
), 1);
592 #ifdef NV50_SCISSORS_CLIPPING
593 OUT_RING (chan
, 0x0000);
595 OUT_RING (chan
, 0x1080);
598 BEGIN_RING(chan
, RING_3D(CLEAR_FLAGS
), 1);
599 OUT_RING (chan
, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT
);
601 /* We use scissors instead of exact view volume clipping,
602 * so they're always enabled.
604 BEGIN_RING(chan
, RING_3D(SCISSOR_ENABLE(0)), 3);
606 OUT_RING (chan
, 8192 << 16);
607 OUT_RING (chan
, 8192 << 16);
609 BEGIN_RING(chan
, RING_3D(RASTERIZE_ENABLE
), 1);
611 BEGIN_RING(chan
, RING_3D(POINT_RASTER_RULES
), 1);
612 OUT_RING (chan
, NV50_3D_POINT_RASTER_RULES_OGL
);
613 BEGIN_RING(chan
, RING_3D(FRAG_COLOR_CLAMP_EN
), 1);
614 OUT_RING (chan
, 0x11111111);
615 BEGIN_RING(chan
, RING_3D(EDGEFLAG_ENABLE
), 1);
620 screen
->tic
.entries
= CALLOC(4096, sizeof(void *));
621 screen
->tsc
.entries
= screen
->tic
.entries
+ 2048;
623 screen
->mm_VRAM_fe0
= nouveau_mm_create(dev
, NOUVEAU_BO_VRAM
, 0xfe0);
625 if (!nv50_blitctx_create(screen
))
628 nouveau_fence_new(&screen
->base
, &screen
->base
.fence
.current
, FALSE
);
633 nv50_screen_destroy(pscreen
);
638 nv50_screen_make_buffers_resident(struct nv50_screen
*screen
)
640 struct nouveau_channel
*chan
= screen
->base
.channel
;
642 const unsigned flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
;
644 MARK_RING(chan
, 0, 5);
645 nouveau_bo_validate(chan
, screen
->code
, flags
);
646 nouveau_bo_validate(chan
, screen
->uniforms
, flags
);
647 nouveau_bo_validate(chan
, screen
->txc
, flags
);
648 nouveau_bo_validate(chan
, screen
->tls_bo
, flags
);
649 nouveau_bo_validate(chan
, screen
->stack_bo
, flags
);
653 nv50_screen_tic_alloc(struct nv50_screen
*screen
, void *entry
)
655 int i
= screen
->tic
.next
;
657 while (screen
->tic
.lock
[i
/ 32] & (1 << (i
% 32)))
658 i
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
660 screen
->tic
.next
= (i
+ 1) & (NV50_TIC_MAX_ENTRIES
- 1);
662 if (screen
->tic
.entries
[i
])
663 nv50_tic_entry(screen
->tic
.entries
[i
])->id
= -1;
665 screen
->tic
.entries
[i
] = entry
;
670 nv50_screen_tsc_alloc(struct nv50_screen
*screen
, void *entry
)
672 int i
= screen
->tsc
.next
;
674 while (screen
->tsc
.lock
[i
/ 32] & (1 << (i
% 32)))
675 i
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
677 screen
->tsc
.next
= (i
+ 1) & (NV50_TSC_MAX_ENTRIES
- 1);
679 if (screen
->tsc
.entries
[i
])
680 nv50_tsc_entry(screen
->tsc
.entries
[i
])->id
= -1;
682 screen
->tsc
.entries
[i
] = entry
;