src/gallium/drivers/nv50/nv50_screen.c

   1 /*
   2  * Copyright 2010 Christoph Bumiller
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #include "util/u_format_s3tc.h"
  24 #include "pipe/p_screen.h"
  25
  26 #include "nv50_fence.h"
  27 #include "nv50_context.h"
  28 #include "nv50_screen.h"
  29
  30 #include "nouveau/nv_object.xml.h"
  31
  32 #ifndef NOUVEAU_GETPARAM_GRAPH_UNITS
  33 # define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  34 #endif
  35
  36 extern int nouveau_device_get_param(struct nouveau_device *dev,
  37                                     uint64_t param, uint64_t *value);
  38
  39 static boolean
  40 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
  41                                 enum pipe_format format,
  42                                 enum pipe_texture_target target,
  43                                 unsigned sample_count,
  44                                 unsigned bindings, unsigned geom_flags)
  45 {
  46    if (sample_count > 1)
  47       return FALSE;
  48
  49    if (!util_format_s3tc_enabled) {
  50       switch (format) {
  51       case PIPE_FORMAT_DXT1_RGB:
  52       case PIPE_FORMAT_DXT1_RGBA:
  53       case PIPE_FORMAT_DXT3_RGBA:
  54       case PIPE_FORMAT_DXT5_RGBA:
  55          return FALSE;
  56       default:
  57          break;
  58       }
  59    }
  60
  61    switch (format) {
  62    case PIPE_FORMAT_Z16_UNORM:
  63       if ((nouveau_screen(pscreen)->device->chipset & 0xf0) != 0xa0)
  64          return FALSE;
  65       break;
  66    default:
  67       break;
  68    }
  69
  70    /* transfers & shared are always supported */
  71    bindings &= ~(PIPE_BIND_TRANSFER_READ |
  72                  PIPE_BIND_TRANSFER_WRITE |
  73                  PIPE_BIND_SHARED);
  74
  75    return (nv50_format_table[format].usage & bindings) == bindings;
  76 }
  77
  78 static int
  79 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  80 {
  81    switch (param) {
  82    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  83    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  84       return 32;
  85    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  86       return 64;
  87    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  88       return 13;
  89    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  90       return 10;
  91    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  92       return 13;
  93    case PIPE_CAP_ARRAY_TEXTURES: /* shader support missing */
  94       return 0;
  95    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  96    case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  97    case PIPE_CAP_TEXTURE_SWIZZLE:
  98    case PIPE_CAP_TEXTURE_SHADOW_MAP:
  99    case PIPE_CAP_NPOT_TEXTURES:
 100    case PIPE_CAP_ANISOTROPIC_FILTER:
 101       return 1;
 102    case PIPE_CAP_TWO_SIDED_STENCIL:
 103    case PIPE_CAP_DEPTH_CLAMP:
 104    case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 105    case PIPE_CAP_POINT_SPRITE:
 106       return 1;
 107    case PIPE_CAP_GLSL:
 108    case PIPE_CAP_SM3:
 109       return 1;
 110    case PIPE_CAP_MAX_RENDER_TARGETS:
 111       return 8;
 112    case PIPE_CAP_TIMER_QUERY:
 113    case PIPE_CAP_OCCLUSION_QUERY:
 114       return 1;
 115    case PIPE_CAP_STREAM_OUTPUT:
 116       return 0;
 117    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 118    case PIPE_CAP_INDEP_BLEND_ENABLE:
 119    case PIPE_CAP_INDEP_BLEND_FUNC:
 120       return 1;
 121    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 122    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 123       return 1;
 124    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 125    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 126       return 0;
 127    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 128       return 0;
 129    case PIPE_CAP_PRIMITIVE_RESTART:
 130    case PIPE_CAP_INSTANCED_DRAWING:
 131       return 1;
 132    default:
 133       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 134       return 0;
 135    }
 136 }
 137
 138 static int
 139 nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 140                              enum pipe_shader_cap param)
 141 {
 142    switch (shader) {
 143    case PIPE_SHADER_VERTEX:
 144    case PIPE_SHADER_GEOMETRY:
 145    case PIPE_SHADER_FRAGMENT:
 146       break;
 147    default:
 148       return 0;
 149    }
 150
 151    switch (param) {
 152    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 153    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 154    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 155    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 156       return 16384;
 157    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 158       return 4;
 159    case PIPE_SHADER_CAP_MAX_INPUTS:
 160       if (shader == PIPE_SHADER_VERTEX)
 161          return 32;
 162       return 0x300 / 16;
 163    case PIPE_SHADER_CAP_MAX_CONSTS:
 164       return 65536 / 16;
 165    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 166       return 14;
 167    case PIPE_SHADER_CAP_MAX_ADDRS:
 168       return 1;
 169    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 170    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 171       return shader != PIPE_SHADER_FRAGMENT;
 172    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 173    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 174       return 1;
 175    case PIPE_SHADER_CAP_MAX_PREDS:
 176       return 0;
 177    case PIPE_SHADER_CAP_MAX_TEMPS:
 178       return NV50_CAP_MAX_PROGRAM_TEMPS;
 179    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 180       return 1;
 181    case PIPE_SHADER_CAP_SUBROUTINES:
 182       return 0; /* please inline, or provide function declarations */
 183    default:
 184       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
 185       return 0;
 186    }
 187 }
 188
 189 static float
 190 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 191 {
 192    switch (param) {
 193    case PIPE_CAP_MAX_LINE_WIDTH:
 194    case PIPE_CAP_MAX_LINE_WIDTH_AA:
 195       return 10.0f;
 196    case PIPE_CAP_MAX_POINT_WIDTH:
 197    case PIPE_CAP_MAX_POINT_WIDTH_AA:
 198       return 64.0f;
 199    case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 200       return 16.0f;
 201    case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 202       return 4.0f;
 203    default:
 204       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
 205       return 0.0f;
 206    }
 207 }
 208
 209 static void
 210 nv50_screen_destroy(struct pipe_screen *pscreen)
 211 {
 212    struct nv50_screen *screen = nv50_screen(pscreen);
 213
 214    if (screen->fence.current) {
 215       nv50_fence_wait(screen->fence.current);
 216       nv50_fence_reference(&screen->fence.current, NULL);
 217    }
 218
 219    nouveau_bo_ref(NULL, &screen->code);
 220    nouveau_bo_ref(NULL, &screen->tls_bo);
 221    nouveau_bo_ref(NULL, &screen->stack_bo);
 222    nouveau_bo_ref(NULL, &screen->txc);
 223    nouveau_bo_ref(NULL, &screen->uniforms);
 224    nouveau_bo_ref(NULL, &screen->fence.bo);
 225
 226    nouveau_resource_destroy(&screen->vp_code_heap);
 227    nouveau_resource_destroy(&screen->gp_code_heap);
 228    nouveau_resource_destroy(&screen->fp_code_heap);
 229
 230    if (screen->tic.entries)
 231       FREE(screen->tic.entries);
 232
 233    nv50_mm_destroy(screen->mm_GART);
 234    nv50_mm_destroy(screen->mm_VRAM);
 235    nv50_mm_destroy(screen->mm_VRAM_fe0);
 236
 237    nouveau_grobj_free(&screen->tesla);
 238    nouveau_grobj_free(&screen->eng2d);
 239    nouveau_grobj_free(&screen->m2mf);
 240
 241    nouveau_notifier_free(&screen->sync);
 242
 243    nouveau_screen_fini(&screen->base);
 244
 245    FREE(screen);
 246 }
 247
 248 static void
 249 nv50_screen_fence_reference(struct pipe_screen *pscreen,
 250                             struct pipe_fence_handle **ptr,
 251                             struct pipe_fence_handle *fence)
 252 {
 253    nv50_fence_reference((struct nv50_fence **)ptr, nv50_fence(fence));
 254 }
 255
 256 static int
 257 nv50_screen_fence_signalled(struct pipe_screen *pscreen,
 258                             struct pipe_fence_handle *fence,
 259                             unsigned flags)
 260 {
 261    return !(nv50_fence_signalled(nv50_fence(fence)));
 262 }
 263
 264 static int
 265 nv50_screen_fence_finish(struct pipe_screen *pscreen,
 266                          struct pipe_fence_handle *fence,
 267                          unsigned flags)
 268 {
 269    return nv50_fence_wait((struct nv50_fence *)fence) != TRUE;
 270 }
 271
 272 #define FAIL_SCREEN_INIT(str, err)                    \
 273    do {                                               \
 274       NOUVEAU_ERR(str, err);                          \
 275       nv50_screen_destroy(pscreen);                   \
 276       return NULL;                                    \
 277    } while(0)
 278
 279 struct pipe_screen *
 280 nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 281 {
 282    struct nv50_screen *screen;
 283    struct nouveau_channel *chan;
 284    struct pipe_screen *pscreen;
 285    uint64_t value;
 286    uint32_t tesla_class;
 287    unsigned stack_size, max_warps, tls_space;
 288    int ret;
 289    unsigned i;
 290
 291    screen = CALLOC_STRUCT(nv50_screen);
 292    if (!screen)
 293       return NULL;
 294    pscreen = &screen->base.base;
 295
 296    ret = nouveau_screen_init(&screen->base, dev);
 297    if (ret)
 298       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 299
 300    chan = screen->base.channel;
 301
 302    pscreen->winsys = ws;
 303    pscreen->destroy = nv50_screen_destroy;
 304    pscreen->context_create = nv50_create;
 305    pscreen->is_format_supported = nv50_screen_is_format_supported;
 306    pscreen->get_param = nv50_screen_get_param;
 307    pscreen->get_shader_param = nv50_screen_get_shader_param;
 308    pscreen->get_paramf = nv50_screen_get_paramf;
 309    pscreen->fence_reference = nv50_screen_fence_reference;
 310    pscreen->fence_signalled = nv50_screen_fence_signalled;
 311    pscreen->fence_finish = nv50_screen_fence_finish;
 312
 313    nv50_screen_init_resource_functions(pscreen);
 314
 315    screen->base.vertex_buffer_flags = screen->base.index_buffer_flags =
 316       NOUVEAU_BO_GART;
 317
 318    ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
 319                         &screen->fence.bo);
 320    if (ret)
 321       goto fail;
 322    nouveau_bo_map(screen->fence.bo, NOUVEAU_BO_RDWR);
 323    screen->fence.map = screen->fence.bo->map;
 324    nouveau_bo_unmap(screen->fence.bo);
 325
 326    ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 327    if (ret)
 328       FAIL_SCREEN_INIT("Error allocating notifier: %d\n", ret);
 329
 330    ret = nouveau_grobj_alloc(chan, 0xbeef5039, NV50_M2MF, &screen->m2mf);
 331    if (ret)
 332       FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret);
 333
 334    BIND_RING (chan, screen->m2mf, NV50_SUBCH_MF);
 335    BEGIN_RING(chan, RING_MF_(NV04_M2MF_DMA_NOTIFY), 3);
 336    OUT_RING  (chan, screen->sync->handle);
 337    OUT_RING  (chan, chan->vram->handle);
 338    OUT_RING  (chan, chan->vram->handle);
 339
 340    ret = nouveau_grobj_alloc(chan, 0xbeef502d, NV50_2D, &screen->eng2d);
 341    if (ret)
 342       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret);
 343
 344    BIND_RING (chan, screen->eng2d, NV50_SUBCH_2D);
 345    BEGIN_RING(chan, RING_2D(DMA_NOTIFY), 4);
 346    OUT_RING  (chan, screen->sync->handle);
 347    OUT_RING  (chan, chan->vram->handle);
 348    OUT_RING  (chan, chan->vram->handle);
 349    OUT_RING  (chan, chan->vram->handle);
 350    BEGIN_RING(chan, RING_2D(OPERATION), 1);
 351    OUT_RING  (chan, NV50_2D_OPERATION_SRCCOPY);
 352    BEGIN_RING(chan, RING_2D(CLIP_ENABLE), 1);
 353    OUT_RING  (chan, 0);
 354    BEGIN_RING(chan, RING_2D(COLOR_KEY_ENABLE), 1);
 355    OUT_RING  (chan, 0);
 356    BEGIN_RING(chan, RING_2D_(0x0888), 1);
 357    OUT_RING  (chan, 1);
 358
 359    switch (dev->chipset & 0xf0) {
 360    case 0x50:
 361       tesla_class = NV50_3D;
 362       break;
 363    case 0x80:
 364    case 0x90:
 365       tesla_class = NV84_3D;
 366       break;
 367    case 0xa0:
 368       switch (dev->chipset) {
 369       case 0xa0:
 370       case 0xaa:
 371       case 0xac:
 372          tesla_class = NVA0_3D;
 373          break;
 374       case 0xaf:
 375          tesla_class = NVAF_3D;
 376          break;
 377       default:
 378          tesla_class = NVA3_3D;
 379          break;
 380       }
 381       break;
 382    default:
 383       FAIL_SCREEN_INIT("Not a known NV50 chipset: NV%02x\n", dev->chipset);
 384       break;
 385    }
 386
 387    ret = nouveau_grobj_alloc(chan, 0xbeef5097, tesla_class, &screen->tesla);
 388    if (ret)
 389       FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret);
 390
 391    BIND_RING (chan, screen->tesla, NV50_SUBCH_3D);
 392
 393    BEGIN_RING(chan, RING_3D(COND_MODE), 1);
 394    OUT_RING  (chan, NV50_3D_COND_MODE_ALWAYS);
 395
 396    BEGIN_RING(chan, RING_3D(DMA_NOTIFY), 1);
 397    OUT_RING  (chan, screen->sync->handle);
 398    BEGIN_RING(chan, RING_3D(DMA_ZETA), 11);
 399    for (i = 0; i < 11; ++i)
 400       OUT_RING(chan, chan->vram->handle);
 401    BEGIN_RING(chan, RING_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
 402    for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
 403       OUT_RING(chan, chan->vram->handle);
 404
 405    BEGIN_RING(chan, RING_3D(REG_MODE), 1);
 406    OUT_RING  (chan, NV50_3D_REG_MODE_STRIPED);
 407    BEGIN_RING(chan, RING_3D(UNK1400_LANES), 1);
 408    OUT_RING  (chan, 0xf);
 409
 410    BEGIN_RING(chan, RING_3D(RT_CONTROL), 1);
 411    OUT_RING  (chan, 1);
 412
 413    BEGIN_RING(chan, RING_3D(CSAA_ENABLE), 1);
 414    OUT_RING  (chan, 0);
 415    BEGIN_RING(chan, RING_3D(MULTISAMPLE_ENABLE), 1);
 416    OUT_RING  (chan, 0);
 417    BEGIN_RING(chan, RING_3D(MULTISAMPLE_MODE), 1);
 418    OUT_RING  (chan, NV50_3D_MULTISAMPLE_MODE_MS1);
 419    BEGIN_RING(chan, RING_3D(MULTISAMPLE_CTRL), 1);
 420    OUT_RING  (chan, 0);
 421
 422    BEGIN_RING(chan, RING_3D(SCREEN_Y_CONTROL), 1);
 423    OUT_RING  (chan, 0);
 424    BEGIN_RING(chan, RING_3D(WINDOW_OFFSET_X), 2);
 425    OUT_RING  (chan, 0);
 426    OUT_RING  (chan, 0);
 427    BEGIN_RING(chan, RING_3D(ZCULL_REGION), 1); /* deactivate ZCULL */
 428    OUT_RING  (chan, 0x3f);
 429
 430    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, &screen->code);
 431    if (ret)
 432       goto fail;
 433
 434    nouveau_resource_init(&screen->vp_code_heap, 0, 1 << 16);
 435    nouveau_resource_init(&screen->gp_code_heap, 0, 1 << 16);
 436    nouveau_resource_init(&screen->fp_code_heap, 0, 1 << 16);
 437
 438    BEGIN_RING(chan, RING_3D(VP_ADDRESS_HIGH), 2);
 439    OUT_RELOCh(chan, screen->code, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 440    OUT_RELOCl(chan, screen->code, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 441
 442    BEGIN_RING(chan, RING_3D(FP_ADDRESS_HIGH), 2);
 443    OUT_RELOCh(chan, screen->code, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 444    OUT_RELOCl(chan, screen->code, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 445
 446    BEGIN_RING(chan, RING_3D(GP_ADDRESS_HIGH), 2);
 447    OUT_RELOCh(chan, screen->code, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 448    OUT_RELOCl(chan, screen->code, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 449
 450    nouveau_device_get_param(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
 451
 452    max_warps  = util_bitcount(value & 0xffff);
 453    max_warps *= util_bitcount((value >> 24) & 0xf) * 32;
 454
 455    stack_size = max_warps * 64 * 8;
 456
 457    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size,
 458                         &screen->stack_bo);
 459    if (ret)
 460       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 461
 462    BEGIN_RING(chan, RING_3D(STACK_ADDRESS_HIGH), 3);
 463    OUT_RELOCh(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 464    OUT_RELOCl(chan, screen->stack_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 465    OUT_RING  (chan, 4);
 466
 467    tls_space = NV50_CAP_MAX_PROGRAM_TEMPS * 16;
 468
 469    screen->tls_size = tls_space * max_warps * 32;
 470
 471    debug_printf("max_warps = %i, tls_size = %lu KiB\n",
 472                 max_warps, screen->tls_size >> 10);
 473
 474    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, screen->tls_size,
 475                         &screen->tls_bo);
 476    if (ret)
 477       FAIL_SCREEN_INIT("Failed to allocate stack bo: %d\n", ret);
 478
 479    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
 480    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 481    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 482    OUT_RING  (chan, util_unsigned_logbase2(tls_space / 8));
 483
 484    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
 485                         &screen->uniforms);
 486    if (ret)
 487       goto fail;
 488
 489    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 490    OUT_RELOCh(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 491    OUT_RELOCl(chan, screen->uniforms, 0 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 492    OUT_RING  (chan, (NV50_CB_PVP << 16) | 0x0000);
 493
 494    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 495    OUT_RELOCh(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 496    OUT_RELOCl(chan, screen->uniforms, 1 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 497    OUT_RING  (chan, (NV50_CB_PGP << 16) | 0x0000);
 498
 499    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 500    OUT_RELOCh(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 501    OUT_RELOCl(chan, screen->uniforms, 2 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 502    OUT_RING  (chan, (NV50_CB_PFP << 16) | 0x0000);
 503
 504    BEGIN_RING(chan, RING_3D(CB_DEF_ADDRESS_HIGH), 3);
 505    OUT_RELOCh(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 506    OUT_RELOCl(chan, screen->uniforms, 3 << 16, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 507    OUT_RING  (chan, (NV50_CB_AUX << 16) | 0x0200);
 508
 509    BEGIN_RING_NI(chan, RING_3D(SET_PROGRAM_CB), 6);
 510    OUT_RING  (chan, (NV50_CB_PVP << 12) | 0x001);
 511    OUT_RING  (chan, (NV50_CB_PGP << 12) | 0x021);
 512    OUT_RING  (chan, (NV50_CB_PFP << 12) | 0x031);
 513    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf01);
 514    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf21);
 515    OUT_RING  (chan, (NV50_CB_AUX << 12) | 0xf31);
 516
 517    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16,
 518                         &screen->txc);
 519    if (ret)
 520       FAIL_SCREEN_INIT("Could not allocate TIC/TSC bo: %d\n", ret);
 521
 522    /* max TIC (bits 4:8) & TSC bindings, per program type */
 523    for (i = 0; i < 3; ++i) {
 524       BEGIN_RING(chan, RING_3D(TEX_LIMITS(i)), 1);
 525       OUT_RING  (chan, 0x54);
 526    }
 527
 528    BEGIN_RING(chan, RING_3D(TIC_ADDRESS_HIGH), 3);
 529    OUT_RELOCh(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 530    OUT_RELOCl(chan, screen->txc, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 531    OUT_RING  (chan, NV50_TIC_MAX_ENTRIES - 1);
 532
 533    BEGIN_RING(chan, RING_3D(TSC_ADDRESS_HIGH), 3);
 534    OUT_RELOCh(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 535    OUT_RELOCl(chan, screen->txc, 65536, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
 536    OUT_RING  (chan, NV50_TSC_MAX_ENTRIES - 1);
 537
 538    BEGIN_RING(chan, RING_3D(LINKED_TSC), 1);
 539    OUT_RING  (chan, 0);
 540
 541    BEGIN_RING(chan, RING_3D(CLIP_RECTS_EN), 1);
 542    OUT_RING  (chan, 0);
 543    BEGIN_RING(chan, RING_3D(CLIP_RECTS_MODE), 1);
 544    OUT_RING  (chan, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
 545    BEGIN_RING(chan, RING_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
 546    for (i = 0; i < 8 * 2; ++i)
 547       OUT_RING(chan, 0);
 548    BEGIN_RING(chan, RING_3D(CLIPID_ENABLE), 1);
 549    OUT_RING  (chan, 0);
 550
 551    BEGIN_RING(chan, RING_3D(VIEWPORT_TRANSFORM_EN), 1);
 552    OUT_RING  (chan, 1);
 553    BEGIN_RING(chan, RING_3D(DEPTH_RANGE_NEAR(0)), 2);
 554    OUT_RINGf (chan, 0.0f);
 555    OUT_RINGf (chan, 1.0f);
 556
 557    BEGIN_RING(chan, RING_3D(VIEW_VOLUME_CLIP_CTRL), 1);
 558 #ifdef NV50_SCISSORS_CLIPPING
 559    OUT_RING  (chan, 0x0000);
 560 #else
 561    OUT_RING  (chan, 0x1080);
 562 #endif
 563
 564    BEGIN_RING(chan, RING_3D(CLEAR_FLAGS), 1);
 565    OUT_RING  (chan, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
 566
 567    /* We use scissors instead of exact view volume clipping,
 568     * so they're always enabled.
 569     */
 570    BEGIN_RING(chan, RING_3D(SCISSOR_ENABLE(0)), 3);
 571    OUT_RING  (chan, 1);
 572    OUT_RING  (chan, 8192 << 16);
 573    OUT_RING  (chan, 8192 << 16);
 574
 575    BEGIN_RING(chan, RING_3D(RASTERIZE_ENABLE), 1);
 576    OUT_RING  (chan, 1);
 577    BEGIN_RING(chan, RING_3D(POINT_RASTER_RULES), 1);
 578    OUT_RING  (chan, NV50_3D_POINT_RASTER_RULES_OGL);
 579    BEGIN_RING(chan, RING_3D(FRAG_COLOR_CLAMP_EN), 1);
 580    OUT_RING  (chan, 0x11111111);
 581    BEGIN_RING(chan, RING_3D(EDGEFLAG_ENABLE), 1);
 582    OUT_RING  (chan, 1);
 583
 584    FIRE_RING (chan);
 585
 586    screen->tic.entries = CALLOC(4096, sizeof(void *));
 587    screen->tsc.entries = screen->tic.entries + 2048;
 588
 589    screen->mm_GART = nv50_mm_create(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP,
 590                                     0x000);
 591    screen->mm_VRAM = nv50_mm_create(dev, NOUVEAU_BO_VRAM, 0x000);
 592    screen->mm_VRAM_fe0 = nv50_mm_create(dev, NOUVEAU_BO_VRAM, 0xfe0);
 593
 594    nv50_screen_fence_new(screen, &screen->fence.current, FALSE);
 595
 596    return pscreen;
 597
 598 fail:
 599    nv50_screen_destroy(pscreen);
 600    return NULL;
 601 }
 602
 603 void
 604 nv50_screen_make_buffers_resident(struct nv50_screen *screen)
 605 {
 606    struct nouveau_channel *chan = screen->base.channel;
 607
 608    const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD;
 609
 610    MARK_RING(chan, 5, 5);
 611    nouveau_bo_validate(chan, screen->code, flags);
 612    nouveau_bo_validate(chan, screen->uniforms, flags);
 613    nouveau_bo_validate(chan, screen->txc, flags);
 614    nouveau_bo_validate(chan, screen->tls_bo, flags);
 615    nouveau_bo_validate(chan, screen->stack_bo, flags);
 616 }
 617
 618 int
 619 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
 620 {
 621    int i = screen->tic.next;
 622
 623    while (screen->tic.lock[i / 32] & (1 << (i % 32)))
 624       i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 625
 626    screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
 627
 628    if (screen->tic.entries[i])
 629       nv50_tic_entry(screen->tic.entries[i])->id = -1;
 630
 631    screen->tic.entries[i] = entry;
 632    return i;
 633 }
 634
 635 int
 636 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
 637 {
 638    int i = screen->tsc.next;
 639
 640    while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
 641       i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 642
 643    screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
 644
 645    if (screen->tsc.entries[i])
 646       nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
 647
 648    screen->tsc.entries[i] = entry;
 649    return i;
 650 }