315ca80c0d2c51557fc1cf252756fe8a9243ecfd
[mesa.git] / src / gallium / drivers / nv50 / nv50_screen.h
1 #ifndef __NV50_SCREEN_H__
2 #define __NV50_SCREEN_H__
3
4 #define NOUVEAU_NVC0
5 #include "nouveau/nouveau_screen.h"
6 #include "nouveau/nouveau_fence.h"
7 #include "nouveau/nouveau_mm.h"
8 #undef NOUVEAU_NVC0
9 #include "nv50_winsys.h"
10 #include "nv50_stateobj.h"
11
12 #define NV50_TIC_MAX_ENTRIES 2048
13 #define NV50_TSC_MAX_ENTRIES 2048
14
15 struct nv50_context;
16
17 #define NV50_CODE_BO_SIZE_LOG2 19
18
19 #define NV50_SCRATCH_SIZE (2 << 20)
20 #define NV50_SCRATCH_NR_BUFFERS 2
21
22 #define NV50_SCREEN_RESIDENT_BO_COUNT 5
23
24 struct nv50_blitctx;
25
26 struct nv50_screen {
27 struct nouveau_screen base;
28 struct nouveau_winsys *nvws;
29
30 struct nv50_context *cur_ctx;
31
32 struct nouveau_bo *code;
33 struct nouveau_bo *uniforms;
34 struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
35 struct nouveau_bo *stack_bo;
36 struct nouveau_bo *tls_bo;
37
38 uint64_t tls_size;
39
40 struct nouveau_resource *vp_code_heap;
41 struct nouveau_resource *gp_code_heap;
42 struct nouveau_resource *fp_code_heap;
43
44 struct nv50_blitctx *blitctx;
45
46 struct {
47 void **entries;
48 int next;
49 uint32_t lock[NV50_TIC_MAX_ENTRIES / 32];
50 } tic;
51
52 struct {
53 void **entries;
54 int next;
55 uint32_t lock[NV50_TSC_MAX_ENTRIES / 32];
56 } tsc;
57
58 struct {
59 uint32_t *map;
60 struct nouveau_bo *bo;
61 } fence;
62
63 struct nouveau_notifier *sync;
64
65 struct nouveau_mman *mm_VRAM_fe0;
66
67 struct nouveau_grobj *tesla;
68 struct nouveau_grobj *eng2d;
69 struct nouveau_grobj *m2mf;
70 };
71
72 static INLINE struct nv50_screen *
73 nv50_screen(struct pipe_screen *screen)
74 {
75 return (struct nv50_screen *)screen;
76 }
77
78 boolean nv50_blitctx_create(struct nv50_screen *);
79
80 void nv50_screen_make_buffers_resident(struct nv50_screen *);
81
82 int nv50_screen_tic_alloc(struct nv50_screen *, void *);
83 int nv50_screen_tsc_alloc(struct nv50_screen *, void *);
84
85 static INLINE void
86 nv50_resource_fence(struct nv04_resource *res, uint32_t flags)
87 {
88 struct nv50_screen *screen = nv50_screen(res->base.screen);
89
90 if (res->mm) {
91 nouveau_fence_ref(screen->base.fence.current, &res->fence);
92
93 if (flags & NOUVEAU_BO_WR)
94 nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
95 }
96 }
97
98 static INLINE void
99 nv50_resource_validate(struct nv04_resource *res, uint32_t flags)
100 {
101 struct nv50_screen *screen = nv50_screen(res->base.screen);
102
103 if (likely(res->bo)) {
104 nouveau_bo_validate(screen->base.channel, res->bo, flags);
105
106 if (flags & NOUVEAU_BO_WR)
107 res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
108 if (flags & NOUVEAU_BO_RD)
109 res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
110
111 nv50_resource_fence(res, flags);
112 }
113 }
114
115 struct nv50_format {
116 uint32_t rt;
117 uint32_t tic;
118 uint32_t vtx;
119 uint32_t usage;
120 };
121
122 extern const struct nv50_format nv50_format_table[];
123
124 static INLINE void
125 nv50_screen_tic_unlock(struct nv50_screen *screen, struct nv50_tic_entry *tic)
126 {
127 if (tic->id >= 0)
128 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
129 }
130
131 static INLINE void
132 nv50_screen_tsc_unlock(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
133 {
134 if (tsc->id >= 0)
135 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
136 }
137
138 static INLINE void
139 nv50_screen_tic_free(struct nv50_screen *screen, struct nv50_tic_entry *tic)
140 {
141 if (tic->id >= 0) {
142 screen->tic.entries[tic->id] = NULL;
143 screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
144 }
145 }
146
147 static INLINE void
148 nv50_screen_tsc_free(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
149 {
150 if (tsc->id >= 0) {
151 screen->tsc.entries[tsc->id] = NULL;
152 screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
153 }
154 }
155
156 #endif