src/gallium/drivers/nv50/nv50_screen.h

   1 #ifndef __NV50_SCREEN_H__
   2 #define __NV50_SCREEN_H__
   3
   4 #include "nouveau/nouveau_screen.h"
   5 #include "nouveau/nouveau_fence.h"
   6 #include "nouveau/nouveau_mm.h"
   7 #include "nouveau/nouveau_heap.h"
   8
   9 #include "nv50_winsys.h"
  10 #include "nv50_stateobj.h"
  11
  12 #define NV50_TIC_MAX_ENTRIES 2048
  13 #define NV50_TSC_MAX_ENTRIES 2048
  14
  15 struct nv50_context;
  16
  17 #define NV50_CODE_BO_SIZE_LOG2 19
  18
  19 #define NV50_SCREEN_RESIDENT_BO_COUNT 5
  20
  21 struct nv50_blitctx;
  22
  23 struct nv50_screen {
  24    struct nouveau_screen base;
  25
  26    struct nv50_context *cur_ctx;
  27
  28    struct nouveau_bo *code;
  29    struct nouveau_bo *uniforms;
  30    struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
  31    struct nouveau_bo *stack_bo;
  32    struct nouveau_bo *tls_bo;
  33
  34    uint64_t tls_size;
  35
  36    struct nouveau_heap *vp_code_heap;
  37    struct nouveau_heap *gp_code_heap;
  38    struct nouveau_heap *fp_code_heap;
  39
  40    struct nv50_blitctx *blitctx;
  41
  42    struct {
  43       void **entries;
  44       int next;
  45       uint32_t lock[NV50_TIC_MAX_ENTRIES / 32];
  46    } tic;
  47
  48    struct {
  49       void **entries;
  50       int next;
  51       uint32_t lock[NV50_TSC_MAX_ENTRIES / 32];
  52    } tsc;
  53
  54    struct {
  55       uint32_t *map;
  56       struct nouveau_bo *bo;
  57    } fence;
  58
  59    struct nouveau_object *sync;
  60
  61    struct nouveau_object *tesla;
  62    struct nouveau_object *eng2d;
  63    struct nouveau_object *m2mf;
  64 };
  65
  66 static INLINE struct nv50_screen *
  67 nv50_screen(struct pipe_screen *screen)
  68 {
  69    return (struct nv50_screen *)screen;
  70 }
  71
  72 boolean nv50_blitctx_create(struct nv50_screen *);
  73
  74 int nv50_screen_tic_alloc(struct nv50_screen *, void *);
  75 int nv50_screen_tsc_alloc(struct nv50_screen *, void *);
  76
  77 static INLINE void
  78 nv50_resource_fence(struct nv04_resource *res, uint32_t flags)
  79 {
  80    struct nv50_screen *screen = nv50_screen(res->base.screen);
  81
  82    if (res->mm) {
  83       nouveau_fence_ref(screen->base.fence.current, &res->fence);
  84       if (flags & NOUVEAU_BO_WR)
  85          nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);
  86    }
  87 }
  88
  89 static INLINE void
  90 nv50_resource_validate(struct nv04_resource *res, uint32_t flags)
  91 {
  92    if (likely(res->bo)) {
  93       if (flags & NOUVEAU_BO_WR)
  94          res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
  95       if (flags & NOUVEAU_BO_RD)
  96          res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
  97
  98       nv50_resource_fence(res, flags);
  99    }
 100 }
 101
 102 struct nv50_format {
 103    uint32_t rt;
 104    uint32_t tic;
 105    uint32_t vtx;
 106    uint32_t usage;
 107 };
 108
 109 extern const struct nv50_format nv50_format_table[];
 110
 111 static INLINE void
 112 nv50_screen_tic_unlock(struct nv50_screen *screen, struct nv50_tic_entry *tic)
 113 {
 114    if (tic->id >= 0)
 115       screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
 116 }
 117
 118 static INLINE void
 119 nv50_screen_tsc_unlock(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
 120 {
 121    if (tsc->id >= 0)
 122       screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
 123 }
 124
 125 static INLINE void
 126 nv50_screen_tic_free(struct nv50_screen *screen, struct nv50_tic_entry *tic)
 127 {
 128    if (tic->id >= 0) {
 129       screen->tic.entries[tic->id] = NULL;
 130       screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
 131    }
 132 }
 133
 134 static INLINE void
 135 nv50_screen_tsc_free(struct nv50_screen *screen, struct nv50_tsc_entry *tsc)
 136 {
 137    if (tsc->id >= 0) {
 138       screen->tsc.entries[tsc->id] = NULL;
 139       screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));
 140    }
 141 }
 142
 143 #endif